Update old comments based on PR feedback

Signed-off-by: Ludvig Liljenberg <[email protected]>

Author: ludfjig

src/hyperlight_host/src/hypervisor/gdb/mod.rs

@@ -276,7 +276,7 @@ pub(crate) enum DebugResponse {
 }
 
 /// Trait for VMs that support debugging capabilities.
-/// This extends the base Hypervisor trait with GDB-specific functionality.
+/// This extends the base Vm trait with GDB-specific functionality.
 pub(crate) trait DebuggableVm: Vm {
     /// Translates a guest virtual address to a guest physical address
     fn translate_gva(&self, gva: u64) -> crate::Result<u64>;

src/hyperlight_host/src/hypervisor/vm/mod.rs

@@ -23,12 +23,13 @@ use crate::Result;
 use crate::hypervisor::regs::{CommonFpu, CommonRegisters, CommonSpecialRegisters};
 use crate::mem::memory_region::MemoryRegion;
 
+/// KVM (Kernel-based Virtual Machine) functionality (linux)
 #[cfg(kvm)]
-/// Functionality to manipulate KVM-based virtual machines
 pub(crate) mod kvm;
-/// HyperV-on-linux functionality
+/// MSHV (Microsoft Hypervisor) functionality (linux)
 #[cfg(mshv3)]
 pub(crate) mod mshv;
+/// WHP (Windows Hypervisor Platform) functionality (windows)
 #[cfg(target_os = "windows")]
 pub(crate) mod whp;
 
@@ -180,6 +181,30 @@ pub(crate) trait Vm: Debug + Send {
 
 #[cfg(test)]
 mod tests {
+    use crate::hypervisor::regs::{CommonSegmentRegister, CommonTableRegister};
+
+    use super::*;
+
+    fn boxed_vm() -> Box<dyn Vm> {
+        let available_vm = get_available_hypervisor().as_ref().unwrap();
+        match available_vm {
+            #[cfg(kvm)]
+            HypervisorType::Kvm => {
+                use crate::hypervisor::vm::kvm::KvmVm;
+                Box::new(KvmVm::new().unwrap())
+            }
+            #[cfg(mshv3)]
+            HypervisorType::Mshv => {
+                use crate::hypervisor::vm::mshv::MshvVm;
+                Box::new(MshvVm::new().unwrap())
+            }
+            #[cfg(target_os = "windows")]
+            HypervisorType::Whp => {
+                use crate::hypervisor::vm::whp::WhpVm;
+                Box::new(WhpVm::new().unwrap())
+            }
+        }
+    }
 
     #[test]
     // TODO: add support for testing on WHP
@@ -199,4 +224,126 @@ mod tests {
             }
         }
     }
+
+    #[test]
+    fn regs() {
+        let vm = boxed_vm();
+
+        let regs = CommonRegisters {
+            rax: 1,
+            rbx: 2,
+            rcx: 3,
+            rdx: 4,
+            rsi: 5,
+            rdi: 6,
+            rsp: 7,
+            rbp: 8,
+            r8: 9,
+            r9: 10,
+            r10: 11,
+            r11: 12,
+            r12: 13,
+            r13: 14,
+            r14: 15,
+            r15: 16,
+            rip: 17,
+            rflags: 0x2,
+        };
+
+        vm.set_regs(&regs).unwrap();
+        let read_regs = vm.regs().unwrap();
+        assert_eq!(regs, read_regs);
+    }
+
+    #[test]
+    fn fpu() {
+        let vm = boxed_vm();
+
+        let fpu = CommonFpu {
+            fpr: [[1; 16]; 8],
+            fcw: 2,
+            fsw: 3,
+            ftwx: 4,
+            last_opcode: 5,
+            last_ip: 6,
+            last_dp: 7,
+            xmm: [[8; 16]; 16],
+            mxcsr: 9,
+            pad1: 0,
+            pad2: 0,
+        };
+        vm.set_fpu(&fpu).unwrap();
+        #[cfg_attr(kvm, allow(unused_mut))]
+        let mut read_fpu = vm.fpu().unwrap();
+        #[cfg(kvm)]
+        {
+            read_fpu.mxcsr = fpu.mxcsr; // KVM get/set fpu does not preserve mxcsr
+        }
+        assert_eq!(fpu, read_fpu);
+    }
+
+    #[test]
+    fn sregs() {
+        let vm = boxed_vm();
+
+        let segment = CommonSegmentRegister {
+            base: 1,
+            limit: 2,
+            selector: 3,
+            type_: 3,
+            present: 1,
+            dpl: 1,
+            db: 0,
+            s: 1,
+            l: 1,
+            g: 1,
+            avl: 1,
+            unusable: 0,
+            padding: 0,
+        };
+
+        let cs_segment = CommonSegmentRegister {
+            base: 1,
+            limit: 0xFFFF,
+            selector: 0x08,
+            type_: 0b1011, // code segment, execute/read, accessed
+            present: 1,
+            dpl: 1,
+            db: 0, // must be 0 in 64-bit mode
+            s: 1,
+            l: 1, // 64-bit mode
+            g: 1,
+            avl: 1,
+            unusable: 0,
+            padding: 0,
+        };
+        let table = CommonTableRegister {
+            base: 12,
+            limit: 13,
+        };
+        let sregs = CommonSpecialRegisters {
+            cs: cs_segment,
+            ds: segment,
+            es: segment,
+            fs: segment,
+            gs: segment,
+            ss: segment,
+            tr: segment,
+            ldt: segment,
+            gdt: table,
+            idt: table,
+            cr0: 0x80000001,
+            cr2: 2,
+            cr3: 3,
+            cr4: 0x20,
+            cr8: 5,
+            efer: 0x500,
+            apic_base: 0xFEE00900,
+            interrupt_bitmap: [0; 4],
+            ..Default::default()
+        };
+        vm.set_sregs(&sregs).unwrap();
+        let read_sregs = vm.sregs().unwrap();
+        assert_eq!(sregs, read_sregs);
+    }
 }