f

Author: mkroening

src/arch/aarch64/kernel/scheduler.rs

@@ -296,7 +296,7 @@ impl TaskFrame for Task {
 		if self.tls.is_none() {
 			use crate::scheduler::task::tls::Tls;
 
-			self.tls = Tls::from_environment();
+			self.tls = Tls::from_env();
 		}
 
 		unsafe {

src/arch/riscv64/kernel/scheduler.rs

@@ -9,8 +9,6 @@ use crate::arch::riscv64::kernel::processor::set_oneshot_timer;
 use crate::arch::riscv64::mm::paging::{BasePageSize, PageSize, PageTableEntryFlags};
 use crate::mm::physicalmem::PHYSICAL_FREE_LIST;
 use crate::mm::virtualmem::KERNEL_FREE_LIST;
-#[cfg(not(feature = "common-os"))]
-use crate::scheduler::task::tls::Tls;
 use crate::scheduler::task::{Task, TaskFrame};
 use crate::{DEFAULT_STACK_SIZE, KERNEL_STACK_SIZE};
 
@@ -317,7 +315,9 @@ impl TaskFrame for Task {
 		// check is TLS is already allocated
 		#[cfg(not(feature = "common-os"))]
 		if self.tls.is_none() {
-			self.tls = Tls::from_environment();
+			use crate::scheduler::task::tls::Tls;
+
+			self.tls = Tls::from_env();
 		}
 
 		unsafe {

src/arch/x86_64/kernel/scheduler.rs

@@ -18,8 +18,6 @@ use crate::env;
 use crate::mm::physicalmem::PHYSICAL_FREE_LIST;
 use crate::mm::virtualmem::KERNEL_FREE_LIST;
 use crate::scheduler::PerCoreSchedulerExt;
-#[cfg(not(feature = "common-os"))]
-use crate::scheduler::task::tls::Tls;
 use crate::scheduler::task::{Task, TaskFrame};
 
 #[repr(C, packed)]
@@ -289,7 +287,9 @@ impl TaskFrame for Task {
 		// Check if TLS is allocated already and if the task uses thread-local storage.
 		#[cfg(not(feature = "common-os"))]
 		if self.tls.is_none() {
-			self.tls = Tls::from_environment();
+			use crate::scheduler::task::tls::Tls;
+
+			self.tls = Tls::from_env();
 		}
 
 		unsafe {

src/scheduler/task/mod.rs

@@ -1,6 +1,6 @@
 #![allow(clippy::type_complexity)]
 
-pub mod tls;
+pub(crate) mod tls;
 
 use alloc::collections::{LinkedList, VecDeque};
 use alloc::rc::Rc;

src/scheduler/task/tls.rs

@@ -1,50 +1,57 @@
-//! Thread-local storage data structures
+//! Thread-local storage data structures.
 //!
-//! See _ELF Handling For Thread-Local Storage_ [[tls]].
+//! See _ELF Handling For Thread-Local Storage_ [\[tls\]] for details.
 //!
-//! - For `riscv`-specifics, see _Thread Local Storage - RISC-V ELF Specification - RISC-V ELF psABI Document_ [[riscv]].
+//! - For ARM specifics, see
+//!   - _4 ADDENDUM: Thread Local Storage - Addenda to, and Errata in, the ABI for the Arm Architecture_ [\[riscv\]] and
+//!   - _Speeding Up Thread-Local Storage Access in Dynamic Libraries in the ARM platform_ [\[paper-lk2006\]].
+//! - For RISC-V specifics, see
+//!   - _Thread Local Storage - RISC-V ELF Specification - RISC-V ELF psABI Document_ [\[riscv\]].
+//! - For x86-64 specifics, see
+//!   - _ELF x86-64-ABI psABI_ [\[x86-64 psABI\]] and
+//!   - _Thread-Local Storage Descriptors for IA32 and AMD64/EM64T_ [\[RFC-TLSDESC-x86\]]
 //!
-//! The dynamic thread vector (dtv) is currently unused.
-//!
-//! [[tls]]: https://akkadia.org/drepper/tls.pdf
-//! [[riscv]]: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/v1.0/riscv-elf.adoc#thread-local-storage
+//! [\[tls\]]: https://akkadia.org/drepper/tls.pdf
+//! [\[arm\]]: https://github.com/ARM-software/abi-aa/blob/2025Q1/addenda32/addenda32.rst#addendum-thread-local-storage
+//! [\[paper-lk2006\]]: https://www.fsfla.org/~lxoliva/writeups/TLS/paper-lk2006.pdf
+//! [\[riscv\]]: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/v1.0/riscv-elf.adoc#thread-local-storage
+//! [\[x86-64 psABI\]]: https://gitlab.com/x86-psABIs/x86-64-ABI/-/jobs/artifacts/master/raw/x86-64-ABI/abi.pdf?job=build
+//! [\[RFC-TLSDESC-x86\]]: https://www.fsfla.org/~lxoliva/writeups/TLS/RFC-TLSDESC-x86.txt
 
 use core::alloc::Layout;
-use core::mem::MaybeUninit;
+use core::mem::{self, MaybeUninit};
 use core::{ptr, slice};
 
 use hermit_entry::boot_info::TlsInfo;
 
 use self::allocation::Allocation;
 
+/// Thread-local storage data structures.
 pub struct Tls {
 	_block: Allocation,
 	thread_ptr: *mut (),
 }
 
+/// Thread control block.
 #[repr(C)]
 struct Tcb {
-	/// > For the implementation on GNU systems we can add one more requirement. The
-	/// > address %gs:0 represents is actually the same as the thread pointer. I.e., the content of
-	/// > the word addressed via %gs:0 is the address of the very same location.
-	///
-	/// [[tls]] Section 3.4.2: IA-32 specific
+	/// Thread pointer.
 	#[cfg(target_arch = "x86_64")]
 	thread_ptr: *mut (),
 
 	/// Pointer to the dynamic thread vector (dtv).
 	///
-	/// Currently unused.
-	dtv_ptr: *mut (),
+	/// Currently not needed on Hermit.
+	dtv: *mut (),
 
-	/// OS-specific TCB data.
+	/// Implementation-defined TCB data.
 	///
-	/// Currently unused.
+	/// Currently not used on Hermit.
 	tcb_data: *mut (),
 }
 
 impl Tls {
-	pub fn new(tls_info: TlsInfo) -> Self {
+	unsafe fn new(tls_info: TlsInfo) -> Self {
 		let start = usize::try_from(tls_info.start).unwrap();
 		let filesz = usize::try_from(tls_info.filesz).unwrap();
 		let memsz = usize::try_from(tls_info.memsz).unwrap();
@@ -53,7 +60,6 @@ impl Tls {
 		// Get TLS initialization image
 		let tls_init_image = {
 			let start = ptr::with_exposed_provenance(start);
-			// SAFETY: We will have to trust the environment here.
 			unsafe { slice::from_raw_parts(start, filesz) }
 		};
 
@@ -62,37 +68,53 @@ impl Tls {
 			.unwrap()
 			.pad_to_align();
 
-		let (tls_layout, data_offset, tcb_offset) =
+		let (layout, tls_offset, tcb_offset) =
 			if cfg!(any(target_arch = "aarch64", target_arch = "riscv64")) {
 				// AArch64 and 64-bit RISC-V use TLS data structures variant I.
-				// This means the TLS data comes after the TCB.
+
+				// Variant I does not guarantee more than 16 bytes of space for the TCB.
+				assert_eq!(tcb_layout.size(), 16);
+
+				// Variant I requires the dtv pointer to be at the start of the TCB.
+				assert_eq!(mem::offset_of!(Tcb, dtv), 0);
+
+				// In variant I, the TLS data comes after the TCB.
 				let (tls_layout, data_offset) = tcb_layout.extend(data_layout).unwrap();
 				(tls_layout.pad_to_align(), data_offset, 0)
 			} else if cfg!(target_arch = "x86_64") {
 				// x86-64 uses TLS data structures variant II.
-				// This means the TCB comes after the TLS data.
+
+				// Variant II (on GNU systems) requires the thread pointer to be at the start of the TCB:
+				// > For the implementation on GNU systems we can add one more requirement. The
+				// > address %gs:0 represents is actually the same as the thread pointer. I.e., the content of
+				// > the word addressed via %gs:0 is the address of the very same location.
+				#[cfg(target_arch = "x86_64")]
+				assert_eq!(mem::offset_of!(Tcb, thread_ptr), 0);
+
+				// In Variant II, the TCB comes after the TLS data.
 				let (tls_layout, tcb_offset) = data_layout.extend(tcb_layout).unwrap();
 				(tls_layout.pad_to_align(), 0, tcb_offset)
 			} else {
 				unimplemented!()
 			};
 
-		let mut block = Allocation::new(tls_layout).unwrap();
+		let mut block = Allocation::new(layout).unwrap();
 
-		// Initialize beginning of the TLS block with TLS initialization image
-		block.as_mut_slice()[data_offset..][..tls_init_image.len()].copy_from_slice(tls_init_image);
+		// Initialize the beginning of the TLS block with the TLS initialization image.
+		block.as_mut_slice()[tls_offset..][..tls_init_image.len()].copy_from_slice(tls_init_image);
 
-		// Fill the rest of the block with zeros
-		block.as_mut_slice()[data_offset..][tls_init_image.len()..data_layout.size()]
+		// Fill the rest of the TLS block with zeros.
+		block.as_mut_slice()[tls_offset..][tls_init_image.len()..data_layout.size()]
 			.fill(MaybeUninit::new(0));
 
-		let thread_ptr = if cfg!(target_arch = "aarch64") {
+		let thread_ptr = if cfg!(target_arch = "riscv64") {
+			// On RISC-V, `tp` points to the address one past the end of the TCB.
+			unsafe { block.as_mut_ptr().add(tls_offset).cast() }
+		} else if cfg!(target_arch = "aarch64") {
+			// For variant I, `tp` points to the start of the block.
 			block.as_mut_ptr().cast()
-		} else if cfg!(target_arch = "riscv64") {
-			// > `tp` containing the address one past the end of the TCB.
-			// [[riscv]]
-			unsafe { block.as_mut_ptr().add(data_offset).cast() }
 		} else if cfg!(target_arch = "x86_64") {
+			// For variant II, `tp` points to the TCB after the TLS data.
 			unsafe { block.as_mut_ptr().add(tcb_offset).cast() }
 		} else {
 			unimplemented!()
@@ -102,7 +124,7 @@ impl Tls {
 		let tcb = Tcb {
 			#[cfg(target_arch = "x86_64")]
 			thread_ptr,
-			dtv_ptr: ptr::null_mut(),
+			dtv: ptr::null_mut(),
 			tcb_data: ptr::null_mut(),
 		};
 		unsafe {
@@ -115,9 +137,10 @@ impl Tls {
 		}
 	}
 
-	pub fn from_environment() -> Option<Self> {
+	pub fn from_env() -> Option<Self> {
 		let tls_info = crate::env::boot_info().load_info.tls_info?;
-		Some(Self::new(tls_info))
+		let this = unsafe { Self::new(tls_info) };
+		Some(this)
 	}
 
 	pub fn thread_ptr(&self) -> *mut () {
@@ -137,20 +160,22 @@ mod allocation {
 
 	impl Allocation {
 		pub fn new(layout: Layout) -> Option<Self> {
-			let ptr = unsafe { ::alloc::alloc::alloc_zeroed(layout) };
+			let ptr = unsafe { ::alloc::alloc::alloc(layout) };
+
 			if ptr.is_null() {
 				return None;
 			}
-			Some(Self { ptr, layout })
-		}
 
-		pub fn as_mut_slice(&mut self) -> &mut [MaybeUninit<u8>] {
-			unsafe { slice::from_raw_parts_mut(self.ptr.cast(), self.layout.size()) }
+			Some(Self { ptr, layout })
 		}
 
 		pub fn as_mut_ptr(&self) -> *mut u8 {
 			self.ptr
 		}
+
+		pub fn as_mut_slice(&mut self) -> &mut [MaybeUninit<u8>] {
+			unsafe { slice::from_raw_parts_mut(self.ptr.cast(), self.layout.size()) }
+		}
 	}
 
 	impl Drop for Allocation {