Ignore case for VHDL

kevinpt · kevinpt · commit be7cdab08a8c · 2018-02-15T21:43:16.000-05:00
diff --git a/hdlparse/vhdl_parser.py b/hdlparse/vhdl_parser.py
@@ -142,7 +142,7 @@
   ],
 }
       
-VhdlLexer = MiniLexer(vhdl_tokens)
+VhdlLexer = MiniLexer(vhdl_tokens, flags=re.MULTILINE | re.IGNORECASE)
 
 
 class VhdlObject(object):

Original file line number	Diff line number	Diff line change
`@@ -142,7 +142,7 @@`
`142`	`142`	`],`
`143`	`143`	`}`
`144`	`144`
`145`		`-VhdlLexer = MiniLexer(vhdl_tokens)`
	`145`	`+VhdlLexer = MiniLexer(vhdl_tokens, flags=re.MULTILINE \| re.IGNORECASE)`
`146`	`146`
`147`	`147`
`148`	`148`	`class VhdlObject(object):`