Removed python 2 style class declaration

Author: michael-etzkorn

hdlparse/verilog_parser.py

@@ -59,7 +59,7 @@
 VerilogLexer = MiniLexer(verilog_tokens)
 
 
-class VerilogObject(object):
+class VerilogObject:
     """Base class for parsed Verilog objects"""
 
     def __init__(self, name, desc=None):
@@ -68,7 +68,7 @@ def __init__(self, name, desc=None):
         self.desc = [] if desc is None else desc
 
 
-class VerilogParameter(object):
+class VerilogParameter:
     """Parameter and port to a module"""
 
     def __init__(self, name, mode=None, data_type=None, default_value=None, desc=None):
@@ -229,7 +229,7 @@ def is_verilog(fname):
     return os.path.splitext(fname)[1].lower() in ('.vlog', '.v')
 
 
-class VerilogExtractor(object):
+class VerilogExtractor:
     """Utility class that caches parsed objects"""
 
     def __init__(self):

hdlparse/vhdl_parser.py

@@ -157,7 +157,7 @@
 VhdlLexer = MiniLexer(vhdl_tokens, flags=re.MULTILINE | re.IGNORECASE)
 
 
-class VhdlObject(object):
+class VhdlObject:
     """Base class for parsed VHDL objects
 
     Args:
@@ -171,7 +171,7 @@ def __init__(self, name, desc=None):
         self.desc = desc
 
 
-class VhdlParameter(object):
+class VhdlParameter:
     """Parameter to subprograms, ports, and generics
 
     Args:
@@ -207,7 +207,7 @@ def __repr__(self):
                                                         self.data_type.name + self.data_type.arange)
 
 
-class VhdlParameterType(object):
+class VhdlParameterType:
     """Parameter type definition
 
     Args:
@@ -684,7 +684,7 @@ def is_vhdl(fname):
     return os.path.splitext(fname)[1].lower() in ('.vhdl', '.vhd')
 
 
-class VhdlExtractor(object):
+class VhdlExtractor:
     """Utility class that caches parsed objects and tracks array type definitions
 
     Args: