Updating bazel build rules to support detailed

PiperOrigin-RevId: 494038560

Author: QuantamHD

pdk/open_road_configuration.bzl

@@ -40,9 +40,15 @@ OpenRoadPdkInfo = provider(
         "rc_script_configuration": "RC script for the various metal layers",
         "tapcell_tcl": "TCL file that sets tapcell options. This overrides other tapcell attributes in this rule.",
         "placement_padding_tcl": "TCL Script for handling the placement padding of cells",
+        "detailed_routing_configuration": "optional detailed routing configuration",
     },
 )
 
+DetailedRoutingInfo = provider(
+    "Detailed routing info params for OpenROAD",
+    fields = ["bottom_routing_layer", "top_routing_layer", "via_in_pin_bottom_layer", "via_in_pin_top_layer", "enable_via_gen"],
+)
+
 def _open_road_pdk_configuration_impl(ctx):
     return [
         OpenRoadPdkInfo(
@@ -69,6 +75,7 @@ def _open_road_pdk_configuration_impl(ctx):
             rc_script_configuration = ctx.file.rc_script_configuration,
             tapcell_tcl = ctx.file.tapcell_tcl,
             placement_padding_tcl = ctx.file.placement_padding_tcl,
+            detailed_routing_configuration = ctx.attr.detailed_routing_configuration,
         ),
     ]
 
@@ -98,7 +105,29 @@ open_road_pdk_configuration = rule(
         "rc_script_configuration": attr.label(allow_single_file = True),
         "tapcell_tcl": attr.label(allow_single_file = True, doc = "TCL file that sets tapcell options. This overrides other tapcell attributes in this rule."),
         "placement_padding_tcl": attr.label(allow_single_file = True, doc = "TCL Script for handling the placement padding of cells"),
+        "detailed_routing_configuration": attr.label(providers = [DetailedRoutingInfo]),
+    },
+)
+
+def detailed_routing_configuration_impl(ctx):
+    return [DetailedRoutingInfo(
+        bottom_routing_layer = ctx.attr.bottom_routing_layer,
+        top_routing_layer = ctx.attr.top_routing_layer,
+        via_in_pin_bottom_layer = ctx.attr.via_in_pin_bottom_layer,
+        via_in_pin_top_layer = ctx.attr.via_in_pin_top_layer,
+        enable_via_gen = ctx.attr.enable_via_gen,
+    )]
+
+detailed_routing_configuration = rule(
+    implementation = detailed_routing_configuration_impl,
+    attrs = {
+        "bottom_routing_layer": attr.string(mandatory = True, doc = "Minimum routing layer name"),
+        "top_routing_layer": attr.string(mandatory = True, doc = "Maximum routing layer name"),
+        "via_in_pin_bottom_layer": attr.string(doc = "via in pin bottom layer"),
+        "via_in_pin_top_layer": attr.string(doc = "via in pin top layer"),
+        "enable_via_gen": attr.bool(default = True),
     },
+    provides = [DetailedRoutingInfo],
 )
 
 def assert_has_open_road_configuration(synthesis_info):

place_and_route/open_road.bzl

@@ -234,6 +234,8 @@ def openroad_command(ctx, commands, input_db = None, step_name = None, inputs =
         arguments = [
             "-no_init",
             "-no_splash",
+            "-threads",
+            "max",
             "-exit",
             "-log",
             log_file.path,

place_and_route/private/clock_tree_synthesis.bzl

@@ -41,7 +41,7 @@ def clock_tree_synthesis(ctx, open_road_info):
         format_openroad_do_not_use_list(open_road_configuration.do_not_use_cell_list),
         "estimate_parasitics -placement",
         "repair_clock_inverters",
-        "clock_tree_synthesis -root_buf \"{cts_buffer}\" -buf_list \"{cts_buffer}\" -sink_clustering_enable".format(
+        "clock_tree_synthesis -root_buf \"{cts_buffer}\" -buf_list \"{cts_buffer}\" -sink_clustering_enable -post_cts_disable".format(
             cts_buffer = open_road_configuration.cts_buffer_cell,
         ),
         "set_propagated_clock [all_clocks]",

place_and_route/private/detailed_routing.bzl

@@ -15,6 +15,8 @@
 """Detailed Routing openROAD commands"""
 
 load("//place_and_route:open_road.bzl", "OpenRoadInfo", "merge_open_road_info", "openroad_command", "timing_setup_commands")
+load("@rules_hdl//pdk:open_road_configuration.bzl", "DetailedRoutingInfo", "get_open_road_configuration")
+load("//synthesis:build_defs.bzl", "SynthesisInfo")
 
 def detailed_routing(ctx, open_road_info):
     """Performs detailed routing.
@@ -34,8 +36,27 @@ def detailed_routing(ctx, open_road_info):
     output_drc = ctx.actions.declare_file("{}_output_drc".format(ctx.attr.name))
     routed_def = ctx.actions.declare_file("{}_detail_routed.def".format(ctx.attr.name))
 
+    open_road_configuration = get_open_road_configuration(ctx.attr.synthesized_rtl[SynthesisInfo])
+
+    detailed_routing_configs = None
+    if open_road_configuration.detailed_routing_configuration:
+        detailed_routing_configs = open_road_configuration.detailed_routing_configuration[DetailedRoutingInfo]
+
+    detailed_routing_args = ""
+    if detailed_routing_configs:
+        if detailed_routing_configs.bottom_routing_layer:
+            detailed_routing_args += " -bottom_routing_layer " + detailed_routing_configs.bottom_routing_layer
+        if detailed_routing_configs.top_routing_layer:
+            detailed_routing_args += " -top_routing_layer " + detailed_routing_configs.top_routing_layer
+        if detailed_routing_configs.via_in_pin_bottom_layer:
+            detailed_routing_args += " -via_in_pin_bottom_layer " + detailed_routing_configs.via_in_pin_bottom_layer
+        if detailed_routing_configs.via_in_pin_top_layer:
+            detailed_routing_args += " -via_in_pin_top_layer " + detailed_routing_configs.via_in_pin_top_layer
+        if detailed_routing_configs.enable_via_gen:
+            detailed_routing_args += " -disable_via_gen "
+
     open_road_commands = timing_setup_command_struct.commands + [
-        "detailed_route -output_drc {}".format(output_drc.path),
+        "detailed_route -output_drc {} {}".format(output_drc.path, detailed_routing_args),
         "write_def {}".format(
             routed_def.path,
         ),