|
98 | 98 | reg = <0>;
|
99 | 99 | max-speed = <100>;
|
100 | 100 | reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
|
101 |
| - reset-delay-us = <1000>; |
102 |
| - reset-post-delay-us = <1000>; |
| 101 | + reset-assert-us = <1000>; |
| 102 | + reset-deassert-us = <1000>; |
| 103 | + smsc,disable-energy-detect; /* Make plugin detection reliable */ |
103 | 104 | };
|
104 | 105 | };
|
105 | 106 | };
|
106 | 107 |
|
107 | 108 | &i2c1 {
|
108 | 109 | clock-frequency = <100000>;
|
109 |
| - pinctrl-names = "default"; |
| 110 | + pinctrl-names = "default", "gpio"; |
110 | 111 | pinctrl-0 = <&pinctrl_i2c1>;
|
| 112 | + pinctrl-1 = <&pinctrl_i2c1_gpio>; |
| 113 | + scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| 114 | + sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
111 | 115 | status = "okay";
|
112 | 116 | };
|
113 | 117 |
|
114 | 118 | &i2c2 {
|
115 | 119 | clock-frequency = <100000>;
|
116 |
| - pinctrl-names = "default"; |
| 120 | + pinctrl-names = "default", "gpio"; |
117 | 121 | pinctrl-0 = <&pinctrl_i2c2>;
|
| 122 | + pinctrl-1 = <&pinctrl_i2c2_gpio>; |
| 123 | + scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| 124 | + sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
118 | 125 | status = "okay";
|
119 | 126 | };
|
120 | 127 |
|
121 | 128 | &i2c3 {
|
122 | 129 | clock-frequency = <100000>;
|
123 |
| - pinctrl-names = "default"; |
| 130 | + pinctrl-names = "default", "gpio"; |
124 | 131 | pinctrl-0 = <&pinctrl_i2c3>;
|
| 132 | + pinctrl-1 = <&pinctrl_i2c3_gpio>; |
| 133 | + scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| 134 | + sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
125 | 135 | status = "okay";
|
126 | 136 |
|
127 | 137 | ltc3676: pmic@3c {
|
|
287 | 297 | >;
|
288 | 298 | };
|
289 | 299 |
|
| 300 | + pinctrl_i2c1_gpio: i2c1-gpio-grp { |
| 301 | + fsl,pins = < |
| 302 | + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 |
| 303 | + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 |
| 304 | + >; |
| 305 | + }; |
| 306 | + |
290 | 307 | pinctrl_i2c2: i2c2-grp {
|
291 | 308 | fsl,pins = <
|
292 | 309 | MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
|
293 | 310 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
294 | 311 | >;
|
295 | 312 | };
|
296 | 313 |
|
| 314 | + pinctrl_i2c2_gpio: i2c2-gpio-grp { |
| 315 | + fsl,pins = < |
| 316 | + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 |
| 317 | + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 |
| 318 | + >; |
| 319 | + }; |
| 320 | + |
297 | 321 | pinctrl_i2c3: i2c3-grp {
|
298 | 322 | fsl,pins = <
|
299 | 323 | MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
|
300 | 324 | MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
|
301 | 325 | >;
|
302 | 326 | };
|
303 | 327 |
|
| 328 | + pinctrl_i2c3_gpio: i2c3-gpio-grp { |
| 329 | + fsl,pins = < |
| 330 | + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1 |
| 331 | + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 |
| 332 | + >; |
| 333 | + }; |
| 334 | + |
304 | 335 | pinctrl_pmic_hw300: pmic-hw300-grp {
|
305 | 336 | fsl,pins = <
|
306 | 337 | MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1B0B0
|
|
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