diff --git a/README.md b/README.md index 7c80f83..e907bae 100644 --- a/README.md +++ b/README.md @@ -1 +1,48 @@ -# meta-hailo-soc +# Meta-Hailo-Soc # + + +## Introduction + +This repository contains the Hailo layers for OpenEmbedded. + +- **meta-hailo-bsp** + - This layer contains machines and Board Support Package recipes for the Vision Processor Unit architecture. +- **meta-hailo-bsp-examples** + - This layer contains example recipes for the Vision Processor Unit. +- **meta-hailo-dsp** + - This layer contains recipes for the Digital Processing Unit such as firmware, driver and user space applications. +- **meta-hailo-imaging** + - This layer contains recipes for the Image Signal Processing and the Encoder such as firmware, driver and user space applications. +- **meta-hailo-linux** + - This layer contains recipes for the user space such as system configurations and general applications. +- **meta-hailo-media-library** + - This layer contains recipes for the Media Library API such as LDC API, Encoder OSD API and more. + +## Usage +### Prerequisites + +- Install [kas](https://pypi.org/project/kas/) python package. +### Development +- kas directory contains the yml configurations used to initiate the [Bitbake](https://docs.yoctoproject.org/bitbake/) environment +- To initialize the environment and start image compilation run: + - `kas build kas/hailo15-evb.yml` +- To start working with Bitbake CLI, activate the environment by: + - `source poky/oe-init-build-env` + +## Changelog + +See hailo.ai developer zone - Vision Processor Unit changelog (registration required). + +## Contact + +Contact information and support is available at [**hailo.ai**](https://hailo.ai/contact-us/). + +## About Hailo + +Hailo offers breakthrough AI Inference Accelerators and AI Vision Processors uniquely designed to accelerate embedded deep learning applications on edge devices. + +The Hailo AI Inference Accelerators allow edge devices to run deep learning applications at full scale more efficiently, effectively, and sustainably, with an architecture that takes advantage of the core properties of neural networks. + +The Hailo AI Vision Processors (SoC) combine Hailo's patented and field proven AI inferencing capabilities with advanced computer vision engines, generating premium image quality and advanced video analytics. + +For more information, please visit [**hailo.ai**](https://hailo.ai/). \ No newline at end of file diff --git a/kas/hailo15-evb-security-camera-machine.yml b/kas/hailo15-evb-security-camera-machine.yml new file mode 100644 index 0000000..05cb71a --- /dev/null +++ b/kas/hailo15-evb-security-camera-machine.yml @@ -0,0 +1,3 @@ +header: + version: 11 +machine: hailo15-evb-security-camera diff --git a/kas/hailo15-evb.yml b/kas/hailo15-evb.yml new file mode 100644 index 0000000..508947a --- /dev/null +++ b/kas/hailo15-evb.yml @@ -0,0 +1,7 @@ +build_system: openembedded +header: + version: 11 + includes: + - yocto-base.yml + - hailo15-vpu-base.yml + - hailo15-evb-security-camera-machine.yml diff --git a/kas/hailo15-sbc-machine.yml b/kas/hailo15-sbc-machine.yml new file mode 100644 index 0000000..d7be46d --- /dev/null +++ b/kas/hailo15-sbc-machine.yml @@ -0,0 +1,3 @@ +header: + version: 11 +machine: hailo15-sbc diff --git a/kas/hailo15-sbc.yml b/kas/hailo15-sbc.yml new file mode 100644 index 0000000..a6d7534 --- /dev/null +++ b/kas/hailo15-sbc.yml @@ -0,0 +1,7 @@ +build_system: openembedded +header: + version: 11 + includes: + - yocto-base.yml + - hailo15-vpu-base.yml + - hailo15-sbc-machine.yml diff --git a/kas/hailo15-vpu-base.yml b/kas/hailo15-vpu-base.yml new file mode 100644 index 0000000..e378b4a --- /dev/null +++ b/kas/hailo15-vpu-base.yml @@ -0,0 +1,74 @@ +header: + version: 11 + +local_conf_header: + DSP: | + DSP_COMPILATION_MODE = "release" + DSP_FULL_IMAGING = "false" + gst-debug: | + IMAGE_INSTALL:append = " gst-instruments" + PACKAGECONFIG:append:pn-gstreamer1.0 = " gst-tracer-hooks tracer-hooks coretracers" + gstreamer: | + ADD_GSTREAMER_TO_IMAGE = "true" + hailo-integrated-nnc: | + IMAGE_INSTALL:append = " hailo-integrated-nnc" + hailo15-nnc-fw: | + IMAGE_INSTALL:append = " hailo15-nnc-fw" + imx334_enable: | + MACHINE_FEATURES:append = " imx334" + MACHINE_FEATURES:remove = " imx678" + flags: | + LICENSE_FLAGS_ACCEPTED:append = " commercial" + libgsthailo: | + IMAGE_INSTALL:append = " libgsthailo" + libhailort: | + IMAGE_INSTALL:append = " libhailort" + IMAGE_INSTALL:append = " hailortcli" + media-library: | + IMAGE_INSTALL:append = " libgstmedialib libencoderosd" + opencv: | + CORE_IMAGE_EXTRA_INSTALL:append = " opencv" + tappas: | + IMAGE_INSTALL:append = " \ + libgsthailotools \ + hailo-post-processes \ + tappas-apps \ + tappas-tracers" + thermal_debug_en: | + MACHINE_FEATURES:append = " thermal_debug_en" + tools: | + IMAGE_INSTALL:append = " \ + vim \ + tmux \ + htop \ + gdb \ + perf \ + " + x264: | + IMAGE_INSTALL:append = " x264 gstreamer1.0-plugins-ugly" + PACKAGECONFIG:append:pn-gstreamer1.0-plugins-ugly = " x264" + +repos: + meta-hailo: + url: "https://github.com/hailo-ai/meta-hailo.git" + refspec: kirkstone + layers: + meta-hailo-libhailort: + meta-hailo-vpu: + meta-hailo-tappas: + meta-hailo-dsp: + layers: + meta-hailo-dsp: + meta-hailo-bsp: + layers: + meta-hailo-bsp: + meta-hailo-bsp-examples: + meta-hailo-imaging: + layers: + meta-hailo-imaging: + meta-hailo-linux: + layers: + meta-hailo-linux: + meta-hailo-media-library: + layers: + meta-hailo-media-library: diff --git a/kas/yocto-base.yml b/kas/yocto-base.yml new file mode 100644 index 0000000..d8a7d90 --- /dev/null +++ b/kas/yocto-base.yml @@ -0,0 +1,47 @@ +header: + version: 11 +distro: poky + +target: + - core-image-minimal + - hailo-update-image + +local_conf_header: + qt5: | + IMAGE_INSTALL:append = " qtbase" + +repos: + meta-openembedded: + url: "https://git.openembedded.org/meta-openembedded" + refspec: fcc7d7eae82be4c180f2e8fa3db90a8ab3be07b7 + layers: + meta-filesystems: + meta-networking: + meta-oe: + meta-python: + meta-multimedia: + + poky: + url: "https://git.yoctoproject.org/poky" + refspec: a5ea426b1da472fc8549459fff3c1b8c6e02f4b5 + layers: + meta: + meta-poky: + meta-yocto-bsp: + + meta-swupdate: + url: "https://github.com/sbabic/meta-swupdate.git" + refspec: 58878bb980877f51b607d71c3648bd479d68e2a5 + + meta-arm: + url: "https://git.yoctoproject.org/meta-arm" + refspec: c39bb4ce3b60b73d35c5fb06af012432e70d6b38 + layers: + meta-arm-toolchain: + meta-arm: + + meta-qt5: + url: "https://github.com/meta-qt5/meta-qt5.git" + refspec: kirkstone + layers: + .: diff --git a/meta-hailo-bsp-examples/COPYING.MIT b/meta-hailo-bsp-examples/COPYING.MIT new file mode 100644 index 0000000..cd5290f --- /dev/null +++ b/meta-hailo-bsp-examples/COPYING.MIT @@ -0,0 +1,19 @@ +Copyright (c) 2023 Hailo Technologies Ltd. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY kIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. \ No newline at end of file diff --git a/meta-hailo-bsp-examples/conf/layer.conf b/meta-hailo-bsp-examples/conf/layer.conf new file mode 100644 index 0000000..04a3d41 --- /dev/null +++ b/meta-hailo-bsp-examples/conf/layer.conf @@ -0,0 +1,17 @@ +# We have a conf and classes directory, add to BBPATH +BBPATH .= ":${LAYERDIR}" + +# We have recipes-* directories, add to BBFILES +BBFILES += "${LAYERDIR}/hailo-swupdate/recipes-*/*/*.bb \ + ${LAYERDIR}/hailo-swupdate/recipes-*/*/*.bbappend" + +BBFILE_COLLECTIONS += "meta-hailo-bsp-examples" +BBFILE_PATTERN_meta-hailo-bsp-examples = "^${LAYERDIR}/" +BBFILE_PRIORITY_meta-hailo-bsp-examples = "7" + +LAYERDEPENDS_meta-hailo-bsp-examples = "core meta-hailo-bsp" +LAYERSERIES_COMPAT_meta-hailo-bsp-examples = "kirkstone" + +IMAGE_BOOT_FILES += "swupdate-image-${MACHINE}.ext4.gz" +WKS_FILE_DEPENDS += "swupdate-image" + diff --git a/meta-hailo-bsp-examples/hailo-swupdate/recipes-bsp/hailo-update-image/files/resize_rootfs.sh b/meta-hailo-bsp-examples/hailo-swupdate/recipes-bsp/hailo-update-image/files/resize_rootfs.sh new file mode 100644 index 0000000..85adbf3 --- /dev/null +++ b/meta-hailo-bsp-examples/hailo-swupdate/recipes-bsp/hailo-update-image/files/resize_rootfs.sh @@ -0,0 +1,2 @@ +#!/bin/sh +resize2fs /dev/mmcblk$1p2 2>&1 diff --git a/meta-hailo-bsp-examples/hailo-swupdate/recipes-bsp/hailo-update-image/files/sw-description b/meta-hailo-bsp-examples/hailo-swupdate/recipes-bsp/hailo-update-image/files/sw-description new file mode 100644 index 0000000..93c94ab --- /dev/null +++ b/meta-hailo-bsp-examples/hailo-swupdate/recipes-bsp/hailo-update-image/files/sw-description @@ -0,0 +1,70 @@ +software = +{ + version = "v0.34-build-2023-10-03"; + description = "Firmware update for Hailo SoC"; + hardware-compatibility: [ "1.0"]; + partitions: ( + { + type = "diskpart"; + device = "/dev/mmcblk@@SWUPDATE_MMC_INDEX@@"; + properties: { + labeltype = "gpt"; + partition-1 = [ "size=64M", "start=2048", + "name=boot", "type=BC13C2FF-59E6-4262-A352-B275FD6F7172", + "fstype=fat32"]; + partition-2 = ["start=133120", + "name=rootfs", "type=B921B045-1DF0-41C3-AF44-4C6F280D3FAE", + "fstype=ext4"]; + } + } + ); + images: ( + { + filename = "core-image-minimal-@@MACHINE@@.ext4"; + device = "/dev/mmcblk@@SWUPDATE_MMC_INDEX@@p2"; + }, + { + filename = "hailo15_scu_fw.bin"; + device = "/dev/mtdblock0"; + }, + { + filename = "hailo_ddr_configuration.bin"; + device = "/dev/mtdblock1"; + }, + { + filename = "u-boot-initial-env.bin"; + device = "/dev/mtdblock2"; + }, + { + filename = "u-boot-spl.bin"; + device = "/dev/mtdblock3"; + }, + ); + files: ( + { + filename = "fitImage"; + path = "/fitImage"; + device = "/dev/mmcblk@@SWUPDATE_MMC_INDEX@@p1"; + filesystem = "vfat"; + }, + { + filename = "swupdate-image-@@MACHINE@@.ext4.gz"; + path = "/swupdate-image-@@MACHINE@@.ext4.gz"; + device = "/dev/mmcblk@@SWUPDATE_MMC_INDEX@@p1"; + filesystem = "vfat"; + }, + { + filename = "u-boot-tfa.itb"; + path = "/u-boot-tfa.itb"; + device = "/dev/mmcblk@@SWUPDATE_MMC_INDEX@@p1"; + filesystem = "vfat"; + }, + ); + scripts: ( + { + filename = "resize_rootfs.sh"; + type = "postinstall"; + data = "@@SWUPDATE_MMC_INDEX@@"; + } + ); +} diff --git a/meta-hailo-bsp-examples/hailo-swupdate/recipes-bsp/hailo-update-image/hailo-update-image.bb b/meta-hailo-bsp-examples/hailo-swupdate/recipes-bsp/hailo-update-image/hailo-update-image.bb new file mode 100644 index 0000000..8dd8f67 --- /dev/null +++ b/meta-hailo-bsp-examples/hailo-swupdate/recipes-bsp/hailo-update-image/hailo-update-image.bb @@ -0,0 +1,42 @@ +DESCRIPTION = "Recipe generating SWU image for Hailo SoC" +SECTION = "" + +LICENSE = "GPL-2.0-or-later" +LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/GPL-2.0-or-later;md5=fed54355545ffd980b814dab4a3b312c" + +SRC_URI = " \ + file://sw-description \ + file://resize_rootfs.sh \ + " + +SWUPDATE_MMC_INDEX = "0" +SWUPDATE_MMC_INDEX:hailo15-sbc = "1" + +IMAGE_DEPENDS = "core-image-minimal hailo-ddr-configuration-native scu-fw u-boot-tfa-image" + +# images and files that will be included in the .swu image +SWUPDATE_IMAGES += "core-image-minimal" +SWUPDATE_IMAGES += "swupdate-image" +SWUPDATE_IMAGES += "fitImage" +SWUPDATE_IMAGES += "u-boot-tfa.itb" +SWUPDATE_IMAGES += "u-boot-spl.bin" +SWUPDATE_IMAGES += "u-boot-initial-env.bin" +SWUPDATE_IMAGES += "hailo_ddr_configuration.bin" +SWUPDATE_IMAGES += "hailo15_scu_fw.bin" + +SWUPDATE_IMAGES_FSTYPES[core-image-minimal] = ".ext4" +SWUPDATE_IMAGES_FSTYPES[swupdate-image] = ".ext4.gz" +SWUPDATE_IMAGES_FSTYPES[fitImage] = "" +SWUPDATE_IMAGES_NOAPPEND_MACHINE[fitImage] = "1" +SWUPDATE_IMAGES_FSTYPES[u-boot-tfa.itb] = "" +SWUPDATE_IMAGES_NOAPPEND_MACHINE[u-boot-tfa.itb] = "1" +SWUPDATE_IMAGES_FSTYPES[u-boot-spl.bin] = "" +SWUPDATE_IMAGES_NOAPPEND_MACHINE[u-boot-spl.bin] = "1" +SWUPDATE_IMAGES_FSTYPES[u-boot-initial-env.bin] = "" +SWUPDATE_IMAGES_NOAPPEND_MACHINE[u-boot-initial-env.bin] = "1" +SWUPDATE_IMAGES_FSTYPES[hailo_ddr_configuration.bin] = "" +SWUPDATE_IMAGES_NOAPPEND_MACHINE[hailo_ddr_configuration.bin] = "1" +SWUPDATE_IMAGES_FSTYPES[hailo15_scu_fw.bin] = "" +SWUPDATE_IMAGES_NOAPPEND_MACHINE[hailo15_scu_fw.bin] = "1" + +inherit swupdate \ No newline at end of file diff --git a/meta-hailo-bsp-examples/hailo-swupdate/recipes-bsp/run-swupdate-script/files/COPYING.MIT b/meta-hailo-bsp-examples/hailo-swupdate/recipes-bsp/run-swupdate-script/files/COPYING.MIT new file mode 100644 index 0000000..cd5290f --- /dev/null +++ b/meta-hailo-bsp-examples/hailo-swupdate/recipes-bsp/run-swupdate-script/files/COPYING.MIT @@ -0,0 +1,19 @@ +Copyright (c) 2023 Hailo Technologies Ltd. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY kIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. \ No newline at end of file diff --git a/meta-hailo-bsp-examples/hailo-swupdate/recipes-bsp/run-swupdate-script/files/run_swupdate.sh b/meta-hailo-bsp-examples/hailo-swupdate/recipes-bsp/run-swupdate-script/files/run_swupdate.sh new file mode 100644 index 0000000..dd07935 --- /dev/null +++ b/meta-hailo-bsp-examples/hailo-swupdate/recipes-bsp/run-swupdate-script/files/run_swupdate.sh @@ -0,0 +1,69 @@ +#!/bin/bash + +# Script options +declare -i F_HELP=0 +declare -i F_BATCH=0 + +declare -r LOG_MSG="The system will go to reboot and SW update will executed automatically upon next boot. + You can trace SW update logs by executing 'nc -u -l -k 12345' from your Host. + Estimated SW update duration: 2-3 minutes" + +function usage() +{ + echo "Prepare and trigger system for SW update." + echo "Usage: [OPTIONS]" + echo " -h|--help: show help" + echo " -b|--batch: batch mode" + echo "Note: $LOG_MSG" + + return 0 +} + +function main() +{ + if [ $F_HELP -eq 1 ]; then + usage && return 0 + fi + + while [ $F_BATCH -eq 0 ]; do + read -p "You are about to start system installation, continue? (yes/no): " choice + case "$choice" in + yes|Y) echo "You chose to continue."; break;; + no|N) echo "You chose to stop, aborting installation."; return 0;; + *) echo "Invalid input. Please enter 'yes' or 'no'.";; + esac + done + + echo "SW Update: starting..." + echo "$LOG_MSG" + + # Prepare SW update for next system boot + fw_setenv bootdelay 0 + fw_setenv bootmenu_0 "Autodetect=run boot_swupdate" + echo "Rebooting is about to start..." + reboot + + return 0 +} + +echo "run_swupdate: Start execution" +OPTS_SHORT="hb" +OPTS_LONG="help,batch," + +PARSED_OPTIONS=$(getopt -n "$0" -o $OPTS_SHORT -l $OPTS_LONG -- "$@") +# Bad option flags, abort... +[ $? -ne 0 ] && exit 1 +eval set -- "$PARSED_OPTIONS" + +while true; do + case "$1" in + --help|-h) F_HELP=1; shift 1;; + --batch|-b) F_BATCH=1; shift 1;; + -- ) shift; break;; + *) echo "Argument [$1] not handled"; shift; break;; + esac +done + +main +echo "run_swupdate: End execution" +exit \ No newline at end of file diff --git a/meta-hailo-bsp-examples/hailo-swupdate/recipes-bsp/run-swupdate-script/run-swupdate-script.bb b/meta-hailo-bsp-examples/hailo-swupdate/recipes-bsp/run-swupdate-script/run-swupdate-script.bb new file mode 100644 index 0000000..7551715 --- /dev/null +++ b/meta-hailo-bsp-examples/hailo-swupdate/recipes-bsp/run-swupdate-script/run-swupdate-script.bb @@ -0,0 +1,17 @@ +DESCRIPTION = "Run the swupdate process" +SECTION = "apps" +LICENSE = "MIT" +LIC_FILES_CHKSUM = "file://../COPYING.MIT;md5=aa7321c8e0df442b97243c2e1d64c9ee" +RDEPENDS:${PN} += "bash" +targetdir = "/etc" + +run_swupdate_script_file = "run_swupdate.sh" + +SRC_URI = "file://${run_swupdate_script_file} \ + file://COPYING.MIT" + +do_install() { + install -m 0755 -d ${D}${targetdir} + install -m 0500 ${WORKDIR}/${run_swupdate_script_file} ${D}${targetdir} +} +FILES:${PN} += "${targetdir}/${run_swupdate_script_file}" diff --git a/meta-hailo-bsp-examples/hailo-swupdate/recipes-bsp/u-boot/cfg/hailo15_swupdate_enable.cfg b/meta-hailo-bsp-examples/hailo-swupdate/recipes-bsp/u-boot/cfg/hailo15_swupdate_enable.cfg new file mode 100644 index 0000000..0273739 --- /dev/null +++ b/meta-hailo-bsp-examples/hailo-swupdate/recipes-bsp/u-boot/cfg/hailo15_swupdate_enable.cfg @@ -0,0 +1 @@ +CONFIG_HAILO15_SWUPDATE=y diff --git a/meta-hailo-bsp-examples/hailo-swupdate/recipes-bsp/u-boot/u-boot_%.bbappend b/meta-hailo-bsp-examples/hailo-swupdate/recipes-bsp/u-boot/u-boot_%.bbappend new file mode 100644 index 0000000..ae9c045 --- /dev/null +++ b/meta-hailo-bsp-examples/hailo-swupdate/recipes-bsp/u-boot/u-boot_%.bbappend @@ -0,0 +1,3 @@ +FILESEXTRAPATHS:prepend := "${THISDIR}/:" + +SRC_URI:append = " file://cfg/hailo15_swupdate_enable.cfg" diff --git a/meta-hailo-bsp-examples/hailo-swupdate/recipes-core/images/core-image-minimal.bbappend b/meta-hailo-bsp-examples/hailo-swupdate/recipes-core/images/core-image-minimal.bbappend new file mode 100644 index 0000000..ae725b0 --- /dev/null +++ b/meta-hailo-bsp-examples/hailo-swupdate/recipes-core/images/core-image-minimal.bbappend @@ -0,0 +1 @@ +CORE_IMAGE_EXTRA_INSTALL += " u-boot-env libubootenv-bin run-swupdate-script" \ No newline at end of file diff --git a/meta-hailo-bsp-examples/hailo-swupdate/recipes-core/initscripts-hailo-swupdate/initscripts-hailo-swupdate.bb b/meta-hailo-bsp-examples/hailo-swupdate/recipes-core/initscripts-hailo-swupdate/initscripts-hailo-swupdate.bb new file mode 100644 index 0000000..80de1d5 --- /dev/null +++ b/meta-hailo-bsp-examples/hailo-swupdate/recipes-core/initscripts-hailo-swupdate/initscripts-hailo-swupdate.bb @@ -0,0 +1,39 @@ +SUMMARY = "Hailo SWUpdate startup script" +SECTION = "base" +PR = "r0" +LICENSE = "MIT" +LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302" +RDEPENDS:${PN} += "bash" + +SRC_URI = "file://rcS.swupdate \ + " + +RPROVIDES:${PN} += "virtual/initscripts-hailo-swupdate" + +S = "${WORKDIR}" + +HAILO_UPDATE_TFTP_SERVER_IP = "10.0.0.2" +HAILO_UPDATE_FILENAME = "hailo-update-image-${MACHINE}.swu" + +inherit allarch update-alternatives + +do_install () { + install -d ${D}/${sysconfdir} + echo -n "${HAILO_UPDATE_TFTP_SERVER_IP}" > ${WORKDIR}/server_ip + install -m 0755 ${WORKDIR}/server_ip ${D}${sysconfdir}/server_ip + echo -n "${HAILO_UPDATE_FILENAME}" > ${WORKDIR}/update_filename + install -m 0755 ${WORKDIR}/update_filename ${D}${sysconfdir}/update_filename + install -d ${D}/${sysconfdir}/init.d + install -d ${D}${base_sbindir} + install -m 755 ${S}/rcS.swupdate ${D}${base_sbindir}/init +} + +ALTERNATIVE_PRIORITY = "300" +ALTERNATIVE:${PN} = "init" +ALTERNATIVE_LINK_NAME[init] = "${base_sbindir}/init" +ALTERNATIVE_PRIORITY[init] = "60" + +PACKAGES = "${PN}" +FILES:${PN} = "/" + +CONFFILES:${PN} = "" diff --git a/meta-hailo-bsp-examples/hailo-swupdate/recipes-core/initscripts-hailo-swupdate/initscripts-hailo-swupdate/rcS.swupdate b/meta-hailo-bsp-examples/hailo-swupdate/recipes-core/initscripts-hailo-swupdate/initscripts-hailo-swupdate/rcS.swupdate new file mode 100755 index 0000000..c3ab4b0 --- /dev/null +++ b/meta-hailo-bsp-examples/hailo-swupdate/recipes-core/initscripts-hailo-swupdate/initscripts-hailo-swupdate/rcS.swupdate @@ -0,0 +1,52 @@ +#!/bin/bash + +# stop upon error +set -e + +declare SERVER_IP=$(cat /etc/server_ip) +declare SERVER_PORT="12345" +PATH=/sbin:/bin:/usr/sbin:/usr/bin + +function run_swupdate() { + local UPDATE_FILE=$(cat /etc/update_filename) + + cd /tmp + echo "Downloading ${UPDATE_FILE} from ${SERVER_IP}:${SERVER_PORT} via TFTP..." + tftp -g -r "${UPDATE_FILE}" "${SERVER_IP}" + + echo "Running: swupdate -i ${UPDATE_FILE} -v" + swupdate -i "${UPDATE_FILE}" -v + echo "SWUpdate finished" + + echo "Rebooting..." + reboot -f + + return 0 +} + +function main() { + umask 022 + mount -t proc proc /proc + mount -t sysfs sysfs /sys + mount -t tmpfs tmpfs /tmp + # disable kernel print to serial + echo 0 >/proc/sys/kernel/printk + + ln -s /tmp /var/volatile + + /etc/init.d/networking start + + echo "Waiting for networking service is up..." + + # Waiting for networking sericve is up + sleep 10 + + # The goal is to dump SW update output to both stdout and to remote 'nc' listener. + run_swupdate |& tee /proc/self/fd/2 | nc -u "${SERVER_IP}" "${SERVER_PORT}" + + return 0 +} + +main + +exit 0 diff --git a/meta-hailo-bsp-examples/hailo-swupdate/recipes-extended/images/swupdate-image.bbappend b/meta-hailo-bsp-examples/hailo-swupdate/recipes-extended/images/swupdate-image.bbappend new file mode 100644 index 0000000..6957ad1 --- /dev/null +++ b/meta-hailo-bsp-examples/hailo-swupdate/recipes-extended/images/swupdate-image.bbappend @@ -0,0 +1,15 @@ +IMAGE_INSTALL = "\ + base-files \ + base-passwd \ + busybox \ + mtd-utils \ + mtd-utils-ubifs \ + libconfig \ + swupdate \ + util-linux-sfdisk \ + e2fsprogs-resize2fs \ + u-boot-env \ + init-ifupdown \ + virtual/initscripts-hailo-swupdate \ +" +IMAGE_FSTYPES = "ext4.gz" \ No newline at end of file diff --git a/meta-hailo-bsp-examples/hailo-swupdate/recipes-support/swupdate/0001-Add-FAT32-filesystem-support.patch b/meta-hailo-bsp-examples/hailo-swupdate/recipes-support/swupdate/0001-Add-FAT32-filesystem-support.patch new file mode 100644 index 0000000..46994a4 --- /dev/null +++ b/meta-hailo-bsp-examples/hailo-swupdate/recipes-support/swupdate/0001-Add-FAT32-filesystem-support.patch @@ -0,0 +1,54 @@ +From d698a375b8cb9af466ff4477f1a7d9c1198a772b Mon Sep 17 00:00:00 2001 +From: Yaron Micher +Date: Sun, 28 May 2023 19:46:23 +0300 +Subject: [PATCH] Add FAT32 filesystem support + +--- + fs/diskformat.c | 1 + + fs/fat_fs.c | 12 ++++++++++-- + 2 files changed, 11 insertions(+), 2 deletions(-) + +diff --git a/fs/diskformat.c b/fs/diskformat.c +index 8d58fc3..0a72105 100644 +--- a/fs/diskformat.c ++++ b/fs/diskformat.c +@@ -27,6 +27,7 @@ struct supported_filesystems { + static struct supported_filesystems fs[] = { + #if defined(CONFIG_FAT_FILESYSTEM) + {"vfat", fat_mkfs}, ++ {"fat32", fat_mkfs}, + #endif + #if defined(CONFIG_EXT_FILESYSTEM) + {"ext2", ext_mkfs_short}, +diff --git a/fs/fat_fs.c b/fs/fat_fs.c +index 93e3489..5473404 100644 +--- a/fs/fat_fs.c ++++ b/fs/fat_fs.c +@@ -15,8 +15,10 @@ + #include "ff.h" + + +-int fat_mkfs(const char *device_name, const char __attribute__ ((__unused__)) *fstype) ++int fat_mkfs(const char *device_name, const char *fstype) + { ++ int fs_fmt; ++ + if (fatfs_init(device_name)) + return -1; + +@@ -27,8 +29,14 @@ int fat_mkfs(const char *device_name, const char __attribute__ ((__unused__)) *f + return -ENOMEM; + } + ++ if (!strcmp(fstype, "fat32")) { ++ fs_fmt = FM_FAT32; ++ } else { ++ fs_fmt = FM_ANY; ++ } ++ + MKFS_PARM mkfs_parm = { +- .fmt = FM_ANY | FM_SFD, ++ .fmt = fs_fmt | FM_SFD, + .au_size = 0, + .align = 0, + .n_fat = 0, diff --git a/meta-hailo-bsp-examples/hailo-swupdate/recipes-support/swupdate/cfg/fragment.cfg b/meta-hailo-bsp-examples/hailo-swupdate/recipes-support/swupdate/cfg/fragment.cfg new file mode 100644 index 0000000..2221659 --- /dev/null +++ b/meta-hailo-bsp-examples/hailo-swupdate/recipes-support/swupdate/cfg/fragment.cfg @@ -0,0 +1,7 @@ +CONFIG_DISKFORMAT=y +CONFIG_DISKFORMAT_HANDLER=y +CONFIG_FAT_FILESYSTEM=y +CONFIG_EXT_FILESYSTEM=y +CONFIG_DISKPART=y +CONFIG_DISKPART_FORMAT=y +# CONFIG_HW_COMPATIBILITY is not set diff --git a/meta-hailo-bsp-examples/hailo-swupdate/recipes-support/swupdate/swupdate_%.bbappend b/meta-hailo-bsp-examples/hailo-swupdate/recipes-support/swupdate/swupdate_%.bbappend new file mode 100644 index 0000000..28e1dab --- /dev/null +++ b/meta-hailo-bsp-examples/hailo-swupdate/recipes-support/swupdate/swupdate_%.bbappend @@ -0,0 +1,3 @@ +FILESEXTRAPATHS:prepend := "${THISDIR}/:" +SRC_URI += " file://cfg/fragment.cfg" +SRC_URI += " file://0001-Add-FAT32-filesystem-support.patch" diff --git a/meta-hailo-bsp/README.md b/meta-hailo-bsp/README.md new file mode 100644 index 0000000..52ae6f8 --- /dev/null +++ b/meta-hailo-bsp/README.md @@ -0,0 +1,12 @@ +meta-hailo-bsp +=========== +Yocto BSP layer for Hailo boards + +## Description +This is the general hardware specific BSP overlay for Hailo boards. + +The layer provides: + +* Kernel support +* U-Boot support +* Partitioned image for SD-Card (using `OpenEmbedded Image Creator`) diff --git a/meta-hailo-bsp/classes/hailo-cc312-sign.bbclass b/meta-hailo-bsp/classes/hailo-cc312-sign.bbclass new file mode 100644 index 0000000..2a29854 --- /dev/null +++ b/meta-hailo-bsp/classes/hailo-cc312-sign.bbclass @@ -0,0 +1,41 @@ +# This class is used for signing binary files for authentication using cryptocell-312 +# by Hailo-15 SCU. +# +# Recipes using this class should declare the following variables: +# - HAILO_CC312_SIGNED_BINARY: path to the output signed binary +# - HAILO_CC312_UNSIGNED_BINARY: path to the binary to sign +# +# a file ${HAILO_CC312_UNSIGNED_BINARY}.padded will be created +# + +DEPENDS += "cryptocell-312-runtime-native" +DEPENDS += "hailo-secureboot-assets" + +do_hailo_cc312_sign[depends] += " hailo-secureboot-assets:do_deploy" + +CERT_KEYPAIR ?= "${DEPLOY_DIR_IMAGE}/customer.key" +HAILO_CC312_PADDED_UNSIGNED_BINARY = "${HAILO_CC312_UNSIGNED_BINARY}.padded" + +do_hailo_cc312_sign() { + # pad so the signed content is aligned to 4 byte + dd if=${HAILO_CC312_UNSIGNED_BINARY} of=${HAILO_CC312_PADDED_UNSIGNED_BINARY} ibs=4 conv=sync + unsigned_binary_size=$(printf "0x%x" `stat -c "%s" "${HAILO_CC312_PADDED_UNSIGNED_BINARY}"`) + + # <32b mem load addr> <32b flash store addr> <32b image max size> + cat < ${B}/images_table +${HAILO_CC312_PADDED_UNSIGNED_BINARY} 0xffffffff 0 ${unsigned_binary_size} 0 +EOF + + cat < ${B}/certificate_config +[CNT-CFG] +load-verify-scheme=1 +crypto-type=0 +aes-ce-id=0 +nvcounter-val=0 +cert-keypair=${CERT_KEYPAIR} +images-table=${B}/images_table +cert-pkg=${B}/certificate.bin +EOF + cert_sb_content_util.py ${B}/certificate_config -cfg_file ${STAGING_ETCDIR_NATIVE}/cc_proj.cfg + cat ${B}/certificate.bin ${HAILO_CC312_PADDED_UNSIGNED_BINARY} > ${HAILO_CC312_SIGNED_BINARY} +} diff --git a/meta-hailo-bsp/conf/layer.conf b/meta-hailo-bsp/conf/layer.conf new file mode 100644 index 0000000..e59bca8 --- /dev/null +++ b/meta-hailo-bsp/conf/layer.conf @@ -0,0 +1,22 @@ +# We have a conf and classes directory, add to BBPATH +BBPATH .= ":${LAYERDIR}" + +# We have recipes-* directories, add to BBFILES +BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \ + ${LAYERDIR}/recipes-*/*/*.bbappend" + +BBFILE_COLLECTIONS += "meta-hailo-bsp" +BBFILE_PATTERN_meta-hailo-bsp = "^${LAYERDIR}/" +BBFILE_PRIORITY_meta-hailo-bsp = "6" + +LAYERDEPENDS_meta-hailo-bsp = " \ + core \ + meta-arm \ +" + +LAYERSERIES_COMPAT_meta-hailo-bsp = "kirkstone" + +IMAGE_ROOTFS_EXTRA_SPACE = "262144" + +IMAGE_INSTALL:append = " recovery-fw scu-fw" + diff --git a/meta-hailo-bsp/conf/machine/hailo15-base.inc b/meta-hailo-bsp/conf/machine/hailo15-base.inc new file mode 100644 index 0000000..3a47f89 --- /dev/null +++ b/meta-hailo-bsp/conf/machine/hailo15-base.inc @@ -0,0 +1,56 @@ +# Configuration for Hailo15 + +#@TYPE: Machine +#@NAME: Hailo15 machine +#@DESCRIPTION: Machine configuration for Hailo15 + +require conf/machine/include/arm/arch-armv8a.inc + +MACHINEOVERRIDES =. "hailo15:" + +PREFERRED_PROVIDER_virtual/kernel_forcevariable = "linux-yocto-hailo" +PREFERRED_PROVIDER_virtual/kernel = "linux-yocto-hailo" + +TARGET_ARCH = "aarch64" +TUNE_FEATURES = "aarch64" + +IMAGE_FSTYPES = "wic ext4" +WKS_FILE = "sd.wks" + +IMAGE_BOOT_FILES += "fitImage u-boot-tfa.itb" + +KERNEL_IMAGETYPE = "fitImage" +KERNEL_CLASSES += "kernel-fitimage" +KERNEL_ALT_IMAGETYPE = "vmlinux" + +WKS_FILE_DEPENDS += " linux-yocto-hailo u-boot-tfa-image" +EXTRA_IMAGEDEPENDS += " u-boot-tfa-image" +EXTRA_IMAGEDEPENDS += " hailo-ddr-configuration-native" +UBOOT_ELF = "u-boot" + +# This is the kernel load address and entry point - which are the same address in our case. +# u-boot uncompresses and copies the kernel from the fitImage (that it loads to DRAM) +# into this address. Since u-boot SPL is copied by the SCU to 0x80000000 (DRAM start), +# and the secondary cores (cores 1-3) are running from u-boot SPL's load address, +# we can't use the beginning of the DRAM as the kernel load address. +# We load it to offset 2MiB in the DRAM since the u-boot (SPL) image is located in QSPI flash +# and is smaller than that. +UBOOT_LOADADDRESS="0x80200000" +UBOOT_ENTRYPOINT="0x80200000" + +SERIAL_CONSOLES = "115200;ttyS1" + +hostname:pn-base-files = "hailo15" + +MACHINE_FEATURES_BACKFILL_CONSIDERED += "rtc " + +UBOOT_SIGN_KEYDIR = "${DEPLOY_DIR_IMAGE}" +UBOOT_SIGN_KEYNAME = "customer" +UBOOT_MKIMAGE_DTCOPTS = "-I dts -O dtb -p 2000" +UBOOT_SIGN_ENABLE = "1" +FIT_SIGN_ALG = "rsa3072" +UBOOT_FIT_SIGN_ALG = "rsa3072" +FIT_SIGN_NUMBITS = "3072" +UBOOT_FIT_SIGN_NUMBITS = "3072" +SPL_SIGN_KEYDIR = "${DEPLOY_DIR_IMAGE}" +SPL_SIGN_KEYNAME = "customer" diff --git a/meta-hailo-bsp/conf/machine/hailo15-evb-2-camera-vpu.conf b/meta-hailo-bsp/conf/machine/hailo15-evb-2-camera-vpu.conf new file mode 100644 index 0000000..38dfc2e --- /dev/null +++ b/meta-hailo-bsp/conf/machine/hailo15-evb-2-camera-vpu.conf @@ -0,0 +1,3 @@ +require hailo15-evb.inc + +UBOOT_MACHINE = "hailo15_evb_2_camera_vpu_defconfig" diff --git a/meta-hailo-bsp/conf/machine/hailo15-evb-security-camera.conf b/meta-hailo-bsp/conf/machine/hailo15-evb-security-camera.conf new file mode 100644 index 0000000..ed3a216 --- /dev/null +++ b/meta-hailo-bsp/conf/machine/hailo15-evb-security-camera.conf @@ -0,0 +1,3 @@ +require hailo15-evb.inc + +UBOOT_MACHINE = "hailo15_evb_security_camera_defconfig" diff --git a/meta-hailo-bsp/conf/machine/hailo15-evb.inc b/meta-hailo-bsp/conf/machine/hailo15-evb.inc new file mode 100644 index 0000000..a1a31f0 --- /dev/null +++ b/meta-hailo-bsp/conf/machine/hailo15-evb.inc @@ -0,0 +1,3 @@ +require hailo15-base.inc + +MACHINEOVERRIDES =. "hailo15-evb:" diff --git a/meta-hailo-bsp/conf/machine/hailo15-ginger-soc.conf b/meta-hailo-bsp/conf/machine/hailo15-ginger-soc.conf new file mode 100644 index 0000000..825f085 --- /dev/null +++ b/meta-hailo-bsp/conf/machine/hailo15-ginger-soc.conf @@ -0,0 +1,4 @@ +require hailo15-base.inc + +SDIO0_POSTFIX = "${@bb.utils.contains('MACHINE_FEATURES', 'sdio0', '_sdio0', '', d)}" +UBOOT_MACHINE = "hailo15_ginger_soc${SDIO0_POSTFIX}_defconfig" diff --git a/meta-hailo-bsp/conf/machine/hailo15-lavender-dsp.conf b/meta-hailo-bsp/conf/machine/hailo15-lavender-dsp.conf new file mode 100644 index 0000000..f418ecb --- /dev/null +++ b/meta-hailo-bsp/conf/machine/hailo15-lavender-dsp.conf @@ -0,0 +1,3 @@ +require hailo15-base.inc + +UBOOT_MACHINE = "hailo15_lavender_dsp_defconfig" diff --git a/meta-hailo-bsp/conf/machine/hailo15-lavender.conf b/meta-hailo-bsp/conf/machine/hailo15-lavender.conf new file mode 100644 index 0000000..5bd0e69 --- /dev/null +++ b/meta-hailo-bsp/conf/machine/hailo15-lavender.conf @@ -0,0 +1,3 @@ +require hailo15-base.inc + +UBOOT_MACHINE = "hailo15_lavender_defconfig" diff --git a/meta-hailo-bsp/conf/machine/hailo15-sbc.conf b/meta-hailo-bsp/conf/machine/hailo15-sbc.conf new file mode 100644 index 0000000..d798522 --- /dev/null +++ b/meta-hailo-bsp/conf/machine/hailo15-sbc.conf @@ -0,0 +1,3 @@ +require hailo15-base.inc + +UBOOT_MACHINE = "hailo15_sbc_defconfig" diff --git a/meta-hailo-bsp/conf/machine/hailo15-veloce.conf b/meta-hailo-bsp/conf/machine/hailo15-veloce.conf new file mode 100644 index 0000000..a3f1114 --- /dev/null +++ b/meta-hailo-bsp/conf/machine/hailo15-veloce.conf @@ -0,0 +1,8 @@ +require hailo15-base.inc + +UBOOT_MACHINE = "hailo15_veloce_defconfig" +FIT_KERNEL_COMP_ALG = "none" +FIT_KERNEL_COMP_ALG_EXTENSION = "" + +# disable SSH in veloce since it causes key generation at boot time which slows down the boot +EXTRA_IMAGE_FEATURES:remove = "${SSH_SERVER_FEATURES}" diff --git a/meta-hailo-bsp/conf/machine/hailo15-vp.conf b/meta-hailo-bsp/conf/machine/hailo15-vp.conf new file mode 100644 index 0000000..3e56899 --- /dev/null +++ b/meta-hailo-bsp/conf/machine/hailo15-vp.conf @@ -0,0 +1,3 @@ +require hailo15-base.inc + +UBOOT_MACHINE = "hailo15_vp_defconfig" diff --git a/meta-hailo-bsp/hailo15_board_tools/CHANGELOG.md b/meta-hailo-bsp/hailo15_board_tools/CHANGELOG.md new file mode 100644 index 0000000..ac9f763 --- /dev/null +++ b/meta-hailo-bsp/hailo15_board_tools/CHANGELOG.md @@ -0,0 +1,2 @@ +# 1.1.0 +Hailo15 Board tools \ No newline at end of file diff --git a/meta-hailo-bsp/hailo15_board_tools/LICENSE b/meta-hailo-bsp/hailo15_board_tools/LICENSE new file mode 100644 index 0000000..aeed83c --- /dev/null +++ b/meta-hailo-bsp/hailo15_board_tools/LICENSE @@ -0,0 +1,21 @@ +The MIT License (MIT) + +Copyright (c) 2020-2022 Hailo Technologies Ltd. +All rights reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal in +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +the Software, and to permit persons to whom the Software is furnished to do so, +subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. \ No newline at end of file diff --git a/meta-hailo-bsp/hailo15_board_tools/hailo15_board_tools/__init__.py b/meta-hailo-bsp/hailo15_board_tools/hailo15_board_tools/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/meta-hailo-bsp/hailo15_board_tools/hailo15_board_tools/flash_programmers/__init__.py b/meta-hailo-bsp/hailo15_board_tools/hailo15_board_tools/flash_programmers/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/meta-hailo-bsp/hailo15_board_tools/hailo15_board_tools/flash_programmers/flash_programmer.py b/meta-hailo-bsp/hailo15_board_tools/hailo15_board_tools/flash_programmers/flash_programmer.py new file mode 100644 index 0000000..1de7c52 --- /dev/null +++ b/meta-hailo-bsp/hailo15_board_tools/hailo15_board_tools/flash_programmers/flash_programmer.py @@ -0,0 +1,30 @@ +from abc import ABC, abstractmethod +import logging +import sys + +logger = logging.getLogger("BURN_FLASH_HAILO15_LOGGER") +logger.setLevel(logging.INFO) +logger.addHandler(logging.StreamHandler(sys.stdout)) + + +class FlashProgrammer(ABC): + + @abstractmethod + def write(self, address, buffer_data): + pass + + @abstractmethod + def read(self, address, length): + pass + + @abstractmethod + def erase(self, address, length): + pass + + @abstractmethod + def identify(self): + pass + + @abstractmethod + def open_interface(self): + pass diff --git a/meta-hailo-bsp/hailo15_board_tools/hailo15_board_tools/flash_programmers/ftdi_flash_programmer.py b/meta-hailo-bsp/hailo15_board_tools/hailo15_board_tools/flash_programmers/ftdi_flash_programmer.py new file mode 100644 index 0000000..799086d --- /dev/null +++ b/meta-hailo-bsp/hailo15_board_tools/hailo15_board_tools/flash_programmers/ftdi_flash_programmer.py @@ -0,0 +1,53 @@ +from spiflash import serialflash +import math + +from hailo15_board_tools.flash_programmers.flash_programmer import FlashProgrammer, logger + +# Override with our device values +serialflash.N25QFlashDevice.DEVICES.clear() +serialflash.N25QFlashDevice.DEVICES = ({0xBA: 'Micron N25Q', 0xBB: 'Micron MT25'}) +serialflash.N25QFlashDevice.SIZES.clear() +serialflash.N25QFlashDevice.SIZES = {0x15: 1 << 21, 0x16: 1 << 22, 0x17: 1 << 23, 0x18: 1 << 24, 0x21: 1 << 30} + +serialflash.W25xFlashDevice.DEVICES.clear() +serialflash.W25xFlashDevice.DEVICES = {0x30: 'Winbond W25X', 0x40: 'Winbond W25Q', 0x60: 'Winbond W25Q'} +serialflash.W25xFlashDevice.SIZES.clear() +serialflash.W25xFlashDevice.SIZES = {0x11: 1 << 17, 0x12: 1 << 18, 0x13: 1 << 19, 0x14: 1 << 20, + 0x15: 2 << 20, 0x17: 8 << 20, 0x18: 16 << 20, 0x16: 32 << 20, 0x19: 256 << 20} + +serialflash.Mx25lFlashDevice.DEVICES.clear() +serialflash.Mx25lFlashDevice.DEVICES = {0x9E: 'Macronix MX25D', + 0x26: 'Macronix MX25E', + 0x20: 'Macronix MX25E06', + 0x25: 'Macronix MX25U'} +serialflash.Mx25lFlashDevice.SIZES.clear() +serialflash.Mx25lFlashDevice.SIZES = {0x15: 2 << 20, 0x16: 4 << 20, 0x17: 8 << 20, 0x18: 16 << 20, 0x36: 32 << 20} + + +class FtdiFlashProgrammer(FlashProgrammer): + + FTDI_INTERFACE = 2 + FTDI_URL = f'ftdi://ftdi:4232h/{FTDI_INTERFACE}' + + def __init__(self, url=FTDI_URL, freq=30E6): + self.url = url + self.freq = freq + + def open_interface(self): + self._flash_device = serialflash.SerialFlashManager().get_flash_device(url=self.url, cs=0, freq=self.freq) + self.identify() + + def write(self, address, buffer_data): + return self._flash_device.write(address, buffer_data) + + def read(self, address, length): + return self._flash_device.read(address, length) + + def erase(self, address, length): + subsector_size = self._flash_device.get_size('subsector') + block_amount = math.ceil(length / subsector_size) + section_size = block_amount * subsector_size + return self._flash_device.erase(address, section_size) + + def identify(self): + logger.info(f'flash detected "{self._flash_device}"') diff --git a/meta-hailo-bsp/hailo15_board_tools/hailo15_board_tools/flash_programmers/uart_recovery_manager.py b/meta-hailo-bsp/hailo15_board_tools/hailo15_board_tools/flash_programmers/uart_recovery_manager.py new file mode 100644 index 0000000..6493016 --- /dev/null +++ b/meta-hailo-bsp/hailo15_board_tools/hailo15_board_tools/flash_programmers/uart_recovery_manager.py @@ -0,0 +1,138 @@ +import serial + +from hailo15_board_tools.flash_programmers.flash_programmer import FlashProgrammer, logger + +FIRMWARE_VERSION_MAJOR = 1 +FIRMWARE_VERSION_MINOR = 3 + + +class UartRecoveryCommunicator: + + FW_VERSION_OPCODE = 0x0 + JEDEC_OPCODE = 0x1 + WRITE_OPCODE = 0x2 + READ_OPCODE = 0x3 + ERASE_SECTOR_OPCODE = 0x4 + JUMP_BOOTROM_FLASH_OPCODE = 0x5 + ERASE_CHIP_OPCODE = 0x6 + UART_BAUDRATE = 115200 + UART_TIMEOUT = 2 # seconds + JEDEC_ID_LENGTH = 4 + ERASE_SECTOR_END_ACK = 0x55 + ERASE_CHIP_END_ACK = 0x56 + + def __init__(self, serial_device_name): + self.serial_device_name = serial_device_name + + def open_serial(self): + self._serial = serial.Serial(self.serial_device_name, self.UART_BAUDRATE, timeout=self.UART_TIMEOUT) + + def _serial_read(self, size): + buff = self._serial.read(size) + if len(buff) == 0: + raise Exception("Got serial read timeout") + return buff + + def get_flash_programmer(self): + return UartRecoveryFlashProgrammer(self) + + def get_fw_version(self): + opcode = self.FW_VERSION_OPCODE + opcode_bin = opcode.to_bytes(1, byteorder='little') + self._serial.write(opcode_bin) + firmware_major = int.from_bytes(self._serial_read(4), "big") + firmware_minor = int.from_bytes(self._serial_read(4), "big") + return firmware_major, firmware_minor + + def get_jedec_id(self): + opcode = self.JEDEC_OPCODE + opcode_bin = opcode.to_bytes(1, byteorder='little') + self._serial.write(opcode_bin) + return self._serial_read(self.JEDEC_ID_LENGTH).hex() + + def write(self, address, buffer_data): + opcode = self.WRITE_OPCODE + opcode_bin = opcode.to_bytes(1, byteorder='little') + address_bin = address.to_bytes(4, byteorder='little') + length_bin = (len(buffer_data)).to_bytes(4, byteorder='little') + self._serial.write(opcode_bin) + self._serial.write(address_bin) + self._serial.write(length_bin) + self._serial.write(bytearray(buffer_data)) + + def erase(self, address): + opcode = self.ERASE_SECTOR_OPCODE + opcode_bin = opcode.to_bytes(1, byteorder='little') + address_bin = address.to_bytes(4, byteorder='little') + self._serial.write(opcode_bin) + self._serial.write(address_bin) + end_ack = self._serial_read(1) + assert end_ack == self.ERASE_SECTOR_END_ACK.to_bytes(1, byteorder='little'), "Sector erase didn't succeeded" + + def read(self, address, length): + opcode = self.READ_OPCODE + opcode_bin = opcode.to_bytes(1, byteorder='little') + address_bin = address.to_bytes(4, byteorder='little') + length_bin = length.to_bytes(4, byteorder='little') + self._serial.write(opcode_bin) + self._serial.write(address_bin) + self._serial.write(length_bin) + read_data_buffer = self._serial_read(length) + return bytearray(read_data_buffer) + + def jump_bootrom_flash(self): + opcode = self.JUMP_BOOTROM_FLASH_OPCODE + opcode_bin = opcode.to_bytes(1, byteorder='little') + self._serial.write(opcode_bin) + + +class UartRecoveryFlashProgrammer(FlashProgrammer): + QSPI_SECTOR_SIZE = (4*1024) + + def __init__(self, comm: UartRecoveryCommunicator): + self.comm = comm + + def identify(self): + try: + firmware_major, firmware_minor = self.comm.get_fw_version() + except Exception: + raise Exception("could not connect to the recovery agent please \ + try the following:\n \ + 1. Make sure bootstrap set to boot from uart.\n \ + 2. The USB cable connected correctly\n \ + 3. Reset the target and try again") + + if (firmware_major != FIRMWARE_VERSION_MAJOR) or (firmware_minor != FIRMWARE_VERSION_MINOR): + raise Exception("Incompatibility between the FW version and the script version") + + logger.info( + f'UART recovery load script version: {firmware_major}.{firmware_minor}' + ) + + jedec_id = self.comm.get_jedec_id() + jedec_id = ''.join('{:02x}'.format(x) for x in bytearray.fromhex(jedec_id)[::-1]) + + logger.info( + f'flash detected, flash jedec_id: 0x{jedec_id}' + ) + + def write(self, address, buffer_data): + self.comm.write(address, buffer_data) + + def erase(self, address, length): + for sector_offset in range(0, length, self.QSPI_SECTOR_SIZE): + self.comm.erase(address + sector_offset) + + def read(self, address, length): + read_data_buffer = bytearray() + for read_offset in range(0, length, self.QSPI_SECTOR_SIZE): + if read_offset + self.QSPI_SECTOR_SIZE > length: + bytes_to_read = length - read_offset + else: + bytes_to_read = self.QSPI_SECTOR_SIZE + read_data_buffer += self.comm.read(address + read_offset, bytes_to_read) + return read_data_buffer + + def open_interface(self): + self.comm.open_serial() + self.identify() diff --git a/meta-hailo-bsp/hailo15_board_tools/hailo15_board_tools/hailo15_spi_flash_program.py b/meta-hailo-bsp/hailo15_board_tools/hailo15_board_tools/hailo15_spi_flash_program.py new file mode 100644 index 0000000..642fc93 --- /dev/null +++ b/meta-hailo-bsp/hailo15_board_tools/hailo15_board_tools/hailo15_spi_flash_program.py @@ -0,0 +1,207 @@ +#!/usr/bin/env python + +""" +The purpose of this application is to program the Hailo-15 board's flash with the relevant software and configurations. +""" + +import argparse +import hashlib +import os +import time +import subprocess +import tempfile +from contextlib import contextmanager + +from hailo15_board_tools.flash_programmers.flash_programmer import FlashProgrammer, logger +from hailo15_board_tools.flash_programmers.uart_recovery_manager import UartRecoveryCommunicator +from hailo15_board_tools.flash_programmers.ftdi_flash_programmer import FtdiFlashProgrammer + + +class FlashDataValidationException(Exception): + pass + + +class Hailo15FlashManager(): + + def __init__(self, programmer: FlashProgrammer): + self.programmer = programmer + + FLASH_OFFSET_SCU_FW = 0x0 + FLASH_SECTION_SIZE_SCU_FW = 0x40000 + FLASH_OFFSET_DDR_CONFIGURATION = 0x40000 + FLASH_SECTION_SIZE_DDR_CONFIGURATION = 0xF000 + FLASH_OFFSET_CUSTOMER_CERTIFICATE = 0x4F000 + FLASH_SECTION_SIZE_CUSTOMER_CERTIFICATE = 0x1000 + FLASH_OFFSET_SPL_UBOOT_BIN = 0x54000 + FLASH_SECTION_SIZE_UBOOT_SPL = 0x2C000 + FLASH_OFFSET_UBOOT_ENV = 0x50000 + FLASH_SECTION_SIZE_UBOOT_ENV = 0x4000 + + def _program_file(self, file_path, offset, section_size, validate, add_md5=False): + """ This function programs a given file to the SPI flash + + Args: + file_path (str): The file path to program to the SPI flash + offset (hex): The start offset in the SPI flash + section_size (hex): The section size of the given file + validate (bool, optional): Whether to validate content has been programmed successfully . Defaults to True. + add_md5 (bool, optional): Whether to add md5 to the end of the file. Defaults to False. + + Raises: + FlashDataValidationException: raise if validation failed or the file is larger than the section size + SerialFlashValueError: raise if trying to write in address larger than flash (by write function) + """ + data_to_write = None + with open(file_path, 'rb') as input_file: + data_to_write = input_file.read() + + if add_md5: + md5 = hashlib.md5() + md5.update(data_to_write) + data_to_write = b''.join([data_to_write, md5.digest()]) + + if section_size < len(data_to_write): + raise FlashDataValidationException("Provided file is larger than expected") + + self.programmer.write(offset, data_to_write) + + if validate: + read_data = self.programmer.read(offset, len(data_to_write)) + if read_data != data_to_write: + raise FlashDataValidationException("Flash was not programmed successfully") + else: + logger.info('Flash program validatation passed successfully') + + def erase_and_program_flash(self, file_path, offset, reserved_section_size, validate, add_md5=False): + raw_section_size = os.path.getsize(file_path) + if add_md5: + raw_section_size += hashlib.md5().digest_size + + if reserved_section_size < raw_section_size: + raise FlashDataValidationException("Provided file is larger than expected") + + logger.info(f"Erasing flash from {hex(offset)}B to {hex(offset + raw_section_size)}B...") + # Erase function validates that offset and section size are inbounds of flash device + self.programmer.erase(offset, raw_section_size) + logger.info("Erased successfully") + time.sleep(1) + self._program_file(file_path, offset, raw_section_size, validate=validate, add_md5=add_md5) + logger.info(f"Provided file was successfully {file_path} programmed") + + def erase_uboot_env_from_flash(self): + logger.info("Erasing U-Boot env...") + # Erase function validates that offset and section size are inbounds of flash device + self.programmer.erase(self.FLASH_OFFSET_UBOOT_ENV, self.FLASH_SECTION_SIZE_UBOOT_ENV) + time.sleep(1) + + def erase_and_program_scu_fw(self, file_path, validate=1): + logger.info(f"Programming SCU firmware file: {file_path}...") + self.erase_and_program_flash(file_path, + offset=self.FLASH_OFFSET_SCU_FW, + reserved_section_size=self.FLASH_SECTION_SIZE_SCU_FW, validate=validate) + + def erase_and_program_uboot_spl(self, file_path, validate=1): + self.erase_uboot_env_from_flash() + logger.info(f"Programming U-Boot SPL file: {file_path}...") + self.erase_and_program_flash(file_path, + offset=self.FLASH_OFFSET_SPL_UBOOT_BIN, + reserved_section_size=self.FLASH_SECTION_SIZE_UBOOT_SPL, validate=validate) + + @contextmanager + def create_uboot_env(self, env_path, env_size): + env_image_path = tempfile.NamedTemporaryFile(suffix=".bin") + try: + subprocess.run(["mkenvimage", "-s", str(env_size), "-o", env_image_path.name, env_path]) + yield env_image_path + finally: + env_image_path.close() + + def erase_and_program_uboot_env(self, file_path, validate=1): + logger.info(f"Programming U-Boot env file: {file_path}...") + with self.create_uboot_env(file_path, self.FLASH_SECTION_SIZE_UBOOT_ENV) as env_image_path: + logger.info(f"Programming U-Boot env file: {env_image_path.name}...") + self.erase_and_program_flash(env_image_path.name, + offset=self.FLASH_OFFSET_UBOOT_ENV, + reserved_section_size=self.FLASH_SECTION_SIZE_UBOOT_ENV, validate=validate) + + def erase_and_program_ddr_configuration(self, file_path, validate=1): + logger.info(f"Programming DDR configuration file: {file_path}...") + self.erase_and_program_flash(file_path, + offset=self.FLASH_OFFSET_DDR_CONFIGURATION, + reserved_section_size=self.FLASH_SECTION_SIZE_DDR_CONFIGURATION, validate=validate) + + def erase_and_program_customer_certificate(self, file_path, validate=1): + logger.info(f"Programming Customer certificate file: {file_path}...") + self.erase_and_program_flash(file_path, + offset=self.FLASH_OFFSET_CUSTOMER_CERTIFICATE, + reserved_section_size=self.FLASH_SECTION_SIZE_CUSTOMER_CERTIFICATE, + validate=validate) + + +def run(scu_firmware=None, bootloader=None, bootloader_env=None, ddr_configuration=None, customer_cert=None, + verify=True, uart_load=False, serial_device_name='/dev/ttyUSB3', jump_to_flash=False): + if uart_load: + uart_comm = UartRecoveryCommunicator(serial_device_name) + programmer = uart_comm.get_flash_programmer() + else: + programmer = FtdiFlashProgrammer() + + flash_manager = Hailo15FlashManager(programmer) + + flash_manager.programmer.open_interface() + + if scu_firmware: + flash_manager.erase_and_program_scu_fw(scu_firmware, validate=verify) + if bootloader: + flash_manager.erase_and_program_uboot_spl(bootloader, validate=verify) + # U-Boot env program must follow the uboot program + if bootloader_env: + flash_manager.erase_and_program_uboot_env(bootloader_env, validate=verify) + if ddr_configuration: + flash_manager.erase_and_program_ddr_configuration(ddr_configuration, validate=verify) + if customer_cert: + flash_manager.erase_and_program_customer_certificate(customer_cert, validate=verify) + + if uart_load and jump_to_flash: + uart_comm.jump_bootrom_flash() + + +def main(): + parser = argparse.ArgumentParser() + parser.add_argument( + '--scu-firmware', + help='The path to the file containing the SCU firmware binary.') + + parser.add_argument( + '--bootloader', + help='The path to the file containing the U-Boot SPL binary.') + + parser.add_argument( + '--bootloader-env', + help='The path to the file containing the U-Boot env.') + + parser.add_argument( + '--ddr-configuration', + help='The path to the file containing the DDR configuration.') + + parser.add_argument( + '--customer-certificate', + help='The path to the file containing the customer certificate.') + + parser.add_argument('--verify', type=int, choices=[0, 1], default=1, + help='Verify the written data by reviewing and comparing to the written data (default is true)') + + parser.add_argument('--uart-load', action='store_true', + help='Use UART for programming the SPI flash (default is false).') + + parser.add_argument('--serial-device-name', default='/dev/ttyUSB3', + help='The serial device name (default is /dev/ttyUSB3).') + + args = parser.parse_args() + + run(args.scu_firmware, args.bootloader, args.bootloader_env, args.ddr_configuration, + args.customer_certificate, args.verify, args.uart_load, args.serial_device_name) + + +if __name__ == '__main__': + main() diff --git a/meta-hailo-bsp/hailo15_board_tools/hailo15_board_tools/spi_flash_program.py b/meta-hailo-bsp/hailo15_board_tools/hailo15_board_tools/spi_flash_program.py new file mode 100644 index 0000000..2ab68ad --- /dev/null +++ b/meta-hailo-bsp/hailo15_board_tools/hailo15_board_tools/spi_flash_program.py @@ -0,0 +1,49 @@ +import argparse + +from hailo15_board_tools.hailo15_spi_flash_program import Hailo15FlashManager +from hailo15_board_tools.flash_programmers.uart_recovery_manager import UartRecoveryCommunicator +from hailo15_board_tools.flash_programmers.ftdi_flash_programmer import FtdiFlashProgrammer + + +def convert_file_size_to_int(file_size): + if file_size.startswith('0x'): + size = int(file_size, 16) + else: + size = int(file_size) + return size + + +def main(): + parser = argparse.ArgumentParser() + parser.add_argument( + '--file', type=str, required=True, + help='Path to the binary image file to be programmed') + parser.add_argument('--offset', type=int, default=0, + help='Start offset (in bytes) of the given image from the beginning of the SPI flash.') + parser.add_argument('--size', required=True, + help='Size (in bytes) of the given image.') + parser.add_argument('--verify', type=int, choices=[0, 1], default=1, + help='Verify the written data by reading and comparing to the written data (default is true).') + parser.add_argument('--uart-load', action='store_true', + help='Use UART for programming the SPI flash, (default is false).') + parser.add_argument('--serial-device-name', default='/dev/ttyUSB3', + help='The serial device name (default is /dev/ttyUSB3).') + + args = parser.parse_args() + file_size = convert_file_size_to_int(args.size) + + if args.uart_load: + uart_comm = UartRecoveryCommunicator(args.serial_device_name) + programmer = uart_comm.get_flash_programmer() + else: + programmer = FtdiFlashProgrammer() + + flash_manager = Hailo15FlashManager(programmer) + + flash_manager.programmer.open_interface() + + flash_manager.erase_and_program_flash(args.file, args.offset, file_size, args.verify) + + +if __name__ == '__main__': + main() diff --git a/meta-hailo-bsp/hailo15_board_tools/hailo15_board_tools/uart_boot_fw_loader.py b/meta-hailo-bsp/hailo15_board_tools/hailo15_board_tools/uart_boot_fw_loader.py new file mode 100644 index 0000000..4f3b8d3 --- /dev/null +++ b/meta-hailo-bsp/hailo15_board_tools/hailo15_board_tools/uart_boot_fw_loader.py @@ -0,0 +1,208 @@ +import serial +import time +import ctypes +import argparse + +UART_BAUDRATE = 57600 +UART_TIMEOUT = 2 # seconds +UART_RESPONSE_LENGTH = 3 +UART_ACK = 0x55 +FIRMWARE_ADDRESS = 0x20000 +HEADER_ADDRESS = 0x88000 +KEY_CERTIFICATE_ADDRESS = 0x88018 +CONTENT_CERTIFICATE_ADDRESS = 0x886a8 +MAX_CODE_RAM_SIZE = 0x50000 +MAX_KEY_CERTIFICATE_SIZE = 0x690 +MAX_CONTENT_CERTIFICATE_SIZE = 0x5F0 +FIRMWARE_HEADER_MAGIC_HAILO15 = 0xE905DAAB +FIRMWARE_HEADER_VERSION_INITIAL = 0 +SLEEP_TIME_INSTEAD_READ_SECOND = 0.1 +SLEEP_TIME_AFTER_BOOT_SECOND = 2 + + +class UploadException(Exception): + pass + + +class InputException(Exception): + pass + + +class FirmwareHeaderStruct(ctypes.LittleEndianStructure): + _fields_ = [ + ("magic", ctypes.c_uint32), + ("header_version", ctypes.c_uint32), + ("firmware_major", ctypes.c_uint32), + ("firmware_minor", ctypes.c_uint32), + ("firmware_revision", ctypes.c_uint32), + ("code_size", ctypes.c_uint32), + ] + + +class SecureBootCertificateStruct(ctypes.LittleEndianStructure): + _fields_ = [ + ("key_size", ctypes.c_uint32), + ("content_size", ctypes.c_uint32), + ] + + +def calc_checksum(data): + sum1 = 0 + sum2 = 0 + + for b in data: + sum1 = (sum1 + b) % 255 + sum2 = (sum1 + sum2) % 255 + + return ((sum2 << 8) + sum1) + + +class UartBootFWLoader(): + + def __init__(self, is_secure_chip, serial_device_name): + self.is_secure_chip = is_secure_chip + self.serial_device_name = serial_device_name + + def load_file(self, firmware): + firmware_binary_path = open(firmware, 'rb') + firmware_binary_bin = firmware_binary_path.read() + + firmware_header_bin, firmware_code, key_certificate_bin, content_certificate_bin = \ + self.validate_bin_file_and_create_bin_files(firmware_binary_bin) + + end_transaction = bytes(10) + + time.sleep(SLEEP_TIME_AFTER_BOOT_SECOND) # to make sure bootrom is out of reset + + s = serial.Serial(self.serial_device_name, UART_BAUDRATE, timeout=UART_TIMEOUT) + + if self.is_secure_chip: + # read the first magic + s.read(UART_RESPONSE_LENGTH) + + try: + # write firmware + self.write_to_uart(FIRMWARE_ADDRESS, firmware_code, s, self.is_secure_chip) + + # write header + self.write_to_uart(HEADER_ADDRESS, firmware_header_bin, s, self.is_secure_chip) + + # write key_certificate + self.write_to_uart(KEY_CERTIFICATE_ADDRESS, key_certificate_bin, s, self.is_secure_chip) + + # write content _certificate + self.write_to_uart(CONTENT_CERTIFICATE_ADDRESS, content_certificate_bin, s, self.is_secure_chip) + + s.write(end_transaction) + except UploadException: + print("Upload failed, exiting") + + def write_to_uart(self, address, file_bin, s, secure_chip=False): + address_bin = address.to_bytes(4, byteorder='little') + length_bin = (len(file_bin)).to_bytes(4, byteorder='little') + checksum = calc_checksum(address_bin + length_bin) + checksum_bin = checksum.to_bytes(2, byteorder='little') + + s.write(address_bin) + s.write(length_bin) + s.write(checksum_bin) + + # on non-secure chips the UART1_TX is muxed with DFT_JTAG_TDO + # on secure chips we should wait for ack, in non-secure chips we + # can just ignore the checksum and add sleeps instead + + if secure_chip: + ack = s.read(UART_RESPONSE_LENGTH) + if (len(ack) != UART_RESPONSE_LENGTH) or (ack[0] != UART_ACK) or (checksum_bin != ack[1:3]): + print("invalid header checksum: " + str(ack)) + raise UploadException("invalid header") + else: + time.sleep(SLEEP_TIME_INSTEAD_READ_SECOND) + + s.write(file_bin) + + checksum = calc_checksum(file_bin) + checksum_bin = checksum.to_bytes(2, byteorder='little') + + if secure_chip: + ack = s.read(UART_RESPONSE_LENGTH) + if (len(ack) != UART_RESPONSE_LENGTH) or (ack[0] != UART_ACK) or (checksum_bin != ack[1:3]): + print("invalid data ack") + raise UploadException("invalid data ack") + else: + time.sleep(SLEEP_TIME_INSTEAD_READ_SECOND) + + def validate_bin_file_and_create_bin_files(self, firmware_binary_bin): + header_size = ctypes.sizeof(FirmwareHeaderStruct) + certificate_header_size = ctypes.sizeof(SecureBootCertificateStruct) + + firmware_header_bin = firmware_binary_bin[0:header_size] + + firmware_header_struct = FirmwareHeaderStruct.from_buffer_copy(firmware_header_bin) + + if FIRMWARE_HEADER_MAGIC_HAILO15 != firmware_header_struct.magic: + raise InputException("Incorrect firmware header magic") + if FIRMWARE_HEADER_VERSION_INITIAL != firmware_header_struct.header_version: + raise InputException("Incorrect firmware header version") + if MAX_CODE_RAM_SIZE < firmware_header_struct.code_size: + raise InputException("The firmware provided is too large") + + code_size = firmware_header_struct.code_size + + print(f"UART recovery firmware version: {firmware_header_struct.firmware_major}.\ +{firmware_header_struct.firmware_minor}") + + firmware_code = firmware_binary_bin[header_size:(header_size + code_size)] + + certificate_header_offset = header_size + code_size + + certificate_header_bin = firmware_binary_bin[certificate_header_offset: + (certificate_header_offset + certificate_header_size)] + secure_boot_certificate_struct = SecureBootCertificateStruct.from_buffer_copy(certificate_header_bin) + + if MAX_KEY_CERTIFICATE_SIZE < secure_boot_certificate_struct.key_size: + raise InputException("The key certificate provided is too large") + if MAX_CONTENT_CERTIFICATE_SIZE < secure_boot_certificate_struct.content_size: + raise InputException("The content certificate provided is too large") + + key_certificate_size = secure_boot_certificate_struct.key_size + content_certificate_size = secure_boot_certificate_struct.content_size + + key_certificate_offset = certificate_header_offset + certificate_header_size + + content_certificate_offset = key_certificate_offset + key_certificate_size + + if (content_certificate_offset + content_certificate_size) != \ + len(firmware_binary_bin): + raise InputException("Field sizes of either code/certificates don't match the actual firmware size") + + key_certificate_bin = firmware_binary_bin[key_certificate_offset: + (key_certificate_offset + key_certificate_size)] + content_certificate_bin = firmware_binary_bin[content_certificate_offset: + (content_certificate_offset + content_certificate_size)] + + return firmware_header_bin, firmware_code, key_certificate_bin, content_certificate_bin + + +def run(firmware, is_secure_chip=True, serial_device_name='/dev/ttyUSB3'): + uart_boot_fw_loader = UartBootFWLoader(is_secure_chip, serial_device_name) + uart_boot_fw_loader.load_file(firmware) + + +def main(): + parser = argparse.ArgumentParser() + parser.add_argument('--firmware', help='The path to the file containing the firmware binary') + + parser.add_argument('--is-secure-chip', action='store_true', + help='Whether the given chip is in a secure LCS') + + parser.add_argument('--serial-device-name', default='/dev/ttyUSB3', + help='The serial device file name (default /dev/ttyUSB3)') + + args = parser.parse_args() + + run(args.firmware, args.is_secure_chip, args.serial_device_name) + + +if __name__ == '__main__': + main() diff --git a/meta-hailo-bsp/hailo15_board_tools/setup.cfg b/meta-hailo-bsp/hailo15_board_tools/setup.cfg new file mode 100644 index 0000000..de460b5 --- /dev/null +++ b/meta-hailo-bsp/hailo15_board_tools/setup.cfg @@ -0,0 +1,26 @@ +[metadata] +name = hailo15_board_tools +version = 1.1.0 +description = Hailo15 Board Tools +classifiers = + Programming Language :: Python :: 3 :: Only + +[options] +packages = find: +python_requires = >=3.8 +zip_safe = False +include_package_data = True +install_requires = + pyserial==3.5 + pyspiflash==0.6.3 + +[options.entry_points] +console_scripts = + hailo15_spi_flash_program = hailo15_board_tools.hailo15_spi_flash_program:main + spi_flash_program = hailo15_board_tools.spi_flash_program:main + uart_boot_fw_loader = hailo15_board_tools.uart_boot_fw_loader:main + +[flake8] +exclude = .git, __pycache__, build, dist +max-line-length = 120 +max-complexity = 10 \ No newline at end of file diff --git a/meta-hailo-bsp/hailo15_board_tools/setup.py b/meta-hailo-bsp/hailo15_board_tools/setup.py new file mode 100644 index 0000000..6068493 --- /dev/null +++ b/meta-hailo-bsp/hailo15_board_tools/setup.py @@ -0,0 +1,3 @@ +from setuptools import setup + +setup() diff --git a/meta-hailo-bsp/recipes-bsp/alsa-state/alsa-state.bbappend b/meta-hailo-bsp/recipes-bsp/alsa-state/alsa-state.bbappend new file mode 100644 index 0000000..cc9cf1b --- /dev/null +++ b/meta-hailo-bsp/recipes-bsp/alsa-state/alsa-state.bbappend @@ -0,0 +1,8 @@ +DESCRIPTION = "Append Hailo15 default ALSA configuration" +FILESEXTRAPATHS:prepend := "${THISDIR}/files:" +SRC_URI += "file://hailo15_i2s_master_asound.conf" +do_install:append() { + cat ${WORKDIR}/hailo15_i2s_master_asound.conf >> ${D}/etc/asound.conf +} +FILES:${PN} += "/etc/asound.conf" + diff --git a/meta-hailo-bsp/recipes-bsp/alsa-state/files/hailo15_i2s_master_asound.conf b/meta-hailo-bsp/recipes-bsp/alsa-state/files/hailo15_i2s_master_asound.conf new file mode 100644 index 0000000..4fc733b --- /dev/null +++ b/meta-hailo-bsp/recipes-bsp/alsa-state/files/hailo15_i2s_master_asound.conf @@ -0,0 +1,11 @@ +# Default Hailo15 I2S master sampling rate +pcm_slave.hailo15_i2s_master { + pcm "hw:0,0" + rate 48000 +} +# default sampling rate conversion +pcm.!default { + type plug + slave hailo15_i2s_master +} + diff --git a/meta-hailo-bsp/recipes-bsp/cryptocell-312-runtime-native/cryptocell-312-runtime-native.bb b/meta-hailo-bsp/recipes-bsp/cryptocell-312-runtime-native/cryptocell-312-runtime-native.bb new file mode 100644 index 0000000..d02275c --- /dev/null +++ b/meta-hailo-bsp/recipes-bsp/cryptocell-312-runtime-native/cryptocell-312-runtime-native.bb @@ -0,0 +1,31 @@ +SRC_URI = "git://github.com/ARM-software/cryptocell-312-runtime.git;protocol=https;branch=update-cc110-bu-00000-r1p4" +SRCREV = "91539d62a67662e40e7d925694e55bbc7e679f84" +LIC_FILES_CHKSUM += "file://BSD-3-Clause.txt;md5=d2debfe1305a4e8cd5673d2b1f5e86ba" +LICENSE = "BSD-3-Clause" + +DEPENDS = "openssl-native" +RDEPENDS:${PN} = "python3-native" + +S = "${WORKDIR}/git" + +inherit native + +CFLAGS[unexport] = "1" +LDFLAGS[unexport] = "1" +AS[unexport] = "1" +LD[unexport] = "1" +CP_ARGS="-Prf --preserve=mode,timestamps --no-preserve=ownership" + +do_compile () { + oe_runmake -C ${S}/utils/src/ OPENSSL_INC_DIR=${STAGING_INCDIR_NATIVE} OPENSSL_LIB_DIR=${STAGING_LIBDIR_NATIVE} +} + +do_install () { + install -d ${D}${bindir} + install -d ${D}${libdir} + install -d ${D}${sysconfdir} + cp ${CP_ARGS} ${S}/utils/bin/. ${D}${bindir} + cp ${CP_ARGS} ${S}/utils/lib/. ${D}${libdir} + cp ${CP_ARGS} ${S}/utils/src/proj.cfg ${D}${sysconfdir}/cc_proj.cfg + sed -i 's|^#!/usr/local/bin/python3|#!/usr/bin/env python3|' ${D}${bindir}/*.py +} diff --git a/meta-hailo-bsp/recipes-bsp/hailo-ddr-configuration-native/files/LICENSE b/meta-hailo-bsp/recipes-bsp/hailo-ddr-configuration-native/files/LICENSE new file mode 100644 index 0000000..3578ae7 --- /dev/null +++ b/meta-hailo-bsp/recipes-bsp/hailo-ddr-configuration-native/files/LICENSE @@ -0,0 +1,23 @@ + +MIT License + +Copyright (c) 2017-2023 Hailo Technologies Ltd. All rights reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + diff --git a/meta-hailo-bsp/recipes-bsp/hailo-ddr-configuration-native/files/build_ddr_configuration.c b/meta-hailo-bsp/recipes-bsp/hailo-ddr-configuration-native/files/build_ddr_configuration.c new file mode 100644 index 0000000..6752151 --- /dev/null +++ b/meta-hailo-bsp/recipes-bsp/hailo-ddr-configuration-native/files/build_ddr_configuration.c @@ -0,0 +1,229 @@ +/****************************************************************************** +* Legal notice: +* Copyright (C) 2017-2023 Hailo Technologies Ltd. +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef REGCONFIG_FILENAME +#error "Please define REGCONFIG_FILENAME (-D to the compiler) to the path of your regconfig file surrounded by qoutation marks" +#endif +#include REGCONFIG_FILENAME + +#include +#include +#include +#include +#include +#include +#include + +#define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(0[arr])) + +#define DDR_CONFIGURATION_HEADER_MAGIC (0xB725E43D) +#define DDR_CONFIGURATION_HEADER_REVISION (3) + +#define DDR_CTRL_REGS_COUNT (0x19F) +#define DDR_PI_REGS_COUNT (0x12C) +#define DDR_PHY_REGS_COUNT (0x58F) + +_Static_assert(sizeof(DDR_ctrl_registers) == sizeof(uint32_t) * DDR_CTRL_REGS_COUNT, "wrong size of DDR_ctrl_registers"); +_Static_assert(sizeof(DDR_PI_registers) == sizeof(uint32_t) * DDR_PI_REGS_COUNT, "wrong size of DDR_PI_registers"); +_Static_assert(sizeof(DDR_PHY_registers) == sizeof(uint32_t) * DDR_PHY_REGS_COUNT, "wrong size of DDR_PHY_registers"); + +enum ddr_working_mode { + DDR_WORKING_MODE_NORMAL, + DDR_WORKING_MODE_DDRAPP, + DDR_WORKING_MODE_INTEGRATION, +}; + +enum ddr_ctrl_ecc_mode { + DDR_CTRL_ECC_MODE_DISABLED, + DDR_CTRL_ECC_MODE_ENABLED, /* ECC enabled, detection disabled, correction disabled */ + DDR_CTRL_ECC_MODE_DETECTION, /* ECC enabled, detection enabled, correction disabled */ + DDR_CTRL_ECC_MODE_CORRECTION, /* ECC enabled, detection enabled, correction enabled */ +}; + +struct ddr_config_space { + uint32_t header_magic; /* offset: 0x0 */ + uint32_t header_revision; /* offset: 0x4 */ + uint32_t identifier; /* offset: 0x8 */ + uint32_t ctrl_regs[DDR_CTRL_REGS_COUNT]; /* offset: 0xC */ + uint32_t pi_regs[DDR_PI_REGS_COUNT]; /* offset: 0x68C */ + uint32_t phy_regs[DDR_PHY_REGS_COUNT]; /* offset: 0xB3C */ + uint32_t working_mode; /* offset: 0x2174 */ + uint32_t ecc_mode; /* offset: 0x2178 */ + uint32_t bist_enable; /* offset: 0x217C */ + uint32_t operational_freq; /* offset: 0x2180 */ + uint32_t stop_before_controller_start; /* offset: 0x2184 */ + uint32_t f1_frequency; /* offset: 0x2188 */ + uint32_t f2_frequency; /* offset: 0x218C */ + uint32_t temperature_poll_period_ms; /* offset: 0x2190 */ + uint32_t temperature_retraining_threshold_millicelsius; /* offset: 0x2194 */ + uint32_t periodic_io_calibration_disable; /* offset: 0x2198 */ + uint32_t periodic_vref_training_enable; /* offset: 0x219C */ + uint32_t periodic_calvl_training_enable; /* offset: 0x21A0 */ + uint32_t periodic_wrlvl_training_enable; /* offset: 0x21A4 */ + uint32_t periodic_rdlvl_training_enable; /* offset: 0x21A8 */ + uint32_t periodic_rdlvl_gate_training_enable; /* offset: 0x21AC */ + uint32_t periodic_wdqlvl_training_enable; /* offset: 0x21B0 */ +}; + +const uint32_t allowed_frequencies[] = { + 50000000, 100000000, 1598000000, 200000000, + 400000000, 800000000, 1200000000, 1600000000, + 2000000000, 2130000000, 2132000000, 2133000000 +}; + +static bool is_frequency_allowed(uint32_t freq) +{ + for (unsigned int i = 0; i < ARRAY_SIZE(allowed_frequencies); i++) { + if (freq == allowed_frequencies[i]) { + return true; + } + } + return false; +} + +uint32_t calculate_configuration_identifier(const void* config, uint32_t size) { + unsigned char hash[SHA256_DIGEST_LENGTH] = {0}; + uint32_t identifier = 0; + SHA256_CTX sha256; + + SHA256(config, size, hash); + + memcpy(&identifier, hash, sizeof(identifier)); + return identifier; +} + +int main(int argc, char* argv[]) +{ + char *ecc_mode_str, *bist_enable_str, *operational_freq_str, *f1_freq_str, *f2_freq_str, *out_filename; + struct ddr_config_space config_space = {0}; + uint32_t ecc_mode, operational_freq_index, f1_freq, f2_freq; + bool bist_enable; + FILE *file; + size_t bytes_written; + + if (argc != 7) { + fprintf(stderr, "Argument count error. Usage: %s [ecc-mode=disabled/enabled/detection/correction] [bist-enable=enable/disable] [operational-freq-index=f0/f1/f2] [f1-frequency-hz] [f2-frequency-hz] [out-file]\n", argv[0]); + return 1; + } + + ecc_mode_str = argv[1]; + bist_enable_str = argv[2]; + operational_freq_str = argv[3]; + f1_freq_str = argv[4]; + f2_freq_str = argv[5]; + out_filename = argv[6]; + + if (!strcmp(ecc_mode_str, "disabled")) { + ecc_mode = DDR_CTRL_ECC_MODE_DISABLED; + } else if (!strcmp(ecc_mode_str, "enabled")) { + ecc_mode = DDR_CTRL_ECC_MODE_ENABLED; + } else if (!strcmp(ecc_mode_str, "detection")) { + ecc_mode = DDR_CTRL_ECC_MODE_DETECTION; + } else if (!strcmp(ecc_mode_str, "correction")) { + ecc_mode = DDR_CTRL_ECC_MODE_CORRECTION; + } else { + fprintf(stderr, "bad ecc-mode parameter\n"); + return 2; + } + + if (!strcmp(bist_enable_str, "disabled")) { + bist_enable = false; + } else if (!strcmp(bist_enable_str, "enabled")) { + bist_enable = true; + } else { + fprintf(stderr, "bad bist-enable parameter\n"); + return 3; + } + + if (!strcmp(operational_freq_str, "f0")) { + operational_freq_index = 0; + } else if (!strcmp(operational_freq_str, "f1")) { + operational_freq_index = 1; + } else if (!strcmp(operational_freq_str, "f2")) { + operational_freq_index = 2; + } else { + fprintf(stderr, "bad operational-freq-index parameter\n"); + return 4; + } + + f1_freq = strtoul(f1_freq_str, NULL, 10); + if (!is_frequency_allowed(f1_freq)) { + fprintf(stderr, "bad f1-frquency-hz parameter\n"); + return 5; + } + + f2_freq = strtoul(f2_freq_str, NULL, 10); + if (!is_frequency_allowed(f2_freq)) { + fprintf(stderr, "bad f2-frquency-hz parameter\n"); + return 6; + } + + config_space.header_magic = DDR_CONFIGURATION_HEADER_MAGIC; + config_space.header_revision = DDR_CONFIGURATION_HEADER_REVISION; + memcpy(config_space.ctrl_regs, DDR_ctrl_registers, sizeof(DDR_ctrl_registers)); + memcpy(config_space.pi_regs, DDR_PI_registers, sizeof(DDR_PI_registers)); + memcpy(config_space.phy_regs, DDR_PHY_registers, sizeof(DDR_PHY_registers)); + config_space.working_mode = DDR_WORKING_MODE_NORMAL; + config_space.ecc_mode = ecc_mode; + config_space.bist_enable = bist_enable; + config_space.operational_freq = operational_freq_index; + config_space.f1_frequency = f1_freq; + config_space.f2_frequency = f2_freq; + config_space.temperature_poll_period_ms = 1000; + config_space.temperature_retraining_threshold_millicelsius = 5000; + config_space.periodic_io_calibration_disable = false; + config_space.periodic_vref_training_enable = false; + config_space.periodic_calvl_training_enable = false; + config_space.periodic_wrlvl_training_enable = false; + config_space.periodic_rdlvl_training_enable = false; + config_space.periodic_rdlvl_gate_training_enable = false; + config_space.periodic_wdqlvl_training_enable = false; + + /* must be computed after configuration is populated */ + config_space.identifier = calculate_configuration_identifier(&config_space, sizeof(config_space)); + + file = fopen(out_filename, "w"); + if (!file) { + fprintf(stderr, "Could not open output file for writing\n"); + return 7; + } + + bytes_written = fwrite(&config_space, 1, sizeof(config_space), file); + if (bytes_written != sizeof(config_space)) { + fprintf(stderr, "Writing config to output file failed\n"); + return 8; + } + + if(fclose(file)) { + fprintf(stderr, "Closing output file failed\n"); + return 9; + } + + return 0; +} diff --git a/meta-hailo-bsp/recipes-bsp/hailo-ddr-configuration-native/files/hailo15_evb_MT53E1G32D2FW-046.h b/meta-hailo-bsp/recipes-bsp/hailo-ddr-configuration-native/files/hailo15_evb_MT53E1G32D2FW-046.h new file mode 100644 index 0000000..ee9b00a --- /dev/null +++ b/meta-hailo-bsp/recipes-bsp/hailo-ddr-configuration-native/files/hailo15_evb_MT53E1G32D2FW-046.h @@ -0,0 +1,2191 @@ +/****************************************************************************** +* Legal notice: +* Copyright (C) 2012-2023 Cadence Design Systems, Inc. +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +// Auto-generated using DDR Utility + +#ifndef _DDR_CONFIGURATION_H_ +#define _DDR_CONFIGURATION_H_ + +#include + + +uint32_t DDR_ctrl_registers[] = +{ + 0x00000B00, // 0: CONTROLLER_ID:RD:16:16:=0x0000 DRAM_CLASS:RW:8:4:=0x0b START:RW:0:1:=0x00 + 0x00000000, // 1: CONTROLLER_VERSION:RD:0:64:=0x00000000 + 0x00000000, // 2: CONTROLLER_VERSION:RD:0:64:=0x00000000 + 0x00000000, // 3: READ_DATA_FIFO_DEPTH:RD:24:8:=0x00 MAX_CS_REG:RD:16:2:=0x00 MAX_COL_REG:RD:8:4:=0x00 MAX_ROW_REG:RD:0:5:=0x00 + 0x00000000, // 4: WRITE_DATA_FIFO_PTR_WIDTH:RD:16:8:=0x00 WRITE_DATA_FIFO_DEPTH:RD:8:8:=0x00 READ_DATA_FIFO_PTR_WIDTH:RD:0:8:=0x00 + 0x00000000, // 5: ASYNC_CDC_STAGES:RD:24:8:=0x00 MEMCD_RMODW_FIFO_PTR_WIDTH:RD:16:8:=0x00 MEMCD_RMODW_FIFO_DEPTH:RD:0:16:=0x0000 + 0x00000000, // 6: AXI0_TRANS_WRFIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI0_WR_ARRAY_LOG2_DEPTH:RD:16:8:=0x00 AXI0_CMDFIFO_LOG2_DEPTH:RD:0:8:=0x00 + 0x00000000, // 7: AXI1_WR_ARRAY_LOG2_DEPTH:RD:24:8:=0x00 AXI1_CMDFIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:0:8:=0x00 + 0x00000000, // 8: AXI1_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI1_TRANS_WRFIFO_LOG2_DEPTH:RD:0:8:=0x00 + 0x00002710, // 9: TINIT_F0:RW:0:24:=0x002710 + 0x000186A0, // 10: TINIT3_F0:RW:0:24:=0x0186a0 + 0x00000005, // 11: TINIT4_F0:RW:0:24:=0x000005 + 0x00000064, // 12: TINIT5_F0:RW:0:24:=0x000064 + 0x0004E200, // 13: TINIT_F1:RW:0:24:=0x04e200 + 0x0030D400, // 14: TINIT3_F1:RW:0:24:=0x30d400 + 0x00000005, // 15: TINIT4_F1:RW:0:24:=0x000005 + 0x00000C80, // 16: TINIT5_F1:RW:0:24:=0x000c80 + 0x000681C8, // 17: TINIT_F2:RW:0:24:=0x0681c8 + 0x004111C9, // 18: TINIT3_F2:RW:0:24:=0x4111c9 + 0x00000005, // 19: TINIT4_F2:RW:0:24:=0x000005 + 0x000010A9, // 20: NO_AUTO_MRR_INIT:RW:24:1:=0x00 TINIT5_F2:RW:0:24:=0x0010a9 + 0x01000000, // 21: ODT_VALUE:RW:24:1:=0x01 NO_MRW_INIT:RW:16:1:=0x00 DFI_INV_DATA_CS:RW:8:1:=0x00 MRR_ERROR_STATUS:RD:0:1:=0x00 + 0x01001001, // 22: DFIBUS_FREQ_INIT:RW:24:2:=0x01 PHY_INDEP_INIT_MODE:RW:16:1:=0x00 TSREF2PHYMSTR:RW:8:6:=0x10 PHY_INDEP_TRAIN_MODE:RW:0:1:=0x01 + 0x02010000, // 23: DFIBUS_FREQ_F2:RW:24:5:=0x02 DFIBUS_FREQ_F1:RW:16:5:=0x01 DFIBUS_FREQ_F0:RW:8:5:=0x00 DFIBUS_BOOT_FREQ:RW:0:2:=0x00 + 0x00020100, // 24: FREQ_CHANGE_TYPE_F2:RW:16:2:=0x00 FREQ_CHANGE_TYPE_F1:RW:8:2:=0x01 FREQ_CHANGE_TYPE_F0:RW:0:2:=0x02 + 0x0000000A, // 25: TRST_PWRON:RW:0:32:=0x0000000a + 0x00000019, // 26: CKE_INACTIVE:RW:0:32:=0x00000019 + 0x00000000, // 27: RESERVED:RW:8:24:=0x000000 RESERVED:RW:0:1:=0x00 + 0x00000000, // 28: DQS_OSC_ENABLE:RW:16:1:=0x00 RESERVED:RW:8:8:=0x00 RESERVED:RW:0:8:=0x00 + 0x02020200, // 29: TOSCO_F0:RW:24:8:=0x02 FUNC_VALID_CYCLES:RW:16:4:=0x02 DQS_OSC_PERIOD:RW:0:15:=0x0200 + 0x00005640, // 30: DQS_OSC_HIGH_THRESHOLD:RW:24:8:=0x00 DQS_OSC_NORM_THRESHOLD:RW:16:8:=0x00 TOSCO_F2:RW:8:8:=0x56 TOSCO_F1:RW:0:8:=0x40 + 0x00100000, // 31: OSC_VARIANCE_LIMIT:RW:16:16:=0x0010 DQS_OSC_PROMOTE_THRESHOLD:RW:8:8:=0x00 DQS_OSC_TIMEOUT:RW:0:8:=0x00 + 0x00000000, // 32: OSC_BASE_VALUE_0_CS0:RD:8:16:=0x0000 DQS_OSC_REQUEST:WR:0:1:=0x00 + 0x00000000, // 33: OSC_BASE_VALUE_2_CS0:RD:16:16:=0x0000 OSC_BASE_VALUE_1_CS0:RD:0:16:=0x0000 + 0x00000000, // 34: OSC_BASE_VALUE_0_CS1:RD:16:16:=0x0000 OSC_BASE_VALUE_3_CS0:RD:0:16:=0x0000 + 0x00000000, // 35: OSC_BASE_VALUE_2_CS1:RD:16:16:=0x0000 OSC_BASE_VALUE_1_CS1:RD:0:16:=0x0000 + 0x040C0000, // 36: WRLAT_F0:RW:24:7:=0x04 CASLAT_LIN_F0:RW:16:7:=0x0c OSC_BASE_VALUE_3_CS1:RD:0:16:=0x0000 + 0x12480E38, // 37: WRLAT_F2:RW:24:7:=0x12 CASLAT_LIN_F2:RW:16:7:=0x48 WRLAT_F1:RW:8:7:=0x0e CASLAT_LIN_F1:RW:0:7:=0x38 + 0x00050804, // 38: TRRD_F0:RW:16:8:=0x05 TCCD:RW:8:5:=0x08 TBST_INT_INTERVAL:RW:0:3:=0x04 + 0x09040007, // 39: TWTR_F0:RW:24:6:=0x09 TRAS_MIN_F0:RW:16:8:=0x04 TRC_F0:RW:0:9:=0x0007 + 0x0D000203, // 40: TRRD_F1:RW:24:8:=0x0d TFAW_F0:RW:8:9:=0x0002 TRP_F0:RW:0:8:=0x03 + 0x11450062, // 41: TWTR_F1:RW:24:6:=0x11 TRAS_MIN_F1:RW:16:8:=0x45 TRC_F1:RW:0:9:=0x0062 + 0x1100311D, // 42: TRRD_F2:RW:24:8:=0x11 TFAW_F1:RW:8:9:=0x0031 TRP_F1:RW:0:8:=0x1d + 0x175C0083, // 43: TWTR_F2:RW:24:6:=0x17 TRAS_MIN_F2:RW:16:8:=0x5c TRC_F2:RW:0:9:=0x0083 + 0x20004227, // 44: TCCDMW:RW:24:6:=0x20 TFAW_F2:RW:8:9:=0x0042 TRP_F2:RW:0:8:=0x27 + 0x000A0A09, // 45: TMOD_F0:RW:16:8:=0x0a TMRD_F0:RW:8:8:=0x0a TRTP_F0:RW:0:8:=0x09 + 0x040006DB, // 46: TCKE_F0:RW:24:5:=0x04 TRAS_MAX_F0:RW:0:17:=0x0006db + 0x17100D04, // 47: TMOD_F1:RW:24:8:=0x17 TMRD_F1:RW:16:8:=0x10 TRTP_F1:RW:8:8:=0x0d TCKESR_F0:RW:0:8:=0x04 + 0x0C00DB60, // 48: TCKE_F1:RW:24:5:=0x0c TRAS_MAX_F1:RW:0:17:=0x00db60 + 0x1E16110C, // 49: TMOD_F2:RW:24:8:=0x1e TMRD_F2:RW:16:8:=0x16 TRTP_F2:RW:8:8:=0x11 TCKESR_F1:RW:0:8:=0x0c + 0x10012458, // 50: TCKE_F2:RW:24:5:=0x10 TRAS_MAX_F2:RW:0:17:=0x012458 + 0x02030410, // 51: RESERVED:RW:24:3:=0x02 RESERVED:RW:16:3:=0x03 TPPD:RW_D:8:3:=0x04 TCKESR_F2:RW:0:8:=0x10 + 0x1E040500, // 52: TRCD_F1:RW:24:8:=0x1e TWR_F0:RW:16:8:=0x04 TRCD_F0:RW:8:8:=0x05 WRITEINTERP:RW:0:1:=0x00 + 0x0829281F, // 53: TMRR:RW:24:4:=0x08 TWR_F2:RW:16:8:=0x29 TRCD_F2:RW:8:8:=0x28 TWR_F1:RW:0:8:=0x1f + 0x07010100, // 54: TDAL_F0:RW:24:8:=0x07 TRAS_LOCKOUT:RW:16:1:=0x01 CONCURRENTAP:RW:8:1:=0x01 AP:RW:0:1:=0x00 + 0x0304503C, // 55: TRP_AB_F0_0:RW:24:8:=0x03 BSTLEN:RW_D:16:5:=0x04 TDAL_F2:RW:8:8:=0x50 TDAL_F1:RW:0:8:=0x3c + 0x22032D22, // 56: TRP_AB_F1_1:RW:24:8:=0x22 TRP_AB_F0_1:RW:16:8:=0x03 TRP_AB_F2_0:RW:8:8:=0x2d TRP_AB_F1_0:RW:0:8:=0x22 + 0x0000002D, // 57: RESERVED:RW:24:7:=0x00 RESERVED:RW:16:2:=0x00 REG_DIMM_ENABLE:RW:8:1:=0x00 TRP_AB_F2_1:RW:0:8:=0x2d + 0x00000101, // 58: AREFRESH:WR:24:1:=0x00 NO_MEMORY_DM:RW:16:1:=0x00 RESERVED:RW:8:1:=0x01 OPTIMAL_RMODW_EN:RW:0:1:=0x01 + 0x08030100, // 59: CS_COMPARISON_FOR_REFRESH_DEPTH:RW:24:6:=0x08 RESERVED:RW:16:3:=0x03 TREF_ENABLE:RW:8:1:=0x01 AREF_STATUS:RD:0:1:=0x00 + 0x00000013, // 60: TRFC_F0:RW:0:10:=0x0013 + 0x000000BB, // 61: TREF_F0:RW:0:20:=0x0000bb + 0x00000260, // 62: TRFC_F1:RW:0:10:=0x0260 + 0x00001858, // 63: TREF_F1:RW:0:20:=0x001858 + 0x0000032B, // 64: TRFC_F2:RW:0:10:=0x032b + 0x00002073, // 65: TREF_F2:RW:0:20:=0x002073 + 0x00000005, // 66: TREF_INTERVAL:RW:0:20:=0x000005 + 0x00050000, // 67: TRFC_PB_F0:RW:16:10:=0x0005 PBR_NUMERIC_ORDER:RW:8:1:=0x00 PBR_EN:RW:0:1:=0x00 + 0x00980010, // 68: TRFC_PB_F1:RW:16:10:=0x0098 TREFI_PB_F0:RW:0:16:=0x0010 + 0x00CB0304, // 69: TRFC_PB_F2:RW:16:10:=0x00cb TREFI_PB_F1:RW:0:16:=0x0304 + 0x00400408, // 70: PBR_MAX_BANK_WAIT:RW:16:16:=0x0040 TREFI_PB_F2:RW:0:16:=0x0408 + 0x00120103, // 71: AREF_PBR_CONT_DIS_THRESHOLD:RW:24:5:=0x00 AREF_PBR_CONT_EN_THRESHOLD:RW:16:5:=0x12 PBR_CONT_REQ_EN:RW:8:1:=0x01 PBR_BANK_SELECT_DELAY:RW:0:4:=0x03 + 0x000C0005, // 72: TPDEX_F1:RW:16:16:=0x000c TPDEX_F0:RW:0:16:=0x0005 + 0x21080010, // 73: TMRRI_F1:RW:24:8:=0x21 TMRRI_F0:RW:16:8:=0x08 TPDEX_F2:RW:0:16:=0x0010 + 0x0505012B, // 74: TCKEHCS_F0:RW:24:5:=0x05 TCKELCS_F0:RW:16:5:=0x05 TCSCKE_F0:RW:8:5:=0x01 TMRRI_F2:RW:0:8:=0x2b + 0x0301030A, // 75: TCSCKE_F1:RW:24:5:=0x03 CA_DEFAULT_VAL_F0:RW:16:1:=0x01 TZQCKE_F0:RW:8:4:=0x03 TMRWCKEL_F0:RW:0:5:=0x0a + 0x03170C08, // 76: TZQCKE_F1:RW:24:4:=0x03 TMRWCKEL_F1:RW:16:5:=0x17 TCKEHCS_F1:RW:8:5:=0x0c TCKELCS_F1:RW:0:5:=0x08 + 0x100B0401, // 77: TCKEHCS_F2:RW:24:5:=0x10 TCKELCS_F2:RW:16:5:=0x0b TCSCKE_F2:RW:8:5:=0x04 CA_DEFAULT_VAL_F1:RW:0:1:=0x01 + 0x0001041E, // 78: CA_DEFAULT_VAL_F2:RW:16:1:=0x01 TZQCKE_F2:RW:8:4:=0x04 TMRWCKEL_F2:RW:0:5:=0x1e + 0x00140014, // 79: TXSNR_F0:RW:16:16:=0x0014 TXSR_F0:RW:0:16:=0x0014 + 0x026C026C, // 80: TXSNR_F1:RW:16:16:=0x026c TXSR_F1:RW:0:16:=0x026c + 0x033B033B, // 81: TXSNR_F2:RW:16:16:=0x033b TXSR_F2:RW:0:16:=0x033b + 0x03050505, // 82: TSR_F0:RW:24:8:=0x03 TCKCKEL_F0:RW:16:5:=0x05 TCKEHCMD_F0:RW:8:5:=0x05 TCKELCMD_F0:RW:0:5:=0x05 + 0x03010303, // 83: TCMDCKE_F0:RW:24:5:=0x03 TCSCKEH_F0:RW:16:5:=0x01 TCKELPD_F0:RW:8:5:=0x03 TESCKE_F0:RW:0:3:=0x03 + 0x18080C08, // 84: TSR_F1:RW:24:8:=0x18 TCKCKEL_F1:RW:16:5:=0x08 TCKEHCMD_F1:RW:8:5:=0x0c TCKELCMD_F1:RW:0:5:=0x08 + 0x03030C03, // 85: TCMDCKE_F1:RW:24:5:=0x03 TCSCKEH_F1:RW:16:5:=0x03 TCKELPD_F1:RW:8:5:=0x0c TESCKE_F1:RW:0:3:=0x03 + 0x200B100B, // 86: TSR_F2:RW:24:8:=0x20 TCKCKEL_F2:RW:16:5:=0x0b TCKEHCMD_F2:RW:8:5:=0x10 TCKELCMD_F2:RW:0:5:=0x0b + 0x04041004, // 87: TCMDCKE_F2:RW:24:5:=0x04 TCSCKEH_F2:RW:16:5:=0x04 TCKELPD_F2:RW:8:5:=0x10 TESCKE_F2:RW:0:3:=0x04 + 0x03010000, // 88: CKE_DELAY:RW:24:3:=0x03 ENABLE_QUICK_SREFRESH:RW:16:1:=0x01 RESERVED:RW:8:1:=0x00 PWRUP_SREFRESH_EXIT:RW:0:1:=0x00 + 0x00010000, // 89: DFS_ZQ_EN:RW:16:1:=0x01 DFS_STATUS:RD:8:2:=0x00 RESERVED:WR:0:5:=0x00 + 0x00000000, // 90: DFS_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 DFS_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000 + 0x01000000, // 91: RESERVED:RW:24:3:=0x01 ZQ_STATUS_LOG:RD:16:3:=0x00 DFS_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000 + 0x80104002, // 92: RESERVED:RW:24:8:=0x80 RESERVED:RW:16:8:=0x10 RESERVED:RW:8:8:=0x40 RESERVED:RW:0:3:=0x02 + 0x00000000, // 93: UPD_CTRLUPD_HIGH_THRESHOLD_F0:RW:16:16:=0x0000 UPD_CTRLUPD_NORM_THRESHOLD_F0:RW:0:16:=0x0000 + 0x00040005, // 94: UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0004 UPD_CTRLUPD_TIMEOUT_F0:RW:0:16:=0x0005 + 0x00000000, // 95: UPD_CTRLUPD_NORM_THRESHOLD_F1:RW:16:16:=0x0000 UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000 + 0x00050000, // 96: UPD_CTRLUPD_TIMEOUT_F1:RW:16:16:=0x0005 UPD_CTRLUPD_HIGH_THRESHOLD_F1:RW:0:16:=0x0000 + 0x00000004, // 97: UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0004 + 0x00000000, // 98: UPD_CTRLUPD_HIGH_THRESHOLD_F2:RW:16:16:=0x0000 UPD_CTRLUPD_NORM_THRESHOLD_F2:RW:0:16:=0x0000 + 0x00040005, // 99: UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0004 UPD_CTRLUPD_TIMEOUT_F2:RW:0:16:=0x0005 + 0x00000000, // 100: UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000 + 0x00002EC0, // 101: TDFI_PHYMSTR_MAX_F0:RW:0:32:=0x00002ec0 + 0x00002EC0, // 102: TDFI_PHYMSTR_MAX_TYPE0_F0:RW:0:32:=0x00002ec0 + 0x00002EC0, // 103: TDFI_PHYMSTR_MAX_TYPE1_F0:RW:0:32:=0x00002ec0 + 0x00002EC0, // 104: TDFI_PHYMSTR_MAX_TYPE2_F0:RW:0:32:=0x00002ec0 + 0x00002EC0, // 105: TDFI_PHYMSTR_MAX_TYPE3_F0:RW:0:32:=0x00002ec0 + 0x00000000, // 106: PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000 + 0x0000051D, // 107: TDFI_PHYMSTR_RESP_F0:RW:0:20:=0x00051d + 0x00061600, // 108: TDFI_PHYMSTR_MAX_F1:RW:0:32:=0x00061600 + 0x00061600, // 109: TDFI_PHYMSTR_MAX_TYPE0_F1:RW:0:32:=0x00061600 + 0x00061600, // 110: TDFI_PHYMSTR_MAX_TYPE1_F1:RW:0:32:=0x00061600 + 0x00061600, // 111: TDFI_PHYMSTR_MAX_TYPE2_F1:RW:0:32:=0x00061600 + 0x00061600, // 112: TDFI_PHYMSTR_MAX_TYPE3_F1:RW:0:32:=0x00061600 + 0x00000000, // 113: PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000 + 0x0000AA68, // 114: TDFI_PHYMSTR_RESP_F1:RW:0:20:=0x00aa68 + 0x00081CC0, // 115: TDFI_PHYMSTR_MAX_F2:RW:0:32:=0x00081cc0 + 0x00081CC0, // 116: TDFI_PHYMSTR_MAX_TYPE0_F2:RW:0:32:=0x00081cc0 + 0x00081CC0, // 117: TDFI_PHYMSTR_MAX_TYPE1_F2:RW:0:32:=0x00081cc0 + 0x00081CC0, // 118: TDFI_PHYMSTR_MAX_TYPE2_F2:RW:0:32:=0x00081cc0 + 0x00081CC0, // 119: TDFI_PHYMSTR_MAX_TYPE3_F2:RW:0:32:=0x00081cc0 + 0x00000000, // 120: PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000 + 0x0000E325, // 121: PHYMSTR_NO_AREF:RW:24:1:=0x00 TDFI_PHYMSTR_RESP_F2:RW:0:20:=0x00e325 + 0x00000000, // 122: PHYMSTR_TRAIN_AFTER_INIT_COMPLETE:RW:16:1:=0x00 PHYMSTR_DFI_VERSION_4P0V1:RW:8:1:=0x00 PHYMSTR_ERROR_STATUS:RD:0:2:=0x00 + 0x00000000, // 123: MRR_TEMPCHK_HIGH_THRESHOLD_F0:RW:16:16:=0x0000 MRR_TEMPCHK_NORM_THRESHOLD_F0:RW:0:16:=0x0000 + 0x00000000, // 124: MRR_TEMPCHK_NORM_THRESHOLD_F1:RW:16:16:=0x0000 MRR_TEMPCHK_TIMEOUT_F0:RW:0:16:=0x0000 + 0x00000000, // 125: MRR_TEMPCHK_TIMEOUT_F1:RW:16:16:=0x0000 MRR_TEMPCHK_HIGH_THRESHOLD_F1:RW:0:16:=0x0000 + 0x00000000, // 126: MRR_TEMPCHK_HIGH_THRESHOLD_F2:RW:16:16:=0x0000 MRR_TEMPCHK_NORM_THRESHOLD_F2:RW:0:16:=0x0000 + 0x00000000, // 127: PPR_COMMAND:WR:24:3:=0x00 PPR_CONTROL:RW:16:1:=0x00 MRR_TEMPCHK_TIMEOUT_F2:RW:0:16:=0x0000 + 0x00000000, // 128: PPR_ROW_ADDRESS:RW:8:17:=0x000000 PPR_COMMAND_MRW:RW:0:8:=0x00 + 0x00000000, // 129: FM_OVRIDE_CONTROL:RW:24:1:=0x00 PPR_STATUS:RD:16:2:=0x00 PPR_CS_ADDRESS:RW:8:1:=0x00 PPR_BANK_ADDRESS:RW:0:3:=0x00 + 0x08030500, // 130: CKSRE_F1:RW:24:8:=0x08 CKSRX_F0:RW:16:8:=0x03 CKSRE_F0:RW:8:8:=0x05 LOWPOWER_REFRESH_ENABLE:RW:0:2:=0x00 + 0x00040B03, // 131: LP_CMD:WR:24:7:=0x00 CKSRX_F2:RW:16:8:=0x04 CKSRE_F2:RW:8:8:=0x0b CKSRX_F1:RW:0:8:=0x03 + 0x0A090000, // 132: LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0:RW:24:4:=0x0a LPI_SR_LONG_WAKEUP_F0:RW:16:4:=0x09 LPI_SR_SHORT_WAKEUP_F0:RW:8:4:=0x00 LPI_CTRL_IDLE_WAKEUP_F0:RW:0:4:=0x00 + 0x0A090701, // 133: LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0:RW:24:4:=0x0a LPI_SRPD_LONG_WAKEUP_F0:RW:16:4:=0x09 LPI_SRPD_SHORT_WAKEUP_F0:RW:8:4:=0x07 LPI_PD_WAKEUP_F0:RW:0:4:=0x01 + 0x0900000E, // 134: LPI_SR_LONG_WAKEUP_F1:RW:24:4:=0x09 LPI_SR_SHORT_WAKEUP_F1:RW:16:4:=0x00 LPI_CTRL_IDLE_WAKEUP_F1:RW:8:4:=0x00 LPI_TIMER_WAKEUP_F0:RW:0:4:=0x0e + 0x0907010A, // 135: LPI_SRPD_LONG_WAKEUP_F1:RW:24:4:=0x09 LPI_SRPD_SHORT_WAKEUP_F1:RW:16:4:=0x07 LPI_PD_WAKEUP_F1:RW:8:4:=0x01 LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1:RW:0:4:=0x0a + 0x00000E0A, // 136: LPI_SR_SHORT_WAKEUP_F2:RW:24:4:=0x00 LPI_CTRL_IDLE_WAKEUP_F2:RW:16:4:=0x00 LPI_TIMER_WAKEUP_F1:RW:8:4:=0x0e LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1:RW:0:4:=0x0a + 0x07010A09, // 137: LPI_SRPD_SHORT_WAKEUP_F2:RW:24:4:=0x07 LPI_PD_WAKEUP_F2:RW:16:4:=0x01 LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2:RW:8:4:=0x0a LPI_SR_LONG_WAKEUP_F2:RW:0:4:=0x09 + 0x000E0A09, // 138: LPI_WAKEUP_EN:RW:24:6:=0x2f LPI_TIMER_WAKEUP_F2:RW:16:4:=0x0e LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2:RW:8:4:=0x0a LPI_SRPD_LONG_WAKEUP_F2:RW:0:4:=0x09 + 0x07000401, // 139: TDFI_LP_RESP:RW:24:3:=0x07 LPI_WAKEUP_TIMEOUT:RW:8:12:=0x0004 LPI_CTRL_REQ_EN:RW:0:1:=0x01 + 0x00000000, // 140: LP_AUTO_EXIT_EN:RW:24:4:=0x00 LP_AUTO_ENTRY_EN:RW:16:4:=0x00 LP_STATE_CS1:RD:8:7:=0x00 LP_STATE_CS0:RD:0:7:=0x00 + 0x00000000, // 141: LP_AUTO_PD_IDLE:RW:8:12:=0x0000 LP_AUTO_MEM_GATE_EN:RW:0:3:=0x00 + 0x00000000, // 142: LP_AUTO_SR_LONG_MC_GATE_IDLE:RW:24:8:=0x00 LP_AUTO_SR_LONG_IDLE:RW:16:8:=0x00 LP_AUTO_SR_SHORT_IDLE:RW:0:12:=0x0000 + 0x00000000, // 143: HW_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 HW_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000 + 0x00000000, // 144: LPC_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0000 HW_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000 + 0x00000000, // 145: LPC_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 LPC_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000 + 0x00000000, // 146: RESERVED:RW:24:1:=0x00 LPC_SR_PHYMSTR_EN:RW:16:1:=0x00 LPC_SR_PHYUPD_EN:RW:8:1:=0x00 LPC_SR_CTRLUPD_EN:RW:0:1:=0x00 + 0x08080100, // 147: PCPCS_PD_EXIT_DEPTH:RW:24:6:=0x08 PCPCS_PD_ENTER_DEPTH:RW:16:6:=0x08 PCPCS_PD_EN:RW:8:1:=0x01 LPC_SR_ZQ_EN:RW:0:1:=0x00 + 0x01000000, // 148: DFS_ENABLE:RW:24:1:=0x01 RESERVED:RW:16:8:=0x00 PCPCS_PD_MASK:RW:8:2:=0x00 PCPCS_PD_ENTER_TIMER:RW:0:8:=0x00 + 0x800000C0, // 149: TDFI_INIT_COMPLETE_F0:RW_D:16:16:=0x8000 TDFI_INIT_START_F0:RW_D:0:10:=0x00c0 + 0x800000C0, // 150: TDFI_INIT_COMPLETE_F1:RW_D:16:16:=0x8000 TDFI_INIT_START_F1:RW_D:0:10:=0x00c0 + 0x800000C0, // 151: TDFI_INIT_COMPLETE_F2:RW_D:16:16:=0x8000 TDFI_INIT_START_F2:RW_D:0:10:=0x00c0 + 0x00000000, // 152: DFS_PHY_REG_WRITE_EN:RW:8:1:=0x00 CURRENT_REG_COPY:RD:0:2:=0x00 + 0x00001500, // 153: DFS_PHY_REG_WRITE_ADDR:RW:0:32:=0x00001500 + 0x00000000, // 154: DFS_PHY_REG_WRITE_DATA_F0:RW:0:32:=0x00000000 + 0x00000001, // 155: DFS_PHY_REG_WRITE_DATA_F1:RW:0:32:=0x00000001 + 0x00000002, // 156: DFS_PHY_REG_WRITE_DATA_F2:RW:0:32:=0x00000002 + 0x0000100E, // 157: DFS_PHY_REG_WRITE_WAIT:RW:8:16:=0x0010 DFS_PHY_REG_WRITE_MASK:RW:0:4:=0x0e + 0x00000000, // 158: WRITE_MODEREG:RW+:0:27:=0x00000000 + 0x00000000, // 159: READ_MODEREG:RW+:8:17:=0x000000 MRW_STATUS:RD:0:8:=0x00 + 0x00000000, // 160: PERIPHERAL_MRR_DATA:RD:0:40:=0x00000000 + 0x00000000, // 161: AUTO_TEMPCHK_VAL_0:RD:8:16:=0x0000 PERIPHERAL_MRR_DATA:RD:0:40:=0x00 + 0x00000000, // 162: DISABLE_UPDATE_TVRCG:RW:16:1:=0x00 AUTO_TEMPCHK_VAL_1:RD:0:16:=0x0000 + 0x000A0000, // 163: TVRCG_ENABLE_F0:RW:16:10:=0x000a MRW_DFS_UPDATE_FRC:RW:0:2:=0x00 + 0x000D0005, // 164: TFC_F0:RW:16:10:=0x000d TVRCG_DISABLE_F0:RW:0:10:=0x0005 + 0x000D0404, // 165: TVREF_LONG_F0:RW:16:16:=0x000d TCKFSPX_F0:RW:8:5:=0x04 TCKFSPE_F0:RW:0:5:=0x04 + 0x00A00140, // 166: TVRCG_DISABLE_F1:RW:16:10:=0x00a0 TVRCG_ENABLE_F1:RW:0:10:=0x0140 + 0x0C0C0190, // 167: TCKFSPX_F1:RW:24:5:=0x0c TCKFSPE_F1:RW:16:5:=0x0c TFC_F1:RW:0:10:=0x0190 + 0x01AB0190, // 168: TVRCG_ENABLE_F2:RW:16:10:=0x01ab TVREF_LONG_F1:RW:0:16:=0x0190 + 0x021600D6, // 169: TFC_F2:RW:16:10:=0x0216 TVRCG_DISABLE_F2:RW:0:10:=0x00d6 + 0x02161010, // 170: TVREF_LONG_F2:RW:16:16:=0x0216 TCKFSPX_F2:RW:8:5:=0x10 TCKFSPE_F2:RW:0:5:=0x10 + 0x00000000, // 171: MRR_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 MRR_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000 + 0x00000000, // 172: MRW_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0000 MRR_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000 + 0x00000000, // 173: MRW_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 MRW_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000 + 0x2D540004, // 174: MR2_DATA_F1_0:RW:24:8:=0x2d MR1_DATA_F1_0:RW:16:8:=0x54 MR2_DATA_F0_0:RW:8:8:=0x00 MR1_DATA_F0_0:RW:0:8:=0x04 + 0x29003F74, // 175: MR3_DATA_F0_0:RW:24:8:=0x31 MRSINGLE_DATA_0:RW:16:8:=0x00 MR2_DATA_F2_0:RW:8:8:=0x3f MR1_DATA_F2_0:RW:0:8:=0x74 + 0x00002929, // 176: MR4_DATA_F1_0:RW:24:8:=0x00 MR4_DATA_F0_0:RW:16:8:=0x00 MR3_DATA_F2_0:RW:8:8:=0x31 MR3_DATA_F1_0:RW:0:8:=0x31 + 0x00040000, // 177: MR11_DATA_F1_0:RW:24:8:=0x00 MR11_DATA_F0_0:RW:16:8:=0x00 MR8_DATA_0:RD:8:8:=0x00 MR4_DATA_F2_0:RW:0:8:=0x00 + 0x17171700, // 178: MR12_DATA_F2_0:RW:24:8:=0x00 MR12_DATA_F1_0:RW:16:8:=0x00 MR12_DATA_F0_0:RW:8:8:=0x00 MR11_DATA_F2_0:RW:0:8:=0x00 + 0x4D4D0F00, // 179: MR14_DATA_F2_0:RW:24:8:=0x00 MR14_DATA_F1_0:RW:16:8:=0x00 MR14_DATA_F0_0:RW:8:8:=0x00 MR13_DATA_0:RW:0:8:=0x00 + 0x05000000, // 180: MR22_DATA_F0_0:RW:24:8:=0x00 MR20_DATA_0:RD:16:8:=0x00 MR17_DATA_0:RW:8:8:=0x00 MR16_DATA_0:RW:0:8:=0x00 + 0x00040505, // 181: MR2_DATA_F0_1:RW:24:8:=0x00 MR1_DATA_F0_1:RW:16:8:=0x04 MR22_DATA_F2_0:RW:8:8:=0x00 MR22_DATA_F1_0:RW:0:8:=0x00 + 0x3F742D54, // 182: MR2_DATA_F2_1:RW:24:8:=0x3f MR1_DATA_F2_1:RW:16:8:=0x74 MR2_DATA_F1_1:RW:8:8:=0x2d MR1_DATA_F1_1:RW:0:8:=0x54 + 0x29292900, // 183: MR3_DATA_F2_1:RW:24:8:=0x31 MR3_DATA_F1_1:RW:16:8:=0x31 MR3_DATA_F0_1:RW:8:8:=0x31 MRSINGLE_DATA_1:RW:0:8:=0x00 + 0x00000000, // 184: MR8_DATA_1:RD:24:8:=0x00 MR4_DATA_F2_1:RW:16:8:=0x00 MR4_DATA_F1_1:RW:8:8:=0x00 MR4_DATA_F0_1:RW:0:8:=0x00 + 0x17000004, // 185: MR12_DATA_F0_1:RW:24:8:=0x00 MR11_DATA_F2_1:RW:16:8:=0x00 MR11_DATA_F1_1:RW:8:8:=0x00 MR11_DATA_F0_1:RW:0:8:=0x00 + 0x0F001717, // 186: MR14_DATA_F0_1:RW:24:8:=0x00 MR13_DATA_1:RW:16:8:=0x00 MR12_DATA_F2_1:RW:8:8:=0x00 MR12_DATA_F1_1:RW:0:8:=0x00 + 0x00004D4D, // 187: MR17_DATA_1:RW:24:8:=0x00 MR16_DATA_1:RW:16:8:=0x00 MR14_DATA_F2_1:RW:8:8:=0x00 MR14_DATA_F1_1:RW:0:8:=0x00 + 0x05050500, // 188: MR22_DATA_F2_1:RW:24:8:=0x00 MR22_DATA_F1_1:RW:16:8:=0x00 MR22_DATA_F0_1:RW:8:8:=0x00 MR20_DATA_1:RD:0:8:=0x00 + 0x00000020, // 189: MR_FSP_DATA_VALID_F2:RW:24:1:=0x00 MR_FSP_DATA_VALID_F1:RW:16:1:=0x00 MR_FSP_DATA_VALID_F0:RW:8:1:=0x00 MR23_DATA:RW:0:8:=0x20 + 0x00000000, // 190: FSP_PHY_UPDATE_MRW:RW:24:1:=0x00 RESERVED:RD:16:1:=0x00 RESERVED:RD:8:1:=0x00 RL3_SUPPORT_EN:RD:0:2:=0x00 + 0x00000001, // 191: FSP_WR_CURRENT:RW+:24:1:=0x00 FSP_OP_CURRENT:RW+:16:1:=0x00 FSP_STATUS:RW:8:1:=0x00 DFS_ALWAYS_WRITE_FSP:RW:0:1:=0x01 + 0x00000000, // 192: FSP1_FRC:RW+:24:2:=0x00 FSP0_FRC:RW+:16:2:=0x00 FSP1_FRC_VALID:RW+:8:1:=0x00 FSP0_FRC_VALID:RW+:0:1:=0x00 + 0x01000000, // 193: BIST_DATA_CHECK:RW:24:1:=0x01 ADDR_SPACE:RW:16:6:=0x00 BIST_RESULT:RD:8:2:=0x00 BIST_GO:WR:0:1:=0x00 + 0x00000001, // 194: BIST_ADDR_CHECK:RW:0:1:=0x01 + 0x00000000, // 195: BIST_START_ADDRESS:RW:0:35:=0x00000000 + 0x00000000, // 196: BIST_START_ADDRESS:RW:0:35:=0x00 + 0x00000000, // 197: BIST_DATA_MASK:RW:0:64:=0x00000000 + 0x00000000, // 198: BIST_DATA_MASK:RW:0:64:=0x00000000 + 0x00000000, // 199: BIST_TEST_MODE:RW:0:3:=0x00 + 0x00000000, // 200: BIST_DATA_PATTERN:RW:0:128:=0x00000000 + 0x00000000, // 201: BIST_DATA_PATTERN:RW:0:128:=0x00000000 + 0x00000000, // 202: BIST_DATA_PATTERN:RW:0:128:=0x00000000 + 0x00000000, // 203: BIST_DATA_PATTERN:RW:0:128:=0x00000000 + 0x00000000, // 204: BIST_ERR_STOP:RW:16:12:=0x0000 BIST_RET_STATE:RD:8:1:=0x00 BIST_RET_STATE_EXIT:WR:0:1:=0x00 + 0x02000000, // 205: INLINE_ECC_BANK_OFFSET:RW:24:3:=0x02 ECC_ENABLE:RW:16:2:=0x00 BIST_ERR_COUNT:RD:0:12:=0x0000 + 0x01080101, // 206: RESERVED:RW:24:1:=0x01 RESERVED:RW:16:4:=0x08 ECC_WRITE_COMBINING_EN:RW:8:1:=0x01 ECC_READ_CACHING_EN:RW:0:1:=0x01 + 0x00000000, // 207: ECC_WRITEBACK_EN:RW:24:1:=0x00 XOR_CHECK_BITS:RW:8:16:=0x0000 FWC:RW+:0:1:=0x00 + 0x00000000, // 208: ECC_DISABLE_W_UC_ERR:RW:0:1:=0x00 + 0x00000000, // 209: ECC_U_ADDR:RD:0:35:=0x00000000 + 0x00000000, // 210: ECC_U_SYND:RD:8:8:=0x00 ECC_U_ADDR:RD:0:35:=0x00 + 0x00000000, // 211: ECC_U_DATA:RD:0:64:=0x00000000 + 0x00000000, // 212: ECC_U_DATA:RD:0:64:=0x00000000 + 0x00000000, // 213: ECC_C_ADDR:RD:0:35:=0x00000000 + 0x00000000, // 214: ECC_C_SYND:RD:8:8:=0x00 ECC_C_ADDR:RD:0:35:=0x00 + 0x00000000, // 215: ECC_C_DATA:RD:0:64:=0x00000000 + 0x00000000, // 216: ECC_C_DATA:RD:0:64:=0x00000000 + 0x00000000, // 217: NON_ECC_REGION_START_ADDR_0:RW:16:15:=0x0000 ECC_C_ID:RD:8:7:=0x00 ECC_U_ID:RD:0:7:=0x00 + 0x00000000, // 218: NON_ECC_REGION_START_ADDR_1:RW:16:15:=0x0000 NON_ECC_REGION_END_ADDR_0:RW:0:15:=0x0000 + 0x00000000, // 219: NON_ECC_REGION_START_ADDR_2:RW:16:15:=0x0000 NON_ECC_REGION_END_ADDR_1:RW:0:15:=0x0000 + 0x00000000, // 220: ECC_SCRUB_START:WR:24:1:=0x00 NON_ECC_REGION_ENABLE:RW:16:3:=0x00 NON_ECC_REGION_END_ADDR_2:RW:0:15:=0x0000 + 0x00001000, // 221: ECC_SCRUB_MODE:RW:24:1:=0x00 ECC_SCRUB_LEN:RW:8:13:=0x0010 ECC_SCRUB_IN_PROGRESS:RD:0:1:=0x00 + 0x006403E8, // 222: ECC_SCRUB_IDLE_CNT:RW:16:16:=0x0064 ECC_SCRUB_INTERVAL:RW:0:16:=0x03e8 + 0x00000000, // 223: ECC_SCRUB_START_ADDR:RW:0:35:=0x00000000 + 0x00000000, // 224: ECC_SCRUB_START_ADDR:RW:0:35:=0x00 + 0x00000000, // 225: ECC_SCRUB_END_ADDR:RW:0:35:=0x00000000 + 0x15110000, // 226: AREF_HIGH_THRESHOLD:RW:24:5:=0x15 AREF_NORM_THRESHOLD:RW:16:5:=0x11 LONG_COUNT_MASK:RW:8:5:=0x00 ECC_SCRUB_END_ADDR:RW:0:35:=0x00 + 0x00040C18, // 227: AREF_CMD_MAX_PER_TREFI:RW:16:4:=0x04 AREF_MAX_CREDIT:RW:8:5:=0x0c AREF_MAX_DEFICIT:RW:0:5:=0x18 + 0x00000000, // 228: ZQ_CALSTART_HIGH_THRESHOLD_F0:RW:16:16:=0x0000 ZQ_CALSTART_NORM_THRESHOLD_F0:RW:0:16:=0x0000 + 0x00000000, // 229: ZQ_CS_NORM_THRESHOLD_F0:RW:16:16:=0x0000 ZQ_CALLATCH_HIGH_THRESHOLD_F0:RW:0:16:=0x0000 + 0x00000000, // 230: ZQ_CALSTART_TIMEOUT_F0:RW:16:16:=0x0000 ZQ_CS_HIGH_THRESHOLD_F0:RW:0:16:=0x0000 + 0x00000000, // 231: ZQ_CS_TIMEOUT_F0:RW:16:16:=0x0000 ZQ_CALLATCH_TIMEOUT_F0:RW:0:16:=0x0000 + 0x00000000, // 232: ZQ_CALSTART_NORM_THRESHOLD_F1:RW:16:16:=0x0000 ZQ_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000 + 0x00000000, // 233: ZQ_CALLATCH_HIGH_THRESHOLD_F1:RW:16:16:=0x0000 ZQ_CALSTART_HIGH_THRESHOLD_F1:RW:0:16:=0x0000 + 0x00000000, // 234: ZQ_CS_HIGH_THRESHOLD_F1:RW:16:16:=0x0000 ZQ_CS_NORM_THRESHOLD_F1:RW:0:16:=0x0000 + 0x00000000, // 235: ZQ_CALLATCH_TIMEOUT_F1:RW:16:16:=0x0000 ZQ_CALSTART_TIMEOUT_F1:RW:0:16:=0x0000 + 0x00000000, // 236: ZQ_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 ZQ_CS_TIMEOUT_F1:RW:0:16:=0x0000 + 0x00000000, // 237: ZQ_CALSTART_HIGH_THRESHOLD_F2:RW:16:16:=0x0000 ZQ_CALSTART_NORM_THRESHOLD_F2:RW:0:16:=0x0000 + 0x00000000, // 238: ZQ_CS_NORM_THRESHOLD_F2:RW:16:16:=0x0000 ZQ_CALLATCH_HIGH_THRESHOLD_F2:RW:0:16:=0x0000 + 0x00000000, // 239: ZQ_CALSTART_TIMEOUT_F2:RW:16:16:=0x0000 ZQ_CS_HIGH_THRESHOLD_F2:RW:0:16:=0x0000 + 0x00000000, // 240: ZQ_CS_TIMEOUT_F2:RW:16:16:=0x0000 ZQ_CALLATCH_TIMEOUT_F2:RW:0:16:=0x0000 + 0x00030000, // 241: RESERVED:RW:16:3:=0x03 ZQ_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000 + 0x00000000, // 242: WATCHDOG_THRESHOLD_BUS_ARB_F0:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_TASK_ARB_F0:RW:0:16:=0x0000 + 0x00000000, // 243: WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_PORT_ARB_F0:RW:0:16:=0x0000 + 0x00000000, // 244: WATCHDOG_THRESHOLD_SPLIT_F0:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_PORT1_CMD_ARB_F0:RW:0:16:=0x0000 + 0x00000000, // 245: WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_STRATEGY_F0:RW:0:16:=0x0000 + 0x00000000, // 246: WATCHDOG_THRESHOLD_READ_DATA_FIFO1_F0:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0:RW:0:16:=0x0000 + 0x00000000, // 247: WATCHDOG_THRESHOLD_TASK_ARB_F1:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0:RW:0:16:=0x0000 + 0x00000000, // 248: WATCHDOG_THRESHOLD_PORT_ARB_F1:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_BUS_ARB_F1:RW:0:16:=0x0000 + 0x00000000, // 249: WATCHDOG_THRESHOLD_PORT1_CMD_ARB_F1:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1:RW:0:16:=0x0000 + 0x00000000, // 250: WATCHDOG_THRESHOLD_STRATEGY_F1:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_SPLIT_F1:RW:0:16:=0x0000 + 0x00000000, // 251: WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1:RW:0:16:=0x0000 + 0x00000000, // 252: WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_READ_DATA_FIFO1_F1:RW:0:16:=0x0000 + 0x00000000, // 253: WATCHDOG_THRESHOLD_BUS_ARB_F2:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_TASK_ARB_F2:RW:0:16:=0x0000 + 0x00000000, // 254: WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_PORT_ARB_F2:RW:0:16:=0x0000 + 0x00000000, // 255: WATCHDOG_THRESHOLD_SPLIT_F2:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_PORT1_CMD_ARB_F2:RW:0:16:=0x0000 + 0x00000000, // 256: WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_STRATEGY_F2:RW:0:16:=0x0000 + 0x00000000, // 257: WATCHDOG_THRESHOLD_READ_DATA_FIFO1_F2:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2:RW:0:16:=0x0000 + 0x00000000, // 258: WATCHDOG_RELOAD:WR:16:11:=0x0000 WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2:RW:0:16:=0x0000 + 0x00000000, // 259: WATCHDOG_DIAGNOSTIC_MODE:RW:0:11:=0x0000 + 0x00000000, // 260: TIMEOUT_TIMER_LOG:RD:0:19:=0x000000 + 0x01000200, // 261: ZQCL_F0:RW:16:12:=0x0100 ZQINIT_F0:RW_D:0:12:=0x0200 + 0x00320040, // 262: TZQCAL_F0:RW:16:12:=0x0032 ZQCS_F0:RW:0:12:=0x0040 + 0x00020002, // 263: ZQINIT_F1:RW_D:8:12:=0x0200 TZQLAT_F0:RW:0:7:=0x02 + 0x00400100, // 264: ZQCS_F1:RW:16:12:=0x0040 ZQCL_F1:RW:0:12:=0x0100 + 0x00300640, // 265: TZQLAT_F1:RW:16:7:=0x30 TZQCAL_F1:RW:0:12:=0x0640 + 0x01000200, // 266: ZQCL_F2:RW:16:12:=0x0100 ZQINIT_F2:RW_D:0:12:=0x0200 + 0x08550040, // 267: TZQCAL_F2:RW:16:12:=0x0855 ZQCS_F2:RW:0:12:=0x0040 + 0x00000040, // 268: ZQ_REQ_PENDING:RD:24:1:=0x00 ZQ_REQ:WR:16:4:=0x00 ZQ_SW_REQ_START_LATCH_MAP:RW:8:2:=0x00 TZQLAT_F2:RW:0:7:=0x40 + 0x00500003, // 269: ZQRESET_F1:RW:16:12:=0x0050 ZQRESET_F0:RW:0:12:=0x0003 + 0x0100006B, // 270: ZQCS_ROTATE:RW:24:1:=0x01 NO_ZQ_INIT:RW:16:1:=0x00 ZQRESET_F2:RW:0:12:=0x006b + 0x00000000, // 271: ZQ_CAL_LATCH_MAP_1:RW_D:24:2:=0x00 ZQ_CAL_START_MAP_1:RW_D:16:2:=0x00 ZQ_CAL_LATCH_MAP_0:RW_D:8:2:=0x00 ZQ_CAL_START_MAP_0:RW_D:0:2:=0x00 + 0x01010000, // 272: ROW_DIFF_1:RW:24:3:=0x00 ROW_DIFF_0:RW:16:3:=0x00 BANK_DIFF_1:RW:8:2:=0x00 BANK_DIFF_0:RW:0:2:=0x00 + 0x00000202, // 273: CS_VAL_LOWER_0:RW:16:16:=0x0000 COL_DIFF_1:RW:8:4:=0x02 COL_DIFF_0:RW:0:4:=0x02 + 0x00000FFF, // 274: ROW_START_VAL_0:RW:16:3:=0x00 CS_VAL_UPPER_0:RW:0:16:=0x0fff + 0x1FFF1000, // 275: CS_VAL_UPPER_1:RW:16:16:=0x3fff CS_VAL_LOWER_1:RW:0:16:=0x2000 + 0x01FF0000, // 276: CS_MSK_0:RW:16:16:=0x03ff CS_MAP_NON_POW2:RW:8:2:=0x00 ROW_START_VAL_1:RW:0:3:=0x00 + 0x000001FF, // 277: RESERVED:RW:24:5:=0x00 CS_LOWER_ADDR_EN:RW:16:1:=0x00 CS_MSK_1:RW:0:16:=0x03ff + 0xFFFF0B00, // 278: COMMAND_AGE_COUNT:RW:24:8:=0xff AGE_COUNT:RW:16:8:=0xff APREBIT:RW_D:8:5:=0x0b RESERVED:RW:0:1:=0x00 + 0x01010001, // 279: PLACEMENT_EN:RW:24:1:=0x01 BANK_SPLIT_EN:RW:16:1:=0x01 ADDR_COLLISION_MPM_DIS:RW:8:1:=0x00 ADDR_CMP_EN:RW:0:1:=0x01 + 0x01010101, // 280: CS_SAME_EN:RW:24:1:=0x01 RW_SAME_PAGE_EN:RW:16:1:=0x01 RW_SAME_EN:RW:8:1:=0x01 PRIORITY_EN:RW:0:1:=0x01 + 0x01180101, // 281: SWAP_EN:RW:24:1:=0x01 NUM_Q_ENTRIES_ACT_DISABLE:RW:16:5:=0x18 DISABLE_RW_GROUP_W_BNK_CONFLICT:RW:8:2:=0x01 W2R_SPLIT_EN:RW:0:1:=0x01 + 0x00030000, // 282: REDUC:RW:24:1:=0x00 CS_MAP:RW:16:2:=0x03 INHIBIT_DRAM_CMD:RW:8:2:=0x00 DISABLE_RD_INTERLEAVE:RW:0:1:=0x00 + 0x00000000, // 283: + 0x00000000, // 284: + 0x00000000, // 285: + 0x00000000, // 286: READ_ADDR_CHAN_PARITY_EN:RW:24:1:=0x00 WRITE_RESP_CHAN_PARITY_EN:RW:16:1:=0x00 WRITE_DATA_CHAN_PARITY_EN:RW:8:2:=0x00 WRITE_ADDR_CHAN_PARITY_EN:RW:0:1:=0x00 + 0x00000000, // 287: WRITE_PARITY_ERR_BRESP_EN:RW:24:1:=0x00 RESERVED:RW:16:1:=0x00 RESERVED:RW:8:1:=0x00 READ_DATA_CHAN_PARITY_EN:RW:0:1:=0x00 + 0x00000000, // 288: WRITE_RESP_CHAN_CORRUPT_PARITY_EN:RW:24:1:=0x00 WRITE_DATA_CHAN_TRIGGER_PARITY_EN:RW:16:1:=0x00 WRITE_ADDR_CHAN_TRIGGER_PARITY_EN:RW:8:1:=0x00 READ_PARITY_ERR_RRESP_EN:RW:0:1:=0x00 + 0x00000000, // 289: WRITE_PARITY_ERR_CORRUPT_ECC_EN:RW:24:1:=0x00 ECC_AXI_ERROR_RESPONSE_INHIBIT:RW:16:1:=0x00 READ_DATA_CHAN_CORRUPT_PARITY_EN:RW:8:1:=0x00 READ_ADDR_CHAN_TRIGGER_PARITY_EN:RW:0:1:=0x00 + 0x04010100, // 290: DEVICE1_BYTE0_CS0:RW:24:4:=0x04 DEVICE0_BYTE0_CS0:RW:16:4:=0x01 MEMDATA_RATIO_0:RW:8:3:=0x01 ENHANCED_PARITY_PROTECTION_EN:RW:0:1:=0x00 + 0x01010000, // 291: DEVICE0_BYTE0_CS1:RW:24:4:=0x01 MEMDATA_RATIO_1:RW:16:3:=0x01 DEVICE3_BYTE0_CS0:RW:8:4:=0x00 DEVICE2_BYTE0_CS0:RW:0:4:=0x00 + 0x00000004, // 292: Q_FULLNESS:RW:24:5:=0x00 DEVICE3_BYTE0_CS1:RW:16:4:=0x00 DEVICE2_BYTE0_CS1:RW:8:4:=0x00 DEVICE1_BYTE0_CS1:RW:0:4:=0x04 + 0x00000000, // 293: CTRLUPD_REQ:WR:24:1:=0x00 CONTROLLER_BUSY:RD:16:1:=0x00 WR_ORDER_REQ:RW:8:2:=0x00 IN_ORDER_ACCEPT:RW:0:1:=0x00 + 0x03030000, // 294: PREAMBLE_SUPPORT_F1:RW:24:2:=0x03 PREAMBLE_SUPPORT_F0:RW:16:2:=0x03 CTRLUPD_AREF_HP_ENABLE:RW:8:1:=0x00 CTRLUPD_REQ_PER_AREF_EN:RW:0:1:=0x00 + 0x01010103, // 295: RD_DBI_EN:RW:24:1:=0x00 WR_DBI_EN:RW:16:1:=0x00 RD_PREAMBLE_TRAINING_EN:RW:8:1:=0x01 PREAMBLE_SUPPORT_F2:RW:0:2:=0x03 + 0x00000000, // 296: DFI_ERROR_INFO:RD:8:20:=0x000000 DFI_ERROR:RD:0:5:=0x00 + 0x00000000, // 297: RESERVED:WR:0:1:=0x00 + 0x00000000, // 298: INT_STATUS:RD:0:36:=0x00000000 + 0x00000000, // 299: INT_STATUS:RD:0:36:=0x00 + 0x00000000, // 300: INT_ACK:WR:0:35:=0x00000000 + 0x00000000, // 301: INT_ACK:WR:0:35:=0x00 + 0x00000000, // 302: INT_MASK:RW:0:36:=0x00000000 + 0x00000000, // 303: INT_MASK:RW:0:36:=0x00 + 0x00000000, // 304: OUT_OF_RANGE_ADDR:RD:0:35:=0x00000000 + 0x00000000, // 305: OUT_OF_RANGE_TYPE:RD:24:7:=0x00 OUT_OF_RANGE_LENGTH:RD:8:13:=0x0000 OUT_OF_RANGE_ADDR:RD:0:35:=0x00 + 0x00000000, // 306: OUT_OF_RANGE_SOURCE_ID:RD:0:7:=0x00 + 0x00000000, // 307: BIST_EXP_DATA:RD:0:128:=0x00000000 + 0x00000000, // 308: BIST_EXP_DATA:RD:0:128:=0x00000000 + 0x00000000, // 309: BIST_EXP_DATA:RD:0:128:=0x00000000 + 0x00000000, // 310: BIST_EXP_DATA:RD:0:128:=0x00000000 + 0x00000000, // 311: BIST_FAIL_DATA:RD:0:128:=0x00000000 + 0x00000000, // 312: BIST_FAIL_DATA:RD:0:128:=0x00000000 + 0x00000000, // 313: BIST_FAIL_DATA:RD:0:128:=0x00000000 + 0x00000000, // 314: BIST_FAIL_DATA:RD:0:128:=0x00000000 + 0x00000000, // 315: BIST_FAIL_ADDR:RD:0:35:=0x00000000 + 0x00000000, // 316: BIST_FAIL_ADDR:RD:0:35:=0x00 + 0x00000000, // 317: PORT_CMD_ERROR_ADDR:RD:0:35:=0x00000000 + 0x01000000, // 318: ODT_RD_MAP_CS0:RW:24:2:=0x01 PORT_CMD_ERROR_TYPE:RD:16:2:=0x00 PORT_CMD_ERROR_ID:RD:8:7:=0x00 PORT_CMD_ERROR_ADDR:RD:0:35:=0x00 + 0x00020201, // 319: TODTL_2CMD_F0:RW:24:8:=0x00 ODT_WR_MAP_CS1:RW:16:2:=0x02 ODT_RD_MAP_CS1:RW:8:2:=0x02 ODT_WR_MAP_CS0:RW:0:2:=0x01 + 0x01000101, // 320: TODTH_WR_F1:RW:24:4:=0x01 TODTL_2CMD_F1:RW:16:8:=0x00 TODTH_RD_F0:RW:8:4:=0x01 TODTH_WR_F0:RW:0:4:=0x01 + 0x01010001, // 321: TODTH_RD_F2:RW:24:4:=0x01 TODTH_WR_F2:RW:16:4:=0x01 TODTL_2CMD_F2:RW:8:8:=0x00 TODTH_RD_F1:RW:0:4:=0x01 + 0x00010101, // 322: EN_ODT_ASSERT_EXCEPT_RD:RW:24:1:=0x00 ODT_EN_F2:RW:16:1:=0x01 ODT_EN_F1:RW:8:1:=0x01 ODT_EN_F0:RW:0:1:=0x01 + 0x050A0803, // 323: RD_TO_ODTH_F0:RW:24:6:=0x05 WR_TO_ODTH_F2:RW:16:6:=0x0a WR_TO_ODTH_F1:RW:8:6:=0x08 WR_TO_ODTH_F0:RW:0:6:=0x03 + 0x0C081F18, // 324: RW2MRW_DLY_F1:RW_D:24:5:=0x0c RW2MRW_DLY_F0:RW_D:16:5:=0x08 RD_TO_ODTH_F2:RW:8:6:=0x1f RD_TO_ODTH_F1:RW:0:6:=0x18 + 0x00080210, // 325: W2R_DIFFCS_DLY_F0:RW_D:24:5:=0x00 R2W_DIFFCS_DLY_F0:RW_D:16:5:=0x08 R2R_DIFFCS_DLY_F0:RW_D:8:5:=0x02 RW2MRW_DLY_F2:RW_D:0:5:=0x10 + 0x0A0A020E, // 326: W2R_DIFFCS_DLY_F1:RW_D:24:5:=0x0a R2W_DIFFCS_DLY_F1:RW_D:16:5:=0x0a R2R_DIFFCS_DLY_F1:RW_D:8:5:=0x02 W2W_DIFFCS_DLY_F0:RW_D:0:5:=0x0e + 0x0C0B0206, // 327: W2R_DIFFCS_DLY_F2:RW_D:24:5:=0x0c R2W_DIFFCS_DLY_F2:RW_D:16:5:=0x0b R2R_DIFFCS_DLY_F2:RW_D:8:5:=0x02 W2W_DIFFCS_DLY_F1:RW_D:0:5:=0x06 + 0x0A080007, // 328: R2W_SAMECS_DLY_F1:RW_D:24:5:=0x0a R2W_SAMECS_DLY_F0:RW_D:16:5:=0x08 R2R_SAMECS_DLY:RW:8:5:=0x00 W2W_DIFFCS_DLY_F2:RW_D:0:5:=0x07 + 0x0100000B, // 329: TDQSCK_MAX_F0:RW:24:4:=0x01 W2W_SAMECS_DLY:RW:16:5:=0x00 W2R_SAMECS_DLY:RW:8:5:=0x00 R2W_SAMECS_DLY_F2:RW_D:0:5:=0x0b + 0x08030601, // 330: TDQSCK_MAX_F2:RW:24:4:=0x08 TDQSCK_MIN_F1:RW:16:3:=0x03 TDQSCK_MAX_F1:RW:8:4:=0x06 TDQSCK_MIN_F0:RW:0:3:=0x01 + 0x04000004, // 331: AXI0_R_PRIORITY:RW:24:3:=0x04 AXI0_FIXED_PORT_PRIORITY_ENABLE:RW:16:1:=0x00 AXI0_ALL_STROBES_USED_ENABLE:RW:8:1:=0x00 TDQSCK_MIN_F2:RW:0:3:=0x04 + 0x04000004, // 332: AXI1_R_PRIORITY:RW:24:3:=0x04 AXI1_FIXED_PORT_PRIORITY_ENABLE:RW:16:1:=0x00 AXI1_ALL_STROBES_USED_ENABLE:RW:8:1:=0x00 AXI0_W_PRIORITY:RW:0:3:=0x04 + 0x00000004, // 333: AXI1_W_PRIORITY:RW:0:3:=0x04 + 0x00000000, // 334: PARITY_ERROR_ADDRESS:RD:0:35:=0x00000000 + 0x00000000, // 335: PARITY_ERROR_BUS_CHANNEL:RD:16:13:=0x0000 PARITY_ERROR_MASTER_ID:RD:8:7:=0x00 PARITY_ERROR_ADDRESS:RD:0:35:=0x00 + 0x00000000, // 336: PARITY_ERROR_WRITE_DATA:RD:0:128:=0x00000000 + 0x00000000, // 337: PARITY_ERROR_WRITE_DATA:RD:0:128:=0x00000000 + 0x00000000, // 338: PARITY_ERROR_WRITE_DATA:RD:0:128:=0x00000000 + 0x00000000, // 339: PARITY_ERROR_WRITE_DATA:RD:0:128:=0x00000000 + 0x00000000, // 340: WEIGHTED_ROUND_ROBIN_WEIGHT_SHARING:RW:24:1:=0x00 WEIGHTED_ROUND_ROBIN_LATENCY_CONTROL:RW:16:1:=0x00 PARITY_ERROR_WRITE_DATA_PARITY_VECTOR:RD:0:16:=0x0000 + 0x02020200, // 341: AXI0_PRIORITY2_RELATIVE_PRIORITY:RW:24:4:=0x02 AXI0_PRIORITY1_RELATIVE_PRIORITY:RW:16:4:=0x02 AXI0_PRIORITY0_RELATIVE_PRIORITY:RW:8:4:=0x02 WRR_PARAM_VALUE_ERR:RD:0:4:=0x00 + 0x02020202, // 342: AXI0_PRIORITY6_RELATIVE_PRIORITY:RW:24:4:=0x02 AXI0_PRIORITY5_RELATIVE_PRIORITY:RW:16:4:=0x02 AXI0_PRIORITY4_RELATIVE_PRIORITY:RW:8:4:=0x02 AXI0_PRIORITY3_RELATIVE_PRIORITY:RW:0:4:=0x02 + 0x00640002, // 343: AXI0_PRIORITY_RELAX:RW:16:10:=0x0064 AXI0_PORT_ORDERING:RW:8:1:=0x00 AXI0_PRIORITY7_RELATIVE_PRIORITY:RW:0:4:=0x02 + 0x01010101, // 344: AXI1_PRIORITY3_RELATIVE_PRIORITY:RW:24:4:=0x01 AXI1_PRIORITY2_RELATIVE_PRIORITY:RW:16:4:=0x01 AXI1_PRIORITY1_RELATIVE_PRIORITY:RW:8:4:=0x01 AXI1_PRIORITY0_RELATIVE_PRIORITY:RW:0:4:=0x01 + 0x01010101, // 345: AXI1_PRIORITY7_RELATIVE_PRIORITY:RW:24:4:=0x01 AXI1_PRIORITY6_RELATIVE_PRIORITY:RW:16:4:=0x01 AXI1_PRIORITY5_RELATIVE_PRIORITY:RW:8:4:=0x01 AXI1_PRIORITY4_RELATIVE_PRIORITY:RW:0:4:=0x01 + 0x00006401, // 346: CKE_STATUS:RD:24:2:=0x00 AXI1_PRIORITY_RELAX:RW:8:10:=0x0064 AXI1_PORT_ORDERING:RW:0:1:=0x01 + 0x00000000, // 347: DLL_RST_ADJ_DLY:RW:24:8:=0x00 DLL_RST_DELAY:RW:8:16:=0x0000 MEM_RST_VALID:RD:0:1:=0x00 + 0x321B0000, // 348: TDFI_PHY_RDLAT_F1:RW_D:24:7:=0x32 TDFI_PHY_RDLAT_F0:RW_D:16:7:=0x1b UPDATE_ERROR_STATUS:RD:8:7:=0x00 TDFI_PHY_WRLAT:RD:0:7:=0x00 + 0x0A00003A, // 349: TDFI_CTRLUPD_MIN:RW:24:8:=0x0a DRAM_CLK_DISABLE:RW:16:2:=0x00 TDFI_RDDATA_EN:RD:8:7:=0x00 TDFI_PHY_RDLAT_F2:RW_D:0:7:=0x3a + 0x00000176, // 350: TDFI_CTRLUPD_MAX_F0:RW:0:21:=0x000176 + 0x00000200, // 351: TDFI_PHYUPD_TYPE0_F0:RW:0:32:=0x00000200 + 0x00000200, // 352: TDFI_PHYUPD_TYPE1_F0:RW:0:32:=0x00000200 + 0x00000200, // 353: TDFI_PHYUPD_TYPE2_F0:RW:0:32:=0x00000200 + 0x00000200, // 354: TDFI_PHYUPD_TYPE3_F0:RW:0:32:=0x00000200 + 0x00000462, // 355: TDFI_PHYUPD_RESP_F0:RW:0:23:=0x000462 + 0x00000E9C, // 356: TDFI_CTRLUPD_INTERVAL_F0:RW:0:32:=0x00000e9c + 0x00000204, // 357: WRLAT_ADJ_F0:RW:8:7:=0x02 RDLAT_ADJ_F0:RW:0:7:=0x04 + 0x000030B0, // 358: TDFI_CTRLUPD_MAX_F1:RW:0:21:=0x0030b0 + 0x00000200, // 359: TDFI_PHYUPD_TYPE0_F1:RW:0:32:=0x00000200 + 0x00000200, // 360: TDFI_PHYUPD_TYPE1_F1:RW:0:32:=0x00000200 + 0x00000200, // 361: TDFI_PHYUPD_TYPE2_F1:RW:0:32:=0x00000200 + 0x00000200, // 362: TDFI_PHYUPD_TYPE3_F1:RW:0:32:=0x00000200 + 0x00009210, // 363: TDFI_PHYUPD_RESP_F1:RW:0:23:=0x009210 + 0x0001E6E0, // 364: TDFI_CTRLUPD_INTERVAL_F1:RW:0:32:=0x0001e6e0 + 0x00000A10, // 365: WRLAT_ADJ_F1:RW:8:7:=0x0a RDLAT_ADJ_F1:RW:0:7:=0x10 + 0x000040E6, // 366: TDFI_CTRLUPD_MAX_F2:RW:0:21:=0x0040e6 + 0x00000200, // 367: TDFI_PHYUPD_TYPE0_F2:RW:0:32:=0x00000200 + 0x00000200, // 368: TDFI_PHYUPD_TYPE1_F2:RW:0:32:=0x00000200 + 0x00000200, // 369: TDFI_PHYUPD_TYPE2_F2:RW:0:32:=0x00000200 + 0x00000200, // 370: TDFI_PHYUPD_TYPE3_F2:RW:0:32:=0x00000200 + 0x0000C2B2, // 371: TDFI_PHYUPD_RESP_F2:RW:0:23:=0x00c2b2 + 0x000288FC, // 372: TDFI_CTRLUPD_INTERVAL_F2:RW:0:32:=0x000288fc + 0x02020E15, // 373: TDFI_CTRL_DELAY_F1:RW_D:24:4:=0x02 TDFI_CTRL_DELAY_F0:RW_D:16:4:=0x02 WRLAT_ADJ_F2:RW:8:7:=0x0e RDLAT_ADJ_F2:RW:0:7:=0x15 + 0x02030202, // 374: TDFI_PHY_WRDATA_F0:RW:24:3:=0x02 TDFI_DRAM_CLK_ENABLE:RW:16:4:=0x03 TDFI_DRAM_CLK_DISABLE:RW:8:4:=0x02 TDFI_CTRL_DELAY_F2:RW_D:0:4:=0x02 + 0x01000404, // 375: TDFI_WRCSLAT_F0:RW:24:7:=0x01 TDFI_RDCSLAT_F0:RW:16:7:=0x00 TDFI_PHY_WRDATA_F2:RW:8:3:=0x04 TDFI_PHY_WRDATA_F1:RW:0:3:=0x04 + 0x0B1E0716, // 376: TDFI_WRCSLAT_F2:RW:24:7:=0x0b TDFI_RDCSLAT_F2:RW:16:7:=0x1e TDFI_WRCSLAT_F1:RW:8:7:=0x07 TDFI_RDCSLAT_F1:RW:0:7:=0x16 + 0x00010105, // 377: BL_ON_FLY_ENABLE:RW_D:24:1:=0x00 DISABLE_MEMORY_MASKED_WRITE:RW_D:16:1:=0x01 EN_1T_TIMING:RW:8:1:=0x01 TDFI_WRDATA_DELAY:RW:0:8:=0x05 + 0x00010101, // 378: RESERVED:RW_D:24:3:=0x00 RESERVED:RW_D:16:3:=0x01 RESERVED:RW_D:8:3:=0x01 RESERVED:RW_D:0:1:=0x01 + 0x00010101, // 379: RESERVED:RW_D:24:4:=0x00 RESERVED:RW_D:16:3:=0x01 RESERVED:RW_D:8:3:=0x01 RESERVED:RW_D:0:3:=0x01 + 0x00010001, // 380: RESERVED:RW_D:24:4:=0x00 RESERVED:RW_D:16:4:=0x01 RESERVED:RW_D:8:4:=0x00 RESERVED:RW_D:0:4:=0x01 + 0x00000101, // 381: RESERVED:RW_D:24:4:=0x00 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x01 RESERVED:RW_D:0:4:=0x01 + 0x02000201, // 382: RESERVED:RW_D:24:4:=0x02 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x02 RESERVED:RW_D:0:4:=0x01 + 0x02010000, // 383: RESERVED:RW_D:24:4:=0x02 RESERVED:RW_D:16:4:=0x01 RESERVED:RW_D:8:4:=0x00 RESERVED:RW_D:0:4:=0x00 + 0x00000200, // 384: GLOBAL_ERROR_INFO:RW+:24:8:=0x00 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x02 RESERVED:RW_D:0:4:=0x00 + 0x1E060000, // 385: NWR_F1:RW:24:8:=0x1e NWR_F0:RW:16:8:=0x06 AXI_PARITY_ERROR_STATUS:RD:8:2:=0x00 GLOBAL_ERROR_MASK:RW:0:8:=0x00 + 0x00000128, // 386: REGPORT_PARAM_PARITY_PROTECTION_STATUS:RD:16:5:=0x00 RESERVED:RW_D:8:1:=0x01 NWR_F2:RW:0:8:=0x28 + 0xFFFFFFFF, // 387: MC_PARITY_INJECTION_BYTE_ENABLE:RW:0:64:=0xFFFFFFFF + 0xFFFFFFFF, // 388: MC_PARITY_INJECTION_BYTE_ENABLE:RW:0:64:=0xFFFFFFFF + 0x00000000, // 389: REGPORT_WRITE_PARITY_PROTECTION_EN:RW:24:1:=0x00 REGPORT_WRITEMASK_PARITY_PROTECTION_EN:RW:16:1:=0x00 REGPORT_ADDR_PARITY_PROTECTION_EN:RW:8:1:=0x00 MC_PARITY_ERROR_TYPE:RW:0:1:=0x00 + 0x00000000, // 390: REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN:RW:24:1:=0x00 REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN:RW:16:1:=0x00 PARAMREG_PARITY_PROTECTION_EN:RW:8:1:=0x00 REGPORT_READ_PARITY_PROTECTION_EN:RW:0:1:=0x00 + 0x00000000, // 391: PARAMREG_PARITY_PROTECTION_INJECTION_EN:RW:16:1:=0x00 REGPORT_READ_PARITY_PROTECTION_INJECTION_EN:RW:8:1:=0x00 REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN:RW:0:1:=0x00 + 0x00000000, // 392: RESERVED:RD:0:96:=0x00000000 + 0x00000000, // 393: RESERVED:RD:0:96:=0x00000000 + 0x00000000, // 394: RESERVED:RD:0:96:=0x00000000 + 0x00000000, // 395: PORT_TO_CORE_PROTECTION_EN:RW:0:1:=0x00 + 0x00000000, // 396: PORT_TO_CORE_PROTECTION_INJECTION_EN:RW:0:96:=0x00000000 + 0x00000000, // 397: PORT_TO_CORE_PROTECTION_INJECTION_EN:RW:0:96:=0x00000000 + 0x00000000, // 398: PORT_TO_CORE_PROTECTION_INJECTION_EN:RW:0:96:=0x00000000 + 0x00000000, // 399: RESERVED:RD:0:134:=0x00000000 + 0x00000000, // 400: RESERVED:RD:0:134:=0x00000000 + 0x00000000, // 401: RESERVED:RD:0:134:=0x00000000 + 0x00000000, // 402: RESERVED:RD:0:134:=0x00000000 + 0x00000000, // 403: RESERVED:RD:0:134:=0x00 + 0x00000000, // 404: PORT_TO_CORE_LR_ERR_INJ_EN:RW:0:134:=0x00000000 + 0x00000000, // 405: PORT_TO_CORE_LR_ERR_INJ_EN:RW:0:134:=0x00000000 + 0x00000000, // 406: PORT_TO_CORE_LR_ERR_INJ_EN:RW:0:134:=0x00000000 + 0x00000000, // 407: PORT_TO_CORE_LR_ERR_INJ_EN:RW:0:134:=0x00000000 + 0x00000000, // 408: PORT_TO_CORE_LR_ERR_INJ_EN:RW:0:134:=0x00 + 0x00000000, // 409: FAULT_FIFO_PROTECTION_EN:RW:0:55:=0x00000000 + 0x00000000, // 410: FAULT_FIFO_PROTECTION_EN:RW:0:55:=0x000000 + 0x00000000, // 411: FAULT_FIFO_PROTECTION_STATUS:RD:0:55:=0x00000000 + 0x00000000, // 412: FAULT_FIFO_PROTECTION_STATUS:RD:0:55:=0x000000 + 0x00000000, // 413: FAULT_FIFO_PROTECTION_INJECTION_EN:RW:0:55:=0x00000000 + 0x00000000 // 414: FAULT_FIFO_PROTECTION_INJECTION_EN:RW:0:55:=0x000000 +}; + + +uint32_t DDR_PI_registers[] = +{ + 0x00000B00, // 0: PI_DRAM_CLASS:RW:8:4:=0x0b PI_START:RW:0:1:=0x00 + 0x00000000, // 1: PI_VERSION:RD:0:64:=0x00000000 + 0x00000000, // 2: PI_VERSION:RD:0:64:=0x00000000 + 0x00000000, // 3: PI_ID:RD:0:16:=0x0000 + 0x00000000, // 4: + 0x00000101, // 5: PI_NOTCARE_PHYUPD:RW:16:1:=0x00 PI_INIT_LVL_EN:RW:8:1:=0x01 PI_NORMAL_LVL_SEQ:RW:0:1:=0x01 + 0x00640000, // 6: PI_TRAIN_ALL_FREQ_REQ:WR:24:1:=0x00 RESERVED:RW_D:16:8:=0x64 PI_TCMD_GAP:RW:0:16:=0x0000 + 0x00000001, // 7: PI_DFI_PHYMSTR_STATE_SEL_R:RW:24:1:=0x00 PI_DFI_PHYMSTR_CS_STATE_R:RW:16:1:=0x00 PI_DFI_PHYMSTR_TYPE:RW:8:2:=0x00 PI_DFI_VERSION:RW:0:1:=0x01 + 0x00000000, // 8: PI_TDFI_PHYMSTR_MAX:RD:0:32:=0x00000000 + 0x00000000, // 9: PI_TDFI_PHYMSTR_RESP:RD:0:20:=0x000000 + 0x00000000, // 10: PI_TDFI_PHYUPD_RESP:RD:0:20:=0x000000 + 0x00000000, // 11: PI_TDFI_PHYUPD_MAX:RD:0:32:=0x00000000 + 0x00000003, // 12: PI_FREQ_MAP:RW:0:32:=0x00000001 + 0x00010001, // 13: RESERVED:RW:24:1:=0x00 PI_SW_RST_N:RW_D:16:1:=0x01 PI_INIT_DFS_CALVL_ONLY:RW:8:1:=0x00 PI_INIT_WORK_FREQ:RW:0:5:=0x00 + 0x0800000F, // 14: PI_TMRR:RW:24:4:=0x08 PI_SRX_LVL_TARGET_CS_EN:RW:16:1:=0x00 PI_RANK_NUM_PER_CKE:RW:8:5:=0x00 PI_CS_MAP:RW:0:4:=0x0f + 0x00000103, // 15: RESERVED:RW:16:1:=0x00 PI_MCAREF_FORWARD_ONLY:RW:8:1:=0x01 PI_PREAMBLE_SUPPORT:RW:0:2:=0x03 + 0x00000005, // 16: PI_ON_DFIBUS:RD:24:1:=0x00 PI_TREF_INTERVAL:RW:0:20:=0x000005 + 0x00000000, // 17: PI_SW_WRLVL_RESP_0:RD:24:1:=0x00 PI_SWLVL_OP_DONE:RD:16:1:=0x00 PI_SWLVL_LOAD:WR:8:1:=0x00 PI_DATA_RETENTION:RD:0:1:=0x00 + 0x00000000, // 18: PI_SW_RDLVL_RESP_0:RD:24:2:=0x00 PI_SW_WRLVL_RESP_3:RD:16:1:=0x00 PI_SW_WRLVL_RESP_2:RD:8:1:=0x00 PI_SW_WRLVL_RESP_1:RD:0:1:=0x00 + 0x00000000, // 19: PI_SW_CALVL_RESP_0:RD:24:2:=0x00 PI_SW_RDLVL_RESP_3:RD:16:2:=0x00 PI_SW_RDLVL_RESP_2:RD:8:2:=0x00 PI_SW_RDLVL_RESP_1:RD:0:2:=0x00 + 0x00000000, // 20: PI_SWLVL_WR_SLICE_0:WR:24:1:=0x00 PI_SWLVL_EXIT:WR:16:1:=0x00 PI_SWLVL_START:WR:8:1:=0x00 PI_SW_LEVELING_MODE:RW:0:3:=0x00 + 0x00000000, // 21: PI_SWLVL_WR_SLICE_1:WR:24:1:=0x00 PI_SW_WDQLVL_RESP_0:RD:16:2:=0x00 PI_SWLVL_VREF_UPDATE_SLICE_0:WR:8:1:=0x00 PI_SWLVL_RD_SLICE_0:WR:0:1:=0x00 + 0x00000000, // 22: PI_SWLVL_WR_SLICE_2:WR:24:1:=0x00 PI_SW_WDQLVL_RESP_1:RD:16:2:=0x00 PI_SWLVL_VREF_UPDATE_SLICE_1:WR:8:1:=0x00 PI_SWLVL_RD_SLICE_1:WR:0:1:=0x00 + 0x00000000, // 23: PI_SWLVL_WR_SLICE_3:WR:24:1:=0x00 PI_SW_WDQLVL_RESP_2:RD:16:2:=0x00 PI_SWLVL_VREF_UPDATE_SLICE_2:WR:8:1:=0x00 PI_SWLVL_RD_SLICE_2:WR:0:1:=0x00 + 0x00000000, // 24: PI_SWLVL_SM2_START:WR:24:1:=0x00 PI_SW_WDQLVL_RESP_3:RD:16:2:=0x00 PI_SWLVL_VREF_UPDATE_SLICE_3:WR:8:1:=0x00 PI_SWLVL_RD_SLICE_3:WR:0:1:=0x00 + 0x00000000, // 25: PI_DFS_PERIOD_EN:RW:24:1:=0x00 PI_SEQUENTIAL_LVL_REQ:WR:16:1:=0x00 PI_SWLVL_SM2_RD:WR:8:1:=0x00 PI_SWLVL_SM2_WR:WR:0:1:=0x00 + 0x00010100, // 26: PI_WRLVL_REQ:WR:24:1:=0x00 PI_16BIT_DRAM_CONNECT:RW_D:16:1:=0x01 PI_DFI40_POLARITY:RW:8:1:=0x01 PI_SRE_PERIOD_EN:RW:0:1:=0x00 + 0x00280A00, // 27: PI_WLMRD:RW:16:6:=0x28 PI_WLDQSEN:RW:8:6:=0x0a PI_WRLVL_CS:RW:0:2:=0x00 + 0x00000000, // 28: PI_WRLVL_ON_SREF_EXIT:RW:24:1:=0x00 PI_WRLVL_PERIODIC:RW:16:1:=0x00 PI_WRLVL_INTERVAL:RW:0:16:=0x0000 + 0x0F000000, // 29: PI_WRLVL_CS_MAP:RW:24:4:=0x0f PI_WRLVL_ROTATE:RW:16:1:=0x00 PI_WRLVL_RESP_MASK:RW:8:4:=0x00 PI_WRLVL_DISABLE_DFS:RW:0:1:=0x00 + 0x00003200, // 30: PI_TDFI_WRLVL_EN:RW:8:8:=0x32 PI_WRLVL_ERROR_STATUS:RD:0:1:=0x00 + 0x00000000, // 31: PI_TDFI_WRLVL_RESP:RW:0:32:=0x00000000 + 0x00000000, // 32: PI_TDFI_WRLVL_MAX:RW:0:32:=0x00000000 + 0x01010102, // 33: PI_ODT_VALUE:RW:24:4:=0x01 PI_TODTH_RD:RW:16:4:=0x01 PI_TODTH_WR:RW:8:4:=0x01 PI_WRLVL_STROBE_NUM:RW:0:5:=0x02 + 0x00000000, // 34: PI_RDLVL_CS:RW:16:2:=0x00 PI_RDLVL_GATE_REQ:WR:8:1:=0x00 PI_RDLVL_REQ:WR:0:1:=0x00 + 0x0000AAAA, // 35: PI_RDLVL_PAT_0:RW:0:32:=0x000000aa + 0x00005555, // 36: PI_RDLVL_PAT_1:RW:0:32:=0x00000055 + 0x0000B5B5, // 37: PI_RDLVL_PAT_2:RW:0:32:=0x000000b5 + 0x00004A4A, // 38: PI_RDLVL_PAT_3:RW:0:32:=0x0000004a + 0x00005656, // 39: PI_RDLVL_PAT_4:RW:0:32:=0x00000056 + 0x0000A9A9, // 40: PI_RDLVL_PAT_5:RW:0:32:=0x000000a9 + 0x0000A9A9, // 41: PI_RDLVL_PAT_6:RW:0:32:=0x000000a9 + 0x0000B5B5, // 42: PI_RDLVL_PAT_7:RW:0:32:=0x000000b5 + 0x00000000, // 43: PI_RDLVL_DISABLE_DFS:RW:24:1:=0x00 PI_RDLVL_ON_SREF_EXIT:RW:16:1:=0x00 PI_RDLVL_PERIODIC:RW:8:1:=0x00 PI_RDLVL_SEQ_EN:RW:0:4:=0x00 + 0x00000000, // 44: PI_RDLVL_ROTATE:RW:24:1:=0x00 PI_RDLVL_GATE_DISABLE_DFS:RW:16:1:=0x00 PI_RDLVL_GATE_ON_SREF_EXIT:RW:8:1:=0x00 PI_RDLVL_GATE_PERIODIC:RW:0:1:=0x00 + 0x000F0F00, // 45: PI_RDLVL_GATE_CS_MAP:RW:16:4:=0x0f PI_RDLVL_CS_MAP:RW:8:4:=0x0f PI_RDLVL_GATE_ROTATE:RW:0:1:=0x00 + 0x0000001A, // 46: PI_TDFI_RDLVL_RR:RW:0:10:=0x001a + 0x000007D0, // 47: PI_TDFI_RDLVL_RESP:RW:0:32:=0x000007d0 + 0x00000300, // 48: PI_TDFI_RDLVL_EN:RW:8:8:=0x03 PI_RDLVL_RESP_MASK:RW:0:4:=0x00 + 0x00000000, // 49: PI_TDFI_RDLVL_MAX:RW:0:32:=0x00000000 + 0x00000000, // 50: PI_RDLVL_INTERVAL:RW:8:16:=0x0000 PI_RDLVL_ERROR_STATUS:RD:0:1:=0x00 + 0x08080000, // 51: PI_RDLVL_PATTERN_NUM:RW:24:4:=0x01 PI_RDLVL_PATTERN_START:RW:16:4:=0x00 PI_RDLVL_GATE_INTERVAL:RW:0:16:=0x0000 + 0x00010101, // 52: PI_REG_DIMM_ENABLE:RW:24:1:=0x00 PI_RD_PREAMBLE_TRAINING_EN:RW:16:1:=0x01 PI_RDLVL_GATE_STROBE_NUM:RW:8:5:=0x01 PI_RDLVL_STROBE_NUM:RW:0:5:=0x01 + 0x00000000, // 53: PI_CALVL_CS:RW:24:2:=0x00 PI_CALVL_REQ:WR:16:1:=0x00 PI_TDFI_PHY_WRLAT:RD:8:7:=0x00 PI_TDFI_RDDATA_EN:RD:0:7:=0x00 + 0x00030000, // 54: PI_CALVL_PERIODIC:RW:24:1:=0x00 PI_CALVL_SEQ_EN:RW:16:2:=0x03 RESERVED:RW:8:4:=0x00 RESERVED:RW:0:1:=0x00 + 0x0F000000, // 55: PI_CALVL_CS_MAP:RW:24:4:=0x0f PI_CALVL_ROTATE:RW:16:1:=0x00 PI_CALVL_DISABLE_DFS:RW:8:1:=0x00 PI_CALVL_ON_SREF_EXIT:RW:0:1:=0x00 + 0x00000017, // 56: PI_TDFI_CALVL_EN:RW:0:8:=0x17 + 0x00000000, // 57: PI_TDFI_CALVL_RESP:RW:0:32:=0x00000000 + 0x00000000, // 58: PI_TDFI_CALVL_MAX:RW:0:32:=0x00000000 + 0x00000000, // 59: PI_CALVL_INTERVAL:RW:16:16:=0x0000 PI_CALVL_ERROR_STATUS:RD:8:2:=0x00 PI_CALVL_RESP_MASK:RW:0:1:=0x00 + 0x0A0A140A, // 60: PI_TCAEXT:RW:24:5:=0x0a PI_TCACKEH:RW:16:5:=0x0a PI_TCAMRD:RW:8:6:=0x14 PI_TCACKEL:RW:0:5:=0x0a + 0x10020401, // 61: PI_TDFI_INIT_START_MIN:RW:24:8:=0x10 PI_CALVL_VREF_NORMAL_STEPSIZE:RW:16:4:=0x02 PI_CALVL_VREF_INITIAL_STEPSIZE:RW:8:4:=0x04 PI_CA_TRAIN_VREF_EN:RW:0:1:=0x01 + 0x00020805, // 62: PI_SW_CA_TRAIN_VREF:RW:24:7:=0x00 PI_CALVL_STROBE_NUM:RW:16:5:=0x02 PI_TCKCKEH:RW:8:4:=0x08 PI_TDFI_INIT_COMPLETE_MIN:RW:0:8:=0x05 + 0x01000404, // 63: PI_REFRESH_BETWEEN_SEGMENT_DISABLE:RW_D:24:1:=0x01 PI_DRAM_CLK_DISABLE_DEASSERT_SEL:RW:16:1:=0x00 PI_INIT_STARTORCOMPLETE_2_CLKDISABLE:RW:8:8:=0x04 PI_CLKDISABLE_2_INIT_START:RW:0:8:=0x04 + 0x00000000, // 64: PI_FSM_ERROR_INFO_MASK:RW:8:16:=0x0000 PI_MC_DFS_PI_SET_VREF_ENABLE:RW:0:1:=0x00 + 0x00000000, // 65: PI_FSM_ERROR_INFO:RD:16:16:=0x0000 PI_SC_FSM_ERROR_INFO_WOCLR:WR:0:16:=0x0000 + 0x00000101, // 66: PI_WDQLVL_ROTATE:RW:24:1:=0x00 PI_WDQLVL_RESP_MASK:RW:16:4:=0x00 PI_WDQLVL_BST_NUM:RW:8:3:=0x01 PI_WDQLVL_VREF_EN:RW:0:1:=0x01 + 0x0002040F, // 67: PI_WDQLVL_PERIODIC:RW:24:1:=0x00 PI_WDQLVL_VREF_NORMAL_STEPSIZE:RW:16:5:=0x02 PI_WDQLVL_VREF_INITIAL_STEPSIZE:RW:8:5:=0x04 PI_WDQLVL_CS_MAP:RW:0:4:=0x0f + 0x00340000, // 68: PI_TDFI_WDQLVL_EN:RW:16:8:=0x34 PI_WDQLVL_CS:RW:8:2:=0x00 PI_WDQLVL_REQ:WR:0:1:=0x00 + 0x00000000, // 69: PI_TDFI_WDQLVL_RESP:RW:0:32:=0x00000000 + 0x00000000, // 70: PI_TDFI_WDQLVL_MAX:RW:0:32:=0x00000000 + 0x00000000, // 71: PI_WDQLVL_DISABLE_DFS:RW:24:1:=0x00 PI_WDQLVL_ON_SREF_EXIT:RW:16:1:=0x00 PI_WDQLVL_INTERVAL:RW:0:16:=0x0000 + 0x01000000, // 72: PI_PARALLEL_WDQLVL_EN:RW:24:1:=0x01 PI_DQS_OSC_PERIOD_EN:RW:16:1:=0x00 PI_WDQLVL_OSC_EN:RW:8:1:=0x00 PI_WDQLVL_ERROR_STATUS:RD:0:2:=0x00 + 0x00080000, // 73: RESERVED:RW_D:24:4:=0x00 PI_TCCD:RW:16:5:=0x08 PI_ROW_DIFF:RW:8:3:=0x00 PI_BANK_DIFF:RW:0:2:=0x00 + 0x02000200, // 74: RESERVED:RW_D:24:4:=0x02 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x02 RESERVED:RW_D:0:4:=0x00 + 0x01000100, // 75: RESERVED:RW_D:24:4:=0x01 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x01 RESERVED:RW_D:0:4:=0x00 + 0x01000000, // 76: RESERVED:RW_D:24:4:=0x01 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x00 RESERVED:RW_D:0:4:=0x00 + 0x02000200, // 77: RESERVED:RW_D:24:4:=0x02 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x02 RESERVED:RW_D:0:4:=0x00 + 0x00000200, // 78: RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x02 RESERVED:RW_D:0:4:=0x00 + 0x00000000, // 79: PI_INT_STATUS:RD:0:28:=0x00000000 + 0x00000000, // 80: PI_INT_ACK:WR:0:27:=0x00000000 + 0x00000000, // 81: PI_INT_MASK:RW:0:28:=0x00000000 + 0x00000000, // 82: PI_BIST_EXP_DATA:RD:0:128:=0x00000000 + 0x00000000, // 83: PI_BIST_EXP_DATA:RD:0:128:=0x00000000 + 0x00000000, // 84: PI_BIST_EXP_DATA:RD:0:128:=0x00000000 + 0x00000000, // 85: PI_BIST_EXP_DATA:RD:0:128:=0x00000000 + 0x00000000, // 86: PI_BIST_FAIL_DATA:RD:0:128:=0x00000000 + 0x00000000, // 87: PI_BIST_FAIL_DATA:RD:0:128:=0x00000000 + 0x00000000, // 88: PI_BIST_FAIL_DATA:RD:0:128:=0x00000000 + 0x00000000, // 89: PI_BIST_FAIL_DATA:RD:0:128:=0x00000000 + 0x00000000, // 90: PI_BIST_FAIL_ADDR:RD:0:35:=0x00000000 + 0x00000400, // 91: PI_CMD_SWAP_EN:RW_D:24:1:=0x00 PI_LONG_COUNT_MASK:RW:16:5:=0x00 PI_BSTLEN:RW_D:8:5:=0x04 PI_BIST_FAIL_ADDR:RD:0:35:=0x00 + 0x02010000, // 92: PI_DATA_BYTE_SWAP_SLICE2:RW_D:24:2:=0x02 PI_DATA_BYTE_SWAP_SLICE1:RW_D:16:2:=0x01 PI_DATA_BYTE_SWAP_SLICE0:RW_D:8:2:=0x00 PI_DATA_BYTE_SWAP_EN:RW_D:0:1:=0x00 + 0x00080003, // 93: PI_UPDATE_ERROR_STATUS:RD:24:2:=0x00 PI_TDFI_CTRLUPD_MIN:RW:16:8:=0x08 PI_CTRLUPD_REQ_PER_AREF_EN:RW:8:1:=0x00 PI_DATA_BYTE_SWAP_SLICE3:RW_D:0:2:=0x03 + 0x00080000, // 94: PI_BIST_DATA_CHECK:RW:24:1:=0x00 PI_ADDR_SPACE:RW:16:6:=0x08 PI_BIST_RESULT:RD:8:2:=0x00 PI_BIST_GO:RW:0:1:=0x00 + 0x00000001, // 95: PI_BIST_ADDR_CHECK:RW:0:1:=0x01 + 0x00000000, // 96: PI_BIST_START_ADDRESS:RW:0:35:=0x00000000 + 0x0000AA00, // 97: PI_MBIST_INIT_PATTERN:RW:8:8:=0xaa PI_BIST_START_ADDRESS:RW:0:35:=0x00 + 0x00000000, // 98: PI_BIST_DATA_MASK:RW:0:64:=0x00000000 + 0x00000000, // 99: PI_BIST_DATA_MASK:RW:0:64:=0x00000000 + 0x00010000, // 100: PI_BIST_ERR_STOP:RW:16:12:=0x0001 PI_BIST_ERR_COUNT:RD:0:12:=0x0000 + 0x00000000, // 101: PI_BIST_ADDR_MASK_0:RW:0:36:=0x00000000 + 0x00000000, // 102: PI_BIST_ADDR_MASK_0:RW:0:36:=0x00 + 0x00000000, // 103: PI_BIST_ADDR_MASK_1:RW:0:36:=0x00000000 + 0x00000000, // 104: PI_BIST_ADDR_MASK_1:RW:0:36:=0x00 + 0x00000000, // 105: PI_BIST_ADDR_MASK_2:RW:0:36:=0x00000000 + 0x00000000, // 106: PI_BIST_ADDR_MASK_2:RW:0:36:=0x00 + 0x00000000, // 107: PI_BIST_ADDR_MASK_3:RW:0:36:=0x00000000 + 0x00000000, // 108: PI_BIST_ADDR_MASK_3:RW:0:36:=0x00 + 0x00000000, // 109: PI_BIST_ADDR_MASK_4:RW:0:36:=0x00000000 + 0x00000000, // 110: PI_BIST_ADDR_MASK_4:RW:0:36:=0x00 + 0x00000000, // 111: PI_BIST_ADDR_MASK_5:RW:0:36:=0x00000000 + 0x00000000, // 112: PI_BIST_ADDR_MASK_5:RW:0:36:=0x00 + 0x00000000, // 113: PI_BIST_ADDR_MASK_6:RW:0:36:=0x00000000 + 0x00000000, // 114: PI_BIST_ADDR_MASK_6:RW:0:36:=0x00 + 0x00000000, // 115: PI_BIST_ADDR_MASK_7:RW:0:36:=0x00000000 + 0x00000000, // 116: PI_BIST_ADDR_MASK_7:RW:0:36:=0x00 + 0x00000000, // 117: PI_BIST_ADDR_MASK_8:RW:0:36:=0x00000000 + 0x00000000, // 118: PI_BIST_ADDR_MASK_8:RW:0:36:=0x00 + 0x00000000, // 119: PI_BIST_ADDR_MASK_9:RW:0:36:=0x00000000 + 0x00000000, // 120: PI_BIST_PAT_MODE:RW:24:2:=0x00 PI_BIST_ADDR_MODE:RW:16:2:=0x00 PI_BIST_MODE:RW:8:3:=0x00 PI_BIST_ADDR_MASK_9:RW:0:36:=0x00 + 0x00000000, // 121: PI_BIST_USER_PAT:RW:0:128:=0x00000000 + 0x00000000, // 122: PI_BIST_USER_PAT:RW:0:128:=0x00000000 + 0x00000000, // 123: PI_BIST_USER_PAT:RW:0:128:=0x00000000 + 0x00000000, // 124: PI_BIST_USER_PAT:RW:0:128:=0x00000000 + 0x00000008, // 125: PI_BIST_PAT_NUM:RW:0:4:=0x00 + 0x00000000, // 126: PI_BIST_STAGE_0:RW:0:30:=0x00000000 + 0x00000000, // 127: PI_BIST_STAGE_1:RW:0:30:=0x00000000 + 0x00000000, // 128: PI_BIST_STAGE_2:RW:0:30:=0x00000000 + 0x00000000, // 129: PI_BIST_STAGE_3:RW:0:30:=0x00000000 + 0x00000000, // 130: PI_BIST_STAGE_4:RW:0:30:=0x00000000 + 0x00000000, // 131: PI_BIST_STAGE_5:RW:0:30:=0x00000000 + 0x00000000, // 132: PI_BIST_STAGE_6:RW:0:30:=0x00000000 + 0x00000000, // 133: PI_BIST_STAGE_7:RW:0:30:=0x00000000 + 0x00000002, // 134: PI_SREFRESH_EXIT_NO_REFRESH:RW:24:1:=0x00 PI_PWRUP_SREFRESH_EXIT:RW+:16:1:=0x00 PI_SELF_REFRESH_EN:RW:8:1:=0x00 PI_COL_DIFF:RW:0:4:=0x02 + 0x00000000, // 135: PI_NO_PHY_IND_TRAIN_INIT:RW:24:1:=0x00 PI_NO_MRW_INIT:RW:16:1:=0x00 PI_NO_MRW_BT_INIT:RW:8:1:=0x00 PI_SREF_ENTRY_REQ:WR:0:1:=0x00 + 0x00000000, // 136: PI_NO_AUTO_MRR_INIT:RW:0:1:=0x00 + 0x0000000A, // 137: PI_TRST_PWRON:RW:0:32:=0x0000000a + 0x00000019, // 138: PI_CKE_INACTIVE:RW:0:32:=0x00000019 + 0x00000000, // 139: PI_DLL_RST_DELAY:RW:16:16:=0x0000 PI_DRAM_INIT_EN:RW:8:1:=0x00 PI_DLL_RST:RW:0:1:=0x00 + 0x00000000, // 140: PI_DLL_RST_ADJ_DLY:RW:0:8:=0x00 + 0x00000000, // 141: PI_WRITE_MODEREG:RW+:0:26:=0x00000000 + 0x00000000, // 142: PI_READ_MODEREG:RW+:8:17:=0x000000 PI_MRW_STATUS:RD:0:8:=0x00 + 0x00000000, // 143: PI_NO_ZQ_INIT:RW:24:1:=0x00 PI_PERIPHERAL_MRR_DATA_0:RD:0:24:=0x000000 + 0x01000000, // 144: RESERVED:RW:24:1:=0x01 PI_ZQ_REQ_PENDING:RD:16:1:=0x00 RESERVED:WR:8:4:=0x00 RESERVED:RW:0:4:=0x00 + 0x00010003, // 145: PI_MONITOR_0:RD:24:8:=0x00 PI_MONITOR_CAP_SEL_0:RW:16:1:=0x01 PI_MONITOR_SRC_SEL_0:RW:8:4:=0x00 RESERVED:RW:0:3:=0x03 + 0x02000101, // 146: PI_MONITOR_SRC_SEL_2:RW:24:4:=0x02 PI_MONITOR_1:RD:16:8:=0x00 PI_MONITOR_CAP_SEL_1:RW:8:1:=0x01 PI_MONITOR_SRC_SEL_1:RW:0:4:=0x01 + 0x01030001, // 147: PI_MONITOR_CAP_SEL_3:RW:24:1:=0x01 PI_MONITOR_SRC_SEL_3:RW:16:4:=0x03 PI_MONITOR_2:RD:8:8:=0x00 PI_MONITOR_CAP_SEL_2:RW:0:1:=0x01 + 0x00010400, // 148: PI_MONITOR_4:RD:24:8:=0x00 PI_MONITOR_CAP_SEL_4:RW:16:1:=0x01 PI_MONITOR_SRC_SEL_4:RW:8:4:=0x04 PI_MONITOR_3:RD:0:8:=0x00 + 0x06000105, // 149: PI_MONITOR_SRC_SEL_6:RW:24:4:=0x06 PI_MONITOR_5:RD:16:8:=0x00 PI_MONITOR_CAP_SEL_5:RW:8:1:=0x01 PI_MONITOR_SRC_SEL_5:RW:0:4:=0x05 + 0x01070001, // 150: PI_MONITOR_CAP_SEL_7:RW:24:1:=0x01 PI_MONITOR_SRC_SEL_7:RW:16:4:=0x07 PI_MONITOR_6:RD:8:8:=0x00 PI_MONITOR_CAP_SEL_6:RW:0:1:=0x01 + 0x00000000, // 151: PI_MONITOR_7:RD:0:8:=0x00 + 0x00000000, // 152: PI_MONITOR_STROBE:WR:0:8:=0x00 + 0x00000000, // 153: RESERVED:RW:24:1:=0x00 PI_FREQ_RETENTION_NUM:RW+:16:5:=0x00 PI_FREQ_NUMBER_STATUS:RD:8:5:=0x00 PI_DLL_LOCK:RD:0:1:=0x00 + 0x00010001, // 154: RESERVED:RW:24:1:=0x00 PI_POWER_REDUC_EN:RW:16:1:=0x01 RESERVED:RW:8:1:=0x00 PI_PHYMSTR_TYPE:RW:0:2:=0x01 + 0x00000000, // 155: RESERVED:RW:24:1:=0x00 RESERVED:RW:16:1:=0x00 RESERVED:RW:8:1:=0x00 RESERVED:RW:0:1:=0x00 + 0x00000000, // 156: RESERVED:RW:24:1:=0x00 RESERVED:RW:16:1:=0x00 RESERVED:RW:8:1:=0x00 RESERVED:RW:0:1:=0x00 + 0x00000000, // 157: RESERVED:RW:24:1:=0x00 RESERVED:RW:16:1:=0x00 RESERVED:RW:8:1:=0x00 RESERVED:RW:0:1:=0x00 + 0x00000000, // 158: RESERVED:RW:24:1:=0x00 RESERVED:RW:16:1:=0x00 RESERVED:RW:8:1:=0x00 RESERVED:RW:0:1:=0x00 + 0x00000401, // 159: PI_TREFBW_THR:RW:8:9:=0x0004 PI_WRLVL_MAX_STROBE_PEND:RW:0:8:=0x01 + 0x00000000, // 160: PI_FREQ_CHANGE_REG_COPY:RW:0:5:=0x00 + 0x00010000, // 161: PI_CATR:RW:24:4:=0x00 PI_PARALLEL_CALVL_EN:RW:16:1:=0x01 RESERVED:RW:8:5:=0x00 PI_FREQ_SEL_FROM_REGIF:RW:0:1:=0x00 + 0x00000000, // 162: PI_NOTCARE_MC_INIT_START:RW:24:1:=0x00 PI_DISCONNECT_MC:RW:16:1:=0x00 PI_MASK_INIT_COMPLETE:RW:8:1:=0x00 PI_NO_CATR_READ:RW:0:1:=0x00 + 0x2B200100, // 163: PI_TSDO_F2:RW:24:8:=0x2b PI_TSDO_F1:RW:16:8:=0x20 PI_TSDO_F0:RW:8:8:=0x01 PI_TRACE_MC_MR13:RW:0:1:=0x00 + 0x00000034, // 164: PI_TDELAY_RDWR_2_BUS_IDLE_F0:RW:0:8:=0x34 + 0x00000057, // 165: PI_TDELAY_RDWR_2_BUS_IDLE_F1:RW:0:8:=0x57 + 0x00020064, // 166: PI_ZQINIT_F0:RW_D:8:12:=0x0200 PI_TDELAY_RDWR_2_BUS_IDLE_F2:RW:0:8:=0x64 + 0x02000200, // 167: PI_ZQINIT_F2:RW_D:16:12:=0x0200 PI_ZQINIT_F1:RW_D:0:12:=0x0200 + 0x380E0C04, // 168: PI_CASLAT_LIN_F1:RW:24:7:=0x38 PI_WRLAT_F1:RW:16:7:=0x0e PI_CASLAT_LIN_F0:RW:8:7:=0x0c PI_WRLAT_F0:RW:0:7:=0x04 + 0x00134812, // 169: PI_TRFC_F0:RW:16:10:=0x0013 PI_CASLAT_LIN_F2:RW:8:7:=0x48 PI_WRLAT_F2:RW:0:7:=0x12 + 0x000000BB, // 170: PI_TREF_F0:RW:0:20:=0x0000bb + 0x00000260, // 171: PI_TRFC_F1:RW:0:10:=0x0260 + 0x00001858, // 172: PI_TREF_F1:RW:0:20:=0x001858 + 0x0000032B, // 173: PI_TRFC_F2:RW:0:10:=0x032b + 0x04002073, // 174: PI_TDFI_CTRL_DELAY_F0:RW_D:24:4:=0x04 PI_TREF_F2:RW:0:20:=0x002073 + 0x01000404, // 175: PI_WRLVL_EN_F1:RW:24:2:=0x01 PI_WRLVL_EN_F0:RW:16:2:=0x01 PI_TDFI_CTRL_DELAY_F2:RW_D:8:4:=0x04 PI_TDFI_CTRL_DELAY_F1:RW_D:0:4:=0x04 + 0x00001501, // 176: PI_TDFI_WRLVL_WW_F0:RW:8:10:=0x0015 PI_WRLVL_EN_F2:RW:0:2:=0x01 + 0x00150015, // 177: PI_TDFI_WRLVL_WW_F2:RW:16:10:=0x0015 PI_TDFI_WRLVL_WW_F1:RW:0:10:=0x0015 + 0x01000100, // 178: PI_ODT_EN_F1:RW:24:1:=0x01 PI_TODTL_2CMD_F1:RW:16:8:=0x00 PI_ODT_EN_F0:RW:8:1:=0x01 PI_TODTL_2CMD_F0:RW:0:8:=0x00 + 0x00000100, // 179: PI_TODTON_MIN_F0:RW:24:4:=0x00 PI_ODTLON_F0:RW:16:4:=0x00 PI_ODT_EN_F2:RW:8:1:=0x01 PI_TODTL_2CMD_F2:RW:0:8:=0x00 + 0x00000000, // 180: PI_TODTON_MIN_F2:RW:24:4:=0x00 PI_ODTLON_F2:RW:16:4:=0x00 PI_TODTON_MIN_F1:RW:8:4:=0x00 PI_ODTLON_F1:RW:0:4:=0x00 + 0x01010000, // 181: PI_RDLVL_GATE_EN_F1:RW:24:2:=0x01 PI_RDLVL_EN_F1:RW:16:2:=0x01 PI_RDLVL_GATE_EN_F0:RW:8:2:=0x01 PI_RDLVL_EN_F0:RW:0:2:=0x01 + 0x00000101, // 182: PI_RDLVL_RXCAL_EN_F0:RW:24:2:=0x00 PI_RDLVL_PAT0_EN_F0:RW:16:2:=0x00 PI_RDLVL_GATE_EN_F2:RW:8:2:=0x01 PI_RDLVL_EN_F2:RW:0:2:=0x01 + 0x00030000, // 183: PI_RDLVL_RXCAL_EN_F1:RW:24:2:=0x00 PI_RDLVL_PAT0_EN_F1:RW:16:2:=0x00 PI_RDLVL_MULTI_EN_F0:RW:8:2:=0x00 PI_RDLVL_DFE_EN_F0:RW:0:2:=0x00 + 0x00030300, // 184: PI_RDLVL_RXCAL_EN_F2:RW:24:2:=0x00 PI_RDLVL_PAT0_EN_F2:RW:16:2:=0x00 PI_RDLVL_MULTI_EN_F1:RW:8:2:=0x00 PI_RDLVL_DFE_EN_F1:RW:0:2:=0x00 + 0x10040300, // 185: PI_RDLAT_ADJ_F1:RW:24:7:=0x10 PI_RDLAT_ADJ_F0:RW:16:7:=0x04 PI_RDLVL_MULTI_EN_F2:RW:8:2:=0x00 PI_RDLVL_DFE_EN_F2:RW:0:2:=0x00 + 0x0E0A0215, // 186: PI_WRLAT_ADJ_F2:RW:24:7:=0x0e PI_WRLAT_ADJ_F1:RW:16:7:=0x0a PI_WRLAT_ADJ_F0:RW:8:7:=0x02 PI_RDLAT_ADJ_F2:RW:0:7:=0x15 + 0x00040402, // 187: PI_TDFI_PHY_WRDATA_F2:RW:16:3:=0x04 PI_TDFI_PHY_WRDATA_F1:RW:8:3:=0x04 PI_TDFI_PHY_WRDATA_F0:RW:0:3:=0x02 + 0x000C0034, // 188: PI_TDFI_CALVL_CAPTURE_F0:RW:16:10:=0x000c PI_TDFI_CALVL_CC_F0:RW:0:10:=0x0034 + 0x001C0044, // 189: PI_TDFI_CALVL_CAPTURE_F1:RW:16:10:=0x001c PI_TDFI_CALVL_CC_F1:RW:0:10:=0x0044 + 0x00210049, // 190: PI_TDFI_CALVL_CAPTURE_F2:RW:16:10:=0x0021 PI_TDFI_CALVL_CC_F2:RW:0:10:=0x0049 + 0x01010101, // 191: PI_TMRZ_F0:RW:24:5:=0x01 PI_CALVL_EN_F2:RW:16:2:=0x01 PI_CALVL_EN_F1:RW:8:2:=0x01 PI_CALVL_EN_F0:RW:0:2:=0x01 + 0x0003000D, // 192: PI_TMRZ_F1:RW:16:5:=0x03 PI_TCAENT_F0:RW:0:14:=0x000d + 0x00040190, // 193: PI_TMRZ_F2:RW:16:5:=0x04 PI_TCAENT_F1:RW:0:14:=0x0190 + 0x01000216, // 194: PI_TDFI_CASEL_F0:RW:24:5:=0x01 PI_TDFI_CACSCA_F0:RW:16:5:=0x00 PI_TCAENT_F2:RW:0:14:=0x0216 + 0x000E000E, // 195: PI_TVREF_LONG_F0:RW:16:10:=0x000e PI_TVREF_SHORT_F0:RW:0:10:=0x000e + 0x01910100, // 196: PI_TVREF_SHORT_F1:RW:16:10:=0x0191 PI_TDFI_CASEL_F1:RW:8:5:=0x01 PI_TDFI_CACSCA_F1:RW:0:5:=0x00 + 0x01000191, // 197: PI_TDFI_CASEL_F2:RW:24:5:=0x01 PI_TDFI_CACSCA_F2:RW:16:5:=0x00 PI_TVREF_LONG_F1:RW:0:10:=0x0191 + 0x02170217, // 198: PI_TVREF_LONG_F2:RW:16:10:=0x0217 PI_TVREF_SHORT_F2:RW:0:10:=0x0217 + 0x230A230A, // 199: PI_CALVL_VREF_INITIAL_STOP_POINT_F1:RW:24:7:=0x1e PI_CALVL_VREF_INITIAL_START_POINT_F1:RW:16:7:=0x1a PI_CALVL_VREF_INITIAL_STOP_POINT_F0:RW:8:7:=0x1e PI_CALVL_VREF_INITIAL_START_POINT_F0:RW:0:7:=0x1a + 0x0101230A, // 200: PI_CALVL_VREF_DELTA_F1:RW:24:4:=0x01 PI_CALVL_VREF_DELTA_F0:RW:16:4:=0x01 PI_CALVL_VREF_INITIAL_STOP_POINT_F2:RW:8:7:=0x1e PI_CALVL_VREF_INITIAL_START_POINT_F2:RW:0:7:=0x1a + 0x0A070601, // 201: PI_TMRWCKEL_F0:RW:24:8:=0x0a PI_TXP_F0:RW:16:5:=0x07 PI_TDFI_CALVL_STROBE_F0:RW:8:4:=0x06 PI_CALVL_VREF_DELTA_F2:RW:0:4:=0x01 + 0x180F090D, // 202: PI_TMRWCKEL_F1:RW:24:8:=0x18 PI_TXP_F1:RW:16:5:=0x0f PI_TDFI_CALVL_STROBE_F1:RW:8:4:=0x09 PI_TCKELCK_F0:RW:0:5:=0x0d + 0x1F130A11, // 203: PI_TMRWCKEL_F2:RW:24:8:=0x1f PI_TXP_F2:RW:16:5:=0x13 PI_TDFI_CALVL_STROBE_F2:RW:8:4:=0x0a PI_TCKELCK_F1:RW:0:5:=0x11 + 0x0000C014, // 204: PI_TDFI_INIT_START_F0:RW:8:10:=0x00c0 PI_TCKELCK_F2:RW:0:5:=0x14 + 0x00C01000, // 205: PI_TDFI_INIT_START_F1:RW:16:10:=0x00c0 PI_TDFI_INIT_COMPLETE_F0:RW:0:16:=0x1000 + 0x00C01000, // 206: PI_TDFI_INIT_START_F2:RW:16:10:=0x00c0 PI_TDFI_INIT_COMPLETE_F1:RW:0:16:=0x1000 + 0x00021000, // 207: PI_TCKEHDQS_F0:RW:16:6:=0x02 PI_TDFI_INIT_COMPLETE_F2:RW:0:16:=0x1000 + 0x001E000D, // 208: PI_TCKEHDQS_F1:RW:16:6:=0x1e PI_TFC_F0:RW:0:10:=0x000d + 0x00240190, // 209: PI_TCKEHDQS_F2:RW:16:6:=0x24 PI_TFC_F1:RW:0:10:=0x0190 + 0x00110216, // 210: PI_TDFI_WDQLVL_WR_F0:RW:16:10:=0x0011 PI_TFC_F2:RW:0:10:=0x0216 + 0x59400056, // 211: PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0:RW:24:7:=0x1e PI_WDQLVL_VREF_INITIAL_START_POINT_F0:RW:16:7:=0x1a PI_TDFI_WDQLVL_RW_F0:RW:0:10:=0x0056 + 0x00000001, // 212: PI_NTP_TRAIN_EN_F0:RW:16:2:=0x00 PI_WDQLVL_EN_F0:RW:8:2:=0x01 PI_WDQLVL_VREF_DELTA_F0:RW:0:4:=0x01 + 0x005A002C, // 213: PI_TDFI_WDQLVL_RW_F1:RW:16:10:=0x005a PI_TDFI_WDQLVL_WR_F1:RW:0:10:=0x002c + 0x0101321A, // 214: PI_WDQLVL_EN_F1:RW:24:2:=0x01 PI_WDQLVL_VREF_DELTA_F1:RW:16:4:=0x01 PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1:RW:8:7:=0x1e PI_WDQLVL_VREF_INITIAL_START_POINT_F1:RW:0:7:=0x1a + 0x00003600, // 215: PI_TDFI_WDQLVL_WR_F2:RW:8:10:=0x0036 PI_NTP_TRAIN_EN_F1:RW:0:2:=0x00 + 0x321A005B, // 216: PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2:RW:24:7:=0x1e PI_WDQLVL_VREF_INITIAL_START_POINT_F2:RW:16:7:=0x1a PI_TDFI_WDQLVL_RW_F2:RW:0:10:=0x005b + 0x09000101, // 217: PI_TRTP_F0:RW:24:8:=0x09 PI_NTP_TRAIN_EN_F2:RW:16:2:=0x00 PI_WDQLVL_EN_F2:RW:8:2:=0x01 PI_WDQLVL_VREF_DELTA_F2:RW:0:4:=0x01 + 0x04010503, // 218: PI_TWR_F0:RW:24:8:=0x04 PI_TWTR_F0:RW:16:6:=0x01 PI_TRCD_F0:RW:8:8:=0x05 PI_TRP_F0:RW:0:8:=0x03 + 0x0400062B, // 219: PI_TRAS_MIN_F0:RW:24:8:=0x04 PI_TRAS_MAX_F0:RW:0:17:=0x00062b + 0x0A032001, // 220: PI_TMRD_F0:RW:24:8:=0x0a PI_TSR_F0:RW:16:8:=0x03 PI_TCCDMW_F0:RW:8:6:=0x20 PI_TDQSCK_MAX_F0:RW:0:4:=0x01 + 0x1E220D0A, // 221: PI_TRCD_F1:RW:24:8:=0x1e PI_TRP_F1:RW:16:8:=0x22 PI_TRTP_F1:RW:8:8:=0x0d PI_TMRW_F0:RW:0:8:=0x0a + 0x00001F12, // 222: PI_TWR_F1:RW:8:8:=0x1f PI_TWTR_F1:RW:0:6:=0x12 + 0x4500C570, // 223: PI_TRAS_MIN_F1:RW:24:8:=0x45 PI_TRAS_MAX_F1:RW:0:17:=0x00c570 + 0x17182006, // 224: PI_TMRD_F1:RW:24:8:=0x17 PI_TSR_F1:RW:16:8:=0x18 PI_TCCDMW_F1:RW:8:6:=0x20 PI_TDQSCK_MAX_F1:RW:0:4:=0x06 + 0x282D1110, // 225: PI_TRCD_F2:RW:24:8:=0x28 PI_TRP_F2:RW:16:8:=0x2d PI_TRTP_F2:RW:8:8:=0x11 PI_TMRW_F1:RW:0:8:=0x10 + 0x00002918, // 226: PI_TWR_F2:RW:8:8:=0x29 PI_TWTR_F2:RW:0:6:=0x18 + 0x5C01071C, // 227: PI_TRAS_MIN_F2:RW:24:8:=0x5c PI_TRAS_MAX_F2:RW:0:17:=0x01071c + 0x1E202008, // 228: PI_TMRD_F2:RW:24:8:=0x1e PI_TSR_F2:RW:16:8:=0x20 PI_TCCDMW_F2:RW:8:6:=0x20 PI_TDQSCK_MAX_F2:RW:0:4:=0x08 + 0x00017616, // 229: PI_TDFI_CTRLUPD_MAX_F0:RW:8:21:=0x000176 PI_TMRW_F2:RW:0:8:=0x16 + 0x00000E9C, // 230: PI_TDFI_CTRLUPD_INTERVAL_F0:RW:0:32:=0x00000e9c + 0x000030B0, // 231: PI_TDFI_CTRLUPD_MAX_F1:RW:0:21:=0x0030b0 + 0x0001E6E0, // 232: PI_TDFI_CTRLUPD_INTERVAL_F1:RW:0:32:=0x0001e6e0 + 0x000040E6, // 233: PI_TDFI_CTRLUPD_MAX_F2:RW:0:21:=0x0040e6 + 0x000288FC, // 234: PI_TDFI_CTRLUPD_INTERVAL_F2:RW:0:32:=0x000288fc + 0x026C0014, // 235: PI_TXSR_F1:RW:16:16:=0x026c PI_TXSR_F0:RW:0:16:=0x0014 + 0x0303033B, // 236: PI_TEXCKE_F1:RW:24:6:=0x03 PI_TEXCKE_F0:RW:16:6:=0x03 PI_TXSR_F2:RW:0:16:=0x033b + 0x00271004, // 237: PI_TINIT_F0:RW:8:24:=0x002710 PI_TEXCKE_F2:RW:0:6:=0x04 + 0x000186A0, // 238: PI_TINIT3_F0:RW:0:24:=0x0186a0 + 0x00000005, // 239: PI_TINIT4_F0:RW:0:24:=0x000005 + 0x00000064, // 240: PI_TINIT5_F0:RW:0:24:=0x000064 + 0x00000014, // 241: PI_TXSNR_F0:RW:0:16:=0x0014 + 0x0004E200, // 242: PI_TINIT_F1:RW:0:24:=0x04e200 + 0x000186A0, // 243: PI_TINIT3_F1:RW:0:24:=0x0186a0 + 0x00000005, // 244: PI_TINIT4_F1:RW:0:24:=0x000005 + 0x00000C80, // 245: PI_TINIT5_F1:RW:0:24:=0x000c80 + 0x0000026C, // 246: PI_TXSNR_F1:RW:0:16:=0x026c + 0x000681C8, // 247: PI_TINIT_F2:RW:0:24:=0x0681c8 + 0x000186A0, // 248: PI_TINIT3_F2:RW:0:24:=0x0186a0 + 0x00000005, // 249: PI_TINIT4_F2:RW:0:24:=0x000005 + 0x000010A9, // 250: PI_TINIT5_F2:RW:0:24:=0x0010a9 + 0x0100033B, // 251: RESERVED:RW:16:12:=0x0100 PI_TXSNR_F2:RW:0:16:=0x033b + 0x00320040, // 252: PI_TZQCAL_F0:RW:16:12:=0x0032 RESERVED:RW:0:12:=0x0040 + 0x00010002, // 253: RESERVED:RW:8:12:=0x0100 PI_TZQLAT_F0:RW:0:7:=0x02 + 0x06400040, // 254: PI_TZQCAL_F1:RW:16:12:=0x0640 RESERVED:RW:0:12:=0x0040 + 0x00010030, // 255: RESERVED:RW:8:12:=0x0100 PI_TZQLAT_F1:RW:0:7:=0x30 + 0x08550040, // 256: PI_TZQCAL_F2:RW:16:12:=0x0855 RESERVED:RW:0:12:=0x0040 + 0x00000340, // 257: RESERVED:RW:8:12:=0x0003 PI_TZQLAT_F2:RW:0:7:=0x40 + 0x006B0050, // 258: RESERVED:RW:16:12:=0x006b RESERVED:RW:0:12:=0x0050 + 0x08040404, // 259: PI_MR13_DATA_0:RW+:24:8:=0x00 PI_WDQ_OSC_DELTA_INDEX_F2:RW:16:4:=0x04 PI_WDQ_OSC_DELTA_INDEX_F1:RW:8:4:=0x04 PI_WDQ_OSC_DELTA_INDEX_F0:RW:0:4:=0x04 + 0x00000055, // 260: PI_MR20_DATA_0:RW:24:8:=0x00 PI_MR17_DATA_0:RW:16:8:=0x00 PI_MR16_DATA_0:RW:8:8:=0x00 PI_MR15_DATA_0:RW:0:8:=0x55 + 0x55083C5A, // 261: PI_MR15_DATA_1:RW:24:8:=0x55 PI_MR13_DATA_1:RW+:16:8:=0x00 PI_MR40_DATA_0:RW:8:8:=0x3c PI_MR32_DATA_0:RW:0:8:=0x5a + 0x5A000000, // 262: PI_MR32_DATA_1:RW:24:8:=0x5a PI_MR20_DATA_1:RW:16:8:=0x00 PI_MR17_DATA_1:RW:8:8:=0x00 PI_MR16_DATA_1:RW:0:8:=0x00 + 0x0055083C, // 263: PI_MR16_DATA_2:RW:24:8:=0x00 PI_MR15_DATA_2:RW:16:8:=0x55 PI_MR13_DATA_2:RW+:8:8:=0x00 PI_MR40_DATA_1:RW:0:8:=0x3c + 0x3C5A0000, // 264: PI_MR40_DATA_2:RW:24:8:=0x3c PI_MR32_DATA_2:RW:16:8:=0x5a PI_MR20_DATA_2:RW:8:8:=0x00 PI_MR17_DATA_2:RW:0:8:=0x00 + 0x00005508, // 265: PI_MR17_DATA_3:RW:24:8:=0x00 PI_MR16_DATA_3:RW:16:8:=0x00 PI_MR15_DATA_3:RW:8:8:=0x55 PI_MR13_DATA_3:RW+:0:8:=0x00 + 0x0C3C5A00, // 266: PI_CKE_MUX_0:RW_D:24:4:=0x0c PI_MR40_DATA_3:RW:16:8:=0x3c PI_MR32_DATA_3:RW:8:8:=0x5a PI_MR20_DATA_3:RW:0:8:=0x00 + 0x080F0E0D, // 267: PI_CS_MUX_0:RW_D:24:4:=0x08 PI_CKE_MUX_3:RW_D:16:4:=0x0f PI_CKE_MUX_2:RW_D:8:4:=0x0e PI_CKE_MUX_1:RW_D:0:4:=0x0d + 0x000B0A09, // 268: PI_RESET_N_MUX_0:RW_D:24:4:=0x00 PI_CS_MUX_3:RW_D:16:4:=0x0b PI_CS_MUX_2:RW_D:8:4:=0x0a PI_CS_MUX_1:RW_D:0:4:=0x09 + 0x00030201, // 269: PI_MRSINGLE_DATA_0:RW:24:8:=0x00 PI_RESET_N_MUX_3:RW_D:16:4:=0x03 PI_RESET_N_MUX_2:RW_D:8:4:=0x02 PI_RESET_N_MUX_1:RW_D:0:4:=0x01 + 0x01000000, // 270: PI_ZQ_CAL_START_MAP_0:RW_D:24:4:=0x01 PI_MRSINGLE_DATA_3:RW:16:8:=0x00 PI_MRSINGLE_DATA_2:RW:8:8:=0x00 PI_MRSINGLE_DATA_1:RW:0:8:=0x00 + 0x04020201, // 271: PI_ZQ_CAL_START_MAP_2:RW_D:24:4:=0x04 PI_ZQ_CAL_LATCH_MAP_1:RW_D:16:4:=0x02 PI_ZQ_CAL_START_MAP_1:RW_D:8:4:=0x02 PI_ZQ_CAL_LATCH_MAP_0:RW_D:0:4:=0x01 + 0x00080804, // 272: PI_ZQ_CAL_LATCH_MAP_3:RW_D:16:4:=0x08 PI_ZQ_CAL_START_MAP_3:RW_D:8:4:=0x08 PI_ZQ_CAL_LATCH_MAP_2:RW_D:0:4:=0x04 + 0x00000000, // 273: PI_DQS_OSC_BASE_VALUE_1_0:RW+:16:16:=0x0000 PI_DQS_OSC_BASE_VALUE_0_0:RW+:0:16:=0x0000 + 0x00000000, // 274: PI_DQS_OSC_BASE_VALUE_1_1:RW+:16:16:=0x0000 PI_DQS_OSC_BASE_VALUE_0_1:RW+:0:16:=0x0000 + 0x00310004, // 275: PI_MR11_DATA_F0_0:RW+:24:8:=0x00 PI_MR3_DATA_F0_0:RW+:16:8:=0x31 PI_MR2_DATA_F0_0:RW+:8:8:=0x00 PI_MR1_DATA_F0_0:RW+:0:8:=0x04 + 0x00054D17, // 276: PI_MR23_DATA_F0_0:RW:24:8:=0x00 PI_MR22_DATA_F0_0:RW+:16:8:=0x00 PI_MR14_DATA_F0_0:RW+:8:8:=0x4d PI_MR12_DATA_F0_0:RW+:0:8:=0x4d + 0x35F12D54, // 277: PI_MR11_DATA_F1_0:RW+:24:8:=0x00 PI_MR3_DATA_F1_0:RW+:16:8:=0x31 PI_MR2_DATA_F1_0:RW+:8:8:=0x2d PI_MR1_DATA_F1_0:RW+:0:8:=0x54 + 0x00161F17, // 278: PI_MR23_DATA_F1_0:RW:24:8:=0x00 PI_MR22_DATA_F1_0:RW+:16:8:=0x00 PI_MR14_DATA_F1_0:RW+:8:8:=0x4d PI_MR12_DATA_F1_0:RW+:0:8:=0x4d + 0x35F13F74, // 279: PI_MR11_DATA_F2_0:RW+:24:8:=0x00 PI_MR3_DATA_F2_0:RW+:16:8:=0x31 PI_MR2_DATA_F2_0:RW+:8:8:=0x3f PI_MR1_DATA_F2_0:RW+:0:8:=0x74 + 0x00161F17, // 280: PI_MR23_DATA_F2_0:RW:24:8:=0x00 PI_MR22_DATA_F2_0:RW+:16:8:=0x00 PI_MR14_DATA_F2_0:RW+:8:8:=0x4d PI_MR12_DATA_F2_0:RW+:0:8:=0x4d + 0x00310004, // 281: PI_MR11_DATA_F0_1:RW+:24:8:=0x00 PI_MR3_DATA_F0_1:RW+:16:8:=0x31 PI_MR2_DATA_F0_1:RW+:8:8:=0x00 PI_MR1_DATA_F0_1:RW+:0:8:=0x04 + 0x00054D17, // 282: PI_MR23_DATA_F0_1:RW:24:8:=0x00 PI_MR22_DATA_F0_1:RW+:16:8:=0x00 PI_MR14_DATA_F0_1:RW+:8:8:=0x4d PI_MR12_DATA_F0_1:RW+:0:8:=0x4d + 0x35F12D54, // 283: PI_MR11_DATA_F1_1:RW+:24:8:=0x00 PI_MR3_DATA_F1_1:RW+:16:8:=0x31 PI_MR2_DATA_F1_1:RW+:8:8:=0x2d PI_MR1_DATA_F1_1:RW+:0:8:=0x54 + 0x00161F17, // 284: PI_MR23_DATA_F1_1:RW:24:8:=0x00 PI_MR22_DATA_F1_1:RW+:16:8:=0x00 PI_MR14_DATA_F1_1:RW+:8:8:=0x4d PI_MR12_DATA_F1_1:RW+:0:8:=0x4d + 0x35F13F74, // 285: PI_MR11_DATA_F2_1:RW+:24:8:=0x00 PI_MR3_DATA_F2_1:RW+:16:8:=0x31 PI_MR2_DATA_F2_1:RW+:8:8:=0x3f PI_MR1_DATA_F2_1:RW+:0:8:=0x74 + 0x00161F17, // 286: PI_MR23_DATA_F2_1:RW:24:8:=0x00 PI_MR22_DATA_F2_1:RW+:16:8:=0x00 PI_MR14_DATA_F2_1:RW+:8:8:=0x4d PI_MR12_DATA_F2_1:RW+:0:8:=0x4d + 0x00310004, // 287: PI_MR11_DATA_F0_2:RW+:24:8:=0x00 PI_MR3_DATA_F0_2:RW+:16:8:=0x31 PI_MR2_DATA_F0_2:RW+:8:8:=0x00 PI_MR1_DATA_F0_2:RW+:0:8:=0x04 + 0x00054D17, // 288: PI_MR23_DATA_F0_2:RW:24:8:=0x00 PI_MR22_DATA_F0_2:RW+:16:8:=0x00 PI_MR14_DATA_F0_2:RW+:8:8:=0x4d PI_MR12_DATA_F0_2:RW+:0:8:=0x4d + 0x35F12D54, // 289: PI_MR11_DATA_F1_2:RW+:24:8:=0x00 PI_MR3_DATA_F1_2:RW+:16:8:=0x31 PI_MR2_DATA_F1_2:RW+:8:8:=0x2d PI_MR1_DATA_F1_2:RW+:0:8:=0x54 + 0x00161F17, // 290: PI_MR23_DATA_F1_2:RW:24:8:=0x00 PI_MR22_DATA_F1_2:RW+:16:8:=0x00 PI_MR14_DATA_F1_2:RW+:8:8:=0x4d PI_MR12_DATA_F1_2:RW+:0:8:=0x4d + 0x35F13F74, // 291: PI_MR11_DATA_F2_2:RW+:24:8:=0x00 PI_MR3_DATA_F2_2:RW+:16:8:=0x31 PI_MR2_DATA_F2_2:RW+:8:8:=0x3f PI_MR1_DATA_F2_2:RW+:0:8:=0x74 + 0x00161F17, // 292: PI_MR23_DATA_F2_2:RW:24:8:=0x00 PI_MR22_DATA_F2_2:RW+:16:8:=0x00 PI_MR14_DATA_F2_2:RW+:8:8:=0x4d PI_MR12_DATA_F2_2:RW+:0:8:=0x4d + 0x00310004, // 293: PI_MR11_DATA_F0_3:RW+:24:8:=0x00 PI_MR3_DATA_F0_3:RW+:16:8:=0x31 PI_MR2_DATA_F0_3:RW+:8:8:=0x00 PI_MR1_DATA_F0_3:RW+:0:8:=0x04 + 0x00054D17, // 294: PI_MR23_DATA_F0_3:RW:24:8:=0x00 PI_MR22_DATA_F0_3:RW+:16:8:=0x00 PI_MR14_DATA_F0_3:RW+:8:8:=0x4d PI_MR12_DATA_F0_3:RW+:0:8:=0x4d + 0x35F12D54, // 295: PI_MR11_DATA_F1_3:RW+:24:8:=0x00 PI_MR3_DATA_F1_3:RW+:16:8:=0x31 PI_MR2_DATA_F1_3:RW+:8:8:=0x2d PI_MR1_DATA_F1_3:RW+:0:8:=0x54 + 0x00161F17, // 296: PI_MR23_DATA_F1_3:RW:24:8:=0x00 PI_MR22_DATA_F1_3:RW+:16:8:=0x00 PI_MR14_DATA_F1_3:RW+:8:8:=0x4d PI_MR12_DATA_F1_3:RW+:0:8:=0x4d + 0x35F13F74, // 297: PI_MR11_DATA_F2_3:RW+:24:8:=0x00 PI_MR3_DATA_F2_3:RW+:16:8:=0x31 PI_MR2_DATA_F2_3:RW+:8:8:=0x3f PI_MR1_DATA_F2_3:RW+:0:8:=0x74 + 0x00161F17, // 298: PI_MR23_DATA_F2_3:RW:24:8:=0x00 PI_MR22_DATA_F2_3:RW+:16:8:=0x00 PI_MR14_DATA_F2_3:RW+:8:8:=0x4d PI_MR12_DATA_F2_3:RW+:0:8:=0x4d + 0x00000000 // 299: PI_PARITY_ERROR_REGIF:RW:0:11:=0x0000 +}; + + +uint32_t DDR_PHY_registers[] = +{ + 0x000004F0, // 0: PHY_IO_PAD_DELAY_TIMING_BYPASS_0:RW:16:4:=0x00 PHY_CLK_WR_BYPASS_SLAVE_DELAY_0:RW:0:11:=0x04f0 + 0x00000000, // 1: PHY_WRITE_PATH_LAT_ADD_BYPASS_0:RW:16:3:=0x00 PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0:RW:0:10:=0x0000 + 0x00030200, // 2: PHY_CLK_BYPASS_OVERRIDE_0:RW:24:1:=0x00 PHY_BYPASS_TWO_CYC_PREAMBLE_0:RW:16:2:=0x03 PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0:RW:0:10:=0x0200 + 0x00000000, // 3: PHY_SW_WRDQ3_SHIFT_0:RW:24:6:=0x00 PHY_SW_WRDQ2_SHIFT_0:RW:16:6:=0x00 PHY_SW_WRDQ1_SHIFT_0:RW:8:6:=0x00 PHY_SW_WRDQ0_SHIFT_0:RW:0:6:=0x00 + 0x00000000, // 4: PHY_SW_WRDQ7_SHIFT_0:RW:24:6:=0x00 PHY_SW_WRDQ6_SHIFT_0:RW:16:6:=0x00 PHY_SW_WRDQ5_SHIFT_0:RW:8:6:=0x00 PHY_SW_WRDQ4_SHIFT_0:RW:0:6:=0x00 + 0x01030000, // 5: PHY_PER_CS_TRAINING_MULTICAST_EN_0:RW_D:24:1:=0x01 PHY_PER_RANK_CS_MAP_0:RW+:16:2:=0x03 PHY_SW_WRDQS_SHIFT_0:RW:8:4:=0x00 PHY_SW_WRDM_SHIFT_0:RW:0:6:=0x00 + 0x00010000, // 6: PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0:RW:24:5:=0x00 PHY_LP4_BOOT_RDDATA_EN_DLY_0:RW:16:5:=0x01 PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0:RW:8:2:=0x00 PHY_PER_CS_TRAINING_INDEX_0:RW+:0:1:=0x00 + 0x01030004, // 7: PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0:RW:24:5:=0x01 PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0:RW:16:2:=0x03 PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0:RW:8:4:=0x00 PHY_LP4_BOOT_RPTR_UPDATE_0:RW:0:4:=0x04 + 0x01000000, // 8: PHY_LPBK_DFX_TIMEOUT_EN_0:RW:24:1:=0x01 PHY_LPBK_CONTROL_0:RW:8:9:=0x0000 PHY_CTRL_LPBK_EN_0:RW:0:2:=0x00 + 0x00000000, // 9: PHY_AUTO_TIMING_MARGIN_CONTROL_0:RW:0:32:=0x00000000 + 0x00000000, // 10: PHY_AUTO_TIMING_MARGIN_OBS_0:RD:0:28:=0x00000000 + 0x01000001, // 11: PHY_RDLVL_MULTI_PATT_ENABLE_0:RW:24:1:=0x00 PHY_PRBS_PATTERN_MASK_0:RW:8:9:=0x0000 PHY_PRBS_PATTERN_START_0:RW_D:0:7:=0x01 + 0x00000400, // 12: PHY_VREF_TRAIN_OBS_0:RD:16:7:=0x00 PHY_VREF_INITIAL_STEPSIZE_0:RW:8:6:=0x04 PHY_RDLVL_MULTI_PATT_RST_DISABLE_0:RW:0:1:=0x00 + 0x000800C0, // 13: SC_PHY_SNAP_OBS_REGS_0:WR:24:1:=0x00 PHY_GATE_ERROR_DELAY_SELECT_0:RW:16:4:=0x08 PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0:RW:0:10:=0x00c0 + 0x060100CC, // 14: PHY_MEM_CLASS_0:RW:24:3:=0x06 PHY_LPDDR_0:RW:16:1:=0x01 PHY_GATE_SMPL1_SLAVE_DELAY_0:RW:0:9:=0x00cc + 0x00030066, // 15: ON_FLY_GATE_ADJUST_EN_0:RW:16:2:=0x03 PHY_GATE_SMPL2_SLAVE_DELAY_0:RW:0:9:=0x0066 + 0x00000000, // 16: PHY_GATE_TRACKING_OBS_0:RD:0:32:=0x00000000 + 0x00000001, // 17: PHY_LP4_PST_AMBLE_0:RW:8:2:=0x00 PHY_DFI40_POLARITY_0:RW:0:1:=0x01 + 0x0000AAAA, // 18: PHY_RDLVL_PATT8_0:RW:0:32:=0x0000AAAA + 0x00005555, // 19: PHY_RDLVL_PATT9_0:RW:0:32:=0x00005555 + 0x0000B5B5, // 20: PHY_RDLVL_PATT10_0:RW:0:32:=0x0000B5B5 + 0x00004A4A, // 21: PHY_RDLVL_PATT11_0:RW:0:32:=0x00004A4A + 0x00005656, // 22: PHY_RDLVL_PATT12_0:RW:0:32:=0x00005656 + 0x0000A9A9, // 23: PHY_RDLVL_PATT13_0:RW:0:32:=0x0000A9A9 + 0x0000A9A9, // 24: PHY_RDLVL_PATT14_0:RW:0:32:=0x0000A9A9 + 0x0000B5B5, // 25: PHY_RDLVL_PATT15_0:RW:0:32:=0x0000B5B5 + 0x00000000, // 26: PHY_RDDQ_ENC_OBS_SELECT_0:RW:24:3:=0x00 PHY_MASTER_DLY_LOCK_OBS_SELECT_0:RW:16:4:=0x00 PHY_SW_FIFO_PTR_RST_DISABLE_0:RW:8:1:=0x00 PHY_SLAVE_LOOP_CNT_UPDATE_0:RW:0:3:=0x00 + 0x00000000, // 27: PHY_FIFO_PTR_OBS_SELECT_0:RW:24:4:=0x00 PHY_WR_SHIFT_OBS_SELECT_0:RW:16:4:=0x00 PHY_WR_ENC_OBS_SELECT_0:RW:8:4:=0x00 PHY_RDDQS_DQ_ENC_OBS_SELECT_0:RW:0:4:=0x00 + 0x2A000000, // 28: PHY_WRLVL_PER_START_0:RW:24:8:=0x2A PHY_WRLVL_ALGO_0:RW:16:2:=0x00 SC_PHY_LVL_DEBUG_CONT_0:WR:8:1:=0x00 PHY_LVL_DEBUG_MODE_0:RW:0:1:=0x00 + 0x00000808, // 29: PHY_DQ_MASK_0:RW:16:8:=0x00 PHY_WRLVL_UPDT_WAIT_CNT_0:RW:8:4:=0x08 PHY_WRLVL_CAPTURE_CNT_0:RW:0:6:=0x08 + 0x04080000, // 30: PHY_GTLVL_UPDT_WAIT_CNT_0:RW:24:4:=0x04 PHY_GTLVL_CAPTURE_CNT_0:RW:16:6:=0x00 PHY_GTLVL_PER_START_0:RW:0:10:=0x0000 + 0x00000408, // 31: PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0:RW:24:5:=0x00 PHY_RDLVL_OP_MODE_0:RW:16:2:=0x00 PHY_RDLVL_UPDT_WAIT_CNT_0:RW:8:4:=0x04 PHY_RDLVL_CAPTURE_CNT_0:RW:0:6:=0x08 + 0x10300000, // 32: PHY_WDQLVL_BURST_CNT_0:RW:24:6:=0x10 PHY_WDQLVL_CLK_JITTER_TOLERANCE_0:RW:16:8:=0x20 PHY_RDLVL_DATA_MASK_0:RW:8:8:=0x00 PHY_RDLVL_PERIODIC_OBS_SELECT_0:RW:0:8:=0x00 + 0x0C002007, // 33: PHY_WDQLVL_UPDT_WAIT_CNT_0:RW:24:4:=0x0c PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0:RW:8:11:=0x0020 PHY_WDQLVL_PATT_0:RW:0:3:=0x07 + 0x00000000, // 34: SC_PHY_WDQLVL_CLR_PREV_RESULTS_0:WR:16:1:=0x00 PHY_WDQLVL_PERIODIC_OBS_SELECT_0:RW:8:8:=0x00 PHY_WDQLVL_DQDM_OBS_SELECT_0:RW:0:4:=0x00 + 0x00000100, // 35: PHY_WDQLVL_DATADM_MASK_0:RW:0:9:=0x0100 + 0x55555555, // 36: PHY_USER_PATT0_0:RW:0:32:=0x55555555 + 0xAAAAAAAA, // 37: PHY_USER_PATT1_0:RW:0:32:=0xAAAAAAAA + 0x55555555, // 38: PHY_USER_PATT2_0:RW:0:32:=0x55555555 + 0xAAAAAAAA, // 39: PHY_USER_PATT3_0:RW:0:32:=0xAAAAAAAA + 0x00005555, // 40: PHY_NTP_MULT_TRAIN_0:RW:16:1:=0x00 PHY_USER_PATT4_0:RW:0:16:=0x5555 + 0x01000100, // 41: PHY_NTP_PERIOD_THRESHOLD_0:RW:16:10:=0x0100 PHY_NTP_EARLY_THRESHOLD_0:RW:0:10:=0x0100 + 0x00800180, // 42: PHY_NTP_PERIOD_THRESHOLD_MAX_0:RW:16:10:=0x0080 PHY_NTP_PERIOD_THRESHOLD_MIN_0:RW:0:10:=0x0180 + 0x00000001, // 43: PHY_FIFO_PTR_OBS_0:RD:16:8:=0x00 SC_PHY_MANUAL_CLEAR_0:WR:8:6:=0x00 PHY_CALVL_VREF_DRIVING_SLICE_0:RW:0:1:=0x01 + 0x00000000, // 44: PHY_LPBK_RESULT_OBS_0:RD:0:32:=0x00000000 + 0x00000000, // 45: PHY_MASTER_DLY_LOCK_OBS_0:RD:16:11:=0x0000 PHY_LPBK_ERROR_COUNT_OBS_0:RD:0:16:=0x0000 + 0x00000000, // 46: PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0:RD:24:8:=0x00 PHY_MEAS_DLY_STEP_VALUE_0:RD:16:8:=0x00 PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0:RD:8:7:=0x00 PHY_RDDQ_SLV_DLY_ENC_OBS_0:RD:0:7:=0x00 + 0x00000000, // 47: PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0:RD:24:7:=0x00 PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0:RD:8:11:=0x0000 PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0:RD:0:8:=0x00 + 0x00000000, // 48: PHY_WR_SHIFT_OBS_0:RD:16:3:=0x00 PHY_WR_ADDER_SLV_DLY_ENC_OBS_0:RD:8:8:=0x00 PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0:RD:0:8:=0x00 + 0x00000000, // 49: PHY_WRLVL_HARD1_DELAY_OBS_0:RD:16:10:=0x0000 PHY_WRLVL_HARD0_DELAY_OBS_0:RD:0:10:=0x0000 + 0x00000000, // 50: PHY_WRLVL_STATUS_OBS_0:RD:0:17:=0x000000 + 0x00000000, // 51: PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0:RD:16:10:=0x0000 PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0:RD:0:10:=0x0000 + 0x00000000, // 52: PHY_GTLVL_HARD0_DELAY_OBS_0:RD:16:14:=0x0000 PHY_WRLVL_ERROR_OBS_0:RD:0:16:=0x0000 + 0x00000000, // 53: PHY_GTLVL_HARD1_DELAY_OBS_0:RD:0:14:=0x0000 + 0x00000000, // 54: PHY_GTLVL_STATUS_OBS_0:RD:0:18:=0x000000 + 0x00000000, // 55: PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0:RD:16:10:=0x0000 PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0:RD:0:10:=0x0000 + 0x00000000, // 56: PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0:RD:0:2:=0x00 + 0x00000000, // 57: PHY_RDLVL_STATUS_OBS_0:RD:0:32:=0x00000000 + 0x00000000, // 58: PHY_RDLVL_PERIODIC_OBS_0:RD:0:32:=0x00000000 + 0x00000000, // 59: PHY_WDQLVL_DQDM_TE_DLY_OBS_0:RD:16:11:=0x0000 PHY_WDQLVL_DQDM_LE_DLY_OBS_0:RD:0:11:=0x0000 + 0x00000000, // 60: PHY_WDQLVL_STATUS_OBS_0:RD:0:32:=0x00000000 + 0x00000000, // 61: PHY_WDQLVL_PERIODIC_OBS_0:RD:0:32:=0x00000000 + 0x00000000, // 62: PHY_DDL_MODE_0:RW:0:31:=0x00000000 + 0x00000000, // 63: PHY_DDL_MASK_0:RW:0:6:=0x00 + 0x00000000, // 64: PHY_DDL_TEST_OBS_0:RD:0:32:=0x00000000 + 0x00000000, // 65: PHY_DDL_TEST_MSTR_DLY_OBS_0:RD:0:32:=0x00000000 + 0x00000104, // 66: PHY_RX_CAL_OVERRIDE_0:RW:24:1:=0x00 SC_PHY_RX_CAL_START_0:WR:16:1:=0x00 PHY_LP4_WDQS_OE_EXTEND_0:RW:8:1:=0x00 PHY_DDL_TRACK_UPD_THRESHOLD_0:RW:0:8:=0x04 + 0x00000120, // 67: PHY_RX_CAL_DQ0_0:RW_D+:16:9:=0x0000 PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0:RW:8:1:=0x01 PHY_RX_CAL_SAMPLE_WAIT_0:RW:0:8:=0x20 + 0x00000000, // 68: PHY_RX_CAL_DQ2_0:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQ1_0:RW_D+:0:9:=0x0000 + 0x00000000, // 69: PHY_RX_CAL_DQ4_0:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQ3_0:RW_D+:0:9:=0x0000 + 0x00000000, // 70: PHY_RX_CAL_DQ6_0:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQ5_0:RW_D+:0:9:=0x0000 + 0x00000000, // 71: PHY_RX_CAL_DQ7_0:RW_D+:0:9:=0x0000 + 0x00000000, // 72: PHY_RX_CAL_DM_0:RW_D+:0:18:=0x000000 + 0x00000000, // 73: PHY_RX_CAL_FDBK_0:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQS_0:RW_D+:0:9:=0x0000 + 0x00000000, // 74: PHY_RX_CAL_LOCK_OBS_0:RD:16:9:=0x0000 PHY_RX_CAL_OBS_0:RD:0:11:=0x0000 + 0x00000001, // 75: PHY_RX_CAL_COMP_VAL_0:RW:24:1:=0x00 PHY_RX_CAL_DIFF_ADJUST_0:RW:16:7:=0x00 PHY_RX_CAL_SE_ADJUST_0:RW:8:7:=0x00 PHY_RX_CAL_DISABLE_0:RW_D:0:1:=0x01 + 0x07FF0000, // 76: PHY_PAD_RX_BIAS_EN_0:RW:16:11:=0x07ff PHY_RX_CAL_INDEX_MASK_0:RW:0:12:=0x0000 + 0x0080081F, // 77: PHY_DATA_DC_WEIGHT_0:RW:24:2:=0x00 PHY_DATA_DC_CAL_TIMEOUT_0:RW:16:8:=0x80 PHY_DATA_DC_CAL_SAMPLE_WAIT_0:RW:8:8:=0x08 PHY_STATIC_TOG_DISABLE_0:RW:0:5:=0x1f + 0x00081020, // 78: PHY_DATA_DC_ADJUST_DIRECT_0:RW:24:1:=0x00 PHY_DATA_DC_ADJUST_THRSHLD_0:RW:16:8:=0x08 PHY_DATA_DC_ADJUST_SAMPLE_CNT_0:RW:8:8:=0x10 PHY_DATA_DC_ADJUST_START_0:RW:0:6:=0x20 + 0x04010000, // 79: PHY_FDBK_PWR_CTRL_0:RW:24:3:=0x04 PHY_DATA_DC_SW_RANK_0:RW+:16:2:=0x01 PHY_DATA_DC_CAL_START_0:RW+:8:1:=0x00 PHY_DATA_DC_CAL_POLARITY_0:RW:0:1:=0x00 + 0x00000001, // 80: PHY_SLICE_PWR_RDC_DISABLE_0:RW:24:1:=0x00 PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0:RW_D:16:1:=0x00 PHY_RDPATH_GATE_DISABLE_0:RW_D:8:1:=0x00 PHY_SLV_DLY_CTRL_GATE_DISABLE_0:RW_D:0:1:=0x00 + 0x00000000, // 81: PHY_DS_FSM_ERROR_INFO_0:RD:16:14:=0x0000 PHY_PARITY_ERROR_REGIF_0:RW:0:11:=0x0000 + 0x00000000, // 82: SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0:WR:16:14:=0x0000 PHY_DS_FSM_ERROR_INFO_MASK_0:RW:0:14:=0x0000 + 0x00000100, // 83: SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0:WR:16:5:=0x00 PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0:RW:8:5:=0x01 PHY_DS_TRAIN_CALIB_ERROR_INFO_0:RD:0:5:=0x00 + 0x01CC0C05, // 84: PHY_DQS_TSEL_ENABLE_0:RW+:24:3:=0x01 PHY_DQ_TSEL_SELECT_0:RW+:8:16:=0x4408 PHY_DQ_TSEL_ENABLE_0:RW+:0:3:=0x01 + 0x1B03CC0C, // 85: PHY_VREF_INITIAL_START_POINT_0:RW+:24:7:=0x20 PHY_TWO_CYC_PREAMBLE_0:RW+:16:2:=0x03 PHY_DQS_TSEL_SELECT_0:RW+:0:16:=0x4408 + 0x20000130, // 86: PHY_NTP_WDQ_STEP_SIZE_0:RW+:24:8:=0x20 PHY_NTP_TRAIN_EN_0:RW+:16:1:=0x00 PHY_VREF_TRAINING_CTRL_0:RW+:8:2:=0x01 PHY_VREF_INITIAL_STOP_POINT_0:RW+:0:7:=0x25 + 0x07FF0200, // 87: PHY_NTP_WDQ_STOP_0:RW+:16:11:=0x07FF PHY_NTP_WDQ_START_0:RW+:0:11:=0x0200 + 0x0000DD01, // 88: PHY_SW_WDQLVL_DVW_MIN_EN_0:RW+:24:1:=0x00 PHY_WDQLVL_DVW_MIN_0:RW+:8:10:=0x00dd PHY_NTP_WDQ_BIT_EN_0:RW+:0:8:=0x01 + 0x00000303, // 89: PHY_PAD_RX_DCD_0_0:RW+:24:5:=0x00 PHY_PAD_TX_DCD_0:RW+:16:5:=0x00 PHY_FAST_LVL_EN_0:RW+:8:4:=0x03 PHY_WDQLVL_PER_START_OFFSET_0:RW+:0:6:=0x03 + 0x00000000, // 90: PHY_PAD_RX_DCD_4_0:RW+:24:5:=0x00 PHY_PAD_RX_DCD_3_0:RW+:16:5:=0x00 PHY_PAD_RX_DCD_2_0:RW+:8:5:=0x00 PHY_PAD_RX_DCD_1_0:RW+:0:5:=0x00 + 0x00000000, // 91: PHY_PAD_DM_RX_DCD_0:RW+:24:5:=0x00 PHY_PAD_RX_DCD_7_0:RW+:16:5:=0x00 PHY_PAD_RX_DCD_6_0:RW+:8:5:=0x00 PHY_PAD_RX_DCD_5_0:RW+:0:5:=0x00 + 0x00030000, // 92: PHY_PAD_DSLICE_IO_CFG_0:RW+:16:6:=0x00 PHY_PAD_FDBK_RX_DCD_0:RW+:8:5:=0x00 PHY_PAD_DQS_RX_DCD_0:RW+:0:5:=0x00 + 0x00000000, // 93: PHY_RDDQ1_SLAVE_DELAY_0:RW+:16:10:=0x0000 PHY_RDDQ0_SLAVE_DELAY_0:RW+:0:10:=0x0000 + 0x00000000, // 94: PHY_RDDQ3_SLAVE_DELAY_0:RW+:16:10:=0x0000 PHY_RDDQ2_SLAVE_DELAY_0:RW+:0:10:=0x0000 + 0x00000000, // 95: PHY_RDDQ5_SLAVE_DELAY_0:RW+:16:10:=0x0000 PHY_RDDQ4_SLAVE_DELAY_0:RW+:0:10:=0x0000 + 0x00000000, // 96: PHY_RDDQ7_SLAVE_DELAY_0:RW+:16:10:=0x0000 PHY_RDDQ6_SLAVE_DELAY_0:RW+:0:10:=0x0000 + 0x00050000, // 97: PHY_DATA_DC_CAL_CLK_SEL_0:RW+:16:3:=0x02 PHY_RDDM_SLAVE_DELAY_0:RW+:0:10:=0x0000 + 0x51515042, // 98: PHY_DQS_OE_TIMING_0:RW+:24:8:=0x51 PHY_DQ_TSEL_WR_TIMING_0:RW+:16:8:=0x51 PHY_DQ_TSEL_RD_TIMING_0:RW+:8:8:=0x50 PHY_DQ_OE_TIMING_0:RW+:0:8:=0x42 + 0x31C06000, // 99: PHY_DQS_TSEL_WR_TIMING_0:RW+:24:8:=0x31 PHY_DQS_OE_RD_TIMING_0:RW+:16:8:=0xc0 PHY_DQS_TSEL_RD_TIMING_0:RW+:8:8:=0x60 PHY_IO_PAD_DELAY_TIMING_0:RW+:0:4:=0x00 + 0x07A000A0, // 100: PHY_PAD_VREF_CTRL_DQ_0:RW+:16:12:=0x069f PHY_VREF_SETTING_TIME_0:RW+:0:16:=0x0004 + 0x00C0C001, // 101: PHY_RDDATA_EN_IE_DLY_0:RW+:24:2:=0x00 PHY_DQS_IE_TIMING_0:RW+:16:8:=0xc0 PHY_DQ_IE_TIMING_0:RW+:8:8:=0xc0 PHY_PER_CS_TRAINING_EN_0:RW+:0:1:=0x01 + 0x0E0D0100, // 102: PHY_RDDATA_EN_OE_DLY_0:RW+:24:5:=0x0e PHY_RDDATA_EN_TSEL_DLY_0:RW+:16:5:=0x0d PHY_DBI_MODE_0:RW+:8:1:=0x00 PHY_IE_MODE_0:RW+:0:2:=0x00 + 0x10001000, // 103: PHY_MASTER_DELAY_STEP_0:RW+:24:6:=0x10 PHY_MASTER_DELAY_START_0:RW+:8:11:=0x0010 PHY_SW_MASTER_MODE_0:RW+:0:4:=0x00 + 0x0C063E42, // 104: PHY_WRLVL_DLY_STEP_0:RW+:24:8:=0x0c PHY_RPTR_UPDATE_0:RW+:16:4:=0x06 PHY_MASTER_DELAY_HALF_MEASURE_0:RW+:8:8:=0x3e PHY_MASTER_DELAY_WAIT_0:RW+:0:8:=0x42 + 0x0F0C3701, // 105: PHY_GTLVL_RESP_WAIT_CNT_0:RW+:24:5:=0x0f PHY_GTLVL_DLY_STEP_0:RW+:16:4:=0x0c PHY_WRLVL_RESP_WAIT_CNT_0:RW+:8:6:=0x37 PHY_WRLVL_DLY_FINE_STEP_0:RW+:0:4:=0x01 + 0x01000140, // 106: PHY_GTLVL_FINAL_STEP_0:RW+:16:10:=0x0100 PHY_GTLVL_BACK_STEP_0:RW+:0:10:=0x0140 + 0x0C000120, // 107: PHY_RDLVL_DLY_STEP_0:RW+:24:4:=0x0c PHY_TOGGLE_PRE_SUPPORT_0:RW+:16:1:=0x00 PHY_WDQLVL_QTR_DLY_STEP_0:RW+:8:4:=0x01 PHY_WDQLVL_DLY_STEP_0:RW+:0:8:=0x20 + 0x00000322, // 108: PHY_RDLVL_MAX_EDGE_0:RW+:0:10:=0x0322 + 0x0A0000D0, // 109: PHY_RDLVL_PER_START_OFFSET_0:RW+:24:6:=0x0A PHY_SW_RDLVL_DVW_MIN_EN_0:RW+:16:1:=0x00 PHY_RDLVL_DVW_MIN_0:RW+:0:10:=0x00d0 + 0x00030200, // 110: PHY_DATA_DC_INIT_DISABLE_0:RW+:16:2:=0x00 PHY_WRPATH_GATE_TIMING_0:RW+:8:3:=0x02 PHY_WRPATH_GATE_DISABLE_0:RW+:0:2:=0x00 + 0x02800000, // 111: PHY_DATA_DC_DQ_INIT_SLV_DELAY_0:RW+:16:11:=0x0280 PHY_DATA_DC_DQS_INIT_SLV_DELAY_0:RW+:0:10:=0x0000 + 0x80800000, // 112: PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0:RW+:24:8:=0x80 PHY_DATA_DC_DM_CLK_SE_THRSHLD_0:RW+:16:8:=0x80 PHY_DATA_DC_WDQLVL_ENABLE_0:RW+:8:1:=0x01 PHY_DATA_DC_WRLVL_ENABLE_0:RW+:0:1:=0x01 + 0x000E2010, // 113: PHY_RDDATA_EN_DLY_0:RW+:16:5:=0x0e PHY_MEAS_DLY_STEP_ENABLE_0:RW+:8:6:=0x20 PHY_WDQ_OSC_DELTA_0:RW+:0:7:=0x10 + 0x56247310, // 114: PHY_DQ_DM_SWIZZLE0_0:RW+:0:32:=0x56247310 + 0x00000008, // 115: PHY_DQ_DM_SWIZZLE1_0:RW+:0:4:=0x08 + 0x02800280, // 116: PHY_CLK_WRDQ1_SLAVE_DELAY_0:RW+:16:11:=0x0280 PHY_CLK_WRDQ0_SLAVE_DELAY_0:RW+:0:11:=0x0280 + 0x02800280, // 117: PHY_CLK_WRDQ3_SLAVE_DELAY_0:RW+:16:11:=0x0280 PHY_CLK_WRDQ2_SLAVE_DELAY_0:RW+:0:11:=0x0280 + 0x02800280, // 118: PHY_CLK_WRDQ5_SLAVE_DELAY_0:RW+:16:11:=0x0280 PHY_CLK_WRDQ4_SLAVE_DELAY_0:RW+:0:11:=0x0280 + 0x02800280, // 119: PHY_CLK_WRDQ7_SLAVE_DELAY_0:RW+:16:11:=0x0280 PHY_CLK_WRDQ6_SLAVE_DELAY_0:RW+:0:11:=0x0280 + 0x00000280, // 120: PHY_CLK_WRDQS_SLAVE_DELAY_0:RW+:16:10:=0x0000 PHY_CLK_WRDM_SLAVE_DELAY_0:RW+:0:11:=0x0280 + 0x0000A000, // 121: PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0:RW+:8:10:=0x00a0 PHY_WRLVL_THRESHOLD_ADJUST_0:RW+:0:2:=0x00 + 0x00A000A0, // 122: PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0 + 0x00A000A0, // 123: PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0 + 0x00A000A0, // 124: PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0 + 0x00A000A0, // 125: PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0 + 0x00A000A0, // 126: PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0 + 0x00A000A0, // 127: PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0 + 0x00A000A0, // 128: PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0 + 0x00A000A0, // 129: PHY_RDDQS_DM_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0 + 0x01C200A0, // 130: PHY_RDDQS_GATE_SLAVE_DELAY_0:RW+:16:10:=0x01c2 PHY_RDDQS_DM_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0 + 0x01A00005, // 131: PHY_WRLVL_DELAY_EARLY_THRESHOLD_0:RW+:16:10:=0x01A0 PHY_WRITE_PATH_LAT_ADD_0:RW+:8:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_0:RW+:0:4:=0x05 + 0x00000000, // 132: PHY_WRLVL_EARLY_FORCE_ZERO_0:RW+:16:1:=0x00 PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0:RW+:0:10:=0x0000 + 0x00060000, // 133: PHY_GTLVL_LAT_ADJ_START_0:RW+:16:4:=0x06 PHY_GTLVL_RDDQS_SLV_DLY_START_0:RW+:0:10:=0x0000 + 0x00080200, // 134: PHY_NTP_PASS_0:RW+:24:1:=0x00 PHY_NTP_WRLAT_START_0:RW+:16:4:=0x08 PHY_WDQLVL_DQDM_SLV_DLY_START_0:RW+:0:11:=0x0200 + 0x00000000, // 135: PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0:RW+:0:10:=0x0000 + 0x20202020, // 136: PHY_DATA_DC_DQ2_CLK_ADJUST_0:RW+:24:8:=0x20 PHY_DATA_DC_DQ1_CLK_ADJUST_0:RW+:16:8:=0x20 PHY_DATA_DC_DQ0_CLK_ADJUST_0:RW+:8:8:=0x20 PHY_DATA_DC_DQS_CLK_ADJUST_0:RW+:0:8:=0x20 + 0x20202020, // 137: PHY_DATA_DC_DQ6_CLK_ADJUST_0:RW+:24:8:=0x20 PHY_DATA_DC_DQ5_CLK_ADJUST_0:RW+:16:8:=0x20 PHY_DATA_DC_DQ4_CLK_ADJUST_0:RW+:8:8:=0x20 PHY_DATA_DC_DQ3_CLK_ADJUST_0:RW+:0:8:=0x20 + 0xF0F02020, // 138: PHY_DSLICE_PAD_BOOSTPN_SETTING_0:RW+:16:16:=0x0000 PHY_DATA_DC_DM_CLK_ADJUST_0:RW+:8:8:=0x20 PHY_DATA_DC_DQ7_CLK_ADJUST_0:RW+:0:8:=0x20 + 0x00000000, // 139: PHY_DQS_FFE_0:RW+:16:2:=0x00 PHY_DQ_FFE_0:RW+:8:2:=0x00 PHY_DSLICE_PAD_RX_CTLE_SETTING_0:RW+:0:6:=0x00 + 0x00000000, // 140: + 0x00000000, // 141: + 0x00000000, // 142: + 0x00000000, // 143: + 0x00000000, // 144: + 0x00000000, // 145: + 0x00000000, // 146: + 0x00000000, // 147: + 0x00000000, // 148: + 0x00000000, // 149: + 0x00000000, // 150: + 0x00000000, // 151: + 0x00000000, // 152: + 0x00000000, // 153: + 0x00000000, // 154: + 0x00000000, // 155: + 0x00000000, // 156: + 0x00000000, // 157: + 0x00000000, // 158: + 0x00000000, // 159: + 0x00000000, // 160: + 0x00000000, // 161: + 0x00000000, // 162: + 0x00000000, // 163: + 0x00000000, // 164: + 0x00000000, // 165: + 0x00000000, // 166: + 0x00000000, // 167: + 0x00000000, // 168: + 0x00000000, // 169: + 0x00000000, // 170: + 0x00000000, // 171: + 0x00000000, // 172: + 0x00000000, // 173: + 0x00000000, // 174: + 0x00000000, // 175: + 0x00000000, // 176: + 0x00000000, // 177: + 0x00000000, // 178: + 0x00000000, // 179: + 0x00000000, // 180: + 0x00000000, // 181: + 0x00000000, // 182: + 0x00000000, // 183: + 0x00000000, // 184: + 0x00000000, // 185: + 0x00000000, // 186: + 0x00000000, // 187: + 0x00000000, // 188: + 0x00000000, // 189: + 0x00000000, // 190: + 0x00000000, // 191: + 0x00000000, // 192: + 0x00000000, // 193: + 0x00000000, // 194: + 0x00000000, // 195: + 0x00000000, // 196: + 0x00000000, // 197: + 0x00000000, // 198: + 0x00000000, // 199: + 0x00000000, // 200: + 0x00000000, // 201: + 0x00000000, // 202: + 0x00000000, // 203: + 0x00000000, // 204: + 0x00000000, // 205: + 0x00000000, // 206: + 0x00000000, // 207: + 0x00000000, // 208: + 0x00000000, // 209: + 0x00000000, // 210: + 0x00000000, // 211: + 0x00000000, // 212: + 0x00000000, // 213: + 0x00000000, // 214: + 0x00000000, // 215: + 0x00000000, // 216: + 0x00000000, // 217: + 0x00000000, // 218: + 0x00000000, // 219: + 0x00000000, // 220: + 0x00000000, // 221: + 0x00000000, // 222: + 0x00000000, // 223: + 0x00000000, // 224: + 0x00000000, // 225: + 0x00000000, // 226: + 0x00000000, // 227: + 0x00000000, // 228: + 0x00000000, // 229: + 0x00000000, // 230: + 0x00000000, // 231: + 0x00000000, // 232: + 0x00000000, // 233: + 0x00000000, // 234: + 0x00000000, // 235: + 0x00000000, // 236: + 0x00000000, // 237: + 0x00000000, // 238: + 0x00000000, // 239: + 0x00000000, // 240: + 0x00000000, // 241: + 0x00000000, // 242: + 0x00000000, // 243: + 0x00000000, // 244: + 0x00000000, // 245: + 0x00000000, // 246: + 0x00000000, // 247: + 0x00000000, // 248: + 0x00000000, // 249: + 0x00000000, // 250: + 0x00000000, // 251: + 0x00000000, // 252: + 0x00000000, // 253: + 0x00000000, // 254: + 0x00000000, // 255: + 0x000004F0, // 256: PHY_IO_PAD_DELAY_TIMING_BYPASS_1:RW:16:4:=0x00 PHY_CLK_WR_BYPASS_SLAVE_DELAY_1:RW:0:11:=0x04f0 + 0x00000000, // 257: PHY_WRITE_PATH_LAT_ADD_BYPASS_1:RW:16:3:=0x00 PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1:RW:0:10:=0x0000 + 0x00030200, // 258: PHY_CLK_BYPASS_OVERRIDE_1:RW:24:1:=0x00 PHY_BYPASS_TWO_CYC_PREAMBLE_1:RW:16:2:=0x03 PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1:RW:0:10:=0x0200 + 0x00000000, // 259: PHY_SW_WRDQ3_SHIFT_1:RW:24:6:=0x00 PHY_SW_WRDQ2_SHIFT_1:RW:16:6:=0x00 PHY_SW_WRDQ1_SHIFT_1:RW:8:6:=0x00 PHY_SW_WRDQ0_SHIFT_1:RW:0:6:=0x00 + 0x00000000, // 260: PHY_SW_WRDQ7_SHIFT_1:RW:24:6:=0x00 PHY_SW_WRDQ6_SHIFT_1:RW:16:6:=0x00 PHY_SW_WRDQ5_SHIFT_1:RW:8:6:=0x00 PHY_SW_WRDQ4_SHIFT_1:RW:0:6:=0x00 + 0x01030000, // 261: PHY_PER_CS_TRAINING_MULTICAST_EN_1:RW_D:24:1:=0x01 PHY_PER_RANK_CS_MAP_1:RW+:16:2:=0x03 PHY_SW_WRDQS_SHIFT_1:RW:8:4:=0x00 PHY_SW_WRDM_SHIFT_1:RW:0:6:=0x00 + 0x00010000, // 262: PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1:RW:24:5:=0x00 PHY_LP4_BOOT_RDDATA_EN_DLY_1:RW:16:5:=0x01 PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1:RW:8:2:=0x00 PHY_PER_CS_TRAINING_INDEX_1:RW+:0:1:=0x00 + 0x01030004, // 263: PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1:RW:24:5:=0x01 PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1:RW:16:2:=0x03 PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1:RW:8:4:=0x00 PHY_LP4_BOOT_RPTR_UPDATE_1:RW:0:4:=0x04 + 0x01000000, // 264: PHY_LPBK_DFX_TIMEOUT_EN_1:RW:24:1:=0x01 PHY_LPBK_CONTROL_1:RW:8:9:=0x0000 PHY_CTRL_LPBK_EN_1:RW:0:2:=0x00 + 0x00000000, // 265: PHY_AUTO_TIMING_MARGIN_CONTROL_1:RW:0:32:=0x00000000 + 0x00000000, // 266: PHY_AUTO_TIMING_MARGIN_OBS_1:RD:0:28:=0x00000000 + 0x01000001, // 267: PHY_RDLVL_MULTI_PATT_ENABLE_1:RW:24:1:=0x00 PHY_PRBS_PATTERN_MASK_1:RW:8:9:=0x0000 PHY_PRBS_PATTERN_START_1:RW_D:0:7:=0x01 + 0x00000400, // 268: PHY_VREF_TRAIN_OBS_1:RD:16:7:=0x00 PHY_VREF_INITIAL_STEPSIZE_1:RW:8:6:=0x04 PHY_RDLVL_MULTI_PATT_RST_DISABLE_1:RW:0:1:=0x00 + 0x000800C0, // 269: SC_PHY_SNAP_OBS_REGS_1:WR:24:1:=0x00 PHY_GATE_ERROR_DELAY_SELECT_1:RW:16:4:=0x08 PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1:RW:0:10:=0x00c0 + 0x060100CC, // 270: PHY_MEM_CLASS_1:RW:24:3:=0x06 PHY_LPDDR_1:RW:16:1:=0x01 PHY_GATE_SMPL1_SLAVE_DELAY_1:RW:0:9:=0x00cc + 0x00030066, // 271: ON_FLY_GATE_ADJUST_EN_1:RW:16:2:=0x03 PHY_GATE_SMPL2_SLAVE_DELAY_1:RW:0:9:=0x0066 + 0x00000000, // 272: PHY_GATE_TRACKING_OBS_1:RD:0:32:=0x00000000 + 0x00000001, // 273: PHY_LP4_PST_AMBLE_1:RW:8:2:=0x00 PHY_DFI40_POLARITY_1:RW:0:1:=0x01 + 0x0000AAAA, // 274: PHY_RDLVL_PATT8_1:RW:0:32:=0x0000AAAA + 0x00005555, // 275: PHY_RDLVL_PATT9_1:RW:0:32:=0x00005555 + 0x0000B5B5, // 276: PHY_RDLVL_PATT10_1:RW:0:32:=0x0000B5B5 + 0x00004A4A, // 277: PHY_RDLVL_PATT11_1:RW:0:32:=0x00004A4A + 0x00005656, // 278: PHY_RDLVL_PATT12_1:RW:0:32:=0x00005656 + 0x0000A9A9, // 279: PHY_RDLVL_PATT13_1:RW:0:32:=0x0000A9A9 + 0x0000A9A9, // 280: PHY_RDLVL_PATT14_1:RW:0:32:=0x0000A9A9 + 0x0000B5B5, // 281: PHY_RDLVL_PATT15_1:RW:0:32:=0x0000B5B5 + 0x00000000, // 282: PHY_RDDQ_ENC_OBS_SELECT_1:RW:24:3:=0x00 PHY_MASTER_DLY_LOCK_OBS_SELECT_1:RW:16:4:=0x00 PHY_SW_FIFO_PTR_RST_DISABLE_1:RW:8:1:=0x00 PHY_SLAVE_LOOP_CNT_UPDATE_1:RW:0:3:=0x00 + 0x00000000, // 283: PHY_FIFO_PTR_OBS_SELECT_1:RW:24:4:=0x00 PHY_WR_SHIFT_OBS_SELECT_1:RW:16:4:=0x00 PHY_WR_ENC_OBS_SELECT_1:RW:8:4:=0x00 PHY_RDDQS_DQ_ENC_OBS_SELECT_1:RW:0:4:=0x00 + 0x2A000000, // 284: PHY_WRLVL_PER_START_1:RW:24:8:=0x2A PHY_WRLVL_ALGO_1:RW:16:2:=0x00 SC_PHY_LVL_DEBUG_CONT_1:WR:8:1:=0x00 PHY_LVL_DEBUG_MODE_1:RW:0:1:=0x00 + 0x00000808, // 285: PHY_DQ_MASK_1:RW:16:8:=0x00 PHY_WRLVL_UPDT_WAIT_CNT_1:RW:8:4:=0x08 PHY_WRLVL_CAPTURE_CNT_1:RW:0:6:=0x08 + 0x04080000, // 286: PHY_GTLVL_UPDT_WAIT_CNT_1:RW:24:4:=0x04 PHY_GTLVL_CAPTURE_CNT_1:RW:16:6:=0x00 PHY_GTLVL_PER_START_1:RW:0:10:=0x0000 + 0x00000408, // 287: PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1:RW:24:5:=0x00 PHY_RDLVL_OP_MODE_1:RW:16:2:=0x00 PHY_RDLVL_UPDT_WAIT_CNT_1:RW:8:4:=0x04 PHY_RDLVL_CAPTURE_CNT_1:RW:0:6:=0x08 + 0x10300000, // 288: PHY_WDQLVL_BURST_CNT_1:RW:24:6:=0x10 PHY_WDQLVL_CLK_JITTER_TOLERANCE_1:RW:16:8:=0x20 PHY_RDLVL_DATA_MASK_1:RW:8:8:=0x00 PHY_RDLVL_PERIODIC_OBS_SELECT_1:RW:0:8:=0x00 + 0x0C002007, // 289: PHY_WDQLVL_UPDT_WAIT_CNT_1:RW:24:4:=0x0c PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1:RW:8:11:=0x0020 PHY_WDQLVL_PATT_1:RW:0:3:=0x07 + 0x00000000, // 290: SC_PHY_WDQLVL_CLR_PREV_RESULTS_1:WR:16:1:=0x00 PHY_WDQLVL_PERIODIC_OBS_SELECT_1:RW:8:8:=0x00 PHY_WDQLVL_DQDM_OBS_SELECT_1:RW:0:4:=0x00 + 0x00000100, // 291: PHY_WDQLVL_DATADM_MASK_1:RW:0:9:=0x0100 + 0x55555555, // 292: PHY_USER_PATT0_1:RW:0:32:=0x55555555 + 0xAAAAAAAA, // 293: PHY_USER_PATT1_1:RW:0:32:=0xAAAAAAAA + 0x55555555, // 294: PHY_USER_PATT2_1:RW:0:32:=0x55555555 + 0xAAAAAAAA, // 295: PHY_USER_PATT3_1:RW:0:32:=0xAAAAAAAA + 0x00005555, // 296: PHY_NTP_MULT_TRAIN_1:RW:16:1:=0x00 PHY_USER_PATT4_1:RW:0:16:=0x5555 + 0x01000100, // 297: PHY_NTP_PERIOD_THRESHOLD_1:RW:16:10:=0x0100 PHY_NTP_EARLY_THRESHOLD_1:RW:0:10:=0x0100 + 0x00800180, // 298: PHY_NTP_PERIOD_THRESHOLD_MAX_1:RW:16:10:=0x0080 PHY_NTP_PERIOD_THRESHOLD_MIN_1:RW:0:10:=0x0180 + 0x00000000, // 299: PHY_FIFO_PTR_OBS_1:RD:16:8:=0x00 SC_PHY_MANUAL_CLEAR_1:WR:8:6:=0x00 PHY_CALVL_VREF_DRIVING_SLICE_1:RW:0:1:=0x00 + 0x00000000, // 300: PHY_LPBK_RESULT_OBS_1:RD:0:32:=0x00000000 + 0x00000000, // 301: PHY_MASTER_DLY_LOCK_OBS_1:RD:16:11:=0x0000 PHY_LPBK_ERROR_COUNT_OBS_1:RD:0:16:=0x0000 + 0x00000000, // 302: PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1:RD:24:8:=0x00 PHY_MEAS_DLY_STEP_VALUE_1:RD:16:8:=0x00 PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1:RD:8:7:=0x00 PHY_RDDQ_SLV_DLY_ENC_OBS_1:RD:0:7:=0x00 + 0x00000000, // 303: PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1:RD:24:7:=0x00 PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1:RD:8:11:=0x0000 PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1:RD:0:8:=0x00 + 0x00000000, // 304: PHY_WR_SHIFT_OBS_1:RD:16:3:=0x00 PHY_WR_ADDER_SLV_DLY_ENC_OBS_1:RD:8:8:=0x00 PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1:RD:0:8:=0x00 + 0x00000000, // 305: PHY_WRLVL_HARD1_DELAY_OBS_1:RD:16:10:=0x0000 PHY_WRLVL_HARD0_DELAY_OBS_1:RD:0:10:=0x0000 + 0x00000000, // 306: PHY_WRLVL_STATUS_OBS_1:RD:0:17:=0x000000 + 0x00000000, // 307: PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1:RD:16:10:=0x0000 PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1:RD:0:10:=0x0000 + 0x00000000, // 308: PHY_GTLVL_HARD0_DELAY_OBS_1:RD:16:14:=0x0000 PHY_WRLVL_ERROR_OBS_1:RD:0:16:=0x0000 + 0x00000000, // 309: PHY_GTLVL_HARD1_DELAY_OBS_1:RD:0:14:=0x0000 + 0x00000000, // 310: PHY_GTLVL_STATUS_OBS_1:RD:0:18:=0x000000 + 0x00000000, // 311: PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1:RD:16:10:=0x0000 PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1:RD:0:10:=0x0000 + 0x00000000, // 312: PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1:RD:0:2:=0x00 + 0x00000000, // 313: PHY_RDLVL_STATUS_OBS_1:RD:0:32:=0x00000000 + 0x00000000, // 314: PHY_RDLVL_PERIODIC_OBS_1:RD:0:32:=0x00000000 + 0x00000000, // 315: PHY_WDQLVL_DQDM_TE_DLY_OBS_1:RD:16:11:=0x0000 PHY_WDQLVL_DQDM_LE_DLY_OBS_1:RD:0:11:=0x0000 + 0x00000000, // 316: PHY_WDQLVL_STATUS_OBS_1:RD:0:32:=0x00000000 + 0x00000000, // 317: PHY_WDQLVL_PERIODIC_OBS_1:RD:0:32:=0x00000000 + 0x00000000, // 318: PHY_DDL_MODE_1:RW:0:31:=0x00000000 + 0x00000000, // 319: PHY_DDL_MASK_1:RW:0:6:=0x00 + 0x00000000, // 320: PHY_DDL_TEST_OBS_1:RD:0:32:=0x00000000 + 0x00000000, // 321: PHY_DDL_TEST_MSTR_DLY_OBS_1:RD:0:32:=0x00000000 + 0x00000104, // 322: PHY_RX_CAL_OVERRIDE_1:RW:24:1:=0x00 SC_PHY_RX_CAL_START_1:WR:16:1:=0x00 PHY_LP4_WDQS_OE_EXTEND_1:RW:8:1:=0x00 PHY_DDL_TRACK_UPD_THRESHOLD_1:RW:0:8:=0x04 + 0x00000120, // 323: PHY_RX_CAL_DQ0_1:RW_D+:16:9:=0x0000 PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1:RW:8:1:=0x01 PHY_RX_CAL_SAMPLE_WAIT_1:RW:0:8:=0x20 + 0x00000000, // 324: PHY_RX_CAL_DQ2_1:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQ1_1:RW_D+:0:9:=0x0000 + 0x00000000, // 325: PHY_RX_CAL_DQ4_1:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQ3_1:RW_D+:0:9:=0x0000 + 0x00000000, // 326: PHY_RX_CAL_DQ6_1:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQ5_1:RW_D+:0:9:=0x0000 + 0x00000000, // 327: PHY_RX_CAL_DQ7_1:RW_D+:0:9:=0x0000 + 0x00000000, // 328: PHY_RX_CAL_DM_1:RW_D+:0:18:=0x000000 + 0x00000000, // 329: PHY_RX_CAL_FDBK_1:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQS_1:RW_D+:0:9:=0x0000 + 0x00000000, // 330: PHY_RX_CAL_LOCK_OBS_1:RD:16:9:=0x0000 PHY_RX_CAL_OBS_1:RD:0:11:=0x0000 + 0x00000001, // 331: PHY_RX_CAL_COMP_VAL_1:RW:24:1:=0x00 PHY_RX_CAL_DIFF_ADJUST_1:RW:16:7:=0x00 PHY_RX_CAL_SE_ADJUST_1:RW:8:7:=0x00 PHY_RX_CAL_DISABLE_1:RW_D:0:1:=0x01 + 0x07FF0000, // 332: PHY_PAD_RX_BIAS_EN_1:RW:16:11:=0x07ff PHY_RX_CAL_INDEX_MASK_1:RW:0:12:=0x0000 + 0x0080081F, // 333: PHY_DATA_DC_WEIGHT_1:RW:24:2:=0x00 PHY_DATA_DC_CAL_TIMEOUT_1:RW:16:8:=0x80 PHY_DATA_DC_CAL_SAMPLE_WAIT_1:RW:8:8:=0x08 PHY_STATIC_TOG_DISABLE_1:RW:0:5:=0x1f + 0x00081020, // 334: PHY_DATA_DC_ADJUST_DIRECT_1:RW:24:1:=0x00 PHY_DATA_DC_ADJUST_THRSHLD_1:RW:16:8:=0x08 PHY_DATA_DC_ADJUST_SAMPLE_CNT_1:RW:8:8:=0x10 PHY_DATA_DC_ADJUST_START_1:RW:0:6:=0x20 + 0x04010000, // 335: PHY_FDBK_PWR_CTRL_1:RW:24:3:=0x04 PHY_DATA_DC_SW_RANK_1:RW+:16:2:=0x01 PHY_DATA_DC_CAL_START_1:RW+:8:1:=0x00 PHY_DATA_DC_CAL_POLARITY_1:RW:0:1:=0x00 + 0x00000001, // 336: PHY_SLICE_PWR_RDC_DISABLE_1:RW:24:1:=0x00 PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1:RW_D:16:1:=0x00 PHY_RDPATH_GATE_DISABLE_1:RW_D:8:1:=0x00 PHY_SLV_DLY_CTRL_GATE_DISABLE_1:RW_D:0:1:=0x00 + 0x00000000, // 337: PHY_DS_FSM_ERROR_INFO_1:RD:16:14:=0x0000 PHY_PARITY_ERROR_REGIF_1:RW:0:11:=0x0000 + 0x00000000, // 338: SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1:WR:16:14:=0x0000 PHY_DS_FSM_ERROR_INFO_MASK_1:RW:0:14:=0x0000 + 0x00000100, // 339: SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1:WR:16:5:=0x00 PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1:RW:8:5:=0x01 PHY_DS_TRAIN_CALIB_ERROR_INFO_1:RD:0:5:=0x00 + 0x01CC0C05, // 340: PHY_DQS_TSEL_ENABLE_1:RW+:24:3:=0x01 PHY_DQ_TSEL_SELECT_1:RW+:8:16:=0x4408 PHY_DQ_TSEL_ENABLE_1:RW+:0:3:=0x01 + 0x1B03CC0C, // 341: PHY_VREF_INITIAL_START_POINT_1:RW+:24:7:=0x20 PHY_TWO_CYC_PREAMBLE_1:RW+:16:2:=0x03 PHY_DQS_TSEL_SELECT_1:RW+:0:16:=0x4408 + 0x20000130, // 342: PHY_NTP_WDQ_STEP_SIZE_1:RW+:24:8:=0x20 PHY_NTP_TRAIN_EN_1:RW+:16:1:=0x00 PHY_VREF_TRAINING_CTRL_1:RW+:8:2:=0x01 PHY_VREF_INITIAL_STOP_POINT_1:RW+:0:7:=0x25 + 0x07FF0200, // 343: PHY_NTP_WDQ_STOP_1:RW+:16:11:=0x07FF PHY_NTP_WDQ_START_1:RW+:0:11:=0x0200 + 0x0000DD01, // 344: PHY_SW_WDQLVL_DVW_MIN_EN_1:RW+:24:1:=0x00 PHY_WDQLVL_DVW_MIN_1:RW+:8:10:=0x00dd PHY_NTP_WDQ_BIT_EN_1:RW+:0:8:=0x01 + 0x00000303, // 345: PHY_PAD_RX_DCD_0_1:RW+:24:5:=0x00 PHY_PAD_TX_DCD_1:RW+:16:5:=0x00 PHY_FAST_LVL_EN_1:RW+:8:4:=0x03 PHY_WDQLVL_PER_START_OFFSET_1:RW+:0:6:=0x03 + 0x00000000, // 346: PHY_PAD_RX_DCD_4_1:RW+:24:5:=0x00 PHY_PAD_RX_DCD_3_1:RW+:16:5:=0x00 PHY_PAD_RX_DCD_2_1:RW+:8:5:=0x00 PHY_PAD_RX_DCD_1_1:RW+:0:5:=0x00 + 0x00000000, // 347: PHY_PAD_DM_RX_DCD_1:RW+:24:5:=0x00 PHY_PAD_RX_DCD_7_1:RW+:16:5:=0x00 PHY_PAD_RX_DCD_6_1:RW+:8:5:=0x00 PHY_PAD_RX_DCD_5_1:RW+:0:5:=0x00 + 0x00030000, // 348: PHY_PAD_DSLICE_IO_CFG_1:RW+:16:6:=0x00 PHY_PAD_FDBK_RX_DCD_1:RW+:8:5:=0x00 PHY_PAD_DQS_RX_DCD_1:RW+:0:5:=0x00 + 0x00000000, // 349: PHY_RDDQ1_SLAVE_DELAY_1:RW+:16:10:=0x0000 PHY_RDDQ0_SLAVE_DELAY_1:RW+:0:10:=0x0000 + 0x00000000, // 350: PHY_RDDQ3_SLAVE_DELAY_1:RW+:16:10:=0x0000 PHY_RDDQ2_SLAVE_DELAY_1:RW+:0:10:=0x0000 + 0x00000000, // 351: PHY_RDDQ5_SLAVE_DELAY_1:RW+:16:10:=0x0000 PHY_RDDQ4_SLAVE_DELAY_1:RW+:0:10:=0x0000 + 0x00000000, // 352: PHY_RDDQ7_SLAVE_DELAY_1:RW+:16:10:=0x0000 PHY_RDDQ6_SLAVE_DELAY_1:RW+:0:10:=0x0000 + 0x00050000, // 353: PHY_DATA_DC_CAL_CLK_SEL_1:RW+:16:3:=0x02 PHY_RDDM_SLAVE_DELAY_1:RW+:0:10:=0x0000 + 0x51515042, // 354: PHY_DQS_OE_TIMING_1:RW+:24:8:=0x51 PHY_DQ_TSEL_WR_TIMING_1:RW+:16:8:=0x51 PHY_DQ_TSEL_RD_TIMING_1:RW+:8:8:=0x50 PHY_DQ_OE_TIMING_1:RW+:0:8:=0x42 + 0x31C06000, // 355: PHY_DQS_TSEL_WR_TIMING_1:RW+:24:8:=0x31 PHY_DQS_OE_RD_TIMING_1:RW+:16:8:=0xc0 PHY_DQS_TSEL_RD_TIMING_1:RW+:8:8:=0x60 PHY_IO_PAD_DELAY_TIMING_1:RW+:0:4:=0x00 + 0x07A000A0, // 356: PHY_PAD_VREF_CTRL_DQ_1:RW+:16:12:=0x069f PHY_VREF_SETTING_TIME_1:RW+:0:16:=0x0004 + 0x00C0C001, // 357: PHY_RDDATA_EN_IE_DLY_1:RW+:24:2:=0x00 PHY_DQS_IE_TIMING_1:RW+:16:8:=0xc0 PHY_DQ_IE_TIMING_1:RW+:8:8:=0xc0 PHY_PER_CS_TRAINING_EN_1:RW+:0:1:=0x01 + 0x0E0D0100, // 358: PHY_RDDATA_EN_OE_DLY_1:RW+:24:5:=0x0e PHY_RDDATA_EN_TSEL_DLY_1:RW+:16:5:=0x0d PHY_DBI_MODE_1:RW+:8:1:=0x00 PHY_IE_MODE_1:RW+:0:2:=0x00 + 0x10001000, // 359: PHY_MASTER_DELAY_STEP_1:RW+:24:6:=0x10 PHY_MASTER_DELAY_START_1:RW+:8:11:=0x0010 PHY_SW_MASTER_MODE_1:RW+:0:4:=0x00 + 0x0C063E42, // 360: PHY_WRLVL_DLY_STEP_1:RW+:24:8:=0x0c PHY_RPTR_UPDATE_1:RW+:16:4:=0x06 PHY_MASTER_DELAY_HALF_MEASURE_1:RW+:8:8:=0x3e PHY_MASTER_DELAY_WAIT_1:RW+:0:8:=0x42 + 0x0F0C3701, // 361: PHY_GTLVL_RESP_WAIT_CNT_1:RW+:24:5:=0x0f PHY_GTLVL_DLY_STEP_1:RW+:16:4:=0x0c PHY_WRLVL_RESP_WAIT_CNT_1:RW+:8:6:=0x37 PHY_WRLVL_DLY_FINE_STEP_1:RW+:0:4:=0x01 + 0x01000140, // 362: PHY_GTLVL_FINAL_STEP_1:RW+:16:10:=0x0100 PHY_GTLVL_BACK_STEP_1:RW+:0:10:=0x0140 + 0x0C000120, // 363: PHY_RDLVL_DLY_STEP_1:RW+:24:4:=0x0c PHY_TOGGLE_PRE_SUPPORT_1:RW+:16:1:=0x00 PHY_WDQLVL_QTR_DLY_STEP_1:RW+:8:4:=0x01 PHY_WDQLVL_DLY_STEP_1:RW+:0:8:=0x20 + 0x00000322, // 364: PHY_RDLVL_MAX_EDGE_1:RW+:0:10:=0x0322 + 0x0A0000D0, // 365: PHY_RDLVL_PER_START_OFFSET_1:RW+:24:6:=0x0A PHY_SW_RDLVL_DVW_MIN_EN_1:RW+:16:1:=0x00 PHY_RDLVL_DVW_MIN_1:RW+:0:10:=0x00d0 + 0x00030200, // 366: PHY_DATA_DC_INIT_DISABLE_1:RW+:16:2:=0x00 PHY_WRPATH_GATE_TIMING_1:RW+:8:3:=0x02 PHY_WRPATH_GATE_DISABLE_1:RW+:0:2:=0x00 + 0x02800000, // 367: PHY_DATA_DC_DQ_INIT_SLV_DELAY_1:RW+:16:11:=0x0280 PHY_DATA_DC_DQS_INIT_SLV_DELAY_1:RW+:0:10:=0x0000 + 0x80800000, // 368: PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1:RW+:24:8:=0x80 PHY_DATA_DC_DM_CLK_SE_THRSHLD_1:RW+:16:8:=0x80 PHY_DATA_DC_WDQLVL_ENABLE_1:RW+:8:1:=0x01 PHY_DATA_DC_WRLVL_ENABLE_1:RW+:0:1:=0x01 + 0x000E2010, // 369: PHY_RDDATA_EN_DLY_1:RW+:16:5:=0x0e PHY_MEAS_DLY_STEP_ENABLE_1:RW+:8:6:=0x20 PHY_WDQ_OSC_DELTA_1:RW+:0:7:=0x10 + 0x52016437, // 370: PHY_DQ_DM_SWIZZLE0_1:RW+:0:32:=0x76543210 + 0x00000008, // 371: PHY_DQ_DM_SWIZZLE1_1:RW+:0:4:=0x08 + 0x02800280, // 372: PHY_CLK_WRDQ1_SLAVE_DELAY_1:RW+:16:11:=0x0280 PHY_CLK_WRDQ0_SLAVE_DELAY_1:RW+:0:11:=0x0280 + 0x02800280, // 373: PHY_CLK_WRDQ3_SLAVE_DELAY_1:RW+:16:11:=0x0280 PHY_CLK_WRDQ2_SLAVE_DELAY_1:RW+:0:11:=0x0280 + 0x02800280, // 374: PHY_CLK_WRDQ5_SLAVE_DELAY_1:RW+:16:11:=0x0280 PHY_CLK_WRDQ4_SLAVE_DELAY_1:RW+:0:11:=0x0280 + 0x02800280, // 375: PHY_CLK_WRDQ7_SLAVE_DELAY_1:RW+:16:11:=0x0280 PHY_CLK_WRDQ6_SLAVE_DELAY_1:RW+:0:11:=0x0280 + 0x00000280, // 376: PHY_CLK_WRDQS_SLAVE_DELAY_1:RW+:16:10:=0x0000 PHY_CLK_WRDM_SLAVE_DELAY_1:RW+:0:11:=0x0280 + 0x0000A000, // 377: PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1:RW+:8:10:=0x00a0 PHY_WRLVL_THRESHOLD_ADJUST_1:RW+:0:2:=0x00 + 0x00A000A0, // 378: PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0 + 0x00A000A0, // 379: PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0 + 0x00A000A0, // 380: PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0 + 0x00A000A0, // 381: PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0 + 0x00A000A0, // 382: PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0 + 0x00A000A0, // 383: PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0 + 0x00A000A0, // 384: PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0 + 0x00A000A0, // 385: PHY_RDDQS_DM_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0 + 0x01C200A0, // 386: PHY_RDDQS_GATE_SLAVE_DELAY_1:RW+:16:10:=0x01c2 PHY_RDDQS_DM_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0 + 0x01A00005, // 387: PHY_WRLVL_DELAY_EARLY_THRESHOLD_1:RW+:16:10:=0x01A0 PHY_WRITE_PATH_LAT_ADD_1:RW+:8:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_1:RW+:0:4:=0x05 + 0x00000000, // 388: PHY_WRLVL_EARLY_FORCE_ZERO_1:RW+:16:1:=0x00 PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1:RW+:0:10:=0x0000 + 0x00060000, // 389: PHY_GTLVL_LAT_ADJ_START_1:RW+:16:4:=0x06 PHY_GTLVL_RDDQS_SLV_DLY_START_1:RW+:0:10:=0x0000 + 0x00080200, // 390: PHY_NTP_PASS_1:RW+:24:1:=0x00 PHY_NTP_WRLAT_START_1:RW+:16:4:=0x08 PHY_WDQLVL_DQDM_SLV_DLY_START_1:RW+:0:11:=0x0200 + 0x00000000, // 391: PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1:RW+:0:10:=0x0000 + 0x20202020, // 392: PHY_DATA_DC_DQ2_CLK_ADJUST_1:RW+:24:8:=0x20 PHY_DATA_DC_DQ1_CLK_ADJUST_1:RW+:16:8:=0x20 PHY_DATA_DC_DQ0_CLK_ADJUST_1:RW+:8:8:=0x20 PHY_DATA_DC_DQS_CLK_ADJUST_1:RW+:0:8:=0x20 + 0x20202020, // 393: PHY_DATA_DC_DQ6_CLK_ADJUST_1:RW+:24:8:=0x20 PHY_DATA_DC_DQ5_CLK_ADJUST_1:RW+:16:8:=0x20 PHY_DATA_DC_DQ4_CLK_ADJUST_1:RW+:8:8:=0x20 PHY_DATA_DC_DQ3_CLK_ADJUST_1:RW+:0:8:=0x20 + 0xF0F02020, // 394: PHY_DSLICE_PAD_BOOSTPN_SETTING_1:RW+:16:16:=0x0000 PHY_DATA_DC_DM_CLK_ADJUST_1:RW+:8:8:=0x20 PHY_DATA_DC_DQ7_CLK_ADJUST_1:RW+:0:8:=0x20 + 0x00000000, // 395: PHY_DQS_FFE_1:RW+:16:2:=0x00 PHY_DQ_FFE_1:RW+:8:2:=0x00 PHY_DSLICE_PAD_RX_CTLE_SETTING_1:RW+:0:6:=0x00 + 0x00000000, // 396: + 0x00000000, // 397: + 0x00000000, // 398: + 0x00000000, // 399: + 0x00000000, // 400: + 0x00000000, // 401: + 0x00000000, // 402: + 0x00000000, // 403: + 0x00000000, // 404: + 0x00000000, // 405: + 0x00000000, // 406: + 0x00000000, // 407: + 0x00000000, // 408: + 0x00000000, // 409: + 0x00000000, // 410: + 0x00000000, // 411: + 0x00000000, // 412: + 0x00000000, // 413: + 0x00000000, // 414: + 0x00000000, // 415: + 0x00000000, // 416: + 0x00000000, // 417: + 0x00000000, // 418: + 0x00000000, // 419: + 0x00000000, // 420: + 0x00000000, // 421: + 0x00000000, // 422: + 0x00000000, // 423: + 0x00000000, // 424: + 0x00000000, // 425: + 0x00000000, // 426: + 0x00000000, // 427: + 0x00000000, // 428: + 0x00000000, // 429: + 0x00000000, // 430: + 0x00000000, // 431: + 0x00000000, // 432: + 0x00000000, // 433: + 0x00000000, // 434: + 0x00000000, // 435: + 0x00000000, // 436: + 0x00000000, // 437: + 0x00000000, // 438: + 0x00000000, // 439: + 0x00000000, // 440: + 0x00000000, // 441: + 0x00000000, // 442: + 0x00000000, // 443: + 0x00000000, // 444: + 0x00000000, // 445: + 0x00000000, // 446: + 0x00000000, // 447: + 0x00000000, // 448: + 0x00000000, // 449: + 0x00000000, // 450: + 0x00000000, // 451: + 0x00000000, // 452: + 0x00000000, // 453: + 0x00000000, // 454: + 0x00000000, // 455: + 0x00000000, // 456: + 0x00000000, // 457: + 0x00000000, // 458: + 0x00000000, // 459: + 0x00000000, // 460: + 0x00000000, // 461: + 0x00000000, // 462: + 0x00000000, // 463: + 0x00000000, // 464: + 0x00000000, // 465: + 0x00000000, // 466: + 0x00000000, // 467: + 0x00000000, // 468: + 0x00000000, // 469: + 0x00000000, // 470: + 0x00000000, // 471: + 0x00000000, // 472: + 0x00000000, // 473: + 0x00000000, // 474: + 0x00000000, // 475: + 0x00000000, // 476: + 0x00000000, // 477: + 0x00000000, // 478: + 0x00000000, // 479: + 0x00000000, // 480: + 0x00000000, // 481: + 0x00000000, // 482: + 0x00000000, // 483: + 0x00000000, // 484: + 0x00000000, // 485: + 0x00000000, // 486: + 0x00000000, // 487: + 0x00000000, // 488: + 0x00000000, // 489: + 0x00000000, // 490: + 0x00000000, // 491: + 0x00000000, // 492: + 0x00000000, // 493: + 0x00000000, // 494: + 0x00000000, // 495: + 0x00000000, // 496: + 0x00000000, // 497: + 0x00000000, // 498: + 0x00000000, // 499: + 0x00000000, // 500: + 0x00000000, // 501: + 0x00000000, // 502: + 0x00000000, // 503: + 0x00000000, // 504: + 0x00000000, // 505: + 0x00000000, // 506: + 0x00000000, // 507: + 0x00000000, // 508: + 0x00000000, // 509: + 0x00000000, // 510: + 0x00000000, // 511: + 0x000004F0, // 512: PHY_IO_PAD_DELAY_TIMING_BYPASS_2:RW:16:4:=0x00 PHY_CLK_WR_BYPASS_SLAVE_DELAY_2:RW:0:11:=0x04f0 + 0x00000000, // 513: PHY_WRITE_PATH_LAT_ADD_BYPASS_2:RW:16:3:=0x00 PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2:RW:0:10:=0x0000 + 0x00030200, // 514: PHY_CLK_BYPASS_OVERRIDE_2:RW:24:1:=0x00 PHY_BYPASS_TWO_CYC_PREAMBLE_2:RW:16:2:=0x03 PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2:RW:0:10:=0x0200 + 0x00000000, // 515: PHY_SW_WRDQ3_SHIFT_2:RW:24:6:=0x00 PHY_SW_WRDQ2_SHIFT_2:RW:16:6:=0x00 PHY_SW_WRDQ1_SHIFT_2:RW:8:6:=0x00 PHY_SW_WRDQ0_SHIFT_2:RW:0:6:=0x00 + 0x00000000, // 516: PHY_SW_WRDQ7_SHIFT_2:RW:24:6:=0x00 PHY_SW_WRDQ6_SHIFT_2:RW:16:6:=0x00 PHY_SW_WRDQ5_SHIFT_2:RW:8:6:=0x00 PHY_SW_WRDQ4_SHIFT_2:RW:0:6:=0x00 + 0x01030000, // 517: PHY_PER_CS_TRAINING_MULTICAST_EN_2:RW_D:24:1:=0x01 PHY_PER_RANK_CS_MAP_2:RW+:16:2:=0x03 PHY_SW_WRDQS_SHIFT_2:RW:8:4:=0x00 PHY_SW_WRDM_SHIFT_2:RW:0:6:=0x00 + 0x00010000, // 518: PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2:RW:24:5:=0x00 PHY_LP4_BOOT_RDDATA_EN_DLY_2:RW:16:5:=0x01 PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2:RW:8:2:=0x00 PHY_PER_CS_TRAINING_INDEX_2:RW+:0:1:=0x00 + 0x01030004, // 519: PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2:RW:24:5:=0x01 PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2:RW:16:2:=0x03 PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2:RW:8:4:=0x00 PHY_LP4_BOOT_RPTR_UPDATE_2:RW:0:4:=0x04 + 0x01000000, // 520: PHY_LPBK_DFX_TIMEOUT_EN_2:RW:24:1:=0x01 PHY_LPBK_CONTROL_2:RW:8:9:=0x0000 PHY_CTRL_LPBK_EN_2:RW:0:2:=0x00 + 0x00000000, // 521: PHY_AUTO_TIMING_MARGIN_CONTROL_2:RW:0:32:=0x00000000 + 0x00000000, // 522: PHY_AUTO_TIMING_MARGIN_OBS_2:RD:0:28:=0x00000000 + 0x01000001, // 523: PHY_RDLVL_MULTI_PATT_ENABLE_2:RW:24:1:=0x00 PHY_PRBS_PATTERN_MASK_2:RW:8:9:=0x0000 PHY_PRBS_PATTERN_START_2:RW_D:0:7:=0x01 + 0x00000400, // 524: PHY_VREF_TRAIN_OBS_2:RD:16:7:=0x00 PHY_VREF_INITIAL_STEPSIZE_2:RW:8:6:=0x04 PHY_RDLVL_MULTI_PATT_RST_DISABLE_2:RW:0:1:=0x00 + 0x000800C0, // 525: SC_PHY_SNAP_OBS_REGS_2:WR:24:1:=0x00 PHY_GATE_ERROR_DELAY_SELECT_2:RW:16:4:=0x08 PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2:RW:0:10:=0x00c0 + 0x060100CC, // 526: PHY_MEM_CLASS_2:RW:24:3:=0x06 PHY_LPDDR_2:RW:16:1:=0x01 PHY_GATE_SMPL1_SLAVE_DELAY_2:RW:0:9:=0x00cc + 0x00030066, // 527: ON_FLY_GATE_ADJUST_EN_2:RW:16:2:=0x03 PHY_GATE_SMPL2_SLAVE_DELAY_2:RW:0:9:=0x0066 + 0x00000000, // 528: PHY_GATE_TRACKING_OBS_2:RD:0:32:=0x00000000 + 0x00000001, // 529: PHY_LP4_PST_AMBLE_2:RW:8:2:=0x00 PHY_DFI40_POLARITY_2:RW:0:1:=0x01 + 0x0000AAAA, // 530: PHY_RDLVL_PATT8_2:RW:0:32:=0x0000AAAA + 0x00005555, // 531: PHY_RDLVL_PATT9_2:RW:0:32:=0x00005555 + 0x0000B5B5, // 532: PHY_RDLVL_PATT10_2:RW:0:32:=0x0000B5B5 + 0x00004A4A, // 533: PHY_RDLVL_PATT11_2:RW:0:32:=0x00004A4A + 0x00005656, // 534: PHY_RDLVL_PATT12_2:RW:0:32:=0x00005656 + 0x0000A9A9, // 535: PHY_RDLVL_PATT13_2:RW:0:32:=0x0000A9A9 + 0x0000A9A9, // 536: PHY_RDLVL_PATT14_2:RW:0:32:=0x0000A9A9 + 0x0000B5B5, // 537: PHY_RDLVL_PATT15_2:RW:0:32:=0x0000B5B5 + 0x00000000, // 538: PHY_RDDQ_ENC_OBS_SELECT_2:RW:24:3:=0x00 PHY_MASTER_DLY_LOCK_OBS_SELECT_2:RW:16:4:=0x00 PHY_SW_FIFO_PTR_RST_DISABLE_2:RW:8:1:=0x00 PHY_SLAVE_LOOP_CNT_UPDATE_2:RW:0:3:=0x00 + 0x00000000, // 539: PHY_FIFO_PTR_OBS_SELECT_2:RW:24:4:=0x00 PHY_WR_SHIFT_OBS_SELECT_2:RW:16:4:=0x00 PHY_WR_ENC_OBS_SELECT_2:RW:8:4:=0x00 PHY_RDDQS_DQ_ENC_OBS_SELECT_2:RW:0:4:=0x00 + 0x2A000000, // 540: PHY_WRLVL_PER_START_2:RW:24:8:=0x2A PHY_WRLVL_ALGO_2:RW:16:2:=0x00 SC_PHY_LVL_DEBUG_CONT_2:WR:8:1:=0x00 PHY_LVL_DEBUG_MODE_2:RW:0:1:=0x00 + 0x00000808, // 541: PHY_DQ_MASK_2:RW:16:8:=0x00 PHY_WRLVL_UPDT_WAIT_CNT_2:RW:8:4:=0x08 PHY_WRLVL_CAPTURE_CNT_2:RW:0:6:=0x08 + 0x04080000, // 542: PHY_GTLVL_UPDT_WAIT_CNT_2:RW:24:4:=0x04 PHY_GTLVL_CAPTURE_CNT_2:RW:16:6:=0x00 PHY_GTLVL_PER_START_2:RW:0:10:=0x0000 + 0x00000408, // 543: PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2:RW:24:5:=0x00 PHY_RDLVL_OP_MODE_2:RW:16:2:=0x00 PHY_RDLVL_UPDT_WAIT_CNT_2:RW:8:4:=0x04 PHY_RDLVL_CAPTURE_CNT_2:RW:0:6:=0x08 + 0x10300000, // 544: PHY_WDQLVL_BURST_CNT_2:RW:24:6:=0x10 PHY_WDQLVL_CLK_JITTER_TOLERANCE_2:RW:16:8:=0x20 PHY_RDLVL_DATA_MASK_2:RW:8:8:=0x00 PHY_RDLVL_PERIODIC_OBS_SELECT_2:RW:0:8:=0x00 + 0x0C002007, // 545: PHY_WDQLVL_UPDT_WAIT_CNT_2:RW:24:4:=0x0c PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2:RW:8:11:=0x0020 PHY_WDQLVL_PATT_2:RW:0:3:=0x07 + 0x00000000, // 546: SC_PHY_WDQLVL_CLR_PREV_RESULTS_2:WR:16:1:=0x00 PHY_WDQLVL_PERIODIC_OBS_SELECT_2:RW:8:8:=0x00 PHY_WDQLVL_DQDM_OBS_SELECT_2:RW:0:4:=0x00 + 0x00000100, // 547: PHY_WDQLVL_DATADM_MASK_2:RW:0:9:=0x0100 + 0x55555555, // 548: PHY_USER_PATT0_2:RW:0:32:=0x55555555 + 0xAAAAAAAA, // 549: PHY_USER_PATT1_2:RW:0:32:=0xAAAAAAAA + 0x55555555, // 550: PHY_USER_PATT2_2:RW:0:32:=0x55555555 + 0xAAAAAAAA, // 551: PHY_USER_PATT3_2:RW:0:32:=0xAAAAAAAA + 0x00005555, // 552: PHY_NTP_MULT_TRAIN_2:RW:16:1:=0x00 PHY_USER_PATT4_2:RW:0:16:=0x5555 + 0x01000100, // 553: PHY_NTP_PERIOD_THRESHOLD_2:RW:16:10:=0x0100 PHY_NTP_EARLY_THRESHOLD_2:RW:0:10:=0x0100 + 0x00800180, // 554: PHY_NTP_PERIOD_THRESHOLD_MAX_2:RW:16:10:=0x0080 PHY_NTP_PERIOD_THRESHOLD_MIN_2:RW:0:10:=0x0180 + 0x00000001, // 555: PHY_FIFO_PTR_OBS_2:RD:16:8:=0x00 SC_PHY_MANUAL_CLEAR_2:WR:8:6:=0x00 PHY_CALVL_VREF_DRIVING_SLICE_2:RW:0:1:=0x01 + 0x00000000, // 556: PHY_LPBK_RESULT_OBS_2:RD:0:32:=0x00000000 + 0x00000000, // 557: PHY_MASTER_DLY_LOCK_OBS_2:RD:16:11:=0x0000 PHY_LPBK_ERROR_COUNT_OBS_2:RD:0:16:=0x0000 + 0x00000000, // 558: PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2:RD:24:8:=0x00 PHY_MEAS_DLY_STEP_VALUE_2:RD:16:8:=0x00 PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2:RD:8:7:=0x00 PHY_RDDQ_SLV_DLY_ENC_OBS_2:RD:0:7:=0x00 + 0x00000000, // 559: PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2:RD:24:7:=0x00 PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2:RD:8:11:=0x0000 PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2:RD:0:8:=0x00 + 0x00000000, // 560: PHY_WR_SHIFT_OBS_2:RD:16:3:=0x00 PHY_WR_ADDER_SLV_DLY_ENC_OBS_2:RD:8:8:=0x00 PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2:RD:0:8:=0x00 + 0x00000000, // 561: PHY_WRLVL_HARD1_DELAY_OBS_2:RD:16:10:=0x0000 PHY_WRLVL_HARD0_DELAY_OBS_2:RD:0:10:=0x0000 + 0x00000000, // 562: PHY_WRLVL_STATUS_OBS_2:RD:0:17:=0x000000 + 0x00000000, // 563: PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2:RD:16:10:=0x0000 PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2:RD:0:10:=0x0000 + 0x00000000, // 564: PHY_GTLVL_HARD0_DELAY_OBS_2:RD:16:14:=0x0000 PHY_WRLVL_ERROR_OBS_2:RD:0:16:=0x0000 + 0x00000000, // 565: PHY_GTLVL_HARD1_DELAY_OBS_2:RD:0:14:=0x0000 + 0x00000000, // 566: PHY_GTLVL_STATUS_OBS_2:RD:0:18:=0x000000 + 0x00000000, // 567: PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2:RD:16:10:=0x0000 PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2:RD:0:10:=0x0000 + 0x00000000, // 568: PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2:RD:0:2:=0x00 + 0x00000000, // 569: PHY_RDLVL_STATUS_OBS_2:RD:0:32:=0x00000000 + 0x00000000, // 570: PHY_RDLVL_PERIODIC_OBS_2:RD:0:32:=0x00000000 + 0x00000000, // 571: PHY_WDQLVL_DQDM_TE_DLY_OBS_2:RD:16:11:=0x0000 PHY_WDQLVL_DQDM_LE_DLY_OBS_2:RD:0:11:=0x0000 + 0x00000000, // 572: PHY_WDQLVL_STATUS_OBS_2:RD:0:32:=0x00000000 + 0x00000000, // 573: PHY_WDQLVL_PERIODIC_OBS_2:RD:0:32:=0x00000000 + 0x00000000, // 574: PHY_DDL_MODE_2:RW:0:31:=0x00000000 + 0x00000000, // 575: PHY_DDL_MASK_2:RW:0:6:=0x00 + 0x00000000, // 576: PHY_DDL_TEST_OBS_2:RD:0:32:=0x00000000 + 0x00000000, // 577: PHY_DDL_TEST_MSTR_DLY_OBS_2:RD:0:32:=0x00000000 + 0x00000104, // 578: PHY_RX_CAL_OVERRIDE_2:RW:24:1:=0x00 SC_PHY_RX_CAL_START_2:WR:16:1:=0x00 PHY_LP4_WDQS_OE_EXTEND_2:RW:8:1:=0x00 PHY_DDL_TRACK_UPD_THRESHOLD_2:RW:0:8:=0x04 + 0x00000120, // 579: PHY_RX_CAL_DQ0_2:RW_D+:16:9:=0x0000 PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2:RW:8:1:=0x01 PHY_RX_CAL_SAMPLE_WAIT_2:RW:0:8:=0x20 + 0x00000000, // 580: PHY_RX_CAL_DQ2_2:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQ1_2:RW_D+:0:9:=0x0000 + 0x00000000, // 581: PHY_RX_CAL_DQ4_2:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQ3_2:RW_D+:0:9:=0x0000 + 0x00000000, // 582: PHY_RX_CAL_DQ6_2:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQ5_2:RW_D+:0:9:=0x0000 + 0x00000000, // 583: PHY_RX_CAL_DQ7_2:RW_D+:0:9:=0x0000 + 0x00000000, // 584: PHY_RX_CAL_DM_2:RW_D+:0:18:=0x000000 + 0x00000000, // 585: PHY_RX_CAL_FDBK_2:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQS_2:RW_D+:0:9:=0x0000 + 0x00000000, // 586: PHY_RX_CAL_LOCK_OBS_2:RD:16:9:=0x0000 PHY_RX_CAL_OBS_2:RD:0:11:=0x0000 + 0x00000001, // 587: PHY_RX_CAL_COMP_VAL_2:RW:24:1:=0x00 PHY_RX_CAL_DIFF_ADJUST_2:RW:16:7:=0x00 PHY_RX_CAL_SE_ADJUST_2:RW:8:7:=0x00 PHY_RX_CAL_DISABLE_2:RW_D:0:1:=0x01 + 0x07FF0000, // 588: PHY_PAD_RX_BIAS_EN_2:RW:16:11:=0x07ff PHY_RX_CAL_INDEX_MASK_2:RW:0:12:=0x0000 + 0x0080081F, // 589: PHY_DATA_DC_WEIGHT_2:RW:24:2:=0x00 PHY_DATA_DC_CAL_TIMEOUT_2:RW:16:8:=0x80 PHY_DATA_DC_CAL_SAMPLE_WAIT_2:RW:8:8:=0x08 PHY_STATIC_TOG_DISABLE_2:RW:0:5:=0x1f + 0x00081020, // 590: PHY_DATA_DC_ADJUST_DIRECT_2:RW:24:1:=0x00 PHY_DATA_DC_ADJUST_THRSHLD_2:RW:16:8:=0x08 PHY_DATA_DC_ADJUST_SAMPLE_CNT_2:RW:8:8:=0x10 PHY_DATA_DC_ADJUST_START_2:RW:0:6:=0x20 + 0x04010000, // 591: PHY_FDBK_PWR_CTRL_2:RW:24:3:=0x04 PHY_DATA_DC_SW_RANK_2:RW+:16:2:=0x01 PHY_DATA_DC_CAL_START_2:RW+:8:1:=0x00 PHY_DATA_DC_CAL_POLARITY_2:RW:0:1:=0x00 + 0x00000001, // 592: PHY_SLICE_PWR_RDC_DISABLE_2:RW:24:1:=0x00 PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2:RW_D:16:1:=0x00 PHY_RDPATH_GATE_DISABLE_2:RW_D:8:1:=0x00 PHY_SLV_DLY_CTRL_GATE_DISABLE_2:RW_D:0:1:=0x00 + 0x00000000, // 593: PHY_DS_FSM_ERROR_INFO_2:RD:16:14:=0x0000 PHY_PARITY_ERROR_REGIF_2:RW:0:11:=0x0000 + 0x00000000, // 594: SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2:WR:16:14:=0x0000 PHY_DS_FSM_ERROR_INFO_MASK_2:RW:0:14:=0x0000 + 0x00000100, // 595: SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2:WR:16:5:=0x00 PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2:RW:8:5:=0x01 PHY_DS_TRAIN_CALIB_ERROR_INFO_2:RD:0:5:=0x00 + 0x01CC0C05, // 596: PHY_DQS_TSEL_ENABLE_2:RW+:24:3:=0x01 PHY_DQ_TSEL_SELECT_2:RW+:8:16:=0x4408 PHY_DQ_TSEL_ENABLE_2:RW+:0:3:=0x01 + 0x1B03CC0C, // 597: PHY_VREF_INITIAL_START_POINT_2:RW+:24:7:=0x20 PHY_TWO_CYC_PREAMBLE_2:RW+:16:2:=0x03 PHY_DQS_TSEL_SELECT_2:RW+:0:16:=0x4408 + 0x20000130, // 598: PHY_NTP_WDQ_STEP_SIZE_2:RW+:24:8:=0x20 PHY_NTP_TRAIN_EN_2:RW+:16:1:=0x00 PHY_VREF_TRAINING_CTRL_2:RW+:8:2:=0x01 PHY_VREF_INITIAL_STOP_POINT_2:RW+:0:7:=0x25 + 0x07FF0200, // 599: PHY_NTP_WDQ_STOP_2:RW+:16:11:=0x07FF PHY_NTP_WDQ_START_2:RW+:0:11:=0x0200 + 0x0000DD01, // 600: PHY_SW_WDQLVL_DVW_MIN_EN_2:RW+:24:1:=0x00 PHY_WDQLVL_DVW_MIN_2:RW+:8:10:=0x00dd PHY_NTP_WDQ_BIT_EN_2:RW+:0:8:=0x01 + 0x00000303, // 601: PHY_PAD_RX_DCD_0_2:RW+:24:5:=0x00 PHY_PAD_TX_DCD_2:RW+:16:5:=0x00 PHY_FAST_LVL_EN_2:RW+:8:4:=0x03 PHY_WDQLVL_PER_START_OFFSET_2:RW+:0:6:=0x03 + 0x00000000, // 602: PHY_PAD_RX_DCD_4_2:RW+:24:5:=0x00 PHY_PAD_RX_DCD_3_2:RW+:16:5:=0x00 PHY_PAD_RX_DCD_2_2:RW+:8:5:=0x00 PHY_PAD_RX_DCD_1_2:RW+:0:5:=0x00 + 0x00000000, // 603: PHY_PAD_DM_RX_DCD_2:RW+:24:5:=0x00 PHY_PAD_RX_DCD_7_2:RW+:16:5:=0x00 PHY_PAD_RX_DCD_6_2:RW+:8:5:=0x00 PHY_PAD_RX_DCD_5_2:RW+:0:5:=0x00 + 0x00030000, // 604: PHY_PAD_DSLICE_IO_CFG_2:RW+:16:6:=0x00 PHY_PAD_FDBK_RX_DCD_2:RW+:8:5:=0x00 PHY_PAD_DQS_RX_DCD_2:RW+:0:5:=0x00 + 0x00000000, // 605: PHY_RDDQ1_SLAVE_DELAY_2:RW+:16:10:=0x0000 PHY_RDDQ0_SLAVE_DELAY_2:RW+:0:10:=0x0000 + 0x00000000, // 606: PHY_RDDQ3_SLAVE_DELAY_2:RW+:16:10:=0x0000 PHY_RDDQ2_SLAVE_DELAY_2:RW+:0:10:=0x0000 + 0x00000000, // 607: PHY_RDDQ5_SLAVE_DELAY_2:RW+:16:10:=0x0000 PHY_RDDQ4_SLAVE_DELAY_2:RW+:0:10:=0x0000 + 0x00000000, // 608: PHY_RDDQ7_SLAVE_DELAY_2:RW+:16:10:=0x0000 PHY_RDDQ6_SLAVE_DELAY_2:RW+:0:10:=0x0000 + 0x00050000, // 609: PHY_DATA_DC_CAL_CLK_SEL_2:RW+:16:3:=0x02 PHY_RDDM_SLAVE_DELAY_2:RW+:0:10:=0x0000 + 0x51515042, // 610: PHY_DQS_OE_TIMING_2:RW+:24:8:=0x51 PHY_DQ_TSEL_WR_TIMING_2:RW+:16:8:=0x51 PHY_DQ_TSEL_RD_TIMING_2:RW+:8:8:=0x50 PHY_DQ_OE_TIMING_2:RW+:0:8:=0x42 + 0x31C06000, // 611: PHY_DQS_TSEL_WR_TIMING_2:RW+:24:8:=0x31 PHY_DQS_OE_RD_TIMING_2:RW+:16:8:=0xc0 PHY_DQS_TSEL_RD_TIMING_2:RW+:8:8:=0x60 PHY_IO_PAD_DELAY_TIMING_2:RW+:0:4:=0x00 + 0x07A000A0, // 612: PHY_PAD_VREF_CTRL_DQ_2:RW+:16:12:=0x069f PHY_VREF_SETTING_TIME_2:RW+:0:16:=0x0004 + 0x00C0C001, // 613: PHY_RDDATA_EN_IE_DLY_2:RW+:24:2:=0x00 PHY_DQS_IE_TIMING_2:RW+:16:8:=0xc0 PHY_DQ_IE_TIMING_2:RW+:8:8:=0xc0 PHY_PER_CS_TRAINING_EN_2:RW+:0:1:=0x01 + 0x0E0D0100, // 614: PHY_RDDATA_EN_OE_DLY_2:RW+:24:5:=0x0e PHY_RDDATA_EN_TSEL_DLY_2:RW+:16:5:=0x0d PHY_DBI_MODE_2:RW+:8:1:=0x00 PHY_IE_MODE_2:RW+:0:2:=0x00 + 0x10001000, // 615: PHY_MASTER_DELAY_STEP_2:RW+:24:6:=0x10 PHY_MASTER_DELAY_START_2:RW+:8:11:=0x0010 PHY_SW_MASTER_MODE_2:RW+:0:4:=0x00 + 0x0C063E42, // 616: PHY_WRLVL_DLY_STEP_2:RW+:24:8:=0x0c PHY_RPTR_UPDATE_2:RW+:16:4:=0x06 PHY_MASTER_DELAY_HALF_MEASURE_2:RW+:8:8:=0x3e PHY_MASTER_DELAY_WAIT_2:RW+:0:8:=0x42 + 0x0F0C3701, // 617: PHY_GTLVL_RESP_WAIT_CNT_2:RW+:24:5:=0x0f PHY_GTLVL_DLY_STEP_2:RW+:16:4:=0x0c PHY_WRLVL_RESP_WAIT_CNT_2:RW+:8:6:=0x37 PHY_WRLVL_DLY_FINE_STEP_2:RW+:0:4:=0x01 + 0x01000140, // 618: PHY_GTLVL_FINAL_STEP_2:RW+:16:10:=0x0100 PHY_GTLVL_BACK_STEP_2:RW+:0:10:=0x0140 + 0x0C000120, // 619: PHY_RDLVL_DLY_STEP_2:RW+:24:4:=0x0c PHY_TOGGLE_PRE_SUPPORT_2:RW+:16:1:=0x00 PHY_WDQLVL_QTR_DLY_STEP_2:RW+:8:4:=0x01 PHY_WDQLVL_DLY_STEP_2:RW+:0:8:=0x20 + 0x00000322, // 620: PHY_RDLVL_MAX_EDGE_2:RW+:0:10:=0x0322 + 0x0A0000D0, // 621: PHY_RDLVL_PER_START_OFFSET_2:RW+:24:6:=0x0A PHY_SW_RDLVL_DVW_MIN_EN_2:RW+:16:1:=0x00 PHY_RDLVL_DVW_MIN_2:RW+:0:10:=0x00d0 + 0x00030200, // 622: PHY_DATA_DC_INIT_DISABLE_2:RW+:16:2:=0x00 PHY_WRPATH_GATE_TIMING_2:RW+:8:3:=0x02 PHY_WRPATH_GATE_DISABLE_2:RW+:0:2:=0x00 + 0x02800000, // 623: PHY_DATA_DC_DQ_INIT_SLV_DELAY_2:RW+:16:11:=0x0280 PHY_DATA_DC_DQS_INIT_SLV_DELAY_2:RW+:0:10:=0x0000 + 0x80800000, // 624: PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2:RW+:24:8:=0x80 PHY_DATA_DC_DM_CLK_SE_THRSHLD_2:RW+:16:8:=0x80 PHY_DATA_DC_WDQLVL_ENABLE_2:RW+:8:1:=0x01 PHY_DATA_DC_WRLVL_ENABLE_2:RW+:0:1:=0x01 + 0x000E2010, // 625: PHY_RDDATA_EN_DLY_2:RW+:16:5:=0x0e PHY_MEAS_DLY_STEP_ENABLE_2:RW+:8:6:=0x20 PHY_WDQ_OSC_DELTA_2:RW+:0:7:=0x10 + 0x21043576, // 626: PHY_DQ_DM_SWIZZLE0_2:RW+:0:32:=0x76543210 + 0x00000008, // 627: PHY_DQ_DM_SWIZZLE1_2:RW+:0:4:=0x08 + 0x02800280, // 628: PHY_CLK_WRDQ1_SLAVE_DELAY_2:RW+:16:11:=0x0280 PHY_CLK_WRDQ0_SLAVE_DELAY_2:RW+:0:11:=0x0280 + 0x02800280, // 629: PHY_CLK_WRDQ3_SLAVE_DELAY_2:RW+:16:11:=0x0280 PHY_CLK_WRDQ2_SLAVE_DELAY_2:RW+:0:11:=0x0280 + 0x02800280, // 630: PHY_CLK_WRDQ5_SLAVE_DELAY_2:RW+:16:11:=0x0280 PHY_CLK_WRDQ4_SLAVE_DELAY_2:RW+:0:11:=0x0280 + 0x02800280, // 631: PHY_CLK_WRDQ7_SLAVE_DELAY_2:RW+:16:11:=0x0280 PHY_CLK_WRDQ6_SLAVE_DELAY_2:RW+:0:11:=0x0280 + 0x00000280, // 632: PHY_CLK_WRDQS_SLAVE_DELAY_2:RW+:16:10:=0x0000 PHY_CLK_WRDM_SLAVE_DELAY_2:RW+:0:11:=0x0280 + 0x0000A000, // 633: PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2:RW+:8:10:=0x00a0 PHY_WRLVL_THRESHOLD_ADJUST_2:RW+:0:2:=0x00 + 0x00A000A0, // 634: PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0 + 0x00A000A0, // 635: PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0 + 0x00A000A0, // 636: PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0 + 0x00A000A0, // 637: PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0 + 0x00A000A0, // 638: PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0 + 0x00A000A0, // 639: PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0 + 0x00A000A0, // 640: PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0 + 0x00A000A0, // 641: PHY_RDDQS_DM_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0 + 0x01C200A0, // 642: PHY_RDDQS_GATE_SLAVE_DELAY_2:RW+:16:10:=0x01c2 PHY_RDDQS_DM_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0 + 0x01A00005, // 643: PHY_WRLVL_DELAY_EARLY_THRESHOLD_2:RW+:16:10:=0x01A0 PHY_WRITE_PATH_LAT_ADD_2:RW+:8:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_2:RW+:0:4:=0x05 + 0x00000000, // 644: PHY_WRLVL_EARLY_FORCE_ZERO_2:RW+:16:1:=0x00 PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2:RW+:0:10:=0x0000 + 0x00060000, // 645: PHY_GTLVL_LAT_ADJ_START_2:RW+:16:4:=0x06 PHY_GTLVL_RDDQS_SLV_DLY_START_2:RW+:0:10:=0x0000 + 0x00080200, // 646: PHY_NTP_PASS_2:RW+:24:1:=0x00 PHY_NTP_WRLAT_START_2:RW+:16:4:=0x08 PHY_WDQLVL_DQDM_SLV_DLY_START_2:RW+:0:11:=0x0200 + 0x00000000, // 647: PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2:RW+:0:10:=0x0000 + 0x20202020, // 648: PHY_DATA_DC_DQ2_CLK_ADJUST_2:RW+:24:8:=0x20 PHY_DATA_DC_DQ1_CLK_ADJUST_2:RW+:16:8:=0x20 PHY_DATA_DC_DQ0_CLK_ADJUST_2:RW+:8:8:=0x20 PHY_DATA_DC_DQS_CLK_ADJUST_2:RW+:0:8:=0x20 + 0x20202020, // 649: PHY_DATA_DC_DQ6_CLK_ADJUST_2:RW+:24:8:=0x20 PHY_DATA_DC_DQ5_CLK_ADJUST_2:RW+:16:8:=0x20 PHY_DATA_DC_DQ4_CLK_ADJUST_2:RW+:8:8:=0x20 PHY_DATA_DC_DQ3_CLK_ADJUST_2:RW+:0:8:=0x20 + 0xF0F02020, // 650: PHY_DSLICE_PAD_BOOSTPN_SETTING_2:RW+:16:16:=0x0000 PHY_DATA_DC_DM_CLK_ADJUST_2:RW+:8:8:=0x20 PHY_DATA_DC_DQ7_CLK_ADJUST_2:RW+:0:8:=0x20 + 0x00000000, // 651: PHY_DQS_FFE_2:RW+:16:2:=0x00 PHY_DQ_FFE_2:RW+:8:2:=0x00 PHY_DSLICE_PAD_RX_CTLE_SETTING_2:RW+:0:6:=0x00 + 0x00000000, // 652: + 0x00000000, // 653: + 0x00000000, // 654: + 0x00000000, // 655: + 0x00000000, // 656: + 0x00000000, // 657: + 0x00000000, // 658: + 0x00000000, // 659: + 0x00000000, // 660: + 0x00000000, // 661: + 0x00000000, // 662: + 0x00000000, // 663: + 0x00000000, // 664: + 0x00000000, // 665: + 0x00000000, // 666: + 0x00000000, // 667: + 0x00000000, // 668: + 0x00000000, // 669: + 0x00000000, // 670: + 0x00000000, // 671: + 0x00000000, // 672: + 0x00000000, // 673: + 0x00000000, // 674: + 0x00000000, // 675: + 0x00000000, // 676: + 0x00000000, // 677: + 0x00000000, // 678: + 0x00000000, // 679: + 0x00000000, // 680: + 0x00000000, // 681: + 0x00000000, // 682: + 0x00000000, // 683: + 0x00000000, // 684: + 0x00000000, // 685: + 0x00000000, // 686: + 0x00000000, // 687: + 0x00000000, // 688: + 0x00000000, // 689: + 0x00000000, // 690: + 0x00000000, // 691: + 0x00000000, // 692: + 0x00000000, // 693: + 0x00000000, // 694: + 0x00000000, // 695: + 0x00000000, // 696: + 0x00000000, // 697: + 0x00000000, // 698: + 0x00000000, // 699: + 0x00000000, // 700: + 0x00000000, // 701: + 0x00000000, // 702: + 0x00000000, // 703: + 0x00000000, // 704: + 0x00000000, // 705: + 0x00000000, // 706: + 0x00000000, // 707: + 0x00000000, // 708: + 0x00000000, // 709: + 0x00000000, // 710: + 0x00000000, // 711: + 0x00000000, // 712: + 0x00000000, // 713: + 0x00000000, // 714: + 0x00000000, // 715: + 0x00000000, // 716: + 0x00000000, // 717: + 0x00000000, // 718: + 0x00000000, // 719: + 0x00000000, // 720: + 0x00000000, // 721: + 0x00000000, // 722: + 0x00000000, // 723: + 0x00000000, // 724: + 0x00000000, // 725: + 0x00000000, // 726: + 0x00000000, // 727: + 0x00000000, // 728: + 0x00000000, // 729: + 0x00000000, // 730: + 0x00000000, // 731: + 0x00000000, // 732: + 0x00000000, // 733: + 0x00000000, // 734: + 0x00000000, // 735: + 0x00000000, // 736: + 0x00000000, // 737: + 0x00000000, // 738: + 0x00000000, // 739: + 0x00000000, // 740: + 0x00000000, // 741: + 0x00000000, // 742: + 0x00000000, // 743: + 0x00000000, // 744: + 0x00000000, // 745: + 0x00000000, // 746: + 0x00000000, // 747: + 0x00000000, // 748: + 0x00000000, // 749: + 0x00000000, // 750: + 0x00000000, // 751: + 0x00000000, // 752: + 0x00000000, // 753: + 0x00000000, // 754: + 0x00000000, // 755: + 0x00000000, // 756: + 0x00000000, // 757: + 0x00000000, // 758: + 0x00000000, // 759: + 0x00000000, // 760: + 0x00000000, // 761: + 0x00000000, // 762: + 0x00000000, // 763: + 0x00000000, // 764: + 0x00000000, // 765: + 0x00000000, // 766: + 0x00000000, // 767: + 0x000004F0, // 768: PHY_IO_PAD_DELAY_TIMING_BYPASS_3:RW:16:4:=0x00 PHY_CLK_WR_BYPASS_SLAVE_DELAY_3:RW:0:11:=0x04f0 + 0x00000000, // 769: PHY_WRITE_PATH_LAT_ADD_BYPASS_3:RW:16:3:=0x00 PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3:RW:0:10:=0x0000 + 0x00030200, // 770: PHY_CLK_BYPASS_OVERRIDE_3:RW:24:1:=0x00 PHY_BYPASS_TWO_CYC_PREAMBLE_3:RW:16:2:=0x03 PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3:RW:0:10:=0x0200 + 0x00000000, // 771: PHY_SW_WRDQ3_SHIFT_3:RW:24:6:=0x00 PHY_SW_WRDQ2_SHIFT_3:RW:16:6:=0x00 PHY_SW_WRDQ1_SHIFT_3:RW:8:6:=0x00 PHY_SW_WRDQ0_SHIFT_3:RW:0:6:=0x00 + 0x00000000, // 772: PHY_SW_WRDQ7_SHIFT_3:RW:24:6:=0x00 PHY_SW_WRDQ6_SHIFT_3:RW:16:6:=0x00 PHY_SW_WRDQ5_SHIFT_3:RW:8:6:=0x00 PHY_SW_WRDQ4_SHIFT_3:RW:0:6:=0x00 + 0x01030000, // 773: PHY_PER_CS_TRAINING_MULTICAST_EN_3:RW_D:24:1:=0x01 PHY_PER_RANK_CS_MAP_3:RW+:16:2:=0x03 PHY_SW_WRDQS_SHIFT_3:RW:8:4:=0x00 PHY_SW_WRDM_SHIFT_3:RW:0:6:=0x00 + 0x00010000, // 774: PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3:RW:24:5:=0x00 PHY_LP4_BOOT_RDDATA_EN_DLY_3:RW:16:5:=0x01 PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3:RW:8:2:=0x00 PHY_PER_CS_TRAINING_INDEX_3:RW+:0:1:=0x00 + 0x01030004, // 775: PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3:RW:24:5:=0x01 PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3:RW:16:2:=0x03 PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3:RW:8:4:=0x00 PHY_LP4_BOOT_RPTR_UPDATE_3:RW:0:4:=0x04 + 0x01000000, // 776: PHY_LPBK_DFX_TIMEOUT_EN_3:RW:24:1:=0x01 PHY_LPBK_CONTROL_3:RW:8:9:=0x0000 PHY_CTRL_LPBK_EN_3:RW:0:2:=0x00 + 0x00000000, // 777: PHY_AUTO_TIMING_MARGIN_CONTROL_3:RW:0:32:=0x00000000 + 0x00000000, // 778: PHY_AUTO_TIMING_MARGIN_OBS_3:RD:0:28:=0x00000000 + 0x01000001, // 779: PHY_RDLVL_MULTI_PATT_ENABLE_3:RW:24:1:=0x00 PHY_PRBS_PATTERN_MASK_3:RW:8:9:=0x0000 PHY_PRBS_PATTERN_START_3:RW_D:0:7:=0x01 + 0x00000400, // 780: PHY_VREF_TRAIN_OBS_3:RD:16:7:=0x00 PHY_VREF_INITIAL_STEPSIZE_3:RW:8:6:=0x04 PHY_RDLVL_MULTI_PATT_RST_DISABLE_3:RW:0:1:=0x00 + 0x000800C0, // 781: SC_PHY_SNAP_OBS_REGS_3:WR:24:1:=0x00 PHY_GATE_ERROR_DELAY_SELECT_3:RW:16:4:=0x08 PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3:RW:0:10:=0x00c0 + 0x060100CC, // 782: PHY_MEM_CLASS_3:RW:24:3:=0x06 PHY_LPDDR_3:RW:16:1:=0x01 PHY_GATE_SMPL1_SLAVE_DELAY_3:RW:0:9:=0x00cc + 0x00030066, // 783: ON_FLY_GATE_ADJUST_EN_3:RW:16:2:=0x03 PHY_GATE_SMPL2_SLAVE_DELAY_3:RW:0:9:=0x0066 + 0x00000000, // 784: PHY_GATE_TRACKING_OBS_3:RD:0:32:=0x00000000 + 0x00000001, // 785: PHY_LP4_PST_AMBLE_3:RW:8:2:=0x00 PHY_DFI40_POLARITY_3:RW:0:1:=0x01 + 0x0000AAAA, // 786: PHY_RDLVL_PATT8_3:RW:0:32:=0x0000AAAA + 0x00005555, // 787: PHY_RDLVL_PATT9_3:RW:0:32:=0x00005555 + 0x0000B5B5, // 788: PHY_RDLVL_PATT10_3:RW:0:32:=0x0000B5B5 + 0x00004A4A, // 789: PHY_RDLVL_PATT11_3:RW:0:32:=0x00004A4A + 0x00005656, // 790: PHY_RDLVL_PATT12_3:RW:0:32:=0x00005656 + 0x0000A9A9, // 791: PHY_RDLVL_PATT13_3:RW:0:32:=0x0000A9A9 + 0x0000A9A9, // 792: PHY_RDLVL_PATT14_3:RW:0:32:=0x0000A9A9 + 0x0000B5B5, // 793: PHY_RDLVL_PATT15_3:RW:0:32:=0x0000B5B5 + 0x00000000, // 794: PHY_RDDQ_ENC_OBS_SELECT_3:RW:24:3:=0x00 PHY_MASTER_DLY_LOCK_OBS_SELECT_3:RW:16:4:=0x00 PHY_SW_FIFO_PTR_RST_DISABLE_3:RW:8:1:=0x00 PHY_SLAVE_LOOP_CNT_UPDATE_3:RW:0:3:=0x00 + 0x00000000, // 795: PHY_FIFO_PTR_OBS_SELECT_3:RW:24:4:=0x00 PHY_WR_SHIFT_OBS_SELECT_3:RW:16:4:=0x00 PHY_WR_ENC_OBS_SELECT_3:RW:8:4:=0x00 PHY_RDDQS_DQ_ENC_OBS_SELECT_3:RW:0:4:=0x00 + 0x2A000000, // 796: PHY_WRLVL_PER_START_3:RW:24:8:=0x2A PHY_WRLVL_ALGO_3:RW:16:2:=0x00 SC_PHY_LVL_DEBUG_CONT_3:WR:8:1:=0x00 PHY_LVL_DEBUG_MODE_3:RW:0:1:=0x00 + 0x00000808, // 797: PHY_DQ_MASK_3:RW:16:8:=0x00 PHY_WRLVL_UPDT_WAIT_CNT_3:RW:8:4:=0x08 PHY_WRLVL_CAPTURE_CNT_3:RW:0:6:=0x08 + 0x04080000, // 798: PHY_GTLVL_UPDT_WAIT_CNT_3:RW:24:4:=0x04 PHY_GTLVL_CAPTURE_CNT_3:RW:16:6:=0x00 PHY_GTLVL_PER_START_3:RW:0:10:=0x0000 + 0x00000408, // 799: PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3:RW:24:5:=0x00 PHY_RDLVL_OP_MODE_3:RW:16:2:=0x00 PHY_RDLVL_UPDT_WAIT_CNT_3:RW:8:4:=0x04 PHY_RDLVL_CAPTURE_CNT_3:RW:0:6:=0x08 + 0x10300000, // 800: PHY_WDQLVL_BURST_CNT_3:RW:24:6:=0x10 PHY_WDQLVL_CLK_JITTER_TOLERANCE_3:RW:16:8:=0x20 PHY_RDLVL_DATA_MASK_3:RW:8:8:=0x00 PHY_RDLVL_PERIODIC_OBS_SELECT_3:RW:0:8:=0x00 + 0x0C002007, // 801: PHY_WDQLVL_UPDT_WAIT_CNT_3:RW:24:4:=0x0c PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3:RW:8:11:=0x0020 PHY_WDQLVL_PATT_3:RW:0:3:=0x07 + 0x00000000, // 802: SC_PHY_WDQLVL_CLR_PREV_RESULTS_3:WR:16:1:=0x00 PHY_WDQLVL_PERIODIC_OBS_SELECT_3:RW:8:8:=0x00 PHY_WDQLVL_DQDM_OBS_SELECT_3:RW:0:4:=0x00 + 0x00000100, // 803: PHY_WDQLVL_DATADM_MASK_3:RW:0:9:=0x0100 + 0x55555555, // 804: PHY_USER_PATT0_3:RW:0:32:=0x55555555 + 0xAAAAAAAA, // 805: PHY_USER_PATT1_3:RW:0:32:=0xAAAAAAAA + 0x55555555, // 806: PHY_USER_PATT2_3:RW:0:32:=0x55555555 + 0xAAAAAAAA, // 807: PHY_USER_PATT3_3:RW:0:32:=0xAAAAAAAA + 0x00005555, // 808: PHY_NTP_MULT_TRAIN_3:RW:16:1:=0x00 PHY_USER_PATT4_3:RW:0:16:=0x5555 + 0x01000100, // 809: PHY_NTP_PERIOD_THRESHOLD_3:RW:16:10:=0x0100 PHY_NTP_EARLY_THRESHOLD_3:RW:0:10:=0x0100 + 0x00800180, // 810: PHY_NTP_PERIOD_THRESHOLD_MAX_3:RW:16:10:=0x0080 PHY_NTP_PERIOD_THRESHOLD_MIN_3:RW:0:10:=0x0180 + 0x00000000, // 811: PHY_FIFO_PTR_OBS_3:RD:16:8:=0x00 SC_PHY_MANUAL_CLEAR_3:WR:8:6:=0x00 PHY_CALVL_VREF_DRIVING_SLICE_3:RW:0:1:=0x00 + 0x00000000, // 812: PHY_LPBK_RESULT_OBS_3:RD:0:32:=0x00000000 + 0x00000000, // 813: PHY_MASTER_DLY_LOCK_OBS_3:RD:16:11:=0x0000 PHY_LPBK_ERROR_COUNT_OBS_3:RD:0:16:=0x0000 + 0x00000000, // 814: PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3:RD:24:8:=0x00 PHY_MEAS_DLY_STEP_VALUE_3:RD:16:8:=0x00 PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3:RD:8:7:=0x00 PHY_RDDQ_SLV_DLY_ENC_OBS_3:RD:0:7:=0x00 + 0x00000000, // 815: PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3:RD:24:7:=0x00 PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3:RD:8:11:=0x0000 PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3:RD:0:8:=0x00 + 0x00000000, // 816: PHY_WR_SHIFT_OBS_3:RD:16:3:=0x00 PHY_WR_ADDER_SLV_DLY_ENC_OBS_3:RD:8:8:=0x00 PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3:RD:0:8:=0x00 + 0x00000000, // 817: PHY_WRLVL_HARD1_DELAY_OBS_3:RD:16:10:=0x0000 PHY_WRLVL_HARD0_DELAY_OBS_3:RD:0:10:=0x0000 + 0x00000000, // 818: PHY_WRLVL_STATUS_OBS_3:RD:0:17:=0x000000 + 0x00000000, // 819: PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3:RD:16:10:=0x0000 PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3:RD:0:10:=0x0000 + 0x00000000, // 820: PHY_GTLVL_HARD0_DELAY_OBS_3:RD:16:14:=0x0000 PHY_WRLVL_ERROR_OBS_3:RD:0:16:=0x0000 + 0x00000000, // 821: PHY_GTLVL_HARD1_DELAY_OBS_3:RD:0:14:=0x0000 + 0x00000000, // 822: PHY_GTLVL_STATUS_OBS_3:RD:0:18:=0x000000 + 0x00000000, // 823: PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3:RD:16:10:=0x0000 PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3:RD:0:10:=0x0000 + 0x00000000, // 824: PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3:RD:0:2:=0x00 + 0x00000000, // 825: PHY_RDLVL_STATUS_OBS_3:RD:0:32:=0x00000000 + 0x00000000, // 826: PHY_RDLVL_PERIODIC_OBS_3:RD:0:32:=0x00000000 + 0x00000000, // 827: PHY_WDQLVL_DQDM_TE_DLY_OBS_3:RD:16:11:=0x0000 PHY_WDQLVL_DQDM_LE_DLY_OBS_3:RD:0:11:=0x0000 + 0x00000000, // 828: PHY_WDQLVL_STATUS_OBS_3:RD:0:32:=0x00000000 + 0x00000000, // 829: PHY_WDQLVL_PERIODIC_OBS_3:RD:0:32:=0x00000000 + 0x00000000, // 830: PHY_DDL_MODE_3:RW:0:31:=0x00000000 + 0x00000000, // 831: PHY_DDL_MASK_3:RW:0:6:=0x00 + 0x00000000, // 832: PHY_DDL_TEST_OBS_3:RD:0:32:=0x00000000 + 0x00000000, // 833: PHY_DDL_TEST_MSTR_DLY_OBS_3:RD:0:32:=0x00000000 + 0x00000104, // 834: PHY_RX_CAL_OVERRIDE_3:RW:24:1:=0x00 SC_PHY_RX_CAL_START_3:WR:16:1:=0x00 PHY_LP4_WDQS_OE_EXTEND_3:RW:8:1:=0x00 PHY_DDL_TRACK_UPD_THRESHOLD_3:RW:0:8:=0x04 + 0x00000120, // 835: PHY_RX_CAL_DQ0_3:RW_D+:16:9:=0x0000 PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3:RW:8:1:=0x01 PHY_RX_CAL_SAMPLE_WAIT_3:RW:0:8:=0x20 + 0x00000000, // 836: PHY_RX_CAL_DQ2_3:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQ1_3:RW_D+:0:9:=0x0000 + 0x00000000, // 837: PHY_RX_CAL_DQ4_3:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQ3_3:RW_D+:0:9:=0x0000 + 0x00000000, // 838: PHY_RX_CAL_DQ6_3:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQ5_3:RW_D+:0:9:=0x0000 + 0x00000000, // 839: PHY_RX_CAL_DQ7_3:RW_D+:0:9:=0x0000 + 0x00000000, // 840: PHY_RX_CAL_DM_3:RW_D+:0:18:=0x000000 + 0x00000000, // 841: PHY_RX_CAL_FDBK_3:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQS_3:RW_D+:0:9:=0x0000 + 0x00000000, // 842: PHY_RX_CAL_LOCK_OBS_3:RD:16:9:=0x0000 PHY_RX_CAL_OBS_3:RD:0:11:=0x0000 + 0x00000001, // 843: PHY_RX_CAL_COMP_VAL_3:RW:24:1:=0x00 PHY_RX_CAL_DIFF_ADJUST_3:RW:16:7:=0x00 PHY_RX_CAL_SE_ADJUST_3:RW:8:7:=0x00 PHY_RX_CAL_DISABLE_3:RW_D:0:1:=0x01 + 0x07FF0000, // 844: PHY_PAD_RX_BIAS_EN_3:RW:16:11:=0x07ff PHY_RX_CAL_INDEX_MASK_3:RW:0:12:=0x0000 + 0x0080081F, // 845: PHY_DATA_DC_WEIGHT_3:RW:24:2:=0x00 PHY_DATA_DC_CAL_TIMEOUT_3:RW:16:8:=0x80 PHY_DATA_DC_CAL_SAMPLE_WAIT_3:RW:8:8:=0x08 PHY_STATIC_TOG_DISABLE_3:RW:0:5:=0x1f + 0x00081020, // 846: PHY_DATA_DC_ADJUST_DIRECT_3:RW:24:1:=0x00 PHY_DATA_DC_ADJUST_THRSHLD_3:RW:16:8:=0x08 PHY_DATA_DC_ADJUST_SAMPLE_CNT_3:RW:8:8:=0x10 PHY_DATA_DC_ADJUST_START_3:RW:0:6:=0x20 + 0x04010000, // 847: PHY_FDBK_PWR_CTRL_3:RW:24:3:=0x04 PHY_DATA_DC_SW_RANK_3:RW+:16:2:=0x01 PHY_DATA_DC_CAL_START_3:RW+:8:1:=0x00 PHY_DATA_DC_CAL_POLARITY_3:RW:0:1:=0x00 + 0x00000001, // 848: PHY_SLICE_PWR_RDC_DISABLE_3:RW:24:1:=0x00 PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3:RW_D:16:1:=0x00 PHY_RDPATH_GATE_DISABLE_3:RW_D:8:1:=0x00 PHY_SLV_DLY_CTRL_GATE_DISABLE_3:RW_D:0:1:=0x00 + 0x00000000, // 849: PHY_DS_FSM_ERROR_INFO_3:RD:16:14:=0x0000 PHY_PARITY_ERROR_REGIF_3:RW:0:11:=0x0000 + 0x00000000, // 850: SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3:WR:16:14:=0x0000 PHY_DS_FSM_ERROR_INFO_MASK_3:RW:0:14:=0x0000 + 0x00000100, // 851: SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3:WR:16:5:=0x00 PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3:RW:8:5:=0x01 PHY_DS_TRAIN_CALIB_ERROR_INFO_3:RD:0:5:=0x00 + 0x01CC0C05, // 852: PHY_DQS_TSEL_ENABLE_3:RW+:24:3:=0x01 PHY_DQ_TSEL_SELECT_3:RW+:8:16:=0x4408 PHY_DQ_TSEL_ENABLE_3:RW+:0:3:=0x01 + 0x1B03CC0C, // 853: PHY_VREF_INITIAL_START_POINT_3:RW+:24:7:=0x20 PHY_TWO_CYC_PREAMBLE_3:RW+:16:2:=0x03 PHY_DQS_TSEL_SELECT_3:RW+:0:16:=0x4408 + 0x20000130, // 854: PHY_NTP_WDQ_STEP_SIZE_3:RW+:24:8:=0x20 PHY_NTP_TRAIN_EN_3:RW+:16:1:=0x00 PHY_VREF_TRAINING_CTRL_3:RW+:8:2:=0x01 PHY_VREF_INITIAL_STOP_POINT_3:RW+:0:7:=0x25 + 0x07FF0200, // 855: PHY_NTP_WDQ_STOP_3:RW+:16:11:=0x07FF PHY_NTP_WDQ_START_3:RW+:0:11:=0x0200 + 0x0000DD01, // 856: PHY_SW_WDQLVL_DVW_MIN_EN_3:RW+:24:1:=0x00 PHY_WDQLVL_DVW_MIN_3:RW+:8:10:=0x00dd PHY_NTP_WDQ_BIT_EN_3:RW+:0:8:=0x01 + 0x00000303, // 857: PHY_PAD_RX_DCD_0_3:RW+:24:5:=0x00 PHY_PAD_TX_DCD_3:RW+:16:5:=0x00 PHY_FAST_LVL_EN_3:RW+:8:4:=0x03 PHY_WDQLVL_PER_START_OFFSET_3:RW+:0:6:=0x03 + 0x00000000, // 858: PHY_PAD_RX_DCD_4_3:RW+:24:5:=0x00 PHY_PAD_RX_DCD_3_3:RW+:16:5:=0x00 PHY_PAD_RX_DCD_2_3:RW+:8:5:=0x00 PHY_PAD_RX_DCD_1_3:RW+:0:5:=0x00 + 0x00000000, // 859: PHY_PAD_DM_RX_DCD_3:RW+:24:5:=0x00 PHY_PAD_RX_DCD_7_3:RW+:16:5:=0x00 PHY_PAD_RX_DCD_6_3:RW+:8:5:=0x00 PHY_PAD_RX_DCD_5_3:RW+:0:5:=0x00 + 0x00030000, // 860: PHY_PAD_DSLICE_IO_CFG_3:RW+:16:6:=0x00 PHY_PAD_FDBK_RX_DCD_3:RW+:8:5:=0x00 PHY_PAD_DQS_RX_DCD_3:RW+:0:5:=0x00 + 0x00000000, // 861: PHY_RDDQ1_SLAVE_DELAY_3:RW+:16:10:=0x0000 PHY_RDDQ0_SLAVE_DELAY_3:RW+:0:10:=0x0000 + 0x00000000, // 862: PHY_RDDQ3_SLAVE_DELAY_3:RW+:16:10:=0x0000 PHY_RDDQ2_SLAVE_DELAY_3:RW+:0:10:=0x0000 + 0x00000000, // 863: PHY_RDDQ5_SLAVE_DELAY_3:RW+:16:10:=0x0000 PHY_RDDQ4_SLAVE_DELAY_3:RW+:0:10:=0x0000 + 0x00000000, // 864: PHY_RDDQ7_SLAVE_DELAY_3:RW+:16:10:=0x0000 PHY_RDDQ6_SLAVE_DELAY_3:RW+:0:10:=0x0000 + 0x00050000, // 865: PHY_DATA_DC_CAL_CLK_SEL_3:RW+:16:3:=0x02 PHY_RDDM_SLAVE_DELAY_3:RW+:0:10:=0x0000 + 0x51515042, // 866: PHY_DQS_OE_TIMING_3:RW+:24:8:=0x51 PHY_DQ_TSEL_WR_TIMING_3:RW+:16:8:=0x51 PHY_DQ_TSEL_RD_TIMING_3:RW+:8:8:=0x50 PHY_DQ_OE_TIMING_3:RW+:0:8:=0x42 + 0x31C06000, // 867: PHY_DQS_TSEL_WR_TIMING_3:RW+:24:8:=0x31 PHY_DQS_OE_RD_TIMING_3:RW+:16:8:=0xc0 PHY_DQS_TSEL_RD_TIMING_3:RW+:8:8:=0x60 PHY_IO_PAD_DELAY_TIMING_3:RW+:0:4:=0x00 + 0x07A000A0, // 868: PHY_PAD_VREF_CTRL_DQ_3:RW+:16:12:=0x069f PHY_VREF_SETTING_TIME_3:RW+:0:16:=0x0004 + 0x00C0C001, // 869: PHY_RDDATA_EN_IE_DLY_3:RW+:24:2:=0x00 PHY_DQS_IE_TIMING_3:RW+:16:8:=0xc0 PHY_DQ_IE_TIMING_3:RW+:8:8:=0xc0 PHY_PER_CS_TRAINING_EN_3:RW+:0:1:=0x01 + 0x0E0D0100, // 870: PHY_RDDATA_EN_OE_DLY_3:RW+:24:5:=0x0e PHY_RDDATA_EN_TSEL_DLY_3:RW+:16:5:=0x0d PHY_DBI_MODE_3:RW+:8:1:=0x00 PHY_IE_MODE_3:RW+:0:2:=0x00 + 0x10001000, // 871: PHY_MASTER_DELAY_STEP_3:RW+:24:6:=0x10 PHY_MASTER_DELAY_START_3:RW+:8:11:=0x0010 PHY_SW_MASTER_MODE_3:RW+:0:4:=0x00 + 0x0C063E42, // 872: PHY_WRLVL_DLY_STEP_3:RW+:24:8:=0x0c PHY_RPTR_UPDATE_3:RW+:16:4:=0x06 PHY_MASTER_DELAY_HALF_MEASURE_3:RW+:8:8:=0x3e PHY_MASTER_DELAY_WAIT_3:RW+:0:8:=0x42 + 0x0F0C3701, // 873: PHY_GTLVL_RESP_WAIT_CNT_3:RW+:24:5:=0x0f PHY_GTLVL_DLY_STEP_3:RW+:16:4:=0x0c PHY_WRLVL_RESP_WAIT_CNT_3:RW+:8:6:=0x37 PHY_WRLVL_DLY_FINE_STEP_3:RW+:0:4:=0x01 + 0x01000140, // 874: PHY_GTLVL_FINAL_STEP_3:RW+:16:10:=0x0100 PHY_GTLVL_BACK_STEP_3:RW+:0:10:=0x0140 + 0x0C000120, // 875: PHY_RDLVL_DLY_STEP_3:RW+:24:4:=0x0c PHY_TOGGLE_PRE_SUPPORT_3:RW+:16:1:=0x00 PHY_WDQLVL_QTR_DLY_STEP_3:RW+:8:4:=0x01 PHY_WDQLVL_DLY_STEP_3:RW+:0:8:=0x20 + 0x00000322, // 876: PHY_RDLVL_MAX_EDGE_3:RW+:0:10:=0x0322 + 0x0A0000D0, // 877: PHY_RDLVL_PER_START_OFFSET_3:RW+:24:6:=0x0A PHY_SW_RDLVL_DVW_MIN_EN_3:RW+:16:1:=0x00 PHY_RDLVL_DVW_MIN_3:RW+:0:10:=0x00d0 + 0x00030200, // 878: PHY_DATA_DC_INIT_DISABLE_3:RW+:16:2:=0x00 PHY_WRPATH_GATE_TIMING_3:RW+:8:3:=0x02 PHY_WRPATH_GATE_DISABLE_3:RW+:0:2:=0x00 + 0x02800000, // 879: PHY_DATA_DC_DQ_INIT_SLV_DELAY_3:RW+:16:11:=0x0280 PHY_DATA_DC_DQS_INIT_SLV_DELAY_3:RW+:0:10:=0x0000 + 0x80800000, // 880: PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3:RW+:24:8:=0x80 PHY_DATA_DC_DM_CLK_SE_THRSHLD_3:RW+:16:8:=0x80 PHY_DATA_DC_WDQLVL_ENABLE_3:RW+:8:1:=0x01 PHY_DATA_DC_WRLVL_ENABLE_3:RW+:0:1:=0x01 + 0x000E2010, // 881: PHY_RDDATA_EN_DLY_3:RW+:16:5:=0x0e PHY_MEAS_DLY_STEP_ENABLE_3:RW+:8:6:=0x20 PHY_WDQ_OSC_DELTA_3:RW+:0:7:=0x10 + 0x06173452, // 882: PHY_DQ_DM_SWIZZLE0_3:RW+:0:32:=0x76543210 + 0x00000008, // 883: PHY_DQ_DM_SWIZZLE1_3:RW+:0:4:=0x08 + 0x02800280, // 884: PHY_CLK_WRDQ1_SLAVE_DELAY_3:RW+:16:11:=0x0280 PHY_CLK_WRDQ0_SLAVE_DELAY_3:RW+:0:11:=0x0280 + 0x02800280, // 885: PHY_CLK_WRDQ3_SLAVE_DELAY_3:RW+:16:11:=0x0280 PHY_CLK_WRDQ2_SLAVE_DELAY_3:RW+:0:11:=0x0280 + 0x02800280, // 886: PHY_CLK_WRDQ5_SLAVE_DELAY_3:RW+:16:11:=0x0280 PHY_CLK_WRDQ4_SLAVE_DELAY_3:RW+:0:11:=0x0280 + 0x02800280, // 887: PHY_CLK_WRDQ7_SLAVE_DELAY_3:RW+:16:11:=0x0280 PHY_CLK_WRDQ6_SLAVE_DELAY_3:RW+:0:11:=0x0280 + 0x00000280, // 888: PHY_CLK_WRDQS_SLAVE_DELAY_3:RW+:16:10:=0x0000 PHY_CLK_WRDM_SLAVE_DELAY_3:RW+:0:11:=0x0280 + 0x0000A000, // 889: PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3:RW+:8:10:=0x00a0 PHY_WRLVL_THRESHOLD_ADJUST_3:RW+:0:2:=0x00 + 0x00A000A0, // 890: PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0 + 0x00A000A0, // 891: PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0 + 0x00A000A0, // 892: PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0 + 0x00A000A0, // 893: PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0 + 0x00A000A0, // 894: PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0 + 0x00A000A0, // 895: PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0 + 0x00A000A0, // 896: PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0 + 0x00A000A0, // 897: PHY_RDDQS_DM_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0 + 0x01C200A0, // 898: PHY_RDDQS_GATE_SLAVE_DELAY_3:RW+:16:10:=0x01c2 PHY_RDDQS_DM_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0 + 0x01A00005, // 899: PHY_WRLVL_DELAY_EARLY_THRESHOLD_3:RW+:16:10:=0x01A0 PHY_WRITE_PATH_LAT_ADD_3:RW+:8:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_3:RW+:0:4:=0x05 + 0x00000000, // 900: PHY_WRLVL_EARLY_FORCE_ZERO_3:RW+:16:1:=0x00 PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3:RW+:0:10:=0x0000 + 0x00060000, // 901: PHY_GTLVL_LAT_ADJ_START_3:RW+:16:4:=0x06 PHY_GTLVL_RDDQS_SLV_DLY_START_3:RW+:0:10:=0x0000 + 0x00080200, // 902: PHY_NTP_PASS_3:RW+:24:1:=0x00 PHY_NTP_WRLAT_START_3:RW+:16:4:=0x08 PHY_WDQLVL_DQDM_SLV_DLY_START_3:RW+:0:11:=0x0200 + 0x00000000, // 903: PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3:RW+:0:10:=0x0000 + 0x20202020, // 904: PHY_DATA_DC_DQ2_CLK_ADJUST_3:RW+:24:8:=0x20 PHY_DATA_DC_DQ1_CLK_ADJUST_3:RW+:16:8:=0x20 PHY_DATA_DC_DQ0_CLK_ADJUST_3:RW+:8:8:=0x20 PHY_DATA_DC_DQS_CLK_ADJUST_3:RW+:0:8:=0x20 + 0x20202020, // 905: PHY_DATA_DC_DQ6_CLK_ADJUST_3:RW+:24:8:=0x20 PHY_DATA_DC_DQ5_CLK_ADJUST_3:RW+:16:8:=0x20 PHY_DATA_DC_DQ4_CLK_ADJUST_3:RW+:8:8:=0x20 PHY_DATA_DC_DQ3_CLK_ADJUST_3:RW+:0:8:=0x20 + 0xF0F02020, // 906: PHY_DSLICE_PAD_BOOSTPN_SETTING_3:RW+:16:16:=0x0000 PHY_DATA_DC_DM_CLK_ADJUST_3:RW+:8:8:=0x20 PHY_DATA_DC_DQ7_CLK_ADJUST_3:RW+:0:8:=0x20 + 0x00000000, // 907: PHY_DQS_FFE_3:RW+:16:2:=0x00 PHY_DQ_FFE_3:RW+:8:2:=0x00 PHY_DSLICE_PAD_RX_CTLE_SETTING_3:RW+:0:6:=0x00 + 0x00000000, // 908: + 0x00000000, // 909: + 0x00000000, // 910: + 0x00000000, // 911: + 0x00000000, // 912: + 0x00000000, // 913: + 0x00000000, // 914: + 0x00000000, // 915: + 0x00000000, // 916: + 0x00000000, // 917: + 0x00000000, // 918: + 0x00000000, // 919: + 0x00000000, // 920: + 0x00000000, // 921: + 0x00000000, // 922: + 0x00000000, // 923: + 0x00000000, // 924: + 0x00000000, // 925: + 0x00000000, // 926: + 0x00000000, // 927: + 0x00000000, // 928: + 0x00000000, // 929: + 0x00000000, // 930: + 0x00000000, // 931: + 0x00000000, // 932: + 0x00000000, // 933: + 0x00000000, // 934: + 0x00000000, // 935: + 0x00000000, // 936: + 0x00000000, // 937: + 0x00000000, // 938: + 0x00000000, // 939: + 0x00000000, // 940: + 0x00000000, // 941: + 0x00000000, // 942: + 0x00000000, // 943: + 0x00000000, // 944: + 0x00000000, // 945: + 0x00000000, // 946: + 0x00000000, // 947: + 0x00000000, // 948: + 0x00000000, // 949: + 0x00000000, // 950: + 0x00000000, // 951: + 0x00000000, // 952: + 0x00000000, // 953: + 0x00000000, // 954: + 0x00000000, // 955: + 0x00000000, // 956: + 0x00000000, // 957: + 0x00000000, // 958: + 0x00000000, // 959: + 0x00000000, // 960: + 0x00000000, // 961: + 0x00000000, // 962: + 0x00000000, // 963: + 0x00000000, // 964: + 0x00000000, // 965: + 0x00000000, // 966: + 0x00000000, // 967: + 0x00000000, // 968: + 0x00000000, // 969: + 0x00000000, // 970: + 0x00000000, // 971: + 0x00000000, // 972: + 0x00000000, // 973: + 0x00000000, // 974: + 0x00000000, // 975: + 0x00000000, // 976: + 0x00000000, // 977: + 0x00000000, // 978: + 0x00000000, // 979: + 0x00000000, // 980: + 0x00000000, // 981: + 0x00000000, // 982: + 0x00000000, // 983: + 0x00000000, // 984: + 0x00000000, // 985: + 0x00000000, // 986: + 0x00000000, // 987: + 0x00000000, // 988: + 0x00000000, // 989: + 0x00000000, // 990: + 0x00000000, // 991: + 0x00000000, // 992: + 0x00000000, // 993: + 0x00000000, // 994: + 0x00000000, // 995: + 0x00000000, // 996: + 0x00000000, // 997: + 0x00000000, // 998: + 0x00000000, // 999: + 0x00000000, // 1000: + 0x00000000, // 1001: + 0x00000000, // 1002: + 0x00000000, // 1003: + 0x00000000, // 1004: + 0x00000000, // 1005: + 0x00000000, // 1006: + 0x00000000, // 1007: + 0x00000000, // 1008: + 0x00000000, // 1009: + 0x00000000, // 1010: + 0x00000000, // 1011: + 0x00000000, // 1012: + 0x00000000, // 1013: + 0x00000000, // 1014: + 0x00000000, // 1015: + 0x00000000, // 1016: + 0x00000000, // 1017: + 0x00000000, // 1018: + 0x00000000, // 1019: + 0x00000000, // 1020: + 0x00000000, // 1021: + 0x00000000, // 1022: + 0x00000000, // 1023: + 0x00000000, // 1024: SC_PHY_ADR_MANUAL_CLEAR_0:WR:24:3:=0x00 PHY_ADR_CLK_BYPASS_OVERRIDE_0:RW:16:1:=0x00 PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0:RW:0:11:=0x0000 + 0x00000000, // 1025: PHY_ADR_LPBK_RESULT_OBS_0:RD:0:32:=0x00000000 + 0x00000000, // 1026: PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0:RW:24:4:=0x00 PHY_ADR_MEAS_DLY_STEP_VALUE_0:RD:16:8:=0x00 PHY_ADR_LPBK_ERROR_COUNT_OBS_0:RD:0:16:=0x0000 + 0x00000000, // 1027: PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0:RD:24:8:=0x00 PHY_ADR_BASE_SLV_DLY_ENC_OBS_0:RD:16:7:=0x00 PHY_ADR_MASTER_DLY_LOCK_OBS_0:RD:0:11:=0x0000 + 0x00000000, // 1028: PHY_ADR_TSEL_ENABLE_0:RW:24:1:=0x00 SC_PHY_ADR_SNAP_OBS_REGS_0:WR:16:1:=0x00 PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0:RW:8:3:=0x00 PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0:RW:0:3:=0x00 + 0x00000100, // 1029: PHY_ADR_PWR_RDC_DISABLE_0:RW:24:1:=0x00 PHY_ADR_PRBS_PATTERN_MASK_0:RW:16:5:=0x00 PHY_ADR_PRBS_PATTERN_START_0:RW_D:8:7:=0x01 PHY_ADR_LPBK_CONTROL_0:RW:0:7:=0x00 + 0x00000201, // 1030: PHY_ADR_IE_MODE_0:RW:24:1:=0x00 PHY_ADR_WRADDR_SHIFT_OBS_0:RD:16:3:=0x00 PHY_ADR_TYPE_0:RW:8:2:=0x02 PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0:RW_D:0:1:=0x00 + 0x00000000, // 1031: PHY_ADR_DDL_MODE_0:RW:0:27:=0x00000000 + 0x00000000, // 1032: PHY_ADR_DDL_MASK_0:RW:0:6:=0x00 + 0x00000000, // 1033: PHY_ADR_DDL_TEST_OBS_0:RD:0:32:=0x00000000 + 0x00000000, // 1034: PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0:RD:0:32:=0x00000000 + 0x00400000, // 1035: PHY_ADR_CALVL_COARSE_DLY_0:RW:16:11:=0x0040 PHY_ADR_CALVL_START_0:RW:0:11:=0x0000 + 0x00000080, // 1036: PHY_ADR_CALVL_QTR_0:RW:0:11:=0x0080 + 0x00DCBA98, // 1037: PHY_ADR_CALVL_SWIZZLE0_0:RW:0:24:=0xdcba98 + 0x03000000, // 1038: PHY_ADR_CALVL_RANK_CTRL_0:RW:24:2:=0x03 PHY_ADR_CALVL_SWIZZLE1_0:RW:0:24:=0x000000 + 0x00200000, // 1039: PHY_ADR_CALVL_PERIODIC_START_OFFSET_0:RW:16:9:=0x0020 PHY_ADR_CALVL_RESP_WAIT_CNT_0:RW:8:4:=0x00 PHY_ADR_CALVL_NUM_PATTERNS_0:RW:0:2:=0x00 + 0x00000000, // 1040: PHY_ADR_CALVL_OBS_SELECT_0:RW:24:3:=0x00 SC_PHY_ADR_CALVL_ERROR_CLR_0:WR:16:1:=0x00 SC_PHY_ADR_CALVL_DEBUG_CONT_0:WR:8:1:=0x00 PHY_ADR_CALVL_DEBUG_MODE_0:RW:0:1:=0x00 + 0x00000000, // 1041: PHY_ADR_CALVL_CH0_OBS0_0:RD:0:32:=0x00000000 + 0x00000000, // 1042: PHY_ADR_CALVL_CH1_OBS0_0:RD:0:32:=0x00000000 + 0x00000000, // 1043: PHY_ADR_CALVL_OBS1_0:RD:0:32:=0x00000000 + 0x00000000, // 1044: PHY_ADR_CALVL_OBS2_0:RD:0:32:=0x00000000 + 0x0000002A, // 1045: PHY_ADR_CALVL_FG_0_0:RW:0:20:=0x00002a + 0x00000015, // 1046: PHY_ADR_CALVL_BG_0_0:RW:0:20:=0x000015 + 0x00000015, // 1047: PHY_ADR_CALVL_FG_1_0:RW:0:20:=0x000015 + 0x0000002A, // 1048: PHY_ADR_CALVL_BG_1_0:RW:0:20:=0x00002a + 0x00000033, // 1049: PHY_ADR_CALVL_FG_2_0:RW:0:20:=0x000033 + 0x0000000C, // 1050: PHY_ADR_CALVL_BG_2_0:RW:0:20:=0x00000c + 0x0000000C, // 1051: PHY_ADR_CALVL_FG_3_0:RW:0:20:=0x00000c + 0x00000033, // 1052: PHY_ADR_CALVL_BG_3_0:RW:0:20:=0x000033 + 0x00543210, // 1053: PHY_ADR_ADDR_SEL_0:RW:0:24:=0x543210 + 0x003F0000, // 1054: PHY_ADR_SEG_MASK_0:RW:24:6:=0x00 PHY_ADR_BIT_MASK_0:RW:16:6:=0x3f PHY_ADR_LP4_BOOT_SLV_DELAY_0:RW:0:10:=0x0000 + 0x000F013F, // 1055: PHY_ADR_SW_TXIO_CTRL_0:RW:24:6:=0x00 PHY_ADR_STATIC_TOG_DISABLE_0:RW:16:4:=0x0f PHY_ADR_CSLVL_TRAIN_MASK_0:RW:8:6:=0x01 PHY_ADR_CALVL_TRAIN_MASK_0:RW:0:6:=0x3f + 0x20202000, // 1056: PHY_ADR_DC_ADR2_CLK_ADJUST_0:RW+:24:8:=0x20 PHY_ADR_DC_ADR1_CLK_ADJUST_0:RW+:16:8:=0x20 PHY_ADR_DC_ADR0_CLK_ADJUST_0:RW+:8:8:=0x20 PHY_ADR_DC_INIT_DISABLE_0:RW+:0:2:=0x00 + 0x00202020, // 1057: PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0:RW_D:24:1:=0x00 PHY_ADR_DC_ADR5_CLK_ADJUST_0:RW+:16:8:=0x20 PHY_ADR_DC_ADR4_CLK_ADJUST_0:RW+:8:8:=0x20 PHY_ADR_DC_ADR3_CLK_ADJUST_0:RW+:0:8:=0x20 + 0x20008008, // 1058: PHY_ADR_DC_ADJUST_START_0:RW:24:6:=0x20 PHY_ADR_DC_WEIGHT_0:RW:16:2:=0x00 PHY_ADR_DC_CAL_TIMEOUT_0:RW:8:8:=0x80 PHY_ADR_DC_CAL_SAMPLE_WAIT_0:RW:0:8:=0x08 + 0x00000810, // 1059: PHY_ADR_DC_CAL_POLARITY_0:RW:24:1:=0x00 PHY_ADR_DC_ADJUST_DIRECT_0:RW:16:1:=0x00 PHY_ADR_DC_ADJUST_THRSHLD_0:RW:8:8:=0x08 PHY_ADR_DC_ADJUST_SAMPLE_CNT_0:RW:0:8:=0x10 + 0x00000F00, // 1060: PHY_PARITY_ERROR_REGIF_ADR_0:RW:16:11:=0x0000 PHY_ADR_SW_TXPWR_CTRL_0:RW:8:6:=0x0f PHY_ADR_DC_CAL_START_0:RW+:0:1:=0x00 + 0x00000000, // 1061: PHY_AS_FSM_ERROR_INFO_MASK_0:RW:16:9:=0x0000 PHY_AS_FSM_ERROR_INFO_0:RD:0:9:=0x0000 + 0x00000000, // 1062: PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0:RW:24:1:=0x00 PHY_AS_TRAIN_CALIB_ERROR_INFO_0:RD:16:1:=0x00 SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0:WR:0:9:=0x0000 + 0x00000000, // 1063: SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0:WR:0:1:=0x00 + 0x0006047C, // 1064: PHY_PAD_ADR_IO_CFG_0:RW+:16:11:=0x0000 PHY_ADR_DC_CAL_CLK_SEL_0:RW+:8:3:=0x02 PHY_ADR_TSEL_SELECT_0:RW+:0:8:=0x44 + 0x00030000, // 1065: PHY_ADR1_SW_WRADDR_SHIFT_0:RW+:24:5:=0x00 PHY_ADR0_CLK_WR_SLAVE_DELAY_0:RW+:8:11:=0x0300 PHY_ADR0_SW_WRADDR_SHIFT_0:RW+:0:5:=0x00 + 0x00000300, // 1066: PHY_ADR2_SW_WRADDR_SHIFT_0:RW+:16:5:=0x00 PHY_ADR1_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 + 0x00000300, // 1067: PHY_ADR3_SW_WRADDR_SHIFT_0:RW+:16:5:=0x00 PHY_ADR2_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 + 0x00000300, // 1068: PHY_ADR4_SW_WRADDR_SHIFT_0:RW+:16:5:=0x00 PHY_ADR3_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 + 0x00000300, // 1069: PHY_ADR5_SW_WRADDR_SHIFT_0:RW+:16:5:=0x00 PHY_ADR4_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 + 0x00000300, // 1070: PHY_ADR_SW_MASTER_MODE_0:RW+:16:4:=0x00 PHY_ADR5_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 + 0x42080010, // 1071: PHY_ADR_MASTER_DELAY_WAIT_0:RW+:24:8:=0x42 PHY_ADR_MASTER_DELAY_STEP_0:RW+:16:6:=0x08 PHY_ADR_MASTER_DELAY_START_0:RW+:0:11:=0x0010 + 0x0000803E, // 1072: PHY_ADR_SW_CALVL_DVW_MIN_EN_0:RW+:24:1:=0x00 PHY_ADR_SW_CALVL_DVW_MIN_0:RW+:8:10:=0x0080 PHY_ADR_MASTER_DELAY_HALF_MEASURE_0:RW+:0:8:=0x3e + 0x00000001, // 1073: PHY_ADR_CALVL_DLY_STEP_0:RW+:0:4:=0x01 + 0x01000102, // 1074: PHY_ADR_DC_INIT_SLV_DELAY_0:RW+:16:10:=0x0100 PHY_ADR_MEAS_DLY_STEP_ENABLE_0:RW+:8:1:=0x01 PHY_ADR_CALVL_CAPTURE_CNT_0:RW+:0:4:=0x02 + 0x00008000, // 1075: PHY_ADR_DC_DM_CLK_THRSHLD_0:RW+:8:8:=0x80 PHY_ADR_DC_CALVL_ENABLE_0:RW+:0:1:=0x01 + 0x00000000, // 1076: + 0x00000000, // 1077: + 0x00000000, // 1078: + 0x00000000, // 1079: + 0x00000000, // 1080: + 0x00000000, // 1081: + 0x00000000, // 1082: + 0x00000000, // 1083: + 0x00000000, // 1084: + 0x00000000, // 1085: + 0x00000000, // 1086: + 0x00000000, // 1087: + 0x00000000, // 1088: + 0x00000000, // 1089: + 0x00000000, // 1090: + 0x00000000, // 1091: + 0x00000000, // 1092: + 0x00000000, // 1093: + 0x00000000, // 1094: + 0x00000000, // 1095: + 0x00000000, // 1096: + 0x00000000, // 1097: + 0x00000000, // 1098: + 0x00000000, // 1099: + 0x00000000, // 1100: + 0x00000000, // 1101: + 0x00000000, // 1102: + 0x00000000, // 1103: + 0x00000000, // 1104: + 0x00000000, // 1105: + 0x00000000, // 1106: + 0x00000000, // 1107: + 0x00000000, // 1108: + 0x00000000, // 1109: + 0x00000000, // 1110: + 0x00000000, // 1111: + 0x00000000, // 1112: + 0x00000000, // 1113: + 0x00000000, // 1114: + 0x00000000, // 1115: + 0x00000000, // 1116: + 0x00000000, // 1117: + 0x00000000, // 1118: + 0x00000000, // 1119: + 0x00000000, // 1120: + 0x00000000, // 1121: + 0x00000000, // 1122: + 0x00000000, // 1123: + 0x00000000, // 1124: + 0x00000000, // 1125: + 0x00000000, // 1126: + 0x00000000, // 1127: + 0x00000000, // 1128: + 0x00000000, // 1129: + 0x00000000, // 1130: + 0x00000000, // 1131: + 0x00000000, // 1132: + 0x00000000, // 1133: + 0x00000000, // 1134: + 0x00000000, // 1135: + 0x00000000, // 1136: + 0x00000000, // 1137: + 0x00000000, // 1138: + 0x00000000, // 1139: + 0x00000000, // 1140: + 0x00000000, // 1141: + 0x00000000, // 1142: + 0x00000000, // 1143: + 0x00000000, // 1144: + 0x00000000, // 1145: + 0x00000000, // 1146: + 0x00000000, // 1147: + 0x00000000, // 1148: + 0x00000000, // 1149: + 0x00000000, // 1150: + 0x00000000, // 1151: + 0x00000000, // 1152: + 0x00000000, // 1153: + 0x00000000, // 1154: + 0x00000000, // 1155: + 0x00000000, // 1156: + 0x00000000, // 1157: + 0x00000000, // 1158: + 0x00000000, // 1159: + 0x00000000, // 1160: + 0x00000000, // 1161: + 0x00000000, // 1162: + 0x00000000, // 1163: + 0x00000000, // 1164: + 0x00000000, // 1165: + 0x00000000, // 1166: + 0x00000000, // 1167: + 0x00000000, // 1168: + 0x00000000, // 1169: + 0x00000000, // 1170: + 0x00000000, // 1171: + 0x00000000, // 1172: + 0x00000000, // 1173: + 0x00000000, // 1174: + 0x00000000, // 1175: + 0x00000000, // 1176: + 0x00000000, // 1177: + 0x00000000, // 1178: + 0x00000000, // 1179: + 0x00000000, // 1180: + 0x00000000, // 1181: + 0x00000000, // 1182: + 0x00000000, // 1183: + 0x00000000, // 1184: + 0x00000000, // 1185: + 0x00000000, // 1186: + 0x00000000, // 1187: + 0x00000000, // 1188: + 0x00000000, // 1189: + 0x00000000, // 1190: + 0x00000000, // 1191: + 0x00000000, // 1192: + 0x00000000, // 1193: + 0x00000000, // 1194: + 0x00000000, // 1195: + 0x00000000, // 1196: + 0x00000000, // 1197: + 0x00000000, // 1198: + 0x00000000, // 1199: + 0x00000000, // 1200: + 0x00000000, // 1201: + 0x00000000, // 1202: + 0x00000000, // 1203: + 0x00000000, // 1204: + 0x00000000, // 1205: + 0x00000000, // 1206: + 0x00000000, // 1207: + 0x00000000, // 1208: + 0x00000000, // 1209: + 0x00000000, // 1210: + 0x00000000, // 1211: + 0x00000000, // 1212: + 0x00000000, // 1213: + 0x00000000, // 1214: + 0x00000000, // 1215: + 0x00000000, // 1216: + 0x00000000, // 1217: + 0x00000000, // 1218: + 0x00000000, // 1219: + 0x00000000, // 1220: + 0x00000000, // 1221: + 0x00000000, // 1222: + 0x00000000, // 1223: + 0x00000000, // 1224: + 0x00000000, // 1225: + 0x00000000, // 1226: + 0x00000000, // 1227: + 0x00000000, // 1228: + 0x00000000, // 1229: + 0x00000000, // 1230: + 0x00000000, // 1231: + 0x00000000, // 1232: + 0x00000000, // 1233: + 0x00000000, // 1234: + 0x00000000, // 1235: + 0x00000000, // 1236: + 0x00000000, // 1237: + 0x00000000, // 1238: + 0x00000000, // 1239: + 0x00000000, // 1240: + 0x00000000, // 1241: + 0x00000000, // 1242: + 0x00000000, // 1243: + 0x00000000, // 1244: + 0x00000000, // 1245: + 0x00000000, // 1246: + 0x00000000, // 1247: + 0x00000000, // 1248: + 0x00000000, // 1249: + 0x00000000, // 1250: + 0x00000000, // 1251: + 0x00000000, // 1252: + 0x00000000, // 1253: + 0x00000000, // 1254: + 0x00000000, // 1255: + 0x00000000, // 1256: + 0x00000000, // 1257: + 0x00000000, // 1258: + 0x00000000, // 1259: + 0x00000000, // 1260: + 0x00000000, // 1261: + 0x00000000, // 1262: + 0x00000000, // 1263: + 0x00000000, // 1264: + 0x00000000, // 1265: + 0x00000000, // 1266: + 0x00000000, // 1267: + 0x00000000, // 1268: + 0x00000000, // 1269: + 0x00000000, // 1270: + 0x00000000, // 1271: + 0x00000000, // 1272: + 0x00000000, // 1273: + 0x00000000, // 1274: + 0x00000000, // 1275: + 0x00000000, // 1276: + 0x00000000, // 1277: + 0x00000000, // 1278: + 0x00000000, // 1279: + 0x00000000, // 1280: PHY_FREQ_SEL:RW:0:2:=0x00 + 0x00000100, // 1281: PHY_SW_GRP0_SHIFT_0:RW+:24:5:=0x00 PHY_FREQ_SEL_INDEX:RW+:16:2:=0x00 PHY_FREQ_SEL_MULTICAST_EN:RW+:8:1:=0x01 PHY_FREQ_SEL_FROM_REGIF:RW_D:0:1:=0x00 + 0x00000000, // 1282: PHY_SW_GRP0_SHIFT_1:RW+:24:5:=0x00 PHY_SW_GRP3_SHIFT_0:RW+:16:5:=0x00 PHY_SW_GRP2_SHIFT_0:RW+:8:5:=0x00 PHY_SW_GRP1_SHIFT_0:RW+:0:5:=0x00 + 0x00000000, // 1283: PHY_SW_GRP3_SHIFT_1:RW+:16:5:=0x00 PHY_SW_GRP2_SHIFT_1:RW+:8:5:=0x00 PHY_SW_GRP1_SHIFT_1:RW+:0:5:=0x00 + 0x00050000, // 1284: PHY_GRP_BYPASS_OVERRIDE:RW:24:1:=0x00 PHY_SW_GRP_BYPASS_SHIFT:RW:16:5:=0x05 PHY_GRP_BYPASS_SLAVE_DELAY:RW:0:11:=0x0000 + 0x04000000, // 1285: PHY_CSLVL_START:RW:16:11:=0x0400 PHY_MANUAL_UPDATE_PHYUPD_ENABLE:RW_D:8:1:=0x00 SC_PHY_MANUAL_UPDATE:WR:0:1:=0x00 + 0x00000055, // 1286: SC_PHY_CSLVL_DEBUG_CONT:WR:24:1:=0x00 PHY_CSLVL_DEBUG_MODE:RW:16:1:=0x00 PHY_CSLVL_COARSE_DLY:RW:0:11:=0x0055 + 0x00000000, // 1287: SC_PHY_CSLVL_ERROR_CLR:WR:0:1:=0x00 + 0x00000000, // 1288: PHY_CSLVL_OBS0:RD:0:32:=0x00000000 + 0x00000000, // 1289: PHY_CSLVL_OBS1:RD:0:32:=0x00000000 + 0x00000000, // 1290: PHY_CSLVL_OBS2:RD:0:32:=0x00000000 + 0x00002001, // 1291: PHY_LP4_BOOT_DISABLE:RW:24:1:=0x00 PHY_CSLVL_PERIODIC_START_OFFSET:RW:8:9:=0x0020 PHY_CSLVL_ENABLE:RW:0:1:=0x01 + 0x0000400F, // 1292: PHY_CSLVL_QTR:RW:8:11:=0x0040 PHY_CSLVL_CS_MAP:RW:0:4:=0x0f + 0x50020040, // 1293: PHY_CALVL_CS_MAP:RW:24:8:=0x50 PHY_CSLVL_COARSE_CAPTURE_CNT:RW:16:4:=0x02 PHY_CSLVL_COARSE_CHK:RW:0:11:=0x0028 + 0x01010000, // 1294: PHY_ADRCTL_LPDDR:RW:24:1:=0x01 PHY_DFI_PHYUPD_TYPE:RW:16:2:=0x01 PHY_ADRCTL_SNAP_OBS_REGS:WR:8:1:=0x00 PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE:RW:0:3:=0x00 + 0x80080001, // 1295: PHY_CLK_DC_CAL_TIMEOUT:RW:24:8:=0x80 PHY_CLK_DC_CAL_SAMPLE_WAIT:RW:16:8:=0x08 PHY_LPDDR3_CS:RW_D:8:1:=0x00 PHY_LP4_ACTIVE:RW:0:1:=0x01 + 0x10200000, // 1296: PHY_CLK_DC_ADJUST_SAMPLE_CNT:RW:24:8:=0x10 PHY_CLK_DC_ADJUST_START:RW:16:6:=0x20 PHY_CLK_DC_FREQ_CHG_ADJ:RW:8:1:=0x00 PHY_CLK_DC_WEIGHT:RW:0:2:=0x00 + 0x00000008, // 1297: PHY_CLK_DC_CAL_START:RW+:24:1:=0x00 PHY_CLK_DC_CAL_POLARITY:RW:16:1:=0x00 PHY_CLK_DC_ADJUST_DIRECT:RW:8:1:=0x00 PHY_CLK_DC_ADJUST_THRSHLD:RW:0:8:=0x08 + 0x00000100, // 1298: PHY_SW_TXIO_CTRL_1:RW:24:4:=0x00 PHY_SW_TXIO_CTRL_0:RW:16:4:=0x00 PHY_CONTINUOUS_CLK_CAL_UPDATE:RW:8:1:=0x00 SC_PHY_UPDATE_CLK_CAL_VALUES:WR:0:1:=0x00 + 0x01090E00, // 1299: PHY_MEMCLK_SW_TXPWR_CTRL:RW:24:1:=0x01 PHY_ADRCTL_SW_TXPWR_CTRL_1:RW:16:4:=0x09 PHY_ADRCTL_SW_TXPWR_CTRL_0:RW:8:4:=0x0e PHY_MEMCLK_SW_TXIO_CTRL:RW:0:1:=0x00 + 0x00040101, // 1300: PHY_STATIC_TOG_CONTROL:RW:16:16:=0x0004 PHY_BYTE_DISABLE_STATIC_TOG_DISABLE:RW:8:1:=0x01 PHY_TOP_STATIC_TOG_DISABLE:RW:0:1:=0x01 + 0x0000010F, // 1301: PHY_LP4_BOOT_PLL_BYPASS:RW:16:1:=0x00 PHY_MEMCLK_STATIC_TOG_DISABLE:RW:8:1:=0x01 PHY_ADRCTL_STATIC_TOG_DISABLE:RW:0:4:=0x0f + 0x00000000, // 1302: PHY_CLK_SWITCH_OBS:RD:0:32:=0x00000000 + 0x00000064, // 1303: PHY_PLL_WAIT:RW:0:16:=0x0064 + 0x00000000, // 1304: PHY_SW_PLL_BYPASS:RW+:0:1:=0x00 + 0x01010000, // 1305: PHY_CS_ACS_ALLOCATION_BIT1_0:RW:24:4:=0x01 PHY_CS_ACS_ALLOCATION_BIT0_0:RW:16:4:=0x01 PHY_SET_DFI_INPUT_1:RW_D:8:4:=0x00 PHY_SET_DFI_INPUT_0:RW_D:0:4:=0x00 + 0x01080402, // 1306: PHY_CS_ACS_ALLOCATION_BIT1_1:RW:24:4:=0x01 PHY_CS_ACS_ALLOCATION_BIT0_1:RW:16:4:=0x08 PHY_CS_ACS_ALLOCATION_BIT3_0:RW:8:4:=0x04 PHY_CS_ACS_ALLOCATION_BIT2_0:RW:0:4:=0x02 + 0x01200F02, // 1307: PHY_CLK_DC_INIT_DISABLE:RW+:24:1:=0x00 PHY_CLK_DC_ADJUST_0:RW+:16:8:=0x20 PHY_CS_ACS_ALLOCATION_BIT3_1:RW:8:4:=0x0f PHY_CS_ACS_ALLOCATION_BIT2_1:RW:0:4:=0x02 + 0x001B4280, // 1308: PHY_LP4_BOOT_PLL_CTRL:RW:8:13:=0x1b42 PHY_CLK_DC_DM_THRSHLD:RW+:0:8:=0x80 + 0x00010004, // 1309: PHY_USE_PLL_DSKEWCALLOCK:RW:16:1:=0x01 PHY_PLL_CTRL_OVERRIDE:RW:0:16:=0x0004 + 0x00050000, // 1310: SC_PHY_PLL_SPO_CAL_SNAP_OBS:WR:24:2:=0x00 PHY_PLL_SPO_CAL_CTRL:RW:0:19:=0x050000 + 0x00000000, // 1311: SC_PHY_PLL_CAL_CLK_MEAS:WR:16:2:=0x00 PHY_PLL_CAL_CLK_MEAS_CYCLES:RW:0:10:=0x0000 + 0x00000000, // 1312: PHY_PLL_OBS_0:RD:0:16:=0x0000 + 0x00000000, // 1313: PHY_PLL_SPO_CAL_OBS_0:RD:0:17:=0x000000 + 0x00000000, // 1314: PHY_PLL_CAL_CLK_MEAS_OBS_0:RD:0:18:=0x000000 + 0x00000000, // 1315: PHY_PLL_OBS_1:RD:0:16:=0x0000 + 0x00000000, // 1316: PHY_PLL_SPO_CAL_OBS_1:RD:0:17:=0x000000 + 0x01000000, // 1317: PHY_LP4_BOOT_LOW_FREQ_SEL:RW:24:1:=0x01 PHY_PLL_CAL_CLK_MEAS_OBS_1:RD:0:18:=0x000000 + 0x00000705, // 1318: PHY_LS_IDLE_EN:RW:16:1:=0x01 PHY_LP_WAKEUP:RW:8:8:=0x07 PHY_TCKSRE_WAIT:RW:0:4:=0x05 + 0x00000054, // 1319: PHY_TDFI_PHY_WRDELAY:RW:16:1:=0x00 PHY_LP_CTRLUPD_CNTR_CFG:RW:0:10:=0x0054 + 0x00024410, // 1320: PHY_PAD_FDBK_TERM:RW+:0:18:=0x004410 + 0x00004410, // 1321: PHY_PAD_DATA_TERM:RW+:0:17:=0x004410 + 0x00004410, // 1322: PHY_PAD_DQS_TERM:RW+:0:17:=0x004410 + 0x00004410, // 1323: PHY_PAD_ADDR_TERM:RW+:0:18:=0x004410 + 0x00004410, // 1324: PHY_PAD_CLK_TERM:RW+:0:18:=0x004410 + 0x00004410, // 1325: PHY_PAD_CKE_TERM:RW+:0:18:=0x004410 + 0x00004410, // 1326: PHY_PAD_RST_TERM:RW+:0:18:=0x004410 + 0x00004410, // 1327: PHY_PAD_CS_TERM:RW+:0:18:=0x004410 + 0x00004410, // 1328: PHY_PAD_ODT_TERM:RW+:0:18:=0x004410 + 0x00000000, // 1329: PHY_ADRCTL_LP3_RX_CAL:RW:16:13:=0x0000 PHY_ADRCTL_RX_CAL:RW:0:10:=0x0000 + 0x00000076, // 1330: PHY_CAL_START_0:WR:24:1:=0x00 PHY_CAL_CLEAR_0:WR:16:1:=0x00 PHY_CAL_MODE_0:RW:0:13:=0x0064 + 0x00001000, // 1331: PHY_CAL_INTERVAL_COUNT_0:RW:0:32:=0x00000000 + 0x00000108, // 1332: PHY_LP4_BOOT_CAL_CLK_SELECT_0:RW:8:3:=0x01 PHY_CAL_SAMPLE_WAIT_0:RW:0:8:=0x08 + 0x00000000, // 1333: PHY_CAL_RESULT_OBS_0:RD:0:24:=0x000000 + 0x00000000, // 1334: PHY_CAL_RESULT2_OBS_0:RD:0:24:=0x000000 + 0x00000000, // 1335: PHY_CAL_RESULT4_OBS_0:RD:0:24:=0x000000 + 0x00000000, // 1336: PHY_CAL_RESULT5_OBS_0:RD:0:24:=0x000000 + 0x00000000, // 1337: PHY_CAL_RESULT6_OBS_0:RD:0:24:=0x000000 + 0x03000000, // 1338: PHY_CAL_CPTR_CNT_0:RW:24:7:=0x03 PHY_CAL_RESULT7_OBS_0:RD:0:24:=0x000000 + 0x00000000, // 1339: PHY_CAL_DBG_CFG_0:RW:24:1:=0x00 PHY_CAL_RCV_FINE_ADJ_0:RW:16:8:=0x00 PHY_CAL_PD_FINE_ADJ_0:RW:8:8:=0x00 PHY_CAL_PU_FINE_ADJ_0:RW:0:8:=0x00 + 0x00000000, // 1340: SC_PHY_PAD_DBG_CONT_0:WR:0:1:=0x00 + 0x00000000, // 1341: PHY_CAL_RESULT3_OBS_0:RD:0:32:=0x00000000 + 0x04102006, // 1342: PHY_CAL_SLOPE_ADJ_0:RW_D:8:20:=0x041020 PHY_ADRCTL_PVT_MAP_0:RW:0:7:=0x35 + 0x00041020, // 1343: PHY_CAL_SLOPE_ADJ_PASS2_0:RW_D:0:20:=0x041020 + 0x01C98C98, // 1344: PHY_CAL_TWO_PASS_CFG_0:RW_D:0:25:=0x01c98c98 + 0x3F400000, // 1345: PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0:RW_D:24:6:=0x3f PHY_CAL_SW_CAL_CFG_0:RW:0:23:=0x400000 + 0x3F3F1F3F, // 1346: PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0:RW_D:24:6:=0x3f PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0:RW_D:16:6:=0x3f PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0:RW_D:8:5:=0x1f PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0:RW_D:0:6:=0x3f + 0x0000001F, // 1347: PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0:RW:24:5:=0x1f PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0:RW:16:6:=0x3f PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0:RW:8:6:=0x3f PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0:RW_D:0:5:=0x1f + 0x00000000, // 1348: PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0:RW:16:5:=0x1f PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0:RW:8:6:=0x3f PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0:RW:0:6:=0x3f + 0x00000000, // 1349: PHY_PARITY_ERROR_REGIF_AC:RW:16:11:=0x0000 PHY_PAD_ATB_CTRL:RW:0:16:=0x0000 + 0x00000000, // 1350: PHY_AC_LPBK_ENABLE:RW:24:2:=0x00 PHY_AC_LPBK_OBS_SELECT:RW:16:1:=0x00 PHY_AC_LPBK_ERR_CLEAR:WR:8:1:=0x00 PHY_ADRCTL_MANUAL_UPDATE:WR:0:1:=0x00 + 0x00010000, // 1351: PHY_AC_PRBS_PATTERN_MASK:RW:24:4:=0x00 PHY_AC_PRBS_PATTERN_START:RW_D:16:7:=0x01 PHY_AC_LPBK_CONTROL:RW:0:9:=0x0000 + 0x00000000, // 1352: PHY_AC_LPBK_RESULT_OBS:RD:0:32:=0x00000000 + 0x00000000, // 1353: PHY_AC_CLK_LPBK_CONTROL:RW:16:6:=0x00 PHY_AC_CLK_LPBK_ENABLE:RW:8:1:=0x00 PHY_AC_CLK_LPBK_OBS_SELECT:RW:0:1:=0x00 + 0x00000000, // 1354: PHY_TOP_PWR_RDC_DISABLE:RW_D:24:1:=0x00 PHY_AC_PWR_RDC_DISABLE:RW:16:1:=0x00 PHY_AC_CLK_LPBK_RESULT_OBS:RD:0:16:=0x0000 + 0x00000001, // 1355: PHY_AC_SLV_DLY_CTRL_GATE_DISABLE:RW_D:0:1:=0x00 + 0x76543210, // 1356: PHY_DATA_BYTE_ORDER_SEL:RW:0:32:=0x76543210 + 0x00010198, // 1357: PHY_ADRCTL_MSTR_DLY_ENC_SEL_0:RW:24:2:=0x00 PHY_CALVL_DEVICE_MAP:RW:16:5:=0x01 PHY_LPDDR4_CONNECT:RW:8:1:=0x01 PHY_DATA_BYTE_ORDER_SEL_HIGH:RW:0:8:=0x98 + 0x00000000, // 1358: PHY_ADRCTL_MSTR_DLY_ENC_SEL_1:RW:0:2:=0x00 + 0x00000000, // 1359: PHY_DDL_AC_ENABLE:RW:0:32:=0x00000000 + 0x00000000, // 1360: PHY_DDL_AC_MODE:RW:0:26:=0x00000000 + 0x00040700, // 1361: PHY_ERR_MASK_EN:RW:24:3:=0x00 PHY_DDL_TRACK_UPD_THRESHOLD_AC:RW:16:8:=0x04 PHY_INIT_UPDATE_CONFIG:RW:8:3:=0x07 PHY_DDL_AC_MASK:RW:0:6:=0x00 + 0x00000000, // 1362: PHY_ERR_STATUS:RW+:0:3:=0x00 + 0x00000000, // 1363: PHY_DS0_DQS_ERR_COUNTER:RD:0:32:=0x00000000 + 0x00000000, // 1364: PHY_DS1_DQS_ERR_COUNTER:RD:0:32:=0x00000000 + 0x00000000, // 1365: PHY_DS2_DQS_ERR_COUNTER:RD:0:32:=0x00000000 + 0x00000000, // 1366: PHY_DS3_DQS_ERR_COUNTER:RD:0:32:=0x00000000 + 0x00000002, // 1367: PHY_DS_INIT_COMPLETE_OBS:RD:24:4:=0x00 PHY_AC_INIT_COMPLETE_OBS:RD:8:10:=0x0000 PHY_DLL_RST_EN:RW_D:0:2:=0x02 + 0x00000000, // 1368: PHY_GRP_SHIFT_OBS_SELECT:RW:24:3:=0x00 PHY_GRP_SLV_DLY_ENC_OBS_SELECT:RW:16:4:=0x00 PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE:RW_D:8:1:=0x00 PHY_UPDATE_MASK:RW:0:1:=0x00 + 0x00000000, // 1369: PHY_GRP_SHIFT_OBS:RD:16:3:=0x00 PHY_GRP_SLV_DLY_ENC_OBS:RD:0:11:=0x0000 + 0x00000000, // 1370: PHY_PLL_LOCK_DEASSERT_MASK:RW:24:3:=0x00 PHY_PARITY_ERROR_REGIF_PS:RW:8:11:=0x0000 PHY_PARITY_ERROR_INJECTION_ENABLE:RW:0:1:=0x00 + 0x00000000, // 1371: SC_PHY_PARITY_ERROR_INFO_WOCLR:WR:16:7:=0x00 PHY_PARITY_ERROR_INFO_MASK:RW:8:7:=0x00 PHY_PARITY_ERROR_INFO:RD:0:7:=0x00 + 0x00000000, // 1372: PHY_TIMEOUT_ERROR_INFO_MASK:RW:16:14:=0x0000 PHY_TIMEOUT_ERROR_INFO:RD:0:14:=0x0000 + 0x00000000, // 1373: PHY_PLL_FREQUENCY_ERROR_MASK:RW:24:6:=0x00 PHY_PLL_FREQUENCY_ERROR:RD:16:4:=0x00 SC_PHY_TIMEOUT_ERROR_INFO_WOCLR:WR:0:14:=0x0000 + 0x00080000, // 1374: PHY_PLL_DSKEWCALOUT_MIN:RW:8:12:=0x0800 SC_PHY_PLL_FREQUENCY_ERROR_WOCLR:WR:0:6:=0x00 + 0x000007FF, // 1375: PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK:RW:24:2:=0x00 PHY_PLL_DSKEWCALOUT_ERROR_INFO:RD:16:2:=0x00 PHY_PLL_DSKEWCALOUT_MAX:RW:0:12:=0x07ff + 0x00000000, // 1376: PHY_TOP_FSM_ERROR_INFO:RD:8:9:=0x0000 SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR:WR:0:2:=0x00 + 0x00000000, // 1377: SC_PHY_TOP_FSM_ERROR_INFO_WOCLR:WR:16:9:=0x0000 PHY_TOP_FSM_ERROR_INFO_MASK:RW:0:9:=0x0000 + 0x00000000, // 1378: PHY_FSM_TRANSIENT_ERROR_INFO_MASK:RW:16:10:=0x0000 PHY_FSM_TRANSIENT_ERROR_INFO:RD:0:10:=0x0000 + 0x00000000, // 1379: PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK:RW:24:2:=0x00 PHY_TOP_TRAIN_CALIB_ERROR_INFO:RD:16:2:=0x00 SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR:WR:0:10:=0x0000 + 0x00000000, // 1380: SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR:WR:24:7:=0x00 PHY_TRAIN_CALIB_ERROR_INFO_MASK:RW:16:7:=0x00 PHY_TRAIN_CALIB_ERROR_INFO:RD:8:7:=0x00 SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR:WR:0:2:=0x00 + 0x00000000, // 1381: PHY_GLOBAL_ERROR_INFO_MASK:RW:8:6:=0x00 PHY_GLOBAL_ERROR_INFO:RD:0:6:=0x00 + 0x000FFFFF, // 1382: PHY_TRAINING_TIMEOUT_VALUE:RW:0:20:=0x0fffff + 0x000FFFFF, // 1383: PHY_INIT_TIMEOUT_VALUE:RW:0:20:=0x0fffff + 0x0000FFFF, // 1384: PHY_LP_TIMEOUT_VALUE:RW:0:16:=0xffff + 0xFFFFFFF0, // 1385: PHY_PHYUPD_TIMEOUT_VALUE:RW:0:32:=0xFFFFFFF0 + 0x030FFFFF, // 1386: PHY_PLL_LOCK_0_MIN_VALUE:RW:24:5:=0x03 PHY_PHYMSTR_TIMEOUT_VALUE:RW:0:20:=0x0fffff + 0x01FFFFFF, // 1387: PHY_PLL_FREQUENCY_DELTA:RW:24:4:=0x01 PHY_RDDATA_VALID_TIMEOUT_VALUE:RW:16:8:=0xff PHY_PLL_LOCK_TIMEOUT_VALUE:RW:0:16:=0xffff + 0x0000FFFF, // 1388: PHY_ADRCTL_FSM_ERROR_INFO_0:RD:16:14:=0x0000 PHY_PLL_FREQUENCY_COMPARE_INTERVAL:RW:0:16:=0xffff + 0x00000000, // 1389: SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0:WR:16:14:=0x0000 PHY_ADRCTL_FSM_ERROR_INFO_MASK_0:RW:0:14:=0x0000 + 0x00000000, // 1390: PHY_ADRCTL_FSM_ERROR_INFO_MASK_1:RW:16:14:=0x0000 PHY_ADRCTL_FSM_ERROR_INFO_1:RD:0:14:=0x0000 + 0x00000000, // 1391: PHY_MEMCLK_FSM_ERROR_INFO_0:RD:16:14:=0x0000 SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1:WR:0:14:=0x0000 + 0x00000000, // 1392: SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0:WR:16:14:=0x0000 PHY_MEMCLK_FSM_ERROR_INFO_MASK_0:RW:0:14:=0x0000 + 0x0001F7C6, // 1393: PHY_PAD_CAL_IO_CFG_0:RW+:0:18:=0x000000 + 0x00000006, // 1394: PHY_PAD_ACS_IO_CFG:RW+:0:14:=0x0000 + 0x00000000, // 1395: PHY_PLL_BYPASS:RW+:0:1:=0x00 + 0x00001142, // 1396: PHY_LOW_FREQ_SEL:RW+:16:1:=0x00 PHY_PLL_CTRL:RW+:0:13:=0x1142 + 0x010207AE, // 1397: PHY_CSLVL_DLY_STEP:RW+:24:4:=0x01 PHY_CSLVL_CAPTURE_CNT:RW+:16:4:=0x02 PHY_PAD_VREF_CTRL_AC:RW:0:12:=0x0600 + 0x01000080, // 1398: PHY_LVL_MEAS_DLY_STEP_ENABLE:RW+:24:1:=0x01 PHY_SW_CSLVL_DVW_MIN_EN:RW+:16:1:=0x00 PHY_SW_CSLVL_DVW_MIN:RW+:0:9:=0x0080 + 0x03000300, // 1399: PHY_GRP1_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_GRP0_SLAVE_DELAY_0:RW+:0:11:=0x0300 + 0x03000300, // 1400: PHY_GRP3_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_GRP2_SLAVE_DELAY_0:RW+:0:11:=0x0300 + 0x00000300, // 1401: PHY_GRP0_SLAVE_DELAY_1:RW+:0:11:=0x0300 + 0x00000300, // 1402: PHY_GRP1_SLAVE_DELAY_1:RW+:0:11:=0x0300 + 0x00000300, // 1403: PHY_GRP2_SLAVE_DELAY_1:RW+:0:11:=0x0300 + 0x00000300, // 1404: PHY_GRP3_SLAVE_DELAY_1:RW+:0:11:=0x0300 + 0x00000005, // 1405: PHY_CLK_DC_CAL_CLK_SEL:RW+:0:3:=0x02 + 0x3183BFCC, // 1406: PHY_PAD_FDBK_DRIVE:RW+:0:30:=0x00030044 + 0x0003000B, // 1407: PHY_PAD_FDBK_DRIVE2:RW+:0:18:=0x030008 + 0x0C000DFF, // 1408: PHY_PAD_DATA_DRIVE:RW+:0:31:=0x00000180 + 0x30000DFF, // 1409: PHY_PAD_DQS_DRIVE:RW+:0:32:=0x00000180 + 0x300DFF11, // 1410: PHY_PAD_ADDR_DRIVE:RW+:0:30:=0x00018011 + 0x01990000, // 1411: PHY_PAD_ADDR_DRIVE2:RW+:0:27:=0x0089ff00 + 0x000DFFCC, // 1412: PHY_PAD_CLK_DRIVE:RW+:0:32:=0x00018044 + 0x00004C11, // 1413: PHY_PAD_CLK_DRIVE2:RW+:0:18:=0x004011 + 0x300DFF11, // 1414: PHY_PAD_CKE_DRIVE:RW+:0:30:=0x00018011 + 0x01990000, // 1415: PHY_PAD_CKE_DRIVE2:RW+:0:27:=0x0089ff00 + 0x300DFF11, // 1416: PHY_PAD_RST_DRIVE:RW+:0:30:=0x00018011 + 0x01990000, // 1417: PHY_PAD_RST_DRIVE2:RW+:0:27:=0x0089ff00 + 0x300DFF11, // 1418: PHY_PAD_CS_DRIVE:RW+:0:30:=0x00018011 + 0x01990000, // 1419: PHY_PAD_CS_DRIVE2:RW+:0:27:=0x0089ff00 + 0x00018011, // 1420: PHY_PAD_ODT_DRIVE:RW+:0:30:=0x00018011 + 0x0199FF00, // 1421: PHY_PAD_ODT_DRIVE2:RW+:0:27:=0x0089ff00 + 0x20040006 // 1422: PHY_CAL_SETTLING_PRD_0:RW+:24:7:=0x20 PHY_CAL_VREF_SWITCH_TIMER_0:RW+:8:16:=0x0400 PHY_CAL_CLK_SELECT_0:RW+:0:3:=0x01 +}; + +#endif /* _DDR_CONFIGURATION_H_ */ + diff --git a/meta-hailo-bsp/recipes-bsp/hailo-ddr-configuration-native/files/hailo15_evb_MT53E1G32D2FW-046_non_official_4000.h b/meta-hailo-bsp/recipes-bsp/hailo-ddr-configuration-native/files/hailo15_evb_MT53E1G32D2FW-046_non_official_4000.h new file mode 100644 index 0000000..51cc45a --- /dev/null +++ b/meta-hailo-bsp/recipes-bsp/hailo-ddr-configuration-native/files/hailo15_evb_MT53E1G32D2FW-046_non_official_4000.h @@ -0,0 +1,2191 @@ +/****************************************************************************** +* Legal notice: +* Copyright (C) 2012-2023 Cadence Design Systems, Inc. +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +// Auto-generated using DDR Utility + +#ifndef _DDR_CONFIGURATION_H_ +#define _DDR_CONFIGURATION_H_ + +#include + + +uint32_t DDR_ctrl_registers[] = +{ + 0x00000B00, // 0: CONTROLLER_ID:RD:16:16:=0x0000 DRAM_CLASS:RW:8:4:=0x0b START:RW:0:1:=0x00 + 0x00000000, // 1: CONTROLLER_VERSION:RD:0:64:=0x00000000 + 0x00000000, // 2: CONTROLLER_VERSION:RD:0:64:=0x00000000 + 0x00000000, // 3: READ_DATA_FIFO_DEPTH:RD:24:8:=0x00 MAX_CS_REG:RD:16:2:=0x00 MAX_COL_REG:RD:8:4:=0x00 MAX_ROW_REG:RD:0:5:=0x00 + 0x00000000, // 4: WRITE_DATA_FIFO_PTR_WIDTH:RD:16:8:=0x00 WRITE_DATA_FIFO_DEPTH:RD:8:8:=0x00 READ_DATA_FIFO_PTR_WIDTH:RD:0:8:=0x00 + 0x00000000, // 5: ASYNC_CDC_STAGES:RD:24:8:=0x00 MEMCD_RMODW_FIFO_PTR_WIDTH:RD:16:8:=0x00 MEMCD_RMODW_FIFO_DEPTH:RD:0:16:=0x0000 + 0x00000000, // 6: AXI0_TRANS_WRFIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI0_WR_ARRAY_LOG2_DEPTH:RD:16:8:=0x00 AXI0_CMDFIFO_LOG2_DEPTH:RD:0:8:=0x00 + 0x00000000, // 7: AXI1_WR_ARRAY_LOG2_DEPTH:RD:24:8:=0x00 AXI1_CMDFIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:0:8:=0x00 + 0x00000000, // 8: AXI1_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI1_TRANS_WRFIFO_LOG2_DEPTH:RD:0:8:=0x00 + 0x00002710, // 9: TINIT_F0:RW:0:24:=0x002710 + 0x000186A0, // 10: TINIT3_F0:RW:0:24:=0x0186a0 + 0x00000005, // 11: TINIT4_F0:RW:0:24:=0x000005 + 0x00000064, // 12: TINIT5_F0:RW:0:24:=0x000064 + 0x0004E200, // 13: TINIT_F1:RW:0:24:=0x04e200 + 0x0030D400, // 14: TINIT3_F1:RW:0:24:=0x30d400 + 0x00000005, // 15: TINIT4_F1:RW:0:24:=0x000005 + 0x00000C80, // 16: TINIT5_F1:RW:0:24:=0x000c80 + 0x000681C8, // 17: TINIT_F2:RW:0:24:=0x0681c8 + 0x004111C9, // 18: TINIT3_F2:RW:0:24:=0x4111c9 + 0x00000005, // 19: TINIT4_F2:RW:0:24:=0x000005 + 0x000010A9, // 20: NO_AUTO_MRR_INIT:RW:24:1:=0x00 TINIT5_F2:RW:0:24:=0x0010a9 + 0x01000000, // 21: ODT_VALUE:RW:24:1:=0x01 NO_MRW_INIT:RW:16:1:=0x00 DFI_INV_DATA_CS:RW:8:1:=0x00 MRR_ERROR_STATUS:RD:0:1:=0x00 + 0x01001001, // 22: DFIBUS_FREQ_INIT:RW:24:2:=0x01 PHY_INDEP_INIT_MODE:RW:16:1:=0x00 TSREF2PHYMSTR:RW:8:6:=0x10 PHY_INDEP_TRAIN_MODE:RW:0:1:=0x01 + 0x02010000, // 23: DFIBUS_FREQ_F2:RW:24:5:=0x02 DFIBUS_FREQ_F1:RW:16:5:=0x01 DFIBUS_FREQ_F0:RW:8:5:=0x00 DFIBUS_BOOT_FREQ:RW:0:2:=0x00 + 0x00020100, // 24: FREQ_CHANGE_TYPE_F2:RW:16:2:=0x00 FREQ_CHANGE_TYPE_F1:RW:8:2:=0x01 FREQ_CHANGE_TYPE_F0:RW:0:2:=0x02 + 0x0000000A, // 25: TRST_PWRON:RW:0:32:=0x0000000a + 0x00000019, // 26: CKE_INACTIVE:RW:0:32:=0x00000019 + 0x00000000, // 27: RESERVED:RW:8:24:=0x000000 RESERVED:RW:0:1:=0x00 + 0x00000000, // 28: DQS_OSC_ENABLE:RW:16:1:=0x00 RESERVED:RW:8:8:=0x00 RESERVED:RW:0:8:=0x00 + 0x02020200, // 29: TOSCO_F0:RW:24:8:=0x02 FUNC_VALID_CYCLES:RW:16:4:=0x02 DQS_OSC_PERIOD:RW:0:15:=0x0200 + 0x00005640, // 30: DQS_OSC_HIGH_THRESHOLD:RW:24:8:=0x00 DQS_OSC_NORM_THRESHOLD:RW:16:8:=0x00 TOSCO_F2:RW:8:8:=0x56 TOSCO_F1:RW:0:8:=0x40 + 0x00100000, // 31: OSC_VARIANCE_LIMIT:RW:16:16:=0x0010 DQS_OSC_PROMOTE_THRESHOLD:RW:8:8:=0x00 DQS_OSC_TIMEOUT:RW:0:8:=0x00 + 0x00000000, // 32: OSC_BASE_VALUE_0_CS0:RD:8:16:=0x0000 DQS_OSC_REQUEST:WR:0:1:=0x00 + 0x00000000, // 33: OSC_BASE_VALUE_2_CS0:RD:16:16:=0x0000 OSC_BASE_VALUE_1_CS0:RD:0:16:=0x0000 + 0x00000000, // 34: OSC_BASE_VALUE_0_CS1:RD:16:16:=0x0000 OSC_BASE_VALUE_3_CS0:RD:0:16:=0x0000 + 0x00000000, // 35: OSC_BASE_VALUE_2_CS1:RD:16:16:=0x0000 OSC_BASE_VALUE_1_CS1:RD:0:16:=0x0000 + 0x040C0000, // 36: WRLAT_F0:RW:24:7:=0x04 CASLAT_LIN_F0:RW:16:7:=0x0c OSC_BASE_VALUE_3_CS1:RD:0:16:=0x0000 + 0x12480E38, // 37: WRLAT_F2:RW:24:7:=0x12 CASLAT_LIN_F2:RW:16:7:=0x48 WRLAT_F1:RW:8:7:=0x0e CASLAT_LIN_F1:RW:0:7:=0x38 + 0x00050804, // 38: TRRD_F0:RW:16:8:=0x05 TCCD:RW:8:5:=0x08 TBST_INT_INTERVAL:RW:0:3:=0x04 + 0x09040007, // 39: TWTR_F0:RW:24:6:=0x09 TRAS_MIN_F0:RW:16:8:=0x04 TRC_F0:RW:0:9:=0x0007 + 0x0D000203, // 40: TRRD_F1:RW:24:8:=0x0d TFAW_F0:RW:8:9:=0x0002 TRP_F0:RW:0:8:=0x03 + 0x11450062, // 41: TWTR_F1:RW:24:6:=0x11 TRAS_MIN_F1:RW:16:8:=0x45 TRC_F1:RW:0:9:=0x0062 + 0x1100311D, // 42: TRRD_F2:RW:24:8:=0x11 TFAW_F1:RW:8:9:=0x0031 TRP_F1:RW:0:8:=0x1d + 0x175C0083, // 43: TWTR_F2:RW:24:6:=0x17 TRAS_MIN_F2:RW:16:8:=0x5c TRC_F2:RW:0:9:=0x0083 + 0x20004227, // 44: TCCDMW:RW:24:6:=0x20 TFAW_F2:RW:8:9:=0x0042 TRP_F2:RW:0:8:=0x27 + 0x000A0A09, // 45: TMOD_F0:RW:16:8:=0x0a TMRD_F0:RW:8:8:=0x0a TRTP_F0:RW:0:8:=0x09 + 0x040006DB, // 46: TCKE_F0:RW:24:5:=0x04 TRAS_MAX_F0:RW:0:17:=0x0006db + 0x17100D04, // 47: TMOD_F1:RW:24:8:=0x17 TMRD_F1:RW:16:8:=0x10 TRTP_F1:RW:8:8:=0x0d TCKESR_F0:RW:0:8:=0x04 + 0x0C00DB60, // 48: TCKE_F1:RW:24:5:=0x0c TRAS_MAX_F1:RW:0:17:=0x00db60 + 0x1E16110C, // 49: TMOD_F2:RW:24:8:=0x1e TMRD_F2:RW:16:8:=0x16 TRTP_F2:RW:8:8:=0x11 TCKESR_F1:RW:0:8:=0x0c + 0x10012458, // 50: TCKE_F2:RW:24:5:=0x10 TRAS_MAX_F2:RW:0:17:=0x012458 + 0x02030410, // 51: RESERVED:RW:24:3:=0x02 RESERVED:RW:16:3:=0x03 TPPD:RW_D:8:3:=0x04 TCKESR_F2:RW:0:8:=0x10 + 0x1E040500, // 52: TRCD_F1:RW:24:8:=0x1e TWR_F0:RW:16:8:=0x04 TRCD_F0:RW:8:8:=0x05 WRITEINTERP:RW:0:1:=0x00 + 0x0829281F, // 53: TMRR:RW:24:4:=0x08 TWR_F2:RW:16:8:=0x29 TRCD_F2:RW:8:8:=0x28 TWR_F1:RW:0:8:=0x1f + 0x07010100, // 54: TDAL_F0:RW:24:8:=0x07 TRAS_LOCKOUT:RW:16:1:=0x01 CONCURRENTAP:RW:8:1:=0x01 AP:RW:0:1:=0x00 + 0x0304503C, // 55: TRP_AB_F0_0:RW:24:8:=0x03 BSTLEN:RW_D:16:5:=0x04 TDAL_F2:RW:8:8:=0x50 TDAL_F1:RW:0:8:=0x3c + 0x22032D22, // 56: TRP_AB_F1_1:RW:24:8:=0x22 TRP_AB_F0_1:RW:16:8:=0x03 TRP_AB_F2_0:RW:8:8:=0x2d TRP_AB_F1_0:RW:0:8:=0x22 + 0x0000002D, // 57: RESERVED:RW:24:7:=0x00 RESERVED:RW:16:2:=0x00 REG_DIMM_ENABLE:RW:8:1:=0x00 TRP_AB_F2_1:RW:0:8:=0x2d + 0x00000101, // 58: AREFRESH:WR:24:1:=0x00 NO_MEMORY_DM:RW:16:1:=0x00 RESERVED:RW:8:1:=0x01 OPTIMAL_RMODW_EN:RW:0:1:=0x01 + 0x08030100, // 59: CS_COMPARISON_FOR_REFRESH_DEPTH:RW:24:6:=0x08 RESERVED:RW:16:3:=0x03 TREF_ENABLE:RW:8:1:=0x01 AREF_STATUS:RD:0:1:=0x00 + 0x00000013, // 60: TRFC_F0:RW:0:10:=0x0013 + 0x000000BB, // 61: TREF_F0:RW:0:20:=0x0000bb + 0x00000260, // 62: TRFC_F1:RW:0:10:=0x0260 + 0x00001858, // 63: TREF_F1:RW:0:20:=0x001858 + 0x0000032B, // 64: TRFC_F2:RW:0:10:=0x032b + 0x00002073, // 65: TREF_F2:RW:0:20:=0x002073 + 0x00000005, // 66: TREF_INTERVAL:RW:0:20:=0x000005 + 0x00050000, // 67: TRFC_PB_F0:RW:16:10:=0x0005 PBR_NUMERIC_ORDER:RW:8:1:=0x00 PBR_EN:RW:0:1:=0x00 + 0x00980010, // 68: TRFC_PB_F1:RW:16:10:=0x0098 TREFI_PB_F0:RW:0:16:=0x0010 + 0x00CB0304, // 69: TRFC_PB_F2:RW:16:10:=0x00cb TREFI_PB_F1:RW:0:16:=0x0304 + 0x00400408, // 70: PBR_MAX_BANK_WAIT:RW:16:16:=0x0040 TREFI_PB_F2:RW:0:16:=0x0408 + 0x00120103, // 71: AREF_PBR_CONT_DIS_THRESHOLD:RW:24:5:=0x00 AREF_PBR_CONT_EN_THRESHOLD:RW:16:5:=0x12 PBR_CONT_REQ_EN:RW:8:1:=0x01 PBR_BANK_SELECT_DELAY:RW:0:4:=0x03 + 0x000C0005, // 72: TPDEX_F1:RW:16:16:=0x000c TPDEX_F0:RW:0:16:=0x0005 + 0x21080010, // 73: TMRRI_F1:RW:24:8:=0x21 TMRRI_F0:RW:16:8:=0x08 TPDEX_F2:RW:0:16:=0x0010 + 0x0505012B, // 74: TCKEHCS_F0:RW:24:5:=0x05 TCKELCS_F0:RW:16:5:=0x05 TCSCKE_F0:RW:8:5:=0x01 TMRRI_F2:RW:0:8:=0x2b + 0x0301030A, // 75: TCSCKE_F1:RW:24:5:=0x03 CA_DEFAULT_VAL_F0:RW:16:1:=0x01 TZQCKE_F0:RW:8:4:=0x03 TMRWCKEL_F0:RW:0:5:=0x0a + 0x03170C08, // 76: TZQCKE_F1:RW:24:4:=0x03 TMRWCKEL_F1:RW:16:5:=0x17 TCKEHCS_F1:RW:8:5:=0x0c TCKELCS_F1:RW:0:5:=0x08 + 0x100B0401, // 77: TCKEHCS_F2:RW:24:5:=0x10 TCKELCS_F2:RW:16:5:=0x0b TCSCKE_F2:RW:8:5:=0x04 CA_DEFAULT_VAL_F1:RW:0:1:=0x01 + 0x0001041E, // 78: CA_DEFAULT_VAL_F2:RW:16:1:=0x01 TZQCKE_F2:RW:8:4:=0x04 TMRWCKEL_F2:RW:0:5:=0x1e + 0x00140014, // 79: TXSNR_F0:RW:16:16:=0x0014 TXSR_F0:RW:0:16:=0x0014 + 0x026C026C, // 80: TXSNR_F1:RW:16:16:=0x026c TXSR_F1:RW:0:16:=0x026c + 0x033B033B, // 81: TXSNR_F2:RW:16:16:=0x033b TXSR_F2:RW:0:16:=0x033b + 0x03050505, // 82: TSR_F0:RW:24:8:=0x03 TCKCKEL_F0:RW:16:5:=0x05 TCKEHCMD_F0:RW:8:5:=0x05 TCKELCMD_F0:RW:0:5:=0x05 + 0x03010303, // 83: TCMDCKE_F0:RW:24:5:=0x03 TCSCKEH_F0:RW:16:5:=0x01 TCKELPD_F0:RW:8:5:=0x03 TESCKE_F0:RW:0:3:=0x03 + 0x18080C08, // 84: TSR_F1:RW:24:8:=0x18 TCKCKEL_F1:RW:16:5:=0x08 TCKEHCMD_F1:RW:8:5:=0x0c TCKELCMD_F1:RW:0:5:=0x08 + 0x03030C03, // 85: TCMDCKE_F1:RW:24:5:=0x03 TCSCKEH_F1:RW:16:5:=0x03 TCKELPD_F1:RW:8:5:=0x0c TESCKE_F1:RW:0:3:=0x03 + 0x200B100B, // 86: TSR_F2:RW:24:8:=0x20 TCKCKEL_F2:RW:16:5:=0x0b TCKEHCMD_F2:RW:8:5:=0x10 TCKELCMD_F2:RW:0:5:=0x0b + 0x04041004, // 87: TCMDCKE_F2:RW:24:5:=0x04 TCSCKEH_F2:RW:16:5:=0x04 TCKELPD_F2:RW:8:5:=0x10 TESCKE_F2:RW:0:3:=0x04 + 0x03010000, // 88: CKE_DELAY:RW:24:3:=0x03 ENABLE_QUICK_SREFRESH:RW:16:1:=0x01 RESERVED:RW:8:1:=0x00 PWRUP_SREFRESH_EXIT:RW:0:1:=0x00 + 0x00010000, // 89: DFS_ZQ_EN:RW:16:1:=0x01 DFS_STATUS:RD:8:2:=0x00 RESERVED:WR:0:5:=0x00 + 0x00000000, // 90: DFS_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 DFS_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000 + 0x01000000, // 91: RESERVED:RW:24:3:=0x01 ZQ_STATUS_LOG:RD:16:3:=0x00 DFS_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000 + 0x80104002, // 92: RESERVED:RW:24:8:=0x80 RESERVED:RW:16:8:=0x10 RESERVED:RW:8:8:=0x40 RESERVED:RW:0:3:=0x02 + 0x00000000, // 93: UPD_CTRLUPD_HIGH_THRESHOLD_F0:RW:16:16:=0x0000 UPD_CTRLUPD_NORM_THRESHOLD_F0:RW:0:16:=0x0000 + 0x00040005, // 94: UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0004 UPD_CTRLUPD_TIMEOUT_F0:RW:0:16:=0x0005 + 0x00000000, // 95: UPD_CTRLUPD_NORM_THRESHOLD_F1:RW:16:16:=0x0000 UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000 + 0x00050000, // 96: UPD_CTRLUPD_TIMEOUT_F1:RW:16:16:=0x0005 UPD_CTRLUPD_HIGH_THRESHOLD_F1:RW:0:16:=0x0000 + 0x00000004, // 97: UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0004 + 0x00000000, // 98: UPD_CTRLUPD_HIGH_THRESHOLD_F2:RW:16:16:=0x0000 UPD_CTRLUPD_NORM_THRESHOLD_F2:RW:0:16:=0x0000 + 0x00040005, // 99: UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0004 UPD_CTRLUPD_TIMEOUT_F2:RW:0:16:=0x0005 + 0x00000000, // 100: UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000 + 0x00002EC0, // 101: TDFI_PHYMSTR_MAX_F0:RW:0:32:=0x00002ec0 + 0x00002EC0, // 102: TDFI_PHYMSTR_MAX_TYPE0_F0:RW:0:32:=0x00002ec0 + 0x00002EC0, // 103: TDFI_PHYMSTR_MAX_TYPE1_F0:RW:0:32:=0x00002ec0 + 0x00002EC0, // 104: TDFI_PHYMSTR_MAX_TYPE2_F0:RW:0:32:=0x00002ec0 + 0x00002EC0, // 105: TDFI_PHYMSTR_MAX_TYPE3_F0:RW:0:32:=0x00002ec0 + 0x00000000, // 106: PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000 + 0x0000051D, // 107: TDFI_PHYMSTR_RESP_F0:RW:0:20:=0x00051d + 0x00061600, // 108: TDFI_PHYMSTR_MAX_F1:RW:0:32:=0x00061600 + 0x00061600, // 109: TDFI_PHYMSTR_MAX_TYPE0_F1:RW:0:32:=0x00061600 + 0x00061600, // 110: TDFI_PHYMSTR_MAX_TYPE1_F1:RW:0:32:=0x00061600 + 0x00061600, // 111: TDFI_PHYMSTR_MAX_TYPE2_F1:RW:0:32:=0x00061600 + 0x00061600, // 112: TDFI_PHYMSTR_MAX_TYPE3_F1:RW:0:32:=0x00061600 + 0x00000000, // 113: PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000 + 0x0000AA68, // 114: TDFI_PHYMSTR_RESP_F1:RW:0:20:=0x00aa68 + 0x00081CC0, // 115: TDFI_PHYMSTR_MAX_F2:RW:0:32:=0x00081cc0 + 0x00081CC0, // 116: TDFI_PHYMSTR_MAX_TYPE0_F2:RW:0:32:=0x00081cc0 + 0x00081CC0, // 117: TDFI_PHYMSTR_MAX_TYPE1_F2:RW:0:32:=0x00081cc0 + 0x00081CC0, // 118: TDFI_PHYMSTR_MAX_TYPE2_F2:RW:0:32:=0x00081cc0 + 0x00081CC0, // 119: TDFI_PHYMSTR_MAX_TYPE3_F2:RW:0:32:=0x00081cc0 + 0x00000000, // 120: PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000 + 0x0000E325, // 121: PHYMSTR_NO_AREF:RW:24:1:=0x00 TDFI_PHYMSTR_RESP_F2:RW:0:20:=0x00e325 + 0x00000000, // 122: PHYMSTR_TRAIN_AFTER_INIT_COMPLETE:RW:16:1:=0x00 PHYMSTR_DFI_VERSION_4P0V1:RW:8:1:=0x00 PHYMSTR_ERROR_STATUS:RD:0:2:=0x00 + 0x00000000, // 123: MRR_TEMPCHK_HIGH_THRESHOLD_F0:RW:16:16:=0x0000 MRR_TEMPCHK_NORM_THRESHOLD_F0:RW:0:16:=0x0000 + 0x00000000, // 124: MRR_TEMPCHK_NORM_THRESHOLD_F1:RW:16:16:=0x0000 MRR_TEMPCHK_TIMEOUT_F0:RW:0:16:=0x0000 + 0x00000000, // 125: MRR_TEMPCHK_TIMEOUT_F1:RW:16:16:=0x0000 MRR_TEMPCHK_HIGH_THRESHOLD_F1:RW:0:16:=0x0000 + 0x00000000, // 126: MRR_TEMPCHK_HIGH_THRESHOLD_F2:RW:16:16:=0x0000 MRR_TEMPCHK_NORM_THRESHOLD_F2:RW:0:16:=0x0000 + 0x00000000, // 127: PPR_COMMAND:WR:24:3:=0x00 PPR_CONTROL:RW:16:1:=0x00 MRR_TEMPCHK_TIMEOUT_F2:RW:0:16:=0x0000 + 0x00000000, // 128: PPR_ROW_ADDRESS:RW:8:17:=0x000000 PPR_COMMAND_MRW:RW:0:8:=0x00 + 0x00000000, // 129: FM_OVRIDE_CONTROL:RW:24:1:=0x00 PPR_STATUS:RD:16:2:=0x00 PPR_CS_ADDRESS:RW:8:1:=0x00 PPR_BANK_ADDRESS:RW:0:3:=0x00 + 0x08030500, // 130: CKSRE_F1:RW:24:8:=0x08 CKSRX_F0:RW:16:8:=0x03 CKSRE_F0:RW:8:8:=0x05 LOWPOWER_REFRESH_ENABLE:RW:0:2:=0x00 + 0x00040B03, // 131: LP_CMD:WR:24:7:=0x00 CKSRX_F2:RW:16:8:=0x04 CKSRE_F2:RW:8:8:=0x0b CKSRX_F1:RW:0:8:=0x03 + 0x0A090000, // 132: LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0:RW:24:4:=0x0a LPI_SR_LONG_WAKEUP_F0:RW:16:4:=0x09 LPI_SR_SHORT_WAKEUP_F0:RW:8:4:=0x00 LPI_CTRL_IDLE_WAKEUP_F0:RW:0:4:=0x00 + 0x0A090701, // 133: LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0:RW:24:4:=0x0a LPI_SRPD_LONG_WAKEUP_F0:RW:16:4:=0x09 LPI_SRPD_SHORT_WAKEUP_F0:RW:8:4:=0x07 LPI_PD_WAKEUP_F0:RW:0:4:=0x01 + 0x0900000E, // 134: LPI_SR_LONG_WAKEUP_F1:RW:24:4:=0x09 LPI_SR_SHORT_WAKEUP_F1:RW:16:4:=0x00 LPI_CTRL_IDLE_WAKEUP_F1:RW:8:4:=0x00 LPI_TIMER_WAKEUP_F0:RW:0:4:=0x0e + 0x0907010A, // 135: LPI_SRPD_LONG_WAKEUP_F1:RW:24:4:=0x09 LPI_SRPD_SHORT_WAKEUP_F1:RW:16:4:=0x07 LPI_PD_WAKEUP_F1:RW:8:4:=0x01 LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1:RW:0:4:=0x0a + 0x00000E0A, // 136: LPI_SR_SHORT_WAKEUP_F2:RW:24:4:=0x00 LPI_CTRL_IDLE_WAKEUP_F2:RW:16:4:=0x00 LPI_TIMER_WAKEUP_F1:RW:8:4:=0x0e LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1:RW:0:4:=0x0a + 0x07010A09, // 137: LPI_SRPD_SHORT_WAKEUP_F2:RW:24:4:=0x07 LPI_PD_WAKEUP_F2:RW:16:4:=0x01 LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2:RW:8:4:=0x0a LPI_SR_LONG_WAKEUP_F2:RW:0:4:=0x09 + 0x000E0A09, // 138: LPI_WAKEUP_EN:RW:24:6:=0x2f LPI_TIMER_WAKEUP_F2:RW:16:4:=0x0e LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2:RW:8:4:=0x0a LPI_SRPD_LONG_WAKEUP_F2:RW:0:4:=0x09 + 0x07000401, // 139: TDFI_LP_RESP:RW:24:3:=0x07 LPI_WAKEUP_TIMEOUT:RW:8:12:=0x0004 LPI_CTRL_REQ_EN:RW:0:1:=0x01 + 0x00000000, // 140: LP_AUTO_EXIT_EN:RW:24:4:=0x00 LP_AUTO_ENTRY_EN:RW:16:4:=0x00 LP_STATE_CS1:RD:8:7:=0x00 LP_STATE_CS0:RD:0:7:=0x00 + 0x00000000, // 141: LP_AUTO_PD_IDLE:RW:8:12:=0x0000 LP_AUTO_MEM_GATE_EN:RW:0:3:=0x00 + 0x00000000, // 142: LP_AUTO_SR_LONG_MC_GATE_IDLE:RW:24:8:=0x00 LP_AUTO_SR_LONG_IDLE:RW:16:8:=0x00 LP_AUTO_SR_SHORT_IDLE:RW:0:12:=0x0000 + 0x00000000, // 143: HW_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 HW_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000 + 0x00000000, // 144: LPC_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0000 HW_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000 + 0x00000000, // 145: LPC_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 LPC_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000 + 0x00000000, // 146: RESERVED:RW:24:1:=0x00 LPC_SR_PHYMSTR_EN:RW:16:1:=0x00 LPC_SR_PHYUPD_EN:RW:8:1:=0x00 LPC_SR_CTRLUPD_EN:RW:0:1:=0x00 + 0x08080100, // 147: PCPCS_PD_EXIT_DEPTH:RW:24:6:=0x08 PCPCS_PD_ENTER_DEPTH:RW:16:6:=0x08 PCPCS_PD_EN:RW:8:1:=0x01 LPC_SR_ZQ_EN:RW:0:1:=0x00 + 0x01000000, // 148: DFS_ENABLE:RW:24:1:=0x01 RESERVED:RW:16:8:=0x00 PCPCS_PD_MASK:RW:8:2:=0x00 PCPCS_PD_ENTER_TIMER:RW:0:8:=0x00 + 0x800000C0, // 149: TDFI_INIT_COMPLETE_F0:RW_D:16:16:=0x8000 TDFI_INIT_START_F0:RW_D:0:10:=0x00c0 + 0x800000C0, // 150: TDFI_INIT_COMPLETE_F1:RW_D:16:16:=0x8000 TDFI_INIT_START_F1:RW_D:0:10:=0x00c0 + 0x800000C0, // 151: TDFI_INIT_COMPLETE_F2:RW_D:16:16:=0x8000 TDFI_INIT_START_F2:RW_D:0:10:=0x00c0 + 0x00000000, // 152: DFS_PHY_REG_WRITE_EN:RW:8:1:=0x00 CURRENT_REG_COPY:RD:0:2:=0x00 + 0x00001500, // 153: DFS_PHY_REG_WRITE_ADDR:RW:0:32:=0x00001500 + 0x00000000, // 154: DFS_PHY_REG_WRITE_DATA_F0:RW:0:32:=0x00000000 + 0x00000001, // 155: DFS_PHY_REG_WRITE_DATA_F1:RW:0:32:=0x00000001 + 0x00000002, // 156: DFS_PHY_REG_WRITE_DATA_F2:RW:0:32:=0x00000002 + 0x0000100E, // 157: DFS_PHY_REG_WRITE_WAIT:RW:8:16:=0x0010 DFS_PHY_REG_WRITE_MASK:RW:0:4:=0x0e + 0x00000000, // 158: WRITE_MODEREG:RW+:0:27:=0x00000000 + 0x00000000, // 159: READ_MODEREG:RW+:8:17:=0x000000 MRW_STATUS:RD:0:8:=0x00 + 0x00000000, // 160: PERIPHERAL_MRR_DATA:RD:0:40:=0x00000000 + 0x00000000, // 161: AUTO_TEMPCHK_VAL_0:RD:8:16:=0x0000 PERIPHERAL_MRR_DATA:RD:0:40:=0x00 + 0x00000000, // 162: DISABLE_UPDATE_TVRCG:RW:16:1:=0x00 AUTO_TEMPCHK_VAL_1:RD:0:16:=0x0000 + 0x000A0000, // 163: TVRCG_ENABLE_F0:RW:16:10:=0x000a MRW_DFS_UPDATE_FRC:RW:0:2:=0x00 + 0x000D0005, // 164: TFC_F0:RW:16:10:=0x000d TVRCG_DISABLE_F0:RW:0:10:=0x0005 + 0x000D0404, // 165: TVREF_LONG_F0:RW:16:16:=0x000d TCKFSPX_F0:RW:8:5:=0x04 TCKFSPE_F0:RW:0:5:=0x04 + 0x00A00140, // 166: TVRCG_DISABLE_F1:RW:16:10:=0x00a0 TVRCG_ENABLE_F1:RW:0:10:=0x0140 + 0x0C0C0190, // 167: TCKFSPX_F1:RW:24:5:=0x0c TCKFSPE_F1:RW:16:5:=0x0c TFC_F1:RW:0:10:=0x0190 + 0x01AB0190, // 168: TVRCG_ENABLE_F2:RW:16:10:=0x01ab TVREF_LONG_F1:RW:0:16:=0x0190 + 0x021600D6, // 169: TFC_F2:RW:16:10:=0x0216 TVRCG_DISABLE_F2:RW:0:10:=0x00d6 + 0x02161010, // 170: TVREF_LONG_F2:RW:16:16:=0x0216 TCKFSPX_F2:RW:8:5:=0x10 TCKFSPE_F2:RW:0:5:=0x10 + 0x00000000, // 171: MRR_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 MRR_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000 + 0x00000000, // 172: MRW_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0000 MRR_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000 + 0x00000000, // 173: MRW_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 MRW_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000 + 0x2D540004, // 174: MR2_DATA_F1_0:RW:24:8:=0x2d MR1_DATA_F1_0:RW:16:8:=0x54 MR2_DATA_F0_0:RW:8:8:=0x00 MR1_DATA_F0_0:RW:0:8:=0x04 + 0x29003F74, // 175: MR3_DATA_F0_0:RW:24:8:=0x31 MRSINGLE_DATA_0:RW:16:8:=0x00 MR2_DATA_F2_0:RW:8:8:=0x3f MR1_DATA_F2_0:RW:0:8:=0x74 + 0x00002929, // 176: MR4_DATA_F1_0:RW:24:8:=0x00 MR4_DATA_F0_0:RW:16:8:=0x00 MR3_DATA_F2_0:RW:8:8:=0x31 MR3_DATA_F1_0:RW:0:8:=0x31 + 0x00040000, // 177: MR11_DATA_F1_0:RW:24:8:=0x00 MR11_DATA_F0_0:RW:16:8:=0x00 MR8_DATA_0:RD:8:8:=0x00 MR4_DATA_F2_0:RW:0:8:=0x00 + 0x17171700, // 178: MR12_DATA_F2_0:RW:24:8:=0x00 MR12_DATA_F1_0:RW:16:8:=0x00 MR12_DATA_F0_0:RW:8:8:=0x00 MR11_DATA_F2_0:RW:0:8:=0x00 + 0x4D4D0F00, // 179: MR14_DATA_F2_0:RW:24:8:=0x00 MR14_DATA_F1_0:RW:16:8:=0x00 MR14_DATA_F0_0:RW:8:8:=0x00 MR13_DATA_0:RW:0:8:=0x00 + 0x05000000, // 180: MR22_DATA_F0_0:RW:24:8:=0x00 MR20_DATA_0:RD:16:8:=0x00 MR17_DATA_0:RW:8:8:=0x00 MR16_DATA_0:RW:0:8:=0x00 + 0x00040505, // 181: MR2_DATA_F0_1:RW:24:8:=0x00 MR1_DATA_F0_1:RW:16:8:=0x04 MR22_DATA_F2_0:RW:8:8:=0x00 MR22_DATA_F1_0:RW:0:8:=0x00 + 0x3F742D54, // 182: MR2_DATA_F2_1:RW:24:8:=0x3f MR1_DATA_F2_1:RW:16:8:=0x74 MR2_DATA_F1_1:RW:8:8:=0x2d MR1_DATA_F1_1:RW:0:8:=0x54 + 0x29292900, // 183: MR3_DATA_F2_1:RW:24:8:=0x31 MR3_DATA_F1_1:RW:16:8:=0x31 MR3_DATA_F0_1:RW:8:8:=0x31 MRSINGLE_DATA_1:RW:0:8:=0x00 + 0x00000000, // 184: MR8_DATA_1:RD:24:8:=0x00 MR4_DATA_F2_1:RW:16:8:=0x00 MR4_DATA_F1_1:RW:8:8:=0x00 MR4_DATA_F0_1:RW:0:8:=0x00 + 0x17000004, // 185: MR12_DATA_F0_1:RW:24:8:=0x00 MR11_DATA_F2_1:RW:16:8:=0x00 MR11_DATA_F1_1:RW:8:8:=0x00 MR11_DATA_F0_1:RW:0:8:=0x00 + 0x0F001717, // 186: MR14_DATA_F0_1:RW:24:8:=0x00 MR13_DATA_1:RW:16:8:=0x00 MR12_DATA_F2_1:RW:8:8:=0x00 MR12_DATA_F1_1:RW:0:8:=0x00 + 0x00004D4D, // 187: MR17_DATA_1:RW:24:8:=0x00 MR16_DATA_1:RW:16:8:=0x00 MR14_DATA_F2_1:RW:8:8:=0x00 MR14_DATA_F1_1:RW:0:8:=0x00 + 0x05050500, // 188: MR22_DATA_F2_1:RW:24:8:=0x00 MR22_DATA_F1_1:RW:16:8:=0x00 MR22_DATA_F0_1:RW:8:8:=0x00 MR20_DATA_1:RD:0:8:=0x00 + 0x00000020, // 189: MR_FSP_DATA_VALID_F2:RW:24:1:=0x00 MR_FSP_DATA_VALID_F1:RW:16:1:=0x00 MR_FSP_DATA_VALID_F0:RW:8:1:=0x00 MR23_DATA:RW:0:8:=0x20 + 0x00000000, // 190: FSP_PHY_UPDATE_MRW:RW:24:1:=0x00 RESERVED:RD:16:1:=0x00 RESERVED:RD:8:1:=0x00 RL3_SUPPORT_EN:RD:0:2:=0x00 + 0x00000001, // 191: FSP_WR_CURRENT:RW+:24:1:=0x00 FSP_OP_CURRENT:RW+:16:1:=0x00 FSP_STATUS:RW:8:1:=0x00 DFS_ALWAYS_WRITE_FSP:RW:0:1:=0x01 + 0x00000000, // 192: FSP1_FRC:RW+:24:2:=0x00 FSP0_FRC:RW+:16:2:=0x00 FSP1_FRC_VALID:RW+:8:1:=0x00 FSP0_FRC_VALID:RW+:0:1:=0x00 + 0x01000000, // 193: BIST_DATA_CHECK:RW:24:1:=0x01 ADDR_SPACE:RW:16:6:=0x00 BIST_RESULT:RD:8:2:=0x00 BIST_GO:WR:0:1:=0x00 + 0x00000001, // 194: BIST_ADDR_CHECK:RW:0:1:=0x01 + 0x00000000, // 195: BIST_START_ADDRESS:RW:0:35:=0x00000000 + 0x00000000, // 196: BIST_START_ADDRESS:RW:0:35:=0x00 + 0x00000000, // 197: BIST_DATA_MASK:RW:0:64:=0x00000000 + 0x00000000, // 198: BIST_DATA_MASK:RW:0:64:=0x00000000 + 0x00000000, // 199: BIST_TEST_MODE:RW:0:3:=0x00 + 0x00000000, // 200: BIST_DATA_PATTERN:RW:0:128:=0x00000000 + 0x00000000, // 201: BIST_DATA_PATTERN:RW:0:128:=0x00000000 + 0x00000000, // 202: BIST_DATA_PATTERN:RW:0:128:=0x00000000 + 0x00000000, // 203: BIST_DATA_PATTERN:RW:0:128:=0x00000000 + 0x00000000, // 204: BIST_ERR_STOP:RW:16:12:=0x0000 BIST_RET_STATE:RD:8:1:=0x00 BIST_RET_STATE_EXIT:WR:0:1:=0x00 + 0x02000000, // 205: INLINE_ECC_BANK_OFFSET:RW:24:3:=0x02 ECC_ENABLE:RW:16:2:=0x00 BIST_ERR_COUNT:RD:0:12:=0x0000 + 0x01080101, // 206: RESERVED:RW:24:1:=0x01 RESERVED:RW:16:4:=0x08 ECC_WRITE_COMBINING_EN:RW:8:1:=0x01 ECC_READ_CACHING_EN:RW:0:1:=0x01 + 0x00000000, // 207: ECC_WRITEBACK_EN:RW:24:1:=0x00 XOR_CHECK_BITS:RW:8:16:=0x0000 FWC:RW+:0:1:=0x00 + 0x00000000, // 208: ECC_DISABLE_W_UC_ERR:RW:0:1:=0x00 + 0x00000000, // 209: ECC_U_ADDR:RD:0:35:=0x00000000 + 0x00000000, // 210: ECC_U_SYND:RD:8:8:=0x00 ECC_U_ADDR:RD:0:35:=0x00 + 0x00000000, // 211: ECC_U_DATA:RD:0:64:=0x00000000 + 0x00000000, // 212: ECC_U_DATA:RD:0:64:=0x00000000 + 0x00000000, // 213: ECC_C_ADDR:RD:0:35:=0x00000000 + 0x00000000, // 214: ECC_C_SYND:RD:8:8:=0x00 ECC_C_ADDR:RD:0:35:=0x00 + 0x00000000, // 215: ECC_C_DATA:RD:0:64:=0x00000000 + 0x00000000, // 216: ECC_C_DATA:RD:0:64:=0x00000000 + 0x00000000, // 217: NON_ECC_REGION_START_ADDR_0:RW:16:15:=0x0000 ECC_C_ID:RD:8:7:=0x00 ECC_U_ID:RD:0:7:=0x00 + 0x00000000, // 218: NON_ECC_REGION_START_ADDR_1:RW:16:15:=0x0000 NON_ECC_REGION_END_ADDR_0:RW:0:15:=0x0000 + 0x00000000, // 219: NON_ECC_REGION_START_ADDR_2:RW:16:15:=0x0000 NON_ECC_REGION_END_ADDR_1:RW:0:15:=0x0000 + 0x00000000, // 220: ECC_SCRUB_START:WR:24:1:=0x00 NON_ECC_REGION_ENABLE:RW:16:3:=0x00 NON_ECC_REGION_END_ADDR_2:RW:0:15:=0x0000 + 0x00001000, // 221: ECC_SCRUB_MODE:RW:24:1:=0x00 ECC_SCRUB_LEN:RW:8:13:=0x0010 ECC_SCRUB_IN_PROGRESS:RD:0:1:=0x00 + 0x006403E8, // 222: ECC_SCRUB_IDLE_CNT:RW:16:16:=0x0064 ECC_SCRUB_INTERVAL:RW:0:16:=0x03e8 + 0x00000000, // 223: ECC_SCRUB_START_ADDR:RW:0:35:=0x00000000 + 0x00000000, // 224: ECC_SCRUB_START_ADDR:RW:0:35:=0x00 + 0x00000000, // 225: ECC_SCRUB_END_ADDR:RW:0:35:=0x00000000 + 0x15110000, // 226: AREF_HIGH_THRESHOLD:RW:24:5:=0x15 AREF_NORM_THRESHOLD:RW:16:5:=0x11 LONG_COUNT_MASK:RW:8:5:=0x00 ECC_SCRUB_END_ADDR:RW:0:35:=0x00 + 0x00040C18, // 227: AREF_CMD_MAX_PER_TREFI:RW:16:4:=0x04 AREF_MAX_CREDIT:RW:8:5:=0x0c AREF_MAX_DEFICIT:RW:0:5:=0x18 + 0x00000000, // 228: ZQ_CALSTART_HIGH_THRESHOLD_F0:RW:16:16:=0x0000 ZQ_CALSTART_NORM_THRESHOLD_F0:RW:0:16:=0x0000 + 0x00000000, // 229: ZQ_CS_NORM_THRESHOLD_F0:RW:16:16:=0x0000 ZQ_CALLATCH_HIGH_THRESHOLD_F0:RW:0:16:=0x0000 + 0x00000000, // 230: ZQ_CALSTART_TIMEOUT_F0:RW:16:16:=0x0000 ZQ_CS_HIGH_THRESHOLD_F0:RW:0:16:=0x0000 + 0x00000000, // 231: ZQ_CS_TIMEOUT_F0:RW:16:16:=0x0000 ZQ_CALLATCH_TIMEOUT_F0:RW:0:16:=0x0000 + 0x00000000, // 232: ZQ_CALSTART_NORM_THRESHOLD_F1:RW:16:16:=0x0000 ZQ_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000 + 0x00000000, // 233: ZQ_CALLATCH_HIGH_THRESHOLD_F1:RW:16:16:=0x0000 ZQ_CALSTART_HIGH_THRESHOLD_F1:RW:0:16:=0x0000 + 0x00000000, // 234: ZQ_CS_HIGH_THRESHOLD_F1:RW:16:16:=0x0000 ZQ_CS_NORM_THRESHOLD_F1:RW:0:16:=0x0000 + 0x00000000, // 235: ZQ_CALLATCH_TIMEOUT_F1:RW:16:16:=0x0000 ZQ_CALSTART_TIMEOUT_F1:RW:0:16:=0x0000 + 0x00000000, // 236: ZQ_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 ZQ_CS_TIMEOUT_F1:RW:0:16:=0x0000 + 0x00000000, // 237: ZQ_CALSTART_HIGH_THRESHOLD_F2:RW:16:16:=0x0000 ZQ_CALSTART_NORM_THRESHOLD_F2:RW:0:16:=0x0000 + 0x00000000, // 238: ZQ_CS_NORM_THRESHOLD_F2:RW:16:16:=0x0000 ZQ_CALLATCH_HIGH_THRESHOLD_F2:RW:0:16:=0x0000 + 0x00000000, // 239: ZQ_CALSTART_TIMEOUT_F2:RW:16:16:=0x0000 ZQ_CS_HIGH_THRESHOLD_F2:RW:0:16:=0x0000 + 0x00000000, // 240: ZQ_CS_TIMEOUT_F2:RW:16:16:=0x0000 ZQ_CALLATCH_TIMEOUT_F2:RW:0:16:=0x0000 + 0x00030000, // 241: RESERVED:RW:16:3:=0x03 ZQ_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000 + 0x00000000, // 242: WATCHDOG_THRESHOLD_BUS_ARB_F0:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_TASK_ARB_F0:RW:0:16:=0x0000 + 0x00000000, // 243: WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_PORT_ARB_F0:RW:0:16:=0x0000 + 0x00000000, // 244: WATCHDOG_THRESHOLD_SPLIT_F0:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_PORT1_CMD_ARB_F0:RW:0:16:=0x0000 + 0x00000000, // 245: WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_STRATEGY_F0:RW:0:16:=0x0000 + 0x00000000, // 246: WATCHDOG_THRESHOLD_READ_DATA_FIFO1_F0:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0:RW:0:16:=0x0000 + 0x00000000, // 247: WATCHDOG_THRESHOLD_TASK_ARB_F1:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0:RW:0:16:=0x0000 + 0x00000000, // 248: WATCHDOG_THRESHOLD_PORT_ARB_F1:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_BUS_ARB_F1:RW:0:16:=0x0000 + 0x00000000, // 249: WATCHDOG_THRESHOLD_PORT1_CMD_ARB_F1:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1:RW:0:16:=0x0000 + 0x00000000, // 250: WATCHDOG_THRESHOLD_STRATEGY_F1:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_SPLIT_F1:RW:0:16:=0x0000 + 0x00000000, // 251: WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1:RW:0:16:=0x0000 + 0x00000000, // 252: WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_READ_DATA_FIFO1_F1:RW:0:16:=0x0000 + 0x00000000, // 253: WATCHDOG_THRESHOLD_BUS_ARB_F2:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_TASK_ARB_F2:RW:0:16:=0x0000 + 0x00000000, // 254: WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_PORT_ARB_F2:RW:0:16:=0x0000 + 0x00000000, // 255: WATCHDOG_THRESHOLD_SPLIT_F2:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_PORT1_CMD_ARB_F2:RW:0:16:=0x0000 + 0x00000000, // 256: WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_STRATEGY_F2:RW:0:16:=0x0000 + 0x00000000, // 257: WATCHDOG_THRESHOLD_READ_DATA_FIFO1_F2:RW:16:16:=0x0000 WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2:RW:0:16:=0x0000 + 0x00000000, // 258: WATCHDOG_RELOAD:WR:16:11:=0x0000 WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2:RW:0:16:=0x0000 + 0x00000000, // 259: WATCHDOG_DIAGNOSTIC_MODE:RW:0:11:=0x0000 + 0x00000000, // 260: TIMEOUT_TIMER_LOG:RD:0:19:=0x000000 + 0x01000200, // 261: ZQCL_F0:RW:16:12:=0x0100 ZQINIT_F0:RW_D:0:12:=0x0200 + 0x00320040, // 262: TZQCAL_F0:RW:16:12:=0x0032 ZQCS_F0:RW:0:12:=0x0040 + 0x00020002, // 263: ZQINIT_F1:RW_D:8:12:=0x0200 TZQLAT_F0:RW:0:7:=0x02 + 0x00400100, // 264: ZQCS_F1:RW:16:12:=0x0040 ZQCL_F1:RW:0:12:=0x0100 + 0x00300640, // 265: TZQLAT_F1:RW:16:7:=0x30 TZQCAL_F1:RW:0:12:=0x0640 + 0x01000200, // 266: ZQCL_F2:RW:16:12:=0x0100 ZQINIT_F2:RW_D:0:12:=0x0200 + 0x08550040, // 267: TZQCAL_F2:RW:16:12:=0x0855 ZQCS_F2:RW:0:12:=0x0040 + 0x00000040, // 268: ZQ_REQ_PENDING:RD:24:1:=0x00 ZQ_REQ:WR:16:4:=0x00 ZQ_SW_REQ_START_LATCH_MAP:RW:8:2:=0x00 TZQLAT_F2:RW:0:7:=0x40 + 0x00500003, // 269: ZQRESET_F1:RW:16:12:=0x0050 ZQRESET_F0:RW:0:12:=0x0003 + 0x0100006B, // 270: ZQCS_ROTATE:RW:24:1:=0x01 NO_ZQ_INIT:RW:16:1:=0x00 ZQRESET_F2:RW:0:12:=0x006b + 0x00000000, // 271: ZQ_CAL_LATCH_MAP_1:RW_D:24:2:=0x00 ZQ_CAL_START_MAP_1:RW_D:16:2:=0x00 ZQ_CAL_LATCH_MAP_0:RW_D:8:2:=0x00 ZQ_CAL_START_MAP_0:RW_D:0:2:=0x00 + 0x01010000, // 272: ROW_DIFF_1:RW:24:3:=0x00 ROW_DIFF_0:RW:16:3:=0x00 BANK_DIFF_1:RW:8:2:=0x00 BANK_DIFF_0:RW:0:2:=0x00 + 0x00000202, // 273: CS_VAL_LOWER_0:RW:16:16:=0x0000 COL_DIFF_1:RW:8:4:=0x02 COL_DIFF_0:RW:0:4:=0x02 + 0x00000FFF, // 274: ROW_START_VAL_0:RW:16:3:=0x00 CS_VAL_UPPER_0:RW:0:16:=0x0fff + 0x1FFF1000, // 275: CS_VAL_UPPER_1:RW:16:16:=0x3fff CS_VAL_LOWER_1:RW:0:16:=0x2000 + 0x01FF0000, // 276: CS_MSK_0:RW:16:16:=0x03ff CS_MAP_NON_POW2:RW:8:2:=0x00 ROW_START_VAL_1:RW:0:3:=0x00 + 0x000001FF, // 277: RESERVED:RW:24:5:=0x00 CS_LOWER_ADDR_EN:RW:16:1:=0x00 CS_MSK_1:RW:0:16:=0x03ff + 0xFFFF0B00, // 278: COMMAND_AGE_COUNT:RW:24:8:=0xff AGE_COUNT:RW:16:8:=0xff APREBIT:RW_D:8:5:=0x0b RESERVED:RW:0:1:=0x00 + 0x01010001, // 279: PLACEMENT_EN:RW:24:1:=0x01 BANK_SPLIT_EN:RW:16:1:=0x01 ADDR_COLLISION_MPM_DIS:RW:8:1:=0x00 ADDR_CMP_EN:RW:0:1:=0x01 + 0x01010101, // 280: CS_SAME_EN:RW:24:1:=0x01 RW_SAME_PAGE_EN:RW:16:1:=0x01 RW_SAME_EN:RW:8:1:=0x01 PRIORITY_EN:RW:0:1:=0x01 + 0x01180101, // 281: SWAP_EN:RW:24:1:=0x01 NUM_Q_ENTRIES_ACT_DISABLE:RW:16:5:=0x18 DISABLE_RW_GROUP_W_BNK_CONFLICT:RW:8:2:=0x01 W2R_SPLIT_EN:RW:0:1:=0x01 + 0x00030000, // 282: REDUC:RW:24:1:=0x00 CS_MAP:RW:16:2:=0x03 INHIBIT_DRAM_CMD:RW:8:2:=0x00 DISABLE_RD_INTERLEAVE:RW:0:1:=0x00 + 0x00000000, // 283: + 0x00000000, // 284: + 0x00000000, // 285: + 0x00000000, // 286: READ_ADDR_CHAN_PARITY_EN:RW:24:1:=0x00 WRITE_RESP_CHAN_PARITY_EN:RW:16:1:=0x00 WRITE_DATA_CHAN_PARITY_EN:RW:8:2:=0x00 WRITE_ADDR_CHAN_PARITY_EN:RW:0:1:=0x00 + 0x00000000, // 287: WRITE_PARITY_ERR_BRESP_EN:RW:24:1:=0x00 RESERVED:RW:16:1:=0x00 RESERVED:RW:8:1:=0x00 READ_DATA_CHAN_PARITY_EN:RW:0:1:=0x00 + 0x00000000, // 288: WRITE_RESP_CHAN_CORRUPT_PARITY_EN:RW:24:1:=0x00 WRITE_DATA_CHAN_TRIGGER_PARITY_EN:RW:16:1:=0x00 WRITE_ADDR_CHAN_TRIGGER_PARITY_EN:RW:8:1:=0x00 READ_PARITY_ERR_RRESP_EN:RW:0:1:=0x00 + 0x00000000, // 289: WRITE_PARITY_ERR_CORRUPT_ECC_EN:RW:24:1:=0x00 ECC_AXI_ERROR_RESPONSE_INHIBIT:RW:16:1:=0x00 READ_DATA_CHAN_CORRUPT_PARITY_EN:RW:8:1:=0x00 READ_ADDR_CHAN_TRIGGER_PARITY_EN:RW:0:1:=0x00 + 0x04010100, // 290: DEVICE1_BYTE0_CS0:RW:24:4:=0x04 DEVICE0_BYTE0_CS0:RW:16:4:=0x01 MEMDATA_RATIO_0:RW:8:3:=0x01 ENHANCED_PARITY_PROTECTION_EN:RW:0:1:=0x00 + 0x01010000, // 291: DEVICE0_BYTE0_CS1:RW:24:4:=0x01 MEMDATA_RATIO_1:RW:16:3:=0x01 DEVICE3_BYTE0_CS0:RW:8:4:=0x00 DEVICE2_BYTE0_CS0:RW:0:4:=0x00 + 0x00000004, // 292: Q_FULLNESS:RW:24:5:=0x00 DEVICE3_BYTE0_CS1:RW:16:4:=0x00 DEVICE2_BYTE0_CS1:RW:8:4:=0x00 DEVICE1_BYTE0_CS1:RW:0:4:=0x04 + 0x00000000, // 293: CTRLUPD_REQ:WR:24:1:=0x00 CONTROLLER_BUSY:RD:16:1:=0x00 WR_ORDER_REQ:RW:8:2:=0x00 IN_ORDER_ACCEPT:RW:0:1:=0x00 + 0x03030000, // 294: PREAMBLE_SUPPORT_F1:RW:24:2:=0x03 PREAMBLE_SUPPORT_F0:RW:16:2:=0x03 CTRLUPD_AREF_HP_ENABLE:RW:8:1:=0x00 CTRLUPD_REQ_PER_AREF_EN:RW:0:1:=0x00 + 0x01010103, // 295: RD_DBI_EN:RW:24:1:=0x00 WR_DBI_EN:RW:16:1:=0x00 RD_PREAMBLE_TRAINING_EN:RW:8:1:=0x01 PREAMBLE_SUPPORT_F2:RW:0:2:=0x03 + 0x00000000, // 296: DFI_ERROR_INFO:RD:8:20:=0x000000 DFI_ERROR:RD:0:5:=0x00 + 0x00000000, // 297: RESERVED:WR:0:1:=0x00 + 0x00000000, // 298: INT_STATUS:RD:0:36:=0x00000000 + 0x00000000, // 299: INT_STATUS:RD:0:36:=0x00 + 0x00000000, // 300: INT_ACK:WR:0:35:=0x00000000 + 0x00000000, // 301: INT_ACK:WR:0:35:=0x00 + 0x00000000, // 302: INT_MASK:RW:0:36:=0x00000000 + 0x00000000, // 303: INT_MASK:RW:0:36:=0x00 + 0x00000000, // 304: OUT_OF_RANGE_ADDR:RD:0:35:=0x00000000 + 0x00000000, // 305: OUT_OF_RANGE_TYPE:RD:24:7:=0x00 OUT_OF_RANGE_LENGTH:RD:8:13:=0x0000 OUT_OF_RANGE_ADDR:RD:0:35:=0x00 + 0x00000000, // 306: OUT_OF_RANGE_SOURCE_ID:RD:0:7:=0x00 + 0x00000000, // 307: BIST_EXP_DATA:RD:0:128:=0x00000000 + 0x00000000, // 308: BIST_EXP_DATA:RD:0:128:=0x00000000 + 0x00000000, // 309: BIST_EXP_DATA:RD:0:128:=0x00000000 + 0x00000000, // 310: BIST_EXP_DATA:RD:0:128:=0x00000000 + 0x00000000, // 311: BIST_FAIL_DATA:RD:0:128:=0x00000000 + 0x00000000, // 312: BIST_FAIL_DATA:RD:0:128:=0x00000000 + 0x00000000, // 313: BIST_FAIL_DATA:RD:0:128:=0x00000000 + 0x00000000, // 314: BIST_FAIL_DATA:RD:0:128:=0x00000000 + 0x00000000, // 315: BIST_FAIL_ADDR:RD:0:35:=0x00000000 + 0x00000000, // 316: BIST_FAIL_ADDR:RD:0:35:=0x00 + 0x00000000, // 317: PORT_CMD_ERROR_ADDR:RD:0:35:=0x00000000 + 0x01000000, // 318: ODT_RD_MAP_CS0:RW:24:2:=0x01 PORT_CMD_ERROR_TYPE:RD:16:2:=0x00 PORT_CMD_ERROR_ID:RD:8:7:=0x00 PORT_CMD_ERROR_ADDR:RD:0:35:=0x00 + 0x00020201, // 319: TODTL_2CMD_F0:RW:24:8:=0x00 ODT_WR_MAP_CS1:RW:16:2:=0x02 ODT_RD_MAP_CS1:RW:8:2:=0x02 ODT_WR_MAP_CS0:RW:0:2:=0x01 + 0x01000101, // 320: TODTH_WR_F1:RW:24:4:=0x01 TODTL_2CMD_F1:RW:16:8:=0x00 TODTH_RD_F0:RW:8:4:=0x01 TODTH_WR_F0:RW:0:4:=0x01 + 0x01010001, // 321: TODTH_RD_F2:RW:24:4:=0x01 TODTH_WR_F2:RW:16:4:=0x01 TODTL_2CMD_F2:RW:8:8:=0x00 TODTH_RD_F1:RW:0:4:=0x01 + 0x00010101, // 322: EN_ODT_ASSERT_EXCEPT_RD:RW:24:1:=0x00 ODT_EN_F2:RW:16:1:=0x01 ODT_EN_F1:RW:8:1:=0x01 ODT_EN_F0:RW:0:1:=0x01 + 0x050A0803, // 323: RD_TO_ODTH_F0:RW:24:6:=0x05 WR_TO_ODTH_F2:RW:16:6:=0x0a WR_TO_ODTH_F1:RW:8:6:=0x08 WR_TO_ODTH_F0:RW:0:6:=0x03 + 0x0C081F18, // 324: RW2MRW_DLY_F1:RW_D:24:5:=0x0c RW2MRW_DLY_F0:RW_D:16:5:=0x08 RD_TO_ODTH_F2:RW:8:6:=0x1f RD_TO_ODTH_F1:RW:0:6:=0x18 + 0x00080210, // 325: W2R_DIFFCS_DLY_F0:RW_D:24:5:=0x00 R2W_DIFFCS_DLY_F0:RW_D:16:5:=0x08 R2R_DIFFCS_DLY_F0:RW_D:8:5:=0x02 RW2MRW_DLY_F2:RW_D:0:5:=0x10 + 0x0A0A020E, // 326: W2R_DIFFCS_DLY_F1:RW_D:24:5:=0x0a R2W_DIFFCS_DLY_F1:RW_D:16:5:=0x0a R2R_DIFFCS_DLY_F1:RW_D:8:5:=0x02 W2W_DIFFCS_DLY_F0:RW_D:0:5:=0x0e + 0x0C0B0206, // 327: W2R_DIFFCS_DLY_F2:RW_D:24:5:=0x0c R2W_DIFFCS_DLY_F2:RW_D:16:5:=0x0b R2R_DIFFCS_DLY_F2:RW_D:8:5:=0x02 W2W_DIFFCS_DLY_F1:RW_D:0:5:=0x06 + 0x0A080007, // 328: R2W_SAMECS_DLY_F1:RW_D:24:5:=0x0a R2W_SAMECS_DLY_F0:RW_D:16:5:=0x08 R2R_SAMECS_DLY:RW:8:5:=0x00 W2W_DIFFCS_DLY_F2:RW_D:0:5:=0x07 + 0x0100000B, // 329: TDQSCK_MAX_F0:RW:24:4:=0x01 W2W_SAMECS_DLY:RW:16:5:=0x00 W2R_SAMECS_DLY:RW:8:5:=0x00 R2W_SAMECS_DLY_F2:RW_D:0:5:=0x0b + 0x08030601, // 330: TDQSCK_MAX_F2:RW:24:4:=0x08 TDQSCK_MIN_F1:RW:16:3:=0x03 TDQSCK_MAX_F1:RW:8:4:=0x06 TDQSCK_MIN_F0:RW:0:3:=0x01 + 0x04000004, // 331: AXI0_R_PRIORITY:RW:24:3:=0x04 AXI0_FIXED_PORT_PRIORITY_ENABLE:RW:16:1:=0x00 AXI0_ALL_STROBES_USED_ENABLE:RW:8:1:=0x00 TDQSCK_MIN_F2:RW:0:3:=0x04 + 0x04000004, // 332: AXI1_R_PRIORITY:RW:24:3:=0x04 AXI1_FIXED_PORT_PRIORITY_ENABLE:RW:16:1:=0x00 AXI1_ALL_STROBES_USED_ENABLE:RW:8:1:=0x00 AXI0_W_PRIORITY:RW:0:3:=0x04 + 0x00000004, // 333: AXI1_W_PRIORITY:RW:0:3:=0x04 + 0x00000000, // 334: PARITY_ERROR_ADDRESS:RD:0:35:=0x00000000 + 0x00000000, // 335: PARITY_ERROR_BUS_CHANNEL:RD:16:13:=0x0000 PARITY_ERROR_MASTER_ID:RD:8:7:=0x00 PARITY_ERROR_ADDRESS:RD:0:35:=0x00 + 0x00000000, // 336: PARITY_ERROR_WRITE_DATA:RD:0:128:=0x00000000 + 0x00000000, // 337: PARITY_ERROR_WRITE_DATA:RD:0:128:=0x00000000 + 0x00000000, // 338: PARITY_ERROR_WRITE_DATA:RD:0:128:=0x00000000 + 0x00000000, // 339: PARITY_ERROR_WRITE_DATA:RD:0:128:=0x00000000 + 0x00000000, // 340: WEIGHTED_ROUND_ROBIN_WEIGHT_SHARING:RW:24:1:=0x00 WEIGHTED_ROUND_ROBIN_LATENCY_CONTROL:RW:16:1:=0x00 PARITY_ERROR_WRITE_DATA_PARITY_VECTOR:RD:0:16:=0x0000 + 0x02020200, // 341: AXI0_PRIORITY2_RELATIVE_PRIORITY:RW:24:4:=0x02 AXI0_PRIORITY1_RELATIVE_PRIORITY:RW:16:4:=0x02 AXI0_PRIORITY0_RELATIVE_PRIORITY:RW:8:4:=0x02 WRR_PARAM_VALUE_ERR:RD:0:4:=0x00 + 0x02020202, // 342: AXI0_PRIORITY6_RELATIVE_PRIORITY:RW:24:4:=0x02 AXI0_PRIORITY5_RELATIVE_PRIORITY:RW:16:4:=0x02 AXI0_PRIORITY4_RELATIVE_PRIORITY:RW:8:4:=0x02 AXI0_PRIORITY3_RELATIVE_PRIORITY:RW:0:4:=0x02 + 0x00640002, // 343: AXI0_PRIORITY_RELAX:RW:16:10:=0x0064 AXI0_PORT_ORDERING:RW:8:1:=0x00 AXI0_PRIORITY7_RELATIVE_PRIORITY:RW:0:4:=0x02 + 0x01010101, // 344: AXI1_PRIORITY3_RELATIVE_PRIORITY:RW:24:4:=0x01 AXI1_PRIORITY2_RELATIVE_PRIORITY:RW:16:4:=0x01 AXI1_PRIORITY1_RELATIVE_PRIORITY:RW:8:4:=0x01 AXI1_PRIORITY0_RELATIVE_PRIORITY:RW:0:4:=0x01 + 0x01010101, // 345: AXI1_PRIORITY7_RELATIVE_PRIORITY:RW:24:4:=0x01 AXI1_PRIORITY6_RELATIVE_PRIORITY:RW:16:4:=0x01 AXI1_PRIORITY5_RELATIVE_PRIORITY:RW:8:4:=0x01 AXI1_PRIORITY4_RELATIVE_PRIORITY:RW:0:4:=0x01 + 0x00006401, // 346: CKE_STATUS:RD:24:2:=0x00 AXI1_PRIORITY_RELAX:RW:8:10:=0x0064 AXI1_PORT_ORDERING:RW:0:1:=0x01 + 0x00000000, // 347: DLL_RST_ADJ_DLY:RW:24:8:=0x00 DLL_RST_DELAY:RW:8:16:=0x0000 MEM_RST_VALID:RD:0:1:=0x00 + 0x321B0000, // 348: TDFI_PHY_RDLAT_F1:RW_D:24:7:=0x32 TDFI_PHY_RDLAT_F0:RW_D:16:7:=0x1b UPDATE_ERROR_STATUS:RD:8:7:=0x00 TDFI_PHY_WRLAT:RD:0:7:=0x00 + 0x0A00003A, // 349: TDFI_CTRLUPD_MIN:RW:24:8:=0x0a DRAM_CLK_DISABLE:RW:16:2:=0x00 TDFI_RDDATA_EN:RD:8:7:=0x00 TDFI_PHY_RDLAT_F2:RW_D:0:7:=0x3a + 0x00000176, // 350: TDFI_CTRLUPD_MAX_F0:RW:0:21:=0x000176 + 0x00000200, // 351: TDFI_PHYUPD_TYPE0_F0:RW:0:32:=0x00000200 + 0x00000200, // 352: TDFI_PHYUPD_TYPE1_F0:RW:0:32:=0x00000200 + 0x00000200, // 353: TDFI_PHYUPD_TYPE2_F0:RW:0:32:=0x00000200 + 0x00000200, // 354: TDFI_PHYUPD_TYPE3_F0:RW:0:32:=0x00000200 + 0x00000462, // 355: TDFI_PHYUPD_RESP_F0:RW:0:23:=0x000462 + 0x00000E9C, // 356: TDFI_CTRLUPD_INTERVAL_F0:RW:0:32:=0x00000e9c + 0x00000204, // 357: WRLAT_ADJ_F0:RW:8:7:=0x02 RDLAT_ADJ_F0:RW:0:7:=0x04 + 0x000030B0, // 358: TDFI_CTRLUPD_MAX_F1:RW:0:21:=0x0030b0 + 0x00000200, // 359: TDFI_PHYUPD_TYPE0_F1:RW:0:32:=0x00000200 + 0x00000200, // 360: TDFI_PHYUPD_TYPE1_F1:RW:0:32:=0x00000200 + 0x00000200, // 361: TDFI_PHYUPD_TYPE2_F1:RW:0:32:=0x00000200 + 0x00000200, // 362: TDFI_PHYUPD_TYPE3_F1:RW:0:32:=0x00000200 + 0x00009210, // 363: TDFI_PHYUPD_RESP_F1:RW:0:23:=0x009210 + 0x0001E6E0, // 364: TDFI_CTRLUPD_INTERVAL_F1:RW:0:32:=0x0001e6e0 + 0x00000A10, // 365: WRLAT_ADJ_F1:RW:8:7:=0x0a RDLAT_ADJ_F1:RW:0:7:=0x10 + 0x000040E6, // 366: TDFI_CTRLUPD_MAX_F2:RW:0:21:=0x0040e6 + 0x00000200, // 367: TDFI_PHYUPD_TYPE0_F2:RW:0:32:=0x00000200 + 0x00000200, // 368: TDFI_PHYUPD_TYPE1_F2:RW:0:32:=0x00000200 + 0x00000200, // 369: TDFI_PHYUPD_TYPE2_F2:RW:0:32:=0x00000200 + 0x00000200, // 370: TDFI_PHYUPD_TYPE3_F2:RW:0:32:=0x00000200 + 0x0000C2B2, // 371: TDFI_PHYUPD_RESP_F2:RW:0:23:=0x00c2b2 + 0x000288FC, // 372: TDFI_CTRLUPD_INTERVAL_F2:RW:0:32:=0x000288fc + 0x02020E15, // 373: TDFI_CTRL_DELAY_F1:RW_D:24:4:=0x02 TDFI_CTRL_DELAY_F0:RW_D:16:4:=0x02 WRLAT_ADJ_F2:RW:8:7:=0x0e RDLAT_ADJ_F2:RW:0:7:=0x15 + 0x02030202, // 374: TDFI_PHY_WRDATA_F0:RW:24:3:=0x02 TDFI_DRAM_CLK_ENABLE:RW:16:4:=0x03 TDFI_DRAM_CLK_DISABLE:RW:8:4:=0x02 TDFI_CTRL_DELAY_F2:RW_D:0:4:=0x02 + 0x01000404, // 375: TDFI_WRCSLAT_F0:RW:24:7:=0x01 TDFI_RDCSLAT_F0:RW:16:7:=0x00 TDFI_PHY_WRDATA_F2:RW:8:3:=0x04 TDFI_PHY_WRDATA_F1:RW:0:3:=0x04 + 0x0B1E0716, // 376: TDFI_WRCSLAT_F2:RW:24:7:=0x0b TDFI_RDCSLAT_F2:RW:16:7:=0x1e TDFI_WRCSLAT_F1:RW:8:7:=0x07 TDFI_RDCSLAT_F1:RW:0:7:=0x16 + 0x00010105, // 377: BL_ON_FLY_ENABLE:RW_D:24:1:=0x00 DISABLE_MEMORY_MASKED_WRITE:RW_D:16:1:=0x01 EN_1T_TIMING:RW:8:1:=0x01 TDFI_WRDATA_DELAY:RW:0:8:=0x05 + 0x00010101, // 378: RESERVED:RW_D:24:3:=0x00 RESERVED:RW_D:16:3:=0x01 RESERVED:RW_D:8:3:=0x01 RESERVED:RW_D:0:1:=0x01 + 0x00010101, // 379: RESERVED:RW_D:24:4:=0x00 RESERVED:RW_D:16:3:=0x01 RESERVED:RW_D:8:3:=0x01 RESERVED:RW_D:0:3:=0x01 + 0x00010001, // 380: RESERVED:RW_D:24:4:=0x00 RESERVED:RW_D:16:4:=0x01 RESERVED:RW_D:8:4:=0x00 RESERVED:RW_D:0:4:=0x01 + 0x00000101, // 381: RESERVED:RW_D:24:4:=0x00 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x01 RESERVED:RW_D:0:4:=0x01 + 0x02000201, // 382: RESERVED:RW_D:24:4:=0x02 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x02 RESERVED:RW_D:0:4:=0x01 + 0x02010000, // 383: RESERVED:RW_D:24:4:=0x02 RESERVED:RW_D:16:4:=0x01 RESERVED:RW_D:8:4:=0x00 RESERVED:RW_D:0:4:=0x00 + 0x00000200, // 384: GLOBAL_ERROR_INFO:RW+:24:8:=0x00 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x02 RESERVED:RW_D:0:4:=0x00 + 0x1E060000, // 385: NWR_F1:RW:24:8:=0x1e NWR_F0:RW:16:8:=0x06 AXI_PARITY_ERROR_STATUS:RD:8:2:=0x00 GLOBAL_ERROR_MASK:RW:0:8:=0x00 + 0x00000128, // 386: REGPORT_PARAM_PARITY_PROTECTION_STATUS:RD:16:5:=0x00 RESERVED:RW_D:8:1:=0x01 NWR_F2:RW:0:8:=0x28 + 0xFFFFFFFF, // 387: MC_PARITY_INJECTION_BYTE_ENABLE:RW:0:64:=0xFFFFFFFF + 0xFFFFFFFF, // 388: MC_PARITY_INJECTION_BYTE_ENABLE:RW:0:64:=0xFFFFFFFF + 0x00000000, // 389: REGPORT_WRITE_PARITY_PROTECTION_EN:RW:24:1:=0x00 REGPORT_WRITEMASK_PARITY_PROTECTION_EN:RW:16:1:=0x00 REGPORT_ADDR_PARITY_PROTECTION_EN:RW:8:1:=0x00 MC_PARITY_ERROR_TYPE:RW:0:1:=0x00 + 0x00000000, // 390: REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN:RW:24:1:=0x00 REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN:RW:16:1:=0x00 PARAMREG_PARITY_PROTECTION_EN:RW:8:1:=0x00 REGPORT_READ_PARITY_PROTECTION_EN:RW:0:1:=0x00 + 0x00000000, // 391: PARAMREG_PARITY_PROTECTION_INJECTION_EN:RW:16:1:=0x00 REGPORT_READ_PARITY_PROTECTION_INJECTION_EN:RW:8:1:=0x00 REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN:RW:0:1:=0x00 + 0x00000000, // 392: RESERVED:RD:0:96:=0x00000000 + 0x00000000, // 393: RESERVED:RD:0:96:=0x00000000 + 0x00000000, // 394: RESERVED:RD:0:96:=0x00000000 + 0x00000000, // 395: PORT_TO_CORE_PROTECTION_EN:RW:0:1:=0x00 + 0x00000000, // 396: PORT_TO_CORE_PROTECTION_INJECTION_EN:RW:0:96:=0x00000000 + 0x00000000, // 397: PORT_TO_CORE_PROTECTION_INJECTION_EN:RW:0:96:=0x00000000 + 0x00000000, // 398: PORT_TO_CORE_PROTECTION_INJECTION_EN:RW:0:96:=0x00000000 + 0x00000000, // 399: RESERVED:RD:0:134:=0x00000000 + 0x00000000, // 400: RESERVED:RD:0:134:=0x00000000 + 0x00000000, // 401: RESERVED:RD:0:134:=0x00000000 + 0x00000000, // 402: RESERVED:RD:0:134:=0x00000000 + 0x00000000, // 403: RESERVED:RD:0:134:=0x00 + 0x00000000, // 404: PORT_TO_CORE_LR_ERR_INJ_EN:RW:0:134:=0x00000000 + 0x00000000, // 405: PORT_TO_CORE_LR_ERR_INJ_EN:RW:0:134:=0x00000000 + 0x00000000, // 406: PORT_TO_CORE_LR_ERR_INJ_EN:RW:0:134:=0x00000000 + 0x00000000, // 407: PORT_TO_CORE_LR_ERR_INJ_EN:RW:0:134:=0x00000000 + 0x00000000, // 408: PORT_TO_CORE_LR_ERR_INJ_EN:RW:0:134:=0x00 + 0x00000000, // 409: FAULT_FIFO_PROTECTION_EN:RW:0:55:=0x00000000 + 0x00000000, // 410: FAULT_FIFO_PROTECTION_EN:RW:0:55:=0x000000 + 0x00000000, // 411: FAULT_FIFO_PROTECTION_STATUS:RD:0:55:=0x00000000 + 0x00000000, // 412: FAULT_FIFO_PROTECTION_STATUS:RD:0:55:=0x000000 + 0x00000000, // 413: FAULT_FIFO_PROTECTION_INJECTION_EN:RW:0:55:=0x00000000 + 0x00000000 // 414: FAULT_FIFO_PROTECTION_INJECTION_EN:RW:0:55:=0x000000 +}; + + +uint32_t DDR_PI_registers[] = +{ + 0x00000B00, // 0: PI_DRAM_CLASS:RW:8:4:=0x0b PI_START:RW:0:1:=0x00 + 0x00000000, // 1: PI_VERSION:RD:0:64:=0x00000000 + 0x00000000, // 2: PI_VERSION:RD:0:64:=0x00000000 + 0x00000000, // 3: PI_ID:RD:0:16:=0x0000 + 0x00000000, // 4: + 0x00000101, // 5: PI_NOTCARE_PHYUPD:RW:16:1:=0x00 PI_INIT_LVL_EN:RW:8:1:=0x01 PI_NORMAL_LVL_SEQ:RW:0:1:=0x01 + 0x00640000, // 6: PI_TRAIN_ALL_FREQ_REQ:WR:24:1:=0x00 RESERVED:RW_D:16:8:=0x64 PI_TCMD_GAP:RW:0:16:=0x0000 + 0x00000001, // 7: PI_DFI_PHYMSTR_STATE_SEL_R:RW:24:1:=0x00 PI_DFI_PHYMSTR_CS_STATE_R:RW:16:1:=0x00 PI_DFI_PHYMSTR_TYPE:RW:8:2:=0x00 PI_DFI_VERSION:RW:0:1:=0x01 + 0x00000000, // 8: PI_TDFI_PHYMSTR_MAX:RD:0:32:=0x00000000 + 0x00000000, // 9: PI_TDFI_PHYMSTR_RESP:RD:0:20:=0x000000 + 0x00000000, // 10: PI_TDFI_PHYUPD_RESP:RD:0:20:=0x000000 + 0x00000000, // 11: PI_TDFI_PHYUPD_MAX:RD:0:32:=0x00000000 + 0x00000003, // 12: PI_FREQ_MAP:RW:0:32:=0x00000001 + 0x00010001, // 13: RESERVED:RW:24:1:=0x00 PI_SW_RST_N:RW_D:16:1:=0x01 PI_INIT_DFS_CALVL_ONLY:RW:8:1:=0x00 PI_INIT_WORK_FREQ:RW:0:5:=0x00 + 0x0800000F, // 14: PI_TMRR:RW:24:4:=0x08 PI_SRX_LVL_TARGET_CS_EN:RW:16:1:=0x00 PI_RANK_NUM_PER_CKE:RW:8:5:=0x00 PI_CS_MAP:RW:0:4:=0x0f + 0x00000103, // 15: RESERVED:RW:16:1:=0x00 PI_MCAREF_FORWARD_ONLY:RW:8:1:=0x01 PI_PREAMBLE_SUPPORT:RW:0:2:=0x03 + 0x00000005, // 16: PI_ON_DFIBUS:RD:24:1:=0x00 PI_TREF_INTERVAL:RW:0:20:=0x000005 + 0x00000000, // 17: PI_SW_WRLVL_RESP_0:RD:24:1:=0x00 PI_SWLVL_OP_DONE:RD:16:1:=0x00 PI_SWLVL_LOAD:WR:8:1:=0x00 PI_DATA_RETENTION:RD:0:1:=0x00 + 0x00000000, // 18: PI_SW_RDLVL_RESP_0:RD:24:2:=0x00 PI_SW_WRLVL_RESP_3:RD:16:1:=0x00 PI_SW_WRLVL_RESP_2:RD:8:1:=0x00 PI_SW_WRLVL_RESP_1:RD:0:1:=0x00 + 0x00000000, // 19: PI_SW_CALVL_RESP_0:RD:24:2:=0x00 PI_SW_RDLVL_RESP_3:RD:16:2:=0x00 PI_SW_RDLVL_RESP_2:RD:8:2:=0x00 PI_SW_RDLVL_RESP_1:RD:0:2:=0x00 + 0x00000000, // 20: PI_SWLVL_WR_SLICE_0:WR:24:1:=0x00 PI_SWLVL_EXIT:WR:16:1:=0x00 PI_SWLVL_START:WR:8:1:=0x00 PI_SW_LEVELING_MODE:RW:0:3:=0x00 + 0x00000000, // 21: PI_SWLVL_WR_SLICE_1:WR:24:1:=0x00 PI_SW_WDQLVL_RESP_0:RD:16:2:=0x00 PI_SWLVL_VREF_UPDATE_SLICE_0:WR:8:1:=0x00 PI_SWLVL_RD_SLICE_0:WR:0:1:=0x00 + 0x00000000, // 22: PI_SWLVL_WR_SLICE_2:WR:24:1:=0x00 PI_SW_WDQLVL_RESP_1:RD:16:2:=0x00 PI_SWLVL_VREF_UPDATE_SLICE_1:WR:8:1:=0x00 PI_SWLVL_RD_SLICE_1:WR:0:1:=0x00 + 0x00000000, // 23: PI_SWLVL_WR_SLICE_3:WR:24:1:=0x00 PI_SW_WDQLVL_RESP_2:RD:16:2:=0x00 PI_SWLVL_VREF_UPDATE_SLICE_2:WR:8:1:=0x00 PI_SWLVL_RD_SLICE_2:WR:0:1:=0x00 + 0x00000000, // 24: PI_SWLVL_SM2_START:WR:24:1:=0x00 PI_SW_WDQLVL_RESP_3:RD:16:2:=0x00 PI_SWLVL_VREF_UPDATE_SLICE_3:WR:8:1:=0x00 PI_SWLVL_RD_SLICE_3:WR:0:1:=0x00 + 0x00000000, // 25: PI_DFS_PERIOD_EN:RW:24:1:=0x00 PI_SEQUENTIAL_LVL_REQ:WR:16:1:=0x00 PI_SWLVL_SM2_RD:WR:8:1:=0x00 PI_SWLVL_SM2_WR:WR:0:1:=0x00 + 0x00010100, // 26: PI_WRLVL_REQ:WR:24:1:=0x00 PI_16BIT_DRAM_CONNECT:RW_D:16:1:=0x01 PI_DFI40_POLARITY:RW:8:1:=0x01 PI_SRE_PERIOD_EN:RW:0:1:=0x00 + 0x00280A00, // 27: PI_WLMRD:RW:16:6:=0x28 PI_WLDQSEN:RW:8:6:=0x0a PI_WRLVL_CS:RW:0:2:=0x00 + 0x00000000, // 28: PI_WRLVL_ON_SREF_EXIT:RW:24:1:=0x00 PI_WRLVL_PERIODIC:RW:16:1:=0x00 PI_WRLVL_INTERVAL:RW:0:16:=0x0000 + 0x0F000000, // 29: PI_WRLVL_CS_MAP:RW:24:4:=0x0f PI_WRLVL_ROTATE:RW:16:1:=0x00 PI_WRLVL_RESP_MASK:RW:8:4:=0x00 PI_WRLVL_DISABLE_DFS:RW:0:1:=0x00 + 0x00003200, // 30: PI_TDFI_WRLVL_EN:RW:8:8:=0x32 PI_WRLVL_ERROR_STATUS:RD:0:1:=0x00 + 0x00000000, // 31: PI_TDFI_WRLVL_RESP:RW:0:32:=0x00000000 + 0x00000000, // 32: PI_TDFI_WRLVL_MAX:RW:0:32:=0x00000000 + 0x01010102, // 33: PI_ODT_VALUE:RW:24:4:=0x01 PI_TODTH_RD:RW:16:4:=0x01 PI_TODTH_WR:RW:8:4:=0x01 PI_WRLVL_STROBE_NUM:RW:0:5:=0x02 + 0x00000000, // 34: PI_RDLVL_CS:RW:16:2:=0x00 PI_RDLVL_GATE_REQ:WR:8:1:=0x00 PI_RDLVL_REQ:WR:0:1:=0x00 + 0x0000AAAA, // 35: PI_RDLVL_PAT_0:RW:0:32:=0x000000aa + 0x00005555, // 36: PI_RDLVL_PAT_1:RW:0:32:=0x00000055 + 0x0000B5B5, // 37: PI_RDLVL_PAT_2:RW:0:32:=0x000000b5 + 0x00004A4A, // 38: PI_RDLVL_PAT_3:RW:0:32:=0x0000004a + 0x00005656, // 39: PI_RDLVL_PAT_4:RW:0:32:=0x00000056 + 0x0000A9A9, // 40: PI_RDLVL_PAT_5:RW:0:32:=0x000000a9 + 0x0000A9A9, // 41: PI_RDLVL_PAT_6:RW:0:32:=0x000000a9 + 0x0000B5B5, // 42: PI_RDLVL_PAT_7:RW:0:32:=0x000000b5 + 0x00000000, // 43: PI_RDLVL_DISABLE_DFS:RW:24:1:=0x00 PI_RDLVL_ON_SREF_EXIT:RW:16:1:=0x00 PI_RDLVL_PERIODIC:RW:8:1:=0x00 PI_RDLVL_SEQ_EN:RW:0:4:=0x00 + 0x00000000, // 44: PI_RDLVL_ROTATE:RW:24:1:=0x00 PI_RDLVL_GATE_DISABLE_DFS:RW:16:1:=0x00 PI_RDLVL_GATE_ON_SREF_EXIT:RW:8:1:=0x00 PI_RDLVL_GATE_PERIODIC:RW:0:1:=0x00 + 0x000F0F00, // 45: PI_RDLVL_GATE_CS_MAP:RW:16:4:=0x0f PI_RDLVL_CS_MAP:RW:8:4:=0x0f PI_RDLVL_GATE_ROTATE:RW:0:1:=0x00 + 0x0000001A, // 46: PI_TDFI_RDLVL_RR:RW:0:10:=0x001a + 0x000007D0, // 47: PI_TDFI_RDLVL_RESP:RW:0:32:=0x000007d0 + 0x00000300, // 48: PI_TDFI_RDLVL_EN:RW:8:8:=0x03 PI_RDLVL_RESP_MASK:RW:0:4:=0x00 + 0x00000000, // 49: PI_TDFI_RDLVL_MAX:RW:0:32:=0x00000000 + 0x00000000, // 50: PI_RDLVL_INTERVAL:RW:8:16:=0x0000 PI_RDLVL_ERROR_STATUS:RD:0:1:=0x00 + 0x08080000, // 51: PI_RDLVL_PATTERN_NUM:RW:24:4:=0x01 PI_RDLVL_PATTERN_START:RW:16:4:=0x00 PI_RDLVL_GATE_INTERVAL:RW:0:16:=0x0000 + 0x00010101, // 52: PI_REG_DIMM_ENABLE:RW:24:1:=0x00 PI_RD_PREAMBLE_TRAINING_EN:RW:16:1:=0x01 PI_RDLVL_GATE_STROBE_NUM:RW:8:5:=0x01 PI_RDLVL_STROBE_NUM:RW:0:5:=0x01 + 0x00000000, // 53: PI_CALVL_CS:RW:24:2:=0x00 PI_CALVL_REQ:WR:16:1:=0x00 PI_TDFI_PHY_WRLAT:RD:8:7:=0x00 PI_TDFI_RDDATA_EN:RD:0:7:=0x00 + 0x00030000, // 54: PI_CALVL_PERIODIC:RW:24:1:=0x00 PI_CALVL_SEQ_EN:RW:16:2:=0x03 RESERVED:RW:8:4:=0x00 RESERVED:RW:0:1:=0x00 + 0x0F000000, // 55: PI_CALVL_CS_MAP:RW:24:4:=0x0f PI_CALVL_ROTATE:RW:16:1:=0x00 PI_CALVL_DISABLE_DFS:RW:8:1:=0x00 PI_CALVL_ON_SREF_EXIT:RW:0:1:=0x00 + 0x00000017, // 56: PI_TDFI_CALVL_EN:RW:0:8:=0x17 + 0x00000000, // 57: PI_TDFI_CALVL_RESP:RW:0:32:=0x00000000 + 0x00000000, // 58: PI_TDFI_CALVL_MAX:RW:0:32:=0x00000000 + 0x00000000, // 59: PI_CALVL_INTERVAL:RW:16:16:=0x0000 PI_CALVL_ERROR_STATUS:RD:8:2:=0x00 PI_CALVL_RESP_MASK:RW:0:1:=0x00 + 0x0A0A140A, // 60: PI_TCAEXT:RW:24:5:=0x0a PI_TCACKEH:RW:16:5:=0x0a PI_TCAMRD:RW:8:6:=0x14 PI_TCACKEL:RW:0:5:=0x0a + 0x10020401, // 61: PI_TDFI_INIT_START_MIN:RW:24:8:=0x10 PI_CALVL_VREF_NORMAL_STEPSIZE:RW:16:4:=0x02 PI_CALVL_VREF_INITIAL_STEPSIZE:RW:8:4:=0x04 PI_CA_TRAIN_VREF_EN:RW:0:1:=0x01 + 0x00020805, // 62: PI_SW_CA_TRAIN_VREF:RW:24:7:=0x00 PI_CALVL_STROBE_NUM:RW:16:5:=0x02 PI_TCKCKEH:RW:8:4:=0x08 PI_TDFI_INIT_COMPLETE_MIN:RW:0:8:=0x05 + 0x01000404, // 63: PI_REFRESH_BETWEEN_SEGMENT_DISABLE:RW_D:24:1:=0x01 PI_DRAM_CLK_DISABLE_DEASSERT_SEL:RW:16:1:=0x00 PI_INIT_STARTORCOMPLETE_2_CLKDISABLE:RW:8:8:=0x04 PI_CLKDISABLE_2_INIT_START:RW:0:8:=0x04 + 0x00000000, // 64: PI_FSM_ERROR_INFO_MASK:RW:8:16:=0x0000 PI_MC_DFS_PI_SET_VREF_ENABLE:RW:0:1:=0x00 + 0x00000000, // 65: PI_FSM_ERROR_INFO:RD:16:16:=0x0000 PI_SC_FSM_ERROR_INFO_WOCLR:WR:0:16:=0x0000 + 0x00000101, // 66: PI_WDQLVL_ROTATE:RW:24:1:=0x00 PI_WDQLVL_RESP_MASK:RW:16:4:=0x00 PI_WDQLVL_BST_NUM:RW:8:3:=0x01 PI_WDQLVL_VREF_EN:RW:0:1:=0x01 + 0x0002040F, // 67: PI_WDQLVL_PERIODIC:RW:24:1:=0x00 PI_WDQLVL_VREF_NORMAL_STEPSIZE:RW:16:5:=0x02 PI_WDQLVL_VREF_INITIAL_STEPSIZE:RW:8:5:=0x04 PI_WDQLVL_CS_MAP:RW:0:4:=0x0f + 0x00340000, // 68: PI_TDFI_WDQLVL_EN:RW:16:8:=0x34 PI_WDQLVL_CS:RW:8:2:=0x00 PI_WDQLVL_REQ:WR:0:1:=0x00 + 0x00000000, // 69: PI_TDFI_WDQLVL_RESP:RW:0:32:=0x00000000 + 0x00000000, // 70: PI_TDFI_WDQLVL_MAX:RW:0:32:=0x00000000 + 0x00000000, // 71: PI_WDQLVL_DISABLE_DFS:RW:24:1:=0x00 PI_WDQLVL_ON_SREF_EXIT:RW:16:1:=0x00 PI_WDQLVL_INTERVAL:RW:0:16:=0x0000 + 0x01000000, // 72: PI_PARALLEL_WDQLVL_EN:RW:24:1:=0x01 PI_DQS_OSC_PERIOD_EN:RW:16:1:=0x00 PI_WDQLVL_OSC_EN:RW:8:1:=0x00 PI_WDQLVL_ERROR_STATUS:RD:0:2:=0x00 + 0x00080000, // 73: RESERVED:RW_D:24:4:=0x00 PI_TCCD:RW:16:5:=0x08 PI_ROW_DIFF:RW:8:3:=0x00 PI_BANK_DIFF:RW:0:2:=0x00 + 0x02000200, // 74: RESERVED:RW_D:24:4:=0x02 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x02 RESERVED:RW_D:0:4:=0x00 + 0x01000100, // 75: RESERVED:RW_D:24:4:=0x01 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x01 RESERVED:RW_D:0:4:=0x00 + 0x01000000, // 76: RESERVED:RW_D:24:4:=0x01 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x00 RESERVED:RW_D:0:4:=0x00 + 0x02000200, // 77: RESERVED:RW_D:24:4:=0x02 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x02 RESERVED:RW_D:0:4:=0x00 + 0x00000200, // 78: RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x02 RESERVED:RW_D:0:4:=0x00 + 0x00000000, // 79: PI_INT_STATUS:RD:0:28:=0x00000000 + 0x00000000, // 80: PI_INT_ACK:WR:0:27:=0x00000000 + 0x00000000, // 81: PI_INT_MASK:RW:0:28:=0x00000000 + 0x00000000, // 82: PI_BIST_EXP_DATA:RD:0:128:=0x00000000 + 0x00000000, // 83: PI_BIST_EXP_DATA:RD:0:128:=0x00000000 + 0x00000000, // 84: PI_BIST_EXP_DATA:RD:0:128:=0x00000000 + 0x00000000, // 85: PI_BIST_EXP_DATA:RD:0:128:=0x00000000 + 0x00000000, // 86: PI_BIST_FAIL_DATA:RD:0:128:=0x00000000 + 0x00000000, // 87: PI_BIST_FAIL_DATA:RD:0:128:=0x00000000 + 0x00000000, // 88: PI_BIST_FAIL_DATA:RD:0:128:=0x00000000 + 0x00000000, // 89: PI_BIST_FAIL_DATA:RD:0:128:=0x00000000 + 0x00000000, // 90: PI_BIST_FAIL_ADDR:RD:0:35:=0x00000000 + 0x00000400, // 91: PI_CMD_SWAP_EN:RW_D:24:1:=0x00 PI_LONG_COUNT_MASK:RW:16:5:=0x00 PI_BSTLEN:RW_D:8:5:=0x04 PI_BIST_FAIL_ADDR:RD:0:35:=0x00 + 0x02010000, // 92: PI_DATA_BYTE_SWAP_SLICE2:RW_D:24:2:=0x02 PI_DATA_BYTE_SWAP_SLICE1:RW_D:16:2:=0x01 PI_DATA_BYTE_SWAP_SLICE0:RW_D:8:2:=0x00 PI_DATA_BYTE_SWAP_EN:RW_D:0:1:=0x00 + 0x00080003, // 93: PI_UPDATE_ERROR_STATUS:RD:24:2:=0x00 PI_TDFI_CTRLUPD_MIN:RW:16:8:=0x08 PI_CTRLUPD_REQ_PER_AREF_EN:RW:8:1:=0x00 PI_DATA_BYTE_SWAP_SLICE3:RW_D:0:2:=0x03 + 0x00080000, // 94: PI_BIST_DATA_CHECK:RW:24:1:=0x00 PI_ADDR_SPACE:RW:16:6:=0x08 PI_BIST_RESULT:RD:8:2:=0x00 PI_BIST_GO:RW:0:1:=0x00 + 0x00000001, // 95: PI_BIST_ADDR_CHECK:RW:0:1:=0x01 + 0x00000000, // 96: PI_BIST_START_ADDRESS:RW:0:35:=0x00000000 + 0x0000AA00, // 97: PI_MBIST_INIT_PATTERN:RW:8:8:=0xaa PI_BIST_START_ADDRESS:RW:0:35:=0x00 + 0x00000000, // 98: PI_BIST_DATA_MASK:RW:0:64:=0x00000000 + 0x00000000, // 99: PI_BIST_DATA_MASK:RW:0:64:=0x00000000 + 0x00010000, // 100: PI_BIST_ERR_STOP:RW:16:12:=0x0001 PI_BIST_ERR_COUNT:RD:0:12:=0x0000 + 0x00000000, // 101: PI_BIST_ADDR_MASK_0:RW:0:36:=0x00000000 + 0x00000000, // 102: PI_BIST_ADDR_MASK_0:RW:0:36:=0x00 + 0x00000000, // 103: PI_BIST_ADDR_MASK_1:RW:0:36:=0x00000000 + 0x00000000, // 104: PI_BIST_ADDR_MASK_1:RW:0:36:=0x00 + 0x00000000, // 105: PI_BIST_ADDR_MASK_2:RW:0:36:=0x00000000 + 0x00000000, // 106: PI_BIST_ADDR_MASK_2:RW:0:36:=0x00 + 0x00000000, // 107: PI_BIST_ADDR_MASK_3:RW:0:36:=0x00000000 + 0x00000000, // 108: PI_BIST_ADDR_MASK_3:RW:0:36:=0x00 + 0x00000000, // 109: PI_BIST_ADDR_MASK_4:RW:0:36:=0x00000000 + 0x00000000, // 110: PI_BIST_ADDR_MASK_4:RW:0:36:=0x00 + 0x00000000, // 111: PI_BIST_ADDR_MASK_5:RW:0:36:=0x00000000 + 0x00000000, // 112: PI_BIST_ADDR_MASK_5:RW:0:36:=0x00 + 0x00000000, // 113: PI_BIST_ADDR_MASK_6:RW:0:36:=0x00000000 + 0x00000000, // 114: PI_BIST_ADDR_MASK_6:RW:0:36:=0x00 + 0x00000000, // 115: PI_BIST_ADDR_MASK_7:RW:0:36:=0x00000000 + 0x00000000, // 116: PI_BIST_ADDR_MASK_7:RW:0:36:=0x00 + 0x00000000, // 117: PI_BIST_ADDR_MASK_8:RW:0:36:=0x00000000 + 0x00000000, // 118: PI_BIST_ADDR_MASK_8:RW:0:36:=0x00 + 0x00000000, // 119: PI_BIST_ADDR_MASK_9:RW:0:36:=0x00000000 + 0x00000000, // 120: PI_BIST_PAT_MODE:RW:24:2:=0x00 PI_BIST_ADDR_MODE:RW:16:2:=0x00 PI_BIST_MODE:RW:8:3:=0x00 PI_BIST_ADDR_MASK_9:RW:0:36:=0x00 + 0x00000000, // 121: PI_BIST_USER_PAT:RW:0:128:=0x00000000 + 0x00000000, // 122: PI_BIST_USER_PAT:RW:0:128:=0x00000000 + 0x00000000, // 123: PI_BIST_USER_PAT:RW:0:128:=0x00000000 + 0x00000000, // 124: PI_BIST_USER_PAT:RW:0:128:=0x00000000 + 0x00000008, // 125: PI_BIST_PAT_NUM:RW:0:4:=0x00 + 0x00000000, // 126: PI_BIST_STAGE_0:RW:0:30:=0x00000000 + 0x00000000, // 127: PI_BIST_STAGE_1:RW:0:30:=0x00000000 + 0x00000000, // 128: PI_BIST_STAGE_2:RW:0:30:=0x00000000 + 0x00000000, // 129: PI_BIST_STAGE_3:RW:0:30:=0x00000000 + 0x00000000, // 130: PI_BIST_STAGE_4:RW:0:30:=0x00000000 + 0x00000000, // 131: PI_BIST_STAGE_5:RW:0:30:=0x00000000 + 0x00000000, // 132: PI_BIST_STAGE_6:RW:0:30:=0x00000000 + 0x00000000, // 133: PI_BIST_STAGE_7:RW:0:30:=0x00000000 + 0x00000002, // 134: PI_SREFRESH_EXIT_NO_REFRESH:RW:24:1:=0x00 PI_PWRUP_SREFRESH_EXIT:RW+:16:1:=0x00 PI_SELF_REFRESH_EN:RW:8:1:=0x00 PI_COL_DIFF:RW:0:4:=0x02 + 0x00000000, // 135: PI_NO_PHY_IND_TRAIN_INIT:RW:24:1:=0x00 PI_NO_MRW_INIT:RW:16:1:=0x00 PI_NO_MRW_BT_INIT:RW:8:1:=0x00 PI_SREF_ENTRY_REQ:WR:0:1:=0x00 + 0x00000000, // 136: PI_NO_AUTO_MRR_INIT:RW:0:1:=0x00 + 0x0000000A, // 137: PI_TRST_PWRON:RW:0:32:=0x0000000a + 0x00000019, // 138: PI_CKE_INACTIVE:RW:0:32:=0x00000019 + 0x00000000, // 139: PI_DLL_RST_DELAY:RW:16:16:=0x0000 PI_DRAM_INIT_EN:RW:8:1:=0x00 PI_DLL_RST:RW:0:1:=0x00 + 0x00000000, // 140: PI_DLL_RST_ADJ_DLY:RW:0:8:=0x00 + 0x00000000, // 141: PI_WRITE_MODEREG:RW+:0:26:=0x00000000 + 0x00000000, // 142: PI_READ_MODEREG:RW+:8:17:=0x000000 PI_MRW_STATUS:RD:0:8:=0x00 + 0x00000000, // 143: PI_NO_ZQ_INIT:RW:24:1:=0x00 PI_PERIPHERAL_MRR_DATA_0:RD:0:24:=0x000000 + 0x01000000, // 144: RESERVED:RW:24:1:=0x01 PI_ZQ_REQ_PENDING:RD:16:1:=0x00 RESERVED:WR:8:4:=0x00 RESERVED:RW:0:4:=0x00 + 0x00010003, // 145: PI_MONITOR_0:RD:24:8:=0x00 PI_MONITOR_CAP_SEL_0:RW:16:1:=0x01 PI_MONITOR_SRC_SEL_0:RW:8:4:=0x00 RESERVED:RW:0:3:=0x03 + 0x02000101, // 146: PI_MONITOR_SRC_SEL_2:RW:24:4:=0x02 PI_MONITOR_1:RD:16:8:=0x00 PI_MONITOR_CAP_SEL_1:RW:8:1:=0x01 PI_MONITOR_SRC_SEL_1:RW:0:4:=0x01 + 0x01030001, // 147: PI_MONITOR_CAP_SEL_3:RW:24:1:=0x01 PI_MONITOR_SRC_SEL_3:RW:16:4:=0x03 PI_MONITOR_2:RD:8:8:=0x00 PI_MONITOR_CAP_SEL_2:RW:0:1:=0x01 + 0x00010400, // 148: PI_MONITOR_4:RD:24:8:=0x00 PI_MONITOR_CAP_SEL_4:RW:16:1:=0x01 PI_MONITOR_SRC_SEL_4:RW:8:4:=0x04 PI_MONITOR_3:RD:0:8:=0x00 + 0x06000105, // 149: PI_MONITOR_SRC_SEL_6:RW:24:4:=0x06 PI_MONITOR_5:RD:16:8:=0x00 PI_MONITOR_CAP_SEL_5:RW:8:1:=0x01 PI_MONITOR_SRC_SEL_5:RW:0:4:=0x05 + 0x01070001, // 150: PI_MONITOR_CAP_SEL_7:RW:24:1:=0x01 PI_MONITOR_SRC_SEL_7:RW:16:4:=0x07 PI_MONITOR_6:RD:8:8:=0x00 PI_MONITOR_CAP_SEL_6:RW:0:1:=0x01 + 0x00000000, // 151: PI_MONITOR_7:RD:0:8:=0x00 + 0x00000000, // 152: PI_MONITOR_STROBE:WR:0:8:=0x00 + 0x00000000, // 153: RESERVED:RW:24:1:=0x00 PI_FREQ_RETENTION_NUM:RW+:16:5:=0x00 PI_FREQ_NUMBER_STATUS:RD:8:5:=0x00 PI_DLL_LOCK:RD:0:1:=0x00 + 0x00010001, // 154: RESERVED:RW:24:1:=0x00 PI_POWER_REDUC_EN:RW:16:1:=0x01 RESERVED:RW:8:1:=0x00 PI_PHYMSTR_TYPE:RW:0:2:=0x01 + 0x00000000, // 155: RESERVED:RW:24:1:=0x00 RESERVED:RW:16:1:=0x00 RESERVED:RW:8:1:=0x00 RESERVED:RW:0:1:=0x00 + 0x00000000, // 156: RESERVED:RW:24:1:=0x00 RESERVED:RW:16:1:=0x00 RESERVED:RW:8:1:=0x00 RESERVED:RW:0:1:=0x00 + 0x00000000, // 157: RESERVED:RW:24:1:=0x00 RESERVED:RW:16:1:=0x00 RESERVED:RW:8:1:=0x00 RESERVED:RW:0:1:=0x00 + 0x00000000, // 158: RESERVED:RW:24:1:=0x00 RESERVED:RW:16:1:=0x00 RESERVED:RW:8:1:=0x00 RESERVED:RW:0:1:=0x00 + 0x00000401, // 159: PI_TREFBW_THR:RW:8:9:=0x0004 PI_WRLVL_MAX_STROBE_PEND:RW:0:8:=0x01 + 0x00000000, // 160: PI_FREQ_CHANGE_REG_COPY:RW:0:5:=0x00 + 0x00010000, // 161: PI_CATR:RW:24:4:=0x00 PI_PARALLEL_CALVL_EN:RW:16:1:=0x01 RESERVED:RW:8:5:=0x00 PI_FREQ_SEL_FROM_REGIF:RW:0:1:=0x00 + 0x00000000, // 162: PI_NOTCARE_MC_INIT_START:RW:24:1:=0x00 PI_DISCONNECT_MC:RW:16:1:=0x00 PI_MASK_INIT_COMPLETE:RW:8:1:=0x00 PI_NO_CATR_READ:RW:0:1:=0x00 + 0x2B200100, // 163: PI_TSDO_F2:RW:24:8:=0x2b PI_TSDO_F1:RW:16:8:=0x20 PI_TSDO_F0:RW:8:8:=0x01 PI_TRACE_MC_MR13:RW:0:1:=0x00 + 0x00000034, // 164: PI_TDELAY_RDWR_2_BUS_IDLE_F0:RW:0:8:=0x34 + 0x00000057, // 165: PI_TDELAY_RDWR_2_BUS_IDLE_F1:RW:0:8:=0x57 + 0x00020064, // 166: PI_ZQINIT_F0:RW_D:8:12:=0x0200 PI_TDELAY_RDWR_2_BUS_IDLE_F2:RW:0:8:=0x64 + 0x02000200, // 167: PI_ZQINIT_F2:RW_D:16:12:=0x0200 PI_ZQINIT_F1:RW_D:0:12:=0x0200 + 0x380E0C04, // 168: PI_CASLAT_LIN_F1:RW:24:7:=0x38 PI_WRLAT_F1:RW:16:7:=0x0e PI_CASLAT_LIN_F0:RW:8:7:=0x0c PI_WRLAT_F0:RW:0:7:=0x04 + 0x00134812, // 169: PI_TRFC_F0:RW:16:10:=0x0013 PI_CASLAT_LIN_F2:RW:8:7:=0x48 PI_WRLAT_F2:RW:0:7:=0x12 + 0x000000BB, // 170: PI_TREF_F0:RW:0:20:=0x0000bb + 0x00000260, // 171: PI_TRFC_F1:RW:0:10:=0x0260 + 0x00001858, // 172: PI_TREF_F1:RW:0:20:=0x001858 + 0x0000032B, // 173: PI_TRFC_F2:RW:0:10:=0x032b + 0x04002073, // 174: PI_TDFI_CTRL_DELAY_F0:RW_D:24:4:=0x04 PI_TREF_F2:RW:0:20:=0x002073 + 0x01000404, // 175: PI_WRLVL_EN_F1:RW:24:2:=0x01 PI_WRLVL_EN_F0:RW:16:2:=0x01 PI_TDFI_CTRL_DELAY_F2:RW_D:8:4:=0x04 PI_TDFI_CTRL_DELAY_F1:RW_D:0:4:=0x04 + 0x00001501, // 176: PI_TDFI_WRLVL_WW_F0:RW:8:10:=0x0015 PI_WRLVL_EN_F2:RW:0:2:=0x01 + 0x00150015, // 177: PI_TDFI_WRLVL_WW_F2:RW:16:10:=0x0015 PI_TDFI_WRLVL_WW_F1:RW:0:10:=0x0015 + 0x00000000, // 178: PI_ODT_EN_F1:RW:24:1:=0x01 PI_TODTL_2CMD_F1:RW:16:8:=0x00 PI_ODT_EN_F0:RW:8:1:=0x01 PI_TODTL_2CMD_F0:RW:0:8:=0x00 + 0x00000000, // 179: PI_TODTON_MIN_F0:RW:24:4:=0x00 PI_ODTLON_F0:RW:16:4:=0x00 PI_ODT_EN_F2:RW:8:1:=0x01 PI_TODTL_2CMD_F2:RW:0:8:=0x00 + 0x00000000, // 180: PI_TODTON_MIN_F2:RW:24:4:=0x00 PI_ODTLON_F2:RW:16:4:=0x00 PI_TODTON_MIN_F1:RW:8:4:=0x00 PI_ODTLON_F1:RW:0:4:=0x00 + 0x01010000, // 181: PI_RDLVL_GATE_EN_F1:RW:24:2:=0x01 PI_RDLVL_EN_F1:RW:16:2:=0x01 PI_RDLVL_GATE_EN_F0:RW:8:2:=0x01 PI_RDLVL_EN_F0:RW:0:2:=0x01 + 0x00000101, // 182: PI_RDLVL_RXCAL_EN_F0:RW:24:2:=0x00 PI_RDLVL_PAT0_EN_F0:RW:16:2:=0x00 PI_RDLVL_GATE_EN_F2:RW:8:2:=0x01 PI_RDLVL_EN_F2:RW:0:2:=0x01 + 0x00030000, // 183: PI_RDLVL_RXCAL_EN_F1:RW:24:2:=0x00 PI_RDLVL_PAT0_EN_F1:RW:16:2:=0x00 PI_RDLVL_MULTI_EN_F0:RW:8:2:=0x00 PI_RDLVL_DFE_EN_F0:RW:0:2:=0x00 + 0x00030300, // 184: PI_RDLVL_RXCAL_EN_F2:RW:24:2:=0x00 PI_RDLVL_PAT0_EN_F2:RW:16:2:=0x00 PI_RDLVL_MULTI_EN_F1:RW:8:2:=0x00 PI_RDLVL_DFE_EN_F1:RW:0:2:=0x00 + 0x10040300, // 185: PI_RDLAT_ADJ_F1:RW:24:7:=0x10 PI_RDLAT_ADJ_F0:RW:16:7:=0x04 PI_RDLVL_MULTI_EN_F2:RW:8:2:=0x00 PI_RDLVL_DFE_EN_F2:RW:0:2:=0x00 + 0x0E0A0215, // 186: PI_WRLAT_ADJ_F2:RW:24:7:=0x0e PI_WRLAT_ADJ_F1:RW:16:7:=0x0a PI_WRLAT_ADJ_F0:RW:8:7:=0x02 PI_RDLAT_ADJ_F2:RW:0:7:=0x15 + 0x00040402, // 187: PI_TDFI_PHY_WRDATA_F2:RW:16:3:=0x04 PI_TDFI_PHY_WRDATA_F1:RW:8:3:=0x04 PI_TDFI_PHY_WRDATA_F0:RW:0:3:=0x02 + 0x000C0034, // 188: PI_TDFI_CALVL_CAPTURE_F0:RW:16:10:=0x000c PI_TDFI_CALVL_CC_F0:RW:0:10:=0x0034 + 0x001C0044, // 189: PI_TDFI_CALVL_CAPTURE_F1:RW:16:10:=0x001c PI_TDFI_CALVL_CC_F1:RW:0:10:=0x0044 + 0x00210049, // 190: PI_TDFI_CALVL_CAPTURE_F2:RW:16:10:=0x0021 PI_TDFI_CALVL_CC_F2:RW:0:10:=0x0049 + 0x01010101, // 191: PI_TMRZ_F0:RW:24:5:=0x01 PI_CALVL_EN_F2:RW:16:2:=0x01 PI_CALVL_EN_F1:RW:8:2:=0x01 PI_CALVL_EN_F0:RW:0:2:=0x01 + 0x0003000D, // 192: PI_TMRZ_F1:RW:16:5:=0x03 PI_TCAENT_F0:RW:0:14:=0x000d + 0x00040190, // 193: PI_TMRZ_F2:RW:16:5:=0x04 PI_TCAENT_F1:RW:0:14:=0x0190 + 0x01000216, // 194: PI_TDFI_CASEL_F0:RW:24:5:=0x01 PI_TDFI_CACSCA_F0:RW:16:5:=0x00 PI_TCAENT_F2:RW:0:14:=0x0216 + 0x000E000E, // 195: PI_TVREF_LONG_F0:RW:16:10:=0x000e PI_TVREF_SHORT_F0:RW:0:10:=0x000e + 0x01910100, // 196: PI_TVREF_SHORT_F1:RW:16:10:=0x0191 PI_TDFI_CASEL_F1:RW:8:5:=0x01 PI_TDFI_CACSCA_F1:RW:0:5:=0x00 + 0x01000191, // 197: PI_TDFI_CASEL_F2:RW:24:5:=0x01 PI_TDFI_CACSCA_F2:RW:16:5:=0x00 PI_TVREF_LONG_F1:RW:0:10:=0x0191 + 0x02170217, // 198: PI_TVREF_LONG_F2:RW:16:10:=0x0217 PI_TVREF_SHORT_F2:RW:0:10:=0x0217 + 0x32195940, // 199: PI_CALVL_VREF_INITIAL_STOP_POINT_F1:RW:24:7:=0x1e PI_CALVL_VREF_INITIAL_START_POINT_F1:RW:16:7:=0x1a PI_CALVL_VREF_INITIAL_STOP_POINT_F0:RW:8:7:=0x1e PI_CALVL_VREF_INITIAL_START_POINT_F0:RW:0:7:=0x1a + 0x01013219, // 200: PI_CALVL_VREF_DELTA_F1:RW:24:4:=0x01 PI_CALVL_VREF_DELTA_F0:RW:16:4:=0x01 PI_CALVL_VREF_INITIAL_STOP_POINT_F2:RW:8:7:=0x1e PI_CALVL_VREF_INITIAL_START_POINT_F2:RW:0:7:=0x1a + 0x0A070601, // 201: PI_TMRWCKEL_F0:RW:24:8:=0x0a PI_TXP_F0:RW:16:5:=0x07 PI_TDFI_CALVL_STROBE_F0:RW:8:4:=0x06 PI_CALVL_VREF_DELTA_F2:RW:0:4:=0x01 + 0x180F090D, // 202: PI_TMRWCKEL_F1:RW:24:8:=0x18 PI_TXP_F1:RW:16:5:=0x0f PI_TDFI_CALVL_STROBE_F1:RW:8:4:=0x09 PI_TCKELCK_F0:RW:0:5:=0x0d + 0x1F130A11, // 203: PI_TMRWCKEL_F2:RW:24:8:=0x1f PI_TXP_F2:RW:16:5:=0x13 PI_TDFI_CALVL_STROBE_F2:RW:8:4:=0x0a PI_TCKELCK_F1:RW:0:5:=0x11 + 0x0000C014, // 204: PI_TDFI_INIT_START_F0:RW:8:10:=0x00c0 PI_TCKELCK_F2:RW:0:5:=0x14 + 0x00C01000, // 205: PI_TDFI_INIT_START_F1:RW:16:10:=0x00c0 PI_TDFI_INIT_COMPLETE_F0:RW:0:16:=0x1000 + 0x00C0ffff, // 206: PI_TDFI_INIT_START_F2:RW:16:10:=0x00c0 PI_TDFI_INIT_COMPLETE_F1:RW:0:16:=0x1000 + 0x0002ffff, // 207: PI_TCKEHDQS_F0:RW:16:6:=0x02 PI_TDFI_INIT_COMPLETE_F2:RW:0:16:=0x1000 + 0x001E000D, // 208: PI_TCKEHDQS_F1:RW:16:6:=0x1e PI_TFC_F0:RW:0:10:=0x000d + 0x00240190, // 209: PI_TCKEHDQS_F2:RW:16:6:=0x24 PI_TFC_F1:RW:0:10:=0x0190 + 0x00110216, // 210: PI_TDFI_WDQLVL_WR_F0:RW:16:10:=0x0011 PI_TFC_F2:RW:0:10:=0x0216 + 0x59400056, // 211: PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0:RW:24:7:=0x1e PI_WDQLVL_VREF_INITIAL_START_POINT_F0:RW:16:7:=0x1a PI_TDFI_WDQLVL_RW_F0:RW:0:10:=0x0056 + 0x00000001, // 212: PI_NTP_TRAIN_EN_F0:RW:16:2:=0x00 PI_WDQLVL_EN_F0:RW:8:2:=0x01 PI_WDQLVL_VREF_DELTA_F0:RW:0:4:=0x01 + 0x005A002C, // 213: PI_TDFI_WDQLVL_RW_F1:RW:16:10:=0x005a PI_TDFI_WDQLVL_WR_F1:RW:0:10:=0x002c + 0x01013219, // 214: PI_WDQLVL_EN_F1:RW:24:2:=0x01 PI_WDQLVL_VREF_DELTA_F1:RW:16:4:=0x01 PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1:RW:8:7:=0x1e PI_WDQLVL_VREF_INITIAL_START_POINT_F1:RW:0:7:=0x1a + 0x00003600, // 215: PI_TDFI_WDQLVL_WR_F2:RW:8:10:=0x0036 PI_NTP_TRAIN_EN_F1:RW:0:2:=0x00 + 0x3219005B, // 216: PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2:RW:24:7:=0x1e PI_WDQLVL_VREF_INITIAL_START_POINT_F2:RW:16:7:=0x1a PI_TDFI_WDQLVL_RW_F2:RW:0:10:=0x005b + 0x09000101, // 217: PI_TRTP_F0:RW:24:8:=0x09 PI_NTP_TRAIN_EN_F2:RW:16:2:=0x00 PI_WDQLVL_EN_F2:RW:8:2:=0x01 PI_WDQLVL_VREF_DELTA_F2:RW:0:4:=0x01 + 0x04010503, // 218: PI_TWR_F0:RW:24:8:=0x04 PI_TWTR_F0:RW:16:6:=0x01 PI_TRCD_F0:RW:8:8:=0x05 PI_TRP_F0:RW:0:8:=0x03 + 0x0400062B, // 219: PI_TRAS_MIN_F0:RW:24:8:=0x04 PI_TRAS_MAX_F0:RW:0:17:=0x00062b + 0x0A032001, // 220: PI_TMRD_F0:RW:24:8:=0x0a PI_TSR_F0:RW:16:8:=0x03 PI_TCCDMW_F0:RW:8:6:=0x20 PI_TDQSCK_MAX_F0:RW:0:4:=0x01 + 0x1E220D0A, // 221: PI_TRCD_F1:RW:24:8:=0x1e PI_TRP_F1:RW:16:8:=0x22 PI_TRTP_F1:RW:8:8:=0x0d PI_TMRW_F0:RW:0:8:=0x0a + 0x00001F12, // 222: PI_TWR_F1:RW:8:8:=0x1f PI_TWTR_F1:RW:0:6:=0x12 + 0x4500C570, // 223: PI_TRAS_MIN_F1:RW:24:8:=0x45 PI_TRAS_MAX_F1:RW:0:17:=0x00c570 + 0x17182006, // 224: PI_TMRD_F1:RW:24:8:=0x17 PI_TSR_F1:RW:16:8:=0x18 PI_TCCDMW_F1:RW:8:6:=0x20 PI_TDQSCK_MAX_F1:RW:0:4:=0x06 + 0x282D1110, // 225: PI_TRCD_F2:RW:24:8:=0x28 PI_TRP_F2:RW:16:8:=0x2d PI_TRTP_F2:RW:8:8:=0x11 PI_TMRW_F1:RW:0:8:=0x10 + 0x00002918, // 226: PI_TWR_F2:RW:8:8:=0x29 PI_TWTR_F2:RW:0:6:=0x18 + 0x5C01071C, // 227: PI_TRAS_MIN_F2:RW:24:8:=0x5c PI_TRAS_MAX_F2:RW:0:17:=0x01071c + 0x1E202008, // 228: PI_TMRD_F2:RW:24:8:=0x1e PI_TSR_F2:RW:16:8:=0x20 PI_TCCDMW_F2:RW:8:6:=0x20 PI_TDQSCK_MAX_F2:RW:0:4:=0x08 + 0x00017616, // 229: PI_TDFI_CTRLUPD_MAX_F0:RW:8:21:=0x000176 PI_TMRW_F2:RW:0:8:=0x16 + 0x00000E9C, // 230: PI_TDFI_CTRLUPD_INTERVAL_F0:RW:0:32:=0x00000e9c + 0x000030B0, // 231: PI_TDFI_CTRLUPD_MAX_F1:RW:0:21:=0x0030b0 + 0x0001E6E0, // 232: PI_TDFI_CTRLUPD_INTERVAL_F1:RW:0:32:=0x0001e6e0 + 0x000040E6, // 233: PI_TDFI_CTRLUPD_MAX_F2:RW:0:21:=0x0040e6 + 0x000288FC, // 234: PI_TDFI_CTRLUPD_INTERVAL_F2:RW:0:32:=0x000288fc + 0x026C0014, // 235: PI_TXSR_F1:RW:16:16:=0x026c PI_TXSR_F0:RW:0:16:=0x0014 + 0x0303033B, // 236: PI_TEXCKE_F1:RW:24:6:=0x03 PI_TEXCKE_F0:RW:16:6:=0x03 PI_TXSR_F2:RW:0:16:=0x033b + 0x00271004, // 237: PI_TINIT_F0:RW:8:24:=0x002710 PI_TEXCKE_F2:RW:0:6:=0x04 + 0x000186A0, // 238: PI_TINIT3_F0:RW:0:24:=0x0186a0 + 0x00000005, // 239: PI_TINIT4_F0:RW:0:24:=0x000005 + 0x00000064, // 240: PI_TINIT5_F0:RW:0:24:=0x000064 + 0x00000014, // 241: PI_TXSNR_F0:RW:0:16:=0x0014 + 0x0004E200, // 242: PI_TINIT_F1:RW:0:24:=0x04e200 + 0x000186A0, // 243: PI_TINIT3_F1:RW:0:24:=0x0186a0 + 0x00000005, // 244: PI_TINIT4_F1:RW:0:24:=0x000005 + 0x00000C80, // 245: PI_TINIT5_F1:RW:0:24:=0x000c80 + 0x0000026C, // 246: PI_TXSNR_F1:RW:0:16:=0x026c + 0x000681C8, // 247: PI_TINIT_F2:RW:0:24:=0x0681c8 + 0x000186A0, // 248: PI_TINIT3_F2:RW:0:24:=0x0186a0 + 0x00000005, // 249: PI_TINIT4_F2:RW:0:24:=0x000005 + 0x000010A9, // 250: PI_TINIT5_F2:RW:0:24:=0x0010a9 + 0x0100033B, // 251: RESERVED:RW:16:12:=0x0100 PI_TXSNR_F2:RW:0:16:=0x033b + 0x00320040, // 252: PI_TZQCAL_F0:RW:16:12:=0x0032 RESERVED:RW:0:12:=0x0040 + 0x00010002, // 253: RESERVED:RW:8:12:=0x0100 PI_TZQLAT_F0:RW:0:7:=0x02 + 0x06400040, // 254: PI_TZQCAL_F1:RW:16:12:=0x0640 RESERVED:RW:0:12:=0x0040 + 0x00010030, // 255: RESERVED:RW:8:12:=0x0100 PI_TZQLAT_F1:RW:0:7:=0x30 + 0x08550040, // 256: PI_TZQCAL_F2:RW:16:12:=0x0855 RESERVED:RW:0:12:=0x0040 + 0x00000340, // 257: RESERVED:RW:8:12:=0x0003 PI_TZQLAT_F2:RW:0:7:=0x40 + 0x006B0050, // 258: RESERVED:RW:16:12:=0x006b RESERVED:RW:0:12:=0x0050 + 0x08040404, // 259: PI_MR13_DATA_0:RW+:24:8:=0x00 PI_WDQ_OSC_DELTA_INDEX_F2:RW:16:4:=0x04 PI_WDQ_OSC_DELTA_INDEX_F1:RW:8:4:=0x04 PI_WDQ_OSC_DELTA_INDEX_F0:RW:0:4:=0x04 + 0x00000055, // 260: PI_MR20_DATA_0:RW:24:8:=0x00 PI_MR17_DATA_0:RW:16:8:=0x00 PI_MR16_DATA_0:RW:8:8:=0x00 PI_MR15_DATA_0:RW:0:8:=0x55 + 0x55083C5A, // 261: PI_MR15_DATA_1:RW:24:8:=0x55 PI_MR13_DATA_1:RW+:16:8:=0x00 PI_MR40_DATA_0:RW:8:8:=0x3c PI_MR32_DATA_0:RW:0:8:=0x5a + 0x5A000000, // 262: PI_MR32_DATA_1:RW:24:8:=0x5a PI_MR20_DATA_1:RW:16:8:=0x00 PI_MR17_DATA_1:RW:8:8:=0x00 PI_MR16_DATA_1:RW:0:8:=0x00 + 0x0055083C, // 263: PI_MR16_DATA_2:RW:24:8:=0x00 PI_MR15_DATA_2:RW:16:8:=0x55 PI_MR13_DATA_2:RW+:8:8:=0x00 PI_MR40_DATA_1:RW:0:8:=0x3c + 0x3C5A0000, // 264: PI_MR40_DATA_2:RW:24:8:=0x3c PI_MR32_DATA_2:RW:16:8:=0x5a PI_MR20_DATA_2:RW:8:8:=0x00 PI_MR17_DATA_2:RW:0:8:=0x00 + 0x00005508, // 265: PI_MR17_DATA_3:RW:24:8:=0x00 PI_MR16_DATA_3:RW:16:8:=0x00 PI_MR15_DATA_3:RW:8:8:=0x55 PI_MR13_DATA_3:RW+:0:8:=0x00 + 0x0C3C5A00, // 266: PI_CKE_MUX_0:RW_D:24:4:=0x0c PI_MR40_DATA_3:RW:16:8:=0x3c PI_MR32_DATA_3:RW:8:8:=0x5a PI_MR20_DATA_3:RW:0:8:=0x00 + 0x080F0E0D, // 267: PI_CS_MUX_0:RW_D:24:4:=0x08 PI_CKE_MUX_3:RW_D:16:4:=0x0f PI_CKE_MUX_2:RW_D:8:4:=0x0e PI_CKE_MUX_1:RW_D:0:4:=0x0d + 0x000B0A09, // 268: PI_RESET_N_MUX_0:RW_D:24:4:=0x00 PI_CS_MUX_3:RW_D:16:4:=0x0b PI_CS_MUX_2:RW_D:8:4:=0x0a PI_CS_MUX_1:RW_D:0:4:=0x09 + 0x00030201, // 269: PI_MRSINGLE_DATA_0:RW:24:8:=0x00 PI_RESET_N_MUX_3:RW_D:16:4:=0x03 PI_RESET_N_MUX_2:RW_D:8:4:=0x02 PI_RESET_N_MUX_1:RW_D:0:4:=0x01 + 0x01000000, // 270: PI_ZQ_CAL_START_MAP_0:RW_D:24:4:=0x01 PI_MRSINGLE_DATA_3:RW:16:8:=0x00 PI_MRSINGLE_DATA_2:RW:8:8:=0x00 PI_MRSINGLE_DATA_1:RW:0:8:=0x00 + 0x04020201, // 271: PI_ZQ_CAL_START_MAP_2:RW_D:24:4:=0x04 PI_ZQ_CAL_LATCH_MAP_1:RW_D:16:4:=0x02 PI_ZQ_CAL_START_MAP_1:RW_D:8:4:=0x02 PI_ZQ_CAL_LATCH_MAP_0:RW_D:0:4:=0x01 + 0x00080804, // 272: PI_ZQ_CAL_LATCH_MAP_3:RW_D:16:4:=0x08 PI_ZQ_CAL_START_MAP_3:RW_D:8:4:=0x08 PI_ZQ_CAL_LATCH_MAP_2:RW_D:0:4:=0x04 + 0x00000000, // 273: PI_DQS_OSC_BASE_VALUE_1_0:RW+:16:16:=0x0000 PI_DQS_OSC_BASE_VALUE_0_0:RW+:0:16:=0x0000 + 0x00000000, // 274: PI_DQS_OSC_BASE_VALUE_1_1:RW+:16:16:=0x0000 PI_DQS_OSC_BASE_VALUE_0_1:RW+:0:16:=0x0000 + 0x00310004, // 275: PI_MR11_DATA_F0_0:RW+:24:8:=0x00 PI_MR3_DATA_F0_0:RW+:16:8:=0x31 PI_MR2_DATA_F0_0:RW+:8:8:=0x00 PI_MR1_DATA_F0_0:RW+:0:8:=0x04 + 0x00054D4D, // 276: PI_MR23_DATA_F0_0:RW:24:8:=0x00 PI_MR22_DATA_F0_0:RW+:16:8:=0x00 PI_MR14_DATA_F0_0:RW+:8:8:=0x4d PI_MR12_DATA_F0_0:RW+:0:8:=0x4d + 0x55F12D54, // 277: PI_MR11_DATA_F1_0:RW+:24:8:=0x00 PI_MR3_DATA_F1_0:RW+:16:8:=0x31 PI_MR2_DATA_F1_0:RW+:8:8:=0x2d PI_MR1_DATA_F1_0:RW+:0:8:=0x54 + 0x00162226, // 278: PI_MR23_DATA_F1_0:RW:24:8:=0x00 PI_MR22_DATA_F1_0:RW+:16:8:=0x00 PI_MR14_DATA_F1_0:RW+:8:8:=0x4d PI_MR12_DATA_F1_0:RW+:0:8:=0x4d + 0x65F13F74, // 279: PI_MR11_DATA_F2_0:RW+:24:8:=0x00 PI_MR3_DATA_F2_0:RW+:16:8:=0x31 PI_MR2_DATA_F2_0:RW+:8:8:=0x3f PI_MR1_DATA_F2_0:RW+:0:8:=0x74 + 0x00161919, // 280: PI_MR23_DATA_F2_0:RW:24:8:=0x00 PI_MR22_DATA_F2_0:RW+:16:8:=0x00 PI_MR14_DATA_F2_0:RW+:8:8:=0x4d PI_MR12_DATA_F2_0:RW+:0:8:=0x4d + 0x00310004, // 281: PI_MR11_DATA_F0_1:RW+:24:8:=0x00 PI_MR3_DATA_F0_1:RW+:16:8:=0x31 PI_MR2_DATA_F0_1:RW+:8:8:=0x00 PI_MR1_DATA_F0_1:RW+:0:8:=0x04 + 0x00054D4D, // 282: PI_MR23_DATA_F0_1:RW:24:8:=0x00 PI_MR22_DATA_F0_1:RW+:16:8:=0x00 PI_MR14_DATA_F0_1:RW+:8:8:=0x4d PI_MR12_DATA_F0_1:RW+:0:8:=0x4d + 0x55F12D54, // 283: PI_MR11_DATA_F1_1:RW+:24:8:=0x00 PI_MR3_DATA_F1_1:RW+:16:8:=0x31 PI_MR2_DATA_F1_1:RW+:8:8:=0x2d PI_MR1_DATA_F1_1:RW+:0:8:=0x54 + 0x003E2226, // 284: PI_MR23_DATA_F1_1:RW:24:8:=0x00 PI_MR22_DATA_F1_1:RW+:16:8:=0x00 PI_MR14_DATA_F1_1:RW+:8:8:=0x4d PI_MR12_DATA_F1_1:RW+:0:8:=0x4d + 0x65F13F74, // 285: PI_MR11_DATA_F2_1:RW+:24:8:=0x00 PI_MR3_DATA_F2_1:RW+:16:8:=0x31 PI_MR2_DATA_F2_1:RW+:8:8:=0x3f PI_MR1_DATA_F2_1:RW+:0:8:=0x74 + 0x003E1919, // 286: PI_MR23_DATA_F2_1:RW:24:8:=0x00 PI_MR22_DATA_F2_1:RW+:16:8:=0x00 PI_MR14_DATA_F2_1:RW+:8:8:=0x4d PI_MR12_DATA_F2_1:RW+:0:8:=0x4d + 0x00310004, // 287: PI_MR11_DATA_F0_2:RW+:24:8:=0x00 PI_MR3_DATA_F0_2:RW+:16:8:=0x31 PI_MR2_DATA_F0_2:RW+:8:8:=0x00 PI_MR1_DATA_F0_2:RW+:0:8:=0x04 + 0x00054D4D, // 288: PI_MR23_DATA_F0_2:RW:24:8:=0x00 PI_MR22_DATA_F0_2:RW+:16:8:=0x00 PI_MR14_DATA_F0_2:RW+:8:8:=0x4d PI_MR12_DATA_F0_2:RW+:0:8:=0x4d + 0x55F12D54, // 289: PI_MR11_DATA_F1_2:RW+:24:8:=0x00 PI_MR3_DATA_F1_2:RW+:16:8:=0x31 PI_MR2_DATA_F1_2:RW+:8:8:=0x2d PI_MR1_DATA_F1_2:RW+:0:8:=0x54 + 0x00362226, // 290: PI_MR23_DATA_F1_2:RW:24:8:=0x00 PI_MR22_DATA_F1_2:RW+:16:8:=0x00 PI_MR14_DATA_F1_2:RW+:8:8:=0x4d PI_MR12_DATA_F1_2:RW+:0:8:=0x4d + 0x65F13F74, // 291: PI_MR11_DATA_F2_2:RW+:24:8:=0x00 PI_MR3_DATA_F2_2:RW+:16:8:=0x31 PI_MR2_DATA_F2_2:RW+:8:8:=0x3f PI_MR1_DATA_F2_2:RW+:0:8:=0x74 + 0x00361919, // 292: PI_MR23_DATA_F2_2:RW:24:8:=0x00 PI_MR22_DATA_F2_2:RW+:16:8:=0x00 PI_MR14_DATA_F2_2:RW+:8:8:=0x4d PI_MR12_DATA_F2_2:RW+:0:8:=0x4d + 0x00310004, // 293: PI_MR11_DATA_F0_3:RW+:24:8:=0x00 PI_MR3_DATA_F0_3:RW+:16:8:=0x31 PI_MR2_DATA_F0_3:RW+:8:8:=0x00 PI_MR1_DATA_F0_3:RW+:0:8:=0x04 + 0x00054D4D, // 294: PI_MR23_DATA_F0_3:RW:24:8:=0x00 PI_MR22_DATA_F0_3:RW+:16:8:=0x00 PI_MR14_DATA_F0_3:RW+:8:8:=0x4d PI_MR12_DATA_F0_3:RW+:0:8:=0x4d + 0x55F12D54, // 295: PI_MR11_DATA_F1_3:RW+:24:8:=0x00 PI_MR3_DATA_F1_3:RW+:16:8:=0x31 PI_MR2_DATA_F1_3:RW+:8:8:=0x2d PI_MR1_DATA_F1_3:RW+:0:8:=0x54 + 0x003E2226, // 296: PI_MR23_DATA_F1_3:RW:24:8:=0x00 PI_MR22_DATA_F1_3:RW+:16:8:=0x00 PI_MR14_DATA_F1_3:RW+:8:8:=0x4d PI_MR12_DATA_F1_3:RW+:0:8:=0x4d + 0x65F13F74, // 297: PI_MR11_DATA_F2_3:RW+:24:8:=0x00 PI_MR3_DATA_F2_3:RW+:16:8:=0x31 PI_MR2_DATA_F2_3:RW+:8:8:=0x3f PI_MR1_DATA_F2_3:RW+:0:8:=0x74 + 0x003E1919, // 298: PI_MR23_DATA_F2_3:RW:24:8:=0x00 PI_MR22_DATA_F2_3:RW+:16:8:=0x00 PI_MR14_DATA_F2_3:RW+:8:8:=0x4d PI_MR12_DATA_F2_3:RW+:0:8:=0x4d + 0x00000000 // 299: PI_PARITY_ERROR_REGIF:RW:0:11:=0x0000 +}; + + +uint32_t DDR_PHY_registers[] = +{ + 0x000004F0, // 0: PHY_IO_PAD_DELAY_TIMING_BYPASS_0:RW:16:4:=0x00 PHY_CLK_WR_BYPASS_SLAVE_DELAY_0:RW:0:11:=0x04f0 + 0x00000000, // 1: PHY_WRITE_PATH_LAT_ADD_BYPASS_0:RW:16:3:=0x00 PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0:RW:0:10:=0x0000 + 0x00030200, // 2: PHY_CLK_BYPASS_OVERRIDE_0:RW:24:1:=0x00 PHY_BYPASS_TWO_CYC_PREAMBLE_0:RW:16:2:=0x03 PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0:RW:0:10:=0x0200 + 0x00000000, // 3: PHY_SW_WRDQ3_SHIFT_0:RW:24:6:=0x00 PHY_SW_WRDQ2_SHIFT_0:RW:16:6:=0x00 PHY_SW_WRDQ1_SHIFT_0:RW:8:6:=0x00 PHY_SW_WRDQ0_SHIFT_0:RW:0:6:=0x00 + 0x00000000, // 4: PHY_SW_WRDQ7_SHIFT_0:RW:24:6:=0x00 PHY_SW_WRDQ6_SHIFT_0:RW:16:6:=0x00 PHY_SW_WRDQ5_SHIFT_0:RW:8:6:=0x00 PHY_SW_WRDQ4_SHIFT_0:RW:0:6:=0x00 + 0x01030000, // 5: PHY_PER_CS_TRAINING_MULTICAST_EN_0:RW_D:24:1:=0x01 PHY_PER_RANK_CS_MAP_0:RW+:16:2:=0x03 PHY_SW_WRDQS_SHIFT_0:RW:8:4:=0x00 PHY_SW_WRDM_SHIFT_0:RW:0:6:=0x00 + 0x00010000, // 6: PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0:RW:24:5:=0x00 PHY_LP4_BOOT_RDDATA_EN_DLY_0:RW:16:5:=0x01 PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0:RW:8:2:=0x00 PHY_PER_CS_TRAINING_INDEX_0:RW+:0:1:=0x00 + 0x01030004, // 7: PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0:RW:24:5:=0x01 PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0:RW:16:2:=0x03 PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0:RW:8:4:=0x00 PHY_LP4_BOOT_RPTR_UPDATE_0:RW:0:4:=0x04 + 0x01000000, // 8: PHY_LPBK_DFX_TIMEOUT_EN_0:RW:24:1:=0x01 PHY_LPBK_CONTROL_0:RW:8:9:=0x0000 PHY_CTRL_LPBK_EN_0:RW:0:2:=0x00 + 0x00000000, // 9: PHY_AUTO_TIMING_MARGIN_CONTROL_0:RW:0:32:=0x00000000 + 0x00000000, // 10: PHY_AUTO_TIMING_MARGIN_OBS_0:RD:0:28:=0x00000000 + 0x01000001, // 11: PHY_RDLVL_MULTI_PATT_ENABLE_0:RW:24:1:=0x00 PHY_PRBS_PATTERN_MASK_0:RW:8:9:=0x0000 PHY_PRBS_PATTERN_START_0:RW_D:0:7:=0x01 + 0x00000400, // 12: PHY_VREF_TRAIN_OBS_0:RD:16:7:=0x00 PHY_VREF_INITIAL_STEPSIZE_0:RW:8:6:=0x04 PHY_RDLVL_MULTI_PATT_RST_DISABLE_0:RW:0:1:=0x00 + 0x000800C0, // 13: SC_PHY_SNAP_OBS_REGS_0:WR:24:1:=0x00 PHY_GATE_ERROR_DELAY_SELECT_0:RW:16:4:=0x08 PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0:RW:0:10:=0x00c0 + 0x060100CC, // 14: PHY_MEM_CLASS_0:RW:24:3:=0x06 PHY_LPDDR_0:RW:16:1:=0x01 PHY_GATE_SMPL1_SLAVE_DELAY_0:RW:0:9:=0x00cc + 0x00030066, // 15: ON_FLY_GATE_ADJUST_EN_0:RW:16:2:=0x03 PHY_GATE_SMPL2_SLAVE_DELAY_0:RW:0:9:=0x0066 + 0x00000000, // 16: PHY_GATE_TRACKING_OBS_0:RD:0:32:=0x00000000 + 0x00000001, // 17: PHY_LP4_PST_AMBLE_0:RW:8:2:=0x00 PHY_DFI40_POLARITY_0:RW:0:1:=0x01 + 0x0000AAAA, // 18: PHY_RDLVL_PATT8_0:RW:0:32:=0x0000AAAA + 0x00005555, // 19: PHY_RDLVL_PATT9_0:RW:0:32:=0x00005555 + 0x0000B5B5, // 20: PHY_RDLVL_PATT10_0:RW:0:32:=0x0000B5B5 + 0x00004A4A, // 21: PHY_RDLVL_PATT11_0:RW:0:32:=0x00004A4A + 0x00005656, // 22: PHY_RDLVL_PATT12_0:RW:0:32:=0x00005656 + 0x0000A9A9, // 23: PHY_RDLVL_PATT13_0:RW:0:32:=0x0000A9A9 + 0x0000A9A9, // 24: PHY_RDLVL_PATT14_0:RW:0:32:=0x0000A9A9 + 0x0000B5B5, // 25: PHY_RDLVL_PATT15_0:RW:0:32:=0x0000B5B5 + 0x00000000, // 26: PHY_RDDQ_ENC_OBS_SELECT_0:RW:24:3:=0x00 PHY_MASTER_DLY_LOCK_OBS_SELECT_0:RW:16:4:=0x00 PHY_SW_FIFO_PTR_RST_DISABLE_0:RW:8:1:=0x00 PHY_SLAVE_LOOP_CNT_UPDATE_0:RW:0:3:=0x00 + 0x00000000, // 27: PHY_FIFO_PTR_OBS_SELECT_0:RW:24:4:=0x00 PHY_WR_SHIFT_OBS_SELECT_0:RW:16:4:=0x00 PHY_WR_ENC_OBS_SELECT_0:RW:8:4:=0x00 PHY_RDDQS_DQ_ENC_OBS_SELECT_0:RW:0:4:=0x00 + 0x2A000000, // 28: PHY_WRLVL_PER_START_0:RW:24:8:=0x2A PHY_WRLVL_ALGO_0:RW:16:2:=0x00 SC_PHY_LVL_DEBUG_CONT_0:WR:8:1:=0x00 PHY_LVL_DEBUG_MODE_0:RW:0:1:=0x00 + 0x00000808, // 29: PHY_DQ_MASK_0:RW:16:8:=0x00 PHY_WRLVL_UPDT_WAIT_CNT_0:RW:8:4:=0x08 PHY_WRLVL_CAPTURE_CNT_0:RW:0:6:=0x08 + 0x04080000, // 30: PHY_GTLVL_UPDT_WAIT_CNT_0:RW:24:4:=0x04 PHY_GTLVL_CAPTURE_CNT_0:RW:16:6:=0x00 PHY_GTLVL_PER_START_0:RW:0:10:=0x0000 + 0x00000408, // 31: PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0:RW:24:5:=0x00 PHY_RDLVL_OP_MODE_0:RW:16:2:=0x00 PHY_RDLVL_UPDT_WAIT_CNT_0:RW:8:4:=0x04 PHY_RDLVL_CAPTURE_CNT_0:RW:0:6:=0x08 + 0x10300000, // 32: PHY_WDQLVL_BURST_CNT_0:RW:24:6:=0x10 PHY_WDQLVL_CLK_JITTER_TOLERANCE_0:RW:16:8:=0x20 PHY_RDLVL_DATA_MASK_0:RW:8:8:=0x00 PHY_RDLVL_PERIODIC_OBS_SELECT_0:RW:0:8:=0x00 + 0x0C002007, // 33: PHY_WDQLVL_UPDT_WAIT_CNT_0:RW:24:4:=0x0c PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0:RW:8:11:=0x0020 PHY_WDQLVL_PATT_0:RW:0:3:=0x07 + 0x00000000, // 34: SC_PHY_WDQLVL_CLR_PREV_RESULTS_0:WR:16:1:=0x00 PHY_WDQLVL_PERIODIC_OBS_SELECT_0:RW:8:8:=0x00 PHY_WDQLVL_DQDM_OBS_SELECT_0:RW:0:4:=0x00 + 0x00000100, // 35: PHY_WDQLVL_DATADM_MASK_0:RW:0:9:=0x0100 + 0x55555555, // 36: PHY_USER_PATT0_0:RW:0:32:=0x55555555 + 0xAAAAAAAA, // 37: PHY_USER_PATT1_0:RW:0:32:=0xAAAAAAAA + 0x55555555, // 38: PHY_USER_PATT2_0:RW:0:32:=0x55555555 + 0xAAAAAAAA, // 39: PHY_USER_PATT3_0:RW:0:32:=0xAAAAAAAA + 0x00005555, // 40: PHY_NTP_MULT_TRAIN_0:RW:16:1:=0x00 PHY_USER_PATT4_0:RW:0:16:=0x5555 + 0x01000100, // 41: PHY_NTP_PERIOD_THRESHOLD_0:RW:16:10:=0x0100 PHY_NTP_EARLY_THRESHOLD_0:RW:0:10:=0x0100 + 0x00800180, // 42: PHY_NTP_PERIOD_THRESHOLD_MAX_0:RW:16:10:=0x0080 PHY_NTP_PERIOD_THRESHOLD_MIN_0:RW:0:10:=0x0180 + 0x00000001, // 43: PHY_FIFO_PTR_OBS_0:RD:16:8:=0x00 SC_PHY_MANUAL_CLEAR_0:WR:8:6:=0x00 PHY_CALVL_VREF_DRIVING_SLICE_0:RW:0:1:=0x01 + 0x00000000, // 44: PHY_LPBK_RESULT_OBS_0:RD:0:32:=0x00000000 + 0x00000000, // 45: PHY_MASTER_DLY_LOCK_OBS_0:RD:16:11:=0x0000 PHY_LPBK_ERROR_COUNT_OBS_0:RD:0:16:=0x0000 + 0x00000000, // 46: PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0:RD:24:8:=0x00 PHY_MEAS_DLY_STEP_VALUE_0:RD:16:8:=0x00 PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0:RD:8:7:=0x00 PHY_RDDQ_SLV_DLY_ENC_OBS_0:RD:0:7:=0x00 + 0x00000000, // 47: PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0:RD:24:7:=0x00 PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0:RD:8:11:=0x0000 PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0:RD:0:8:=0x00 + 0x00000000, // 48: PHY_WR_SHIFT_OBS_0:RD:16:3:=0x00 PHY_WR_ADDER_SLV_DLY_ENC_OBS_0:RD:8:8:=0x00 PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0:RD:0:8:=0x00 + 0x00000000, // 49: PHY_WRLVL_HARD1_DELAY_OBS_0:RD:16:10:=0x0000 PHY_WRLVL_HARD0_DELAY_OBS_0:RD:0:10:=0x0000 + 0x00000000, // 50: PHY_WRLVL_STATUS_OBS_0:RD:0:17:=0x000000 + 0x00000000, // 51: PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0:RD:16:10:=0x0000 PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0:RD:0:10:=0x0000 + 0x00000000, // 52: PHY_GTLVL_HARD0_DELAY_OBS_0:RD:16:14:=0x0000 PHY_WRLVL_ERROR_OBS_0:RD:0:16:=0x0000 + 0x00000000, // 53: PHY_GTLVL_HARD1_DELAY_OBS_0:RD:0:14:=0x0000 + 0x00000000, // 54: PHY_GTLVL_STATUS_OBS_0:RD:0:18:=0x000000 + 0x00000000, // 55: PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0:RD:16:10:=0x0000 PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0:RD:0:10:=0x0000 + 0x00000000, // 56: PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0:RD:0:2:=0x00 + 0x00000000, // 57: PHY_RDLVL_STATUS_OBS_0:RD:0:32:=0x00000000 + 0x00000000, // 58: PHY_RDLVL_PERIODIC_OBS_0:RD:0:32:=0x00000000 + 0x00000000, // 59: PHY_WDQLVL_DQDM_TE_DLY_OBS_0:RD:16:11:=0x0000 PHY_WDQLVL_DQDM_LE_DLY_OBS_0:RD:0:11:=0x0000 + 0x00000000, // 60: PHY_WDQLVL_STATUS_OBS_0:RD:0:32:=0x00000000 + 0x00000000, // 61: PHY_WDQLVL_PERIODIC_OBS_0:RD:0:32:=0x00000000 + 0x00000000, // 62: PHY_DDL_MODE_0:RW:0:31:=0x00000000 + 0x00000000, // 63: PHY_DDL_MASK_0:RW:0:6:=0x00 + 0x00000000, // 64: PHY_DDL_TEST_OBS_0:RD:0:32:=0x00000000 + 0x00000000, // 65: PHY_DDL_TEST_MSTR_DLY_OBS_0:RD:0:32:=0x00000000 + 0x00000104, // 66: PHY_RX_CAL_OVERRIDE_0:RW:24:1:=0x00 SC_PHY_RX_CAL_START_0:WR:16:1:=0x00 PHY_LP4_WDQS_OE_EXTEND_0:RW:8:1:=0x00 PHY_DDL_TRACK_UPD_THRESHOLD_0:RW:0:8:=0x04 + 0x00000120, // 67: PHY_RX_CAL_DQ0_0:RW_D+:16:9:=0x0000 PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0:RW:8:1:=0x01 PHY_RX_CAL_SAMPLE_WAIT_0:RW:0:8:=0x20 + 0x00000000, // 68: PHY_RX_CAL_DQ2_0:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQ1_0:RW_D+:0:9:=0x0000 + 0x00000000, // 69: PHY_RX_CAL_DQ4_0:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQ3_0:RW_D+:0:9:=0x0000 + 0x00000000, // 70: PHY_RX_CAL_DQ6_0:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQ5_0:RW_D+:0:9:=0x0000 + 0x00000000, // 71: PHY_RX_CAL_DQ7_0:RW_D+:0:9:=0x0000 + 0x00000000, // 72: PHY_RX_CAL_DM_0:RW_D+:0:18:=0x000000 + 0x00000000, // 73: PHY_RX_CAL_FDBK_0:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQS_0:RW_D+:0:9:=0x0000 + 0x00000000, // 74: PHY_RX_CAL_LOCK_OBS_0:RD:16:9:=0x0000 PHY_RX_CAL_OBS_0:RD:0:11:=0x0000 + 0x00000001, // 75: PHY_RX_CAL_COMP_VAL_0:RW:24:1:=0x00 PHY_RX_CAL_DIFF_ADJUST_0:RW:16:7:=0x00 PHY_RX_CAL_SE_ADJUST_0:RW:8:7:=0x00 PHY_RX_CAL_DISABLE_0:RW_D:0:1:=0x01 + 0x07FF0000, // 76: PHY_PAD_RX_BIAS_EN_0:RW:16:11:=0x07ff PHY_RX_CAL_INDEX_MASK_0:RW:0:12:=0x0000 + 0x0080081F, // 77: PHY_DATA_DC_WEIGHT_0:RW:24:2:=0x00 PHY_DATA_DC_CAL_TIMEOUT_0:RW:16:8:=0x80 PHY_DATA_DC_CAL_SAMPLE_WAIT_0:RW:8:8:=0x08 PHY_STATIC_TOG_DISABLE_0:RW:0:5:=0x1f + 0x00081020, // 78: PHY_DATA_DC_ADJUST_DIRECT_0:RW:24:1:=0x00 PHY_DATA_DC_ADJUST_THRSHLD_0:RW:16:8:=0x08 PHY_DATA_DC_ADJUST_SAMPLE_CNT_0:RW:8:8:=0x10 PHY_DATA_DC_ADJUST_START_0:RW:0:6:=0x20 + 0x04010000, // 79: PHY_FDBK_PWR_CTRL_0:RW:24:3:=0x04 PHY_DATA_DC_SW_RANK_0:RW+:16:2:=0x01 PHY_DATA_DC_CAL_START_0:RW+:8:1:=0x00 PHY_DATA_DC_CAL_POLARITY_0:RW:0:1:=0x00 + 0x00000001, // 80: PHY_SLICE_PWR_RDC_DISABLE_0:RW:24:1:=0x00 PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0:RW_D:16:1:=0x00 PHY_RDPATH_GATE_DISABLE_0:RW_D:8:1:=0x00 PHY_SLV_DLY_CTRL_GATE_DISABLE_0:RW_D:0:1:=0x00 + 0x00000000, // 81: PHY_DS_FSM_ERROR_INFO_0:RD:16:14:=0x0000 PHY_PARITY_ERROR_REGIF_0:RW:0:11:=0x0000 + 0x00000000, // 82: SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0:WR:16:14:=0x0000 PHY_DS_FSM_ERROR_INFO_MASK_0:RW:0:14:=0x0000 + 0x00000100, // 83: SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0:WR:16:5:=0x00 PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0:RW:8:5:=0x01 PHY_DS_TRAIN_CALIB_ERROR_INFO_0:RD:0:5:=0x00 + 0x05CC0C05, // 84: PHY_DQS_TSEL_ENABLE_0:RW+:24:3:=0x01 PHY_DQ_TSEL_SELECT_0:RW+:8:16:=0x4408 PHY_DQ_TSEL_ENABLE_0:RW+:0:3:=0x01 + 0x1603CC0C, // 85: PHY_VREF_INITIAL_START_POINT_0:RW+:24:7:=0x20 PHY_TWO_CYC_PREAMBLE_0:RW+:16:2:=0x03 PHY_DQS_TSEL_SELECT_0:RW+:0:16:=0x4408 + 0x2000012F, // 86: PHY_NTP_WDQ_STEP_SIZE_0:RW+:24:8:=0x20 PHY_NTP_TRAIN_EN_0:RW+:16:1:=0x00 PHY_VREF_TRAINING_CTRL_0:RW+:8:2:=0x01 PHY_VREF_INITIAL_STOP_POINT_0:RW+:0:7:=0x25 + 0x07FF0200, // 87: PHY_NTP_WDQ_STOP_0:RW+:16:11:=0x07FF PHY_NTP_WDQ_START_0:RW+:0:11:=0x0200 + 0x0000DD01, // 88: PHY_SW_WDQLVL_DVW_MIN_EN_0:RW+:24:1:=0x00 PHY_WDQLVL_DVW_MIN_0:RW+:8:10:=0x00dd PHY_NTP_WDQ_BIT_EN_0:RW+:0:8:=0x01 + 0x00000303, // 89: PHY_PAD_RX_DCD_0_0:RW+:24:5:=0x00 PHY_PAD_TX_DCD_0:RW+:16:5:=0x00 PHY_FAST_LVL_EN_0:RW+:8:4:=0x03 PHY_WDQLVL_PER_START_OFFSET_0:RW+:0:6:=0x03 + 0x00000000, // 90: PHY_PAD_RX_DCD_4_0:RW+:24:5:=0x00 PHY_PAD_RX_DCD_3_0:RW+:16:5:=0x00 PHY_PAD_RX_DCD_2_0:RW+:8:5:=0x00 PHY_PAD_RX_DCD_1_0:RW+:0:5:=0x00 + 0x00000000, // 91: PHY_PAD_DM_RX_DCD_0:RW+:24:5:=0x00 PHY_PAD_RX_DCD_7_0:RW+:16:5:=0x00 PHY_PAD_RX_DCD_6_0:RW+:8:5:=0x00 PHY_PAD_RX_DCD_5_0:RW+:0:5:=0x00 + 0x00030000, // 92: PHY_PAD_DSLICE_IO_CFG_0:RW+:16:6:=0x00 PHY_PAD_FDBK_RX_DCD_0:RW+:8:5:=0x00 PHY_PAD_DQS_RX_DCD_0:RW+:0:5:=0x00 + 0x00000000, // 93: PHY_RDDQ1_SLAVE_DELAY_0:RW+:16:10:=0x0000 PHY_RDDQ0_SLAVE_DELAY_0:RW+:0:10:=0x0000 + 0x00000000, // 94: PHY_RDDQ3_SLAVE_DELAY_0:RW+:16:10:=0x0000 PHY_RDDQ2_SLAVE_DELAY_0:RW+:0:10:=0x0000 + 0x00000000, // 95: PHY_RDDQ5_SLAVE_DELAY_0:RW+:16:10:=0x0000 PHY_RDDQ4_SLAVE_DELAY_0:RW+:0:10:=0x0000 + 0x00000000, // 96: PHY_RDDQ7_SLAVE_DELAY_0:RW+:16:10:=0x0000 PHY_RDDQ6_SLAVE_DELAY_0:RW+:0:10:=0x0000 + 0x00050000, // 97: PHY_DATA_DC_CAL_CLK_SEL_0:RW+:16:3:=0x02 PHY_RDDM_SLAVE_DELAY_0:RW+:0:10:=0x0000 + 0x51515042, // 98: PHY_DQS_OE_TIMING_0:RW+:24:8:=0x51 PHY_DQ_TSEL_WR_TIMING_0:RW+:16:8:=0x51 PHY_DQ_TSEL_RD_TIMING_0:RW+:8:8:=0x50 PHY_DQ_OE_TIMING_0:RW+:0:8:=0x42 + 0x31C06000, // 99: PHY_DQS_TSEL_WR_TIMING_0:RW+:24:8:=0x31 PHY_DQS_OE_RD_TIMING_0:RW+:16:8:=0xc0 PHY_DQS_TSEL_RD_TIMING_0:RW+:8:8:=0x60 PHY_IO_PAD_DELAY_TIMING_0:RW+:0:4:=0x00 + 0x07A000A0, // 100: PHY_PAD_VREF_CTRL_DQ_0:RW+:16:12:=0x069f PHY_VREF_SETTING_TIME_0:RW+:0:16:=0x0004 + 0x00C0C001, // 101: PHY_RDDATA_EN_IE_DLY_0:RW+:24:2:=0x00 PHY_DQS_IE_TIMING_0:RW+:16:8:=0xc0 PHY_DQ_IE_TIMING_0:RW+:8:8:=0xc0 PHY_PER_CS_TRAINING_EN_0:RW+:0:1:=0x01 + 0x0E0D0100, // 102: PHY_RDDATA_EN_OE_DLY_0:RW+:24:5:=0x0e PHY_RDDATA_EN_TSEL_DLY_0:RW+:16:5:=0x0d PHY_DBI_MODE_0:RW+:8:1:=0x00 PHY_IE_MODE_0:RW+:0:2:=0x00 + 0x10001000, // 103: PHY_MASTER_DELAY_STEP_0:RW+:24:6:=0x10 PHY_MASTER_DELAY_START_0:RW+:8:11:=0x0010 PHY_SW_MASTER_MODE_0:RW+:0:4:=0x00 + 0x0C063E42, // 104: PHY_WRLVL_DLY_STEP_0:RW+:24:8:=0x0c PHY_RPTR_UPDATE_0:RW+:16:4:=0x06 PHY_MASTER_DELAY_HALF_MEASURE_0:RW+:8:8:=0x3e PHY_MASTER_DELAY_WAIT_0:RW+:0:8:=0x42 + 0x0F0C3701, // 105: PHY_GTLVL_RESP_WAIT_CNT_0:RW+:24:5:=0x0f PHY_GTLVL_DLY_STEP_0:RW+:16:4:=0x0c PHY_WRLVL_RESP_WAIT_CNT_0:RW+:8:6:=0x37 PHY_WRLVL_DLY_FINE_STEP_0:RW+:0:4:=0x01 + 0x01000140, // 106: PHY_GTLVL_FINAL_STEP_0:RW+:16:10:=0x0100 PHY_GTLVL_BACK_STEP_0:RW+:0:10:=0x0140 + 0x0C000120, // 107: PHY_RDLVL_DLY_STEP_0:RW+:24:4:=0x0c PHY_TOGGLE_PRE_SUPPORT_0:RW+:16:1:=0x00 PHY_WDQLVL_QTR_DLY_STEP_0:RW+:8:4:=0x01 PHY_WDQLVL_DLY_STEP_0:RW+:0:8:=0x20 + 0x00000322, // 108: PHY_RDLVL_MAX_EDGE_0:RW+:0:10:=0x0322 + 0x0A0000D0, // 109: PHY_RDLVL_PER_START_OFFSET_0:RW+:24:6:=0x0A PHY_SW_RDLVL_DVW_MIN_EN_0:RW+:16:1:=0x00 PHY_RDLVL_DVW_MIN_0:RW+:0:10:=0x00d0 + 0x00030200, // 110: PHY_DATA_DC_INIT_DISABLE_0:RW+:16:2:=0x00 PHY_WRPATH_GATE_TIMING_0:RW+:8:3:=0x02 PHY_WRPATH_GATE_DISABLE_0:RW+:0:2:=0x00 + 0x02800000, // 111: PHY_DATA_DC_DQ_INIT_SLV_DELAY_0:RW+:16:11:=0x0280 PHY_DATA_DC_DQS_INIT_SLV_DELAY_0:RW+:0:10:=0x0000 + 0x80800000, // 112: PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0:RW+:24:8:=0x80 PHY_DATA_DC_DM_CLK_SE_THRSHLD_0:RW+:16:8:=0x80 PHY_DATA_DC_WDQLVL_ENABLE_0:RW+:8:1:=0x01 PHY_DATA_DC_WRLVL_ENABLE_0:RW+:0:1:=0x01 + 0x000E2010, // 113: PHY_RDDATA_EN_DLY_0:RW+:16:5:=0x0e PHY_MEAS_DLY_STEP_ENABLE_0:RW+:8:6:=0x20 PHY_WDQ_OSC_DELTA_0:RW+:0:7:=0x10 + 0x56247310, // 114: PHY_DQ_DM_SWIZZLE0_0:RW+:0:32:=0x56247310 + 0x00000008, // 115: PHY_DQ_DM_SWIZZLE1_0:RW+:0:4:=0x08 + 0x02800280, // 116: PHY_CLK_WRDQ1_SLAVE_DELAY_0:RW+:16:11:=0x0280 PHY_CLK_WRDQ0_SLAVE_DELAY_0:RW+:0:11:=0x0280 + 0x02800280, // 117: PHY_CLK_WRDQ3_SLAVE_DELAY_0:RW+:16:11:=0x0280 PHY_CLK_WRDQ2_SLAVE_DELAY_0:RW+:0:11:=0x0280 + 0x02800280, // 118: PHY_CLK_WRDQ5_SLAVE_DELAY_0:RW+:16:11:=0x0280 PHY_CLK_WRDQ4_SLAVE_DELAY_0:RW+:0:11:=0x0280 + 0x02800280, // 119: PHY_CLK_WRDQ7_SLAVE_DELAY_0:RW+:16:11:=0x0280 PHY_CLK_WRDQ6_SLAVE_DELAY_0:RW+:0:11:=0x0280 + 0x00000280, // 120: PHY_CLK_WRDQS_SLAVE_DELAY_0:RW+:16:10:=0x0000 PHY_CLK_WRDM_SLAVE_DELAY_0:RW+:0:11:=0x0280 + 0x0000A000, // 121: PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0:RW+:8:10:=0x00a0 PHY_WRLVL_THRESHOLD_ADJUST_0:RW+:0:2:=0x00 + 0x00A000A0, // 122: PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0 + 0x00A000A0, // 123: PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0 + 0x00A000A0, // 124: PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0 + 0x00A000A0, // 125: PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0 + 0x00A000A0, // 126: PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0 + 0x00A000A0, // 127: PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0 + 0x00A000A0, // 128: PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0 + 0x00A000A0, // 129: PHY_RDDQS_DM_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0 + 0x01C200A0, // 130: PHY_RDDQS_GATE_SLAVE_DELAY_0:RW+:16:10:=0x01c2 PHY_RDDQS_DM_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0 + 0x01A00005, // 131: PHY_WRLVL_DELAY_EARLY_THRESHOLD_0:RW+:16:10:=0x01A0 PHY_WRITE_PATH_LAT_ADD_0:RW+:8:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_0:RW+:0:4:=0x05 + 0x00000000, // 132: PHY_WRLVL_EARLY_FORCE_ZERO_0:RW+:16:1:=0x00 PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0:RW+:0:10:=0x0000 + 0x00060000, // 133: PHY_GTLVL_LAT_ADJ_START_0:RW+:16:4:=0x06 PHY_GTLVL_RDDQS_SLV_DLY_START_0:RW+:0:10:=0x0000 + 0x00080200, // 134: PHY_NTP_PASS_0:RW+:24:1:=0x00 PHY_NTP_WRLAT_START_0:RW+:16:4:=0x08 PHY_WDQLVL_DQDM_SLV_DLY_START_0:RW+:0:11:=0x0200 + 0x00000000, // 135: PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0:RW+:0:10:=0x0000 + 0x20202020, // 136: PHY_DATA_DC_DQ2_CLK_ADJUST_0:RW+:24:8:=0x20 PHY_DATA_DC_DQ1_CLK_ADJUST_0:RW+:16:8:=0x20 PHY_DATA_DC_DQ0_CLK_ADJUST_0:RW+:8:8:=0x20 PHY_DATA_DC_DQS_CLK_ADJUST_0:RW+:0:8:=0x20 + 0x20202020, // 137: PHY_DATA_DC_DQ6_CLK_ADJUST_0:RW+:24:8:=0x20 PHY_DATA_DC_DQ5_CLK_ADJUST_0:RW+:16:8:=0x20 PHY_DATA_DC_DQ4_CLK_ADJUST_0:RW+:8:8:=0x20 PHY_DATA_DC_DQ3_CLK_ADJUST_0:RW+:0:8:=0x20 + 0xF0F02020, // 138: PHY_DSLICE_PAD_BOOSTPN_SETTING_0:RW+:16:16:=0x0000 PHY_DATA_DC_DM_CLK_ADJUST_0:RW+:8:8:=0x20 PHY_DATA_DC_DQ7_CLK_ADJUST_0:RW+:0:8:=0x20 + 0x00000000, // 139: PHY_DQS_FFE_0:RW+:16:2:=0x00 PHY_DQ_FFE_0:RW+:8:2:=0x00 PHY_DSLICE_PAD_RX_CTLE_SETTING_0:RW+:0:6:=0x00 + 0x00000000, // 140: + 0x00000000, // 141: + 0x00000000, // 142: + 0x00000000, // 143: + 0x00000000, // 144: + 0x00000000, // 145: + 0x00000000, // 146: + 0x00000000, // 147: + 0x00000000, // 148: + 0x00000000, // 149: + 0x00000000, // 150: + 0x00000000, // 151: + 0x00000000, // 152: + 0x00000000, // 153: + 0x00000000, // 154: + 0x00000000, // 155: + 0x00000000, // 156: + 0x00000000, // 157: + 0x00000000, // 158: + 0x00000000, // 159: + 0x00000000, // 160: + 0x00000000, // 161: + 0x00000000, // 162: + 0x00000000, // 163: + 0x00000000, // 164: + 0x00000000, // 165: + 0x00000000, // 166: + 0x00000000, // 167: + 0x00000000, // 168: + 0x00000000, // 169: + 0x00000000, // 170: + 0x00000000, // 171: + 0x00000000, // 172: + 0x00000000, // 173: + 0x00000000, // 174: + 0x00000000, // 175: + 0x00000000, // 176: + 0x00000000, // 177: + 0x00000000, // 178: + 0x00000000, // 179: + 0x00000000, // 180: + 0x00000000, // 181: + 0x00000000, // 182: + 0x00000000, // 183: + 0x00000000, // 184: + 0x00000000, // 185: + 0x00000000, // 186: + 0x00000000, // 187: + 0x00000000, // 188: + 0x00000000, // 189: + 0x00000000, // 190: + 0x00000000, // 191: + 0x00000000, // 192: + 0x00000000, // 193: + 0x00000000, // 194: + 0x00000000, // 195: + 0x00000000, // 196: + 0x00000000, // 197: + 0x00000000, // 198: + 0x00000000, // 199: + 0x00000000, // 200: + 0x00000000, // 201: + 0x00000000, // 202: + 0x00000000, // 203: + 0x00000000, // 204: + 0x00000000, // 205: + 0x00000000, // 206: + 0x00000000, // 207: + 0x00000000, // 208: + 0x00000000, // 209: + 0x00000000, // 210: + 0x00000000, // 211: + 0x00000000, // 212: + 0x00000000, // 213: + 0x00000000, // 214: + 0x00000000, // 215: + 0x00000000, // 216: + 0x00000000, // 217: + 0x00000000, // 218: + 0x00000000, // 219: + 0x00000000, // 220: + 0x00000000, // 221: + 0x00000000, // 222: + 0x00000000, // 223: + 0x00000000, // 224: + 0x00000000, // 225: + 0x00000000, // 226: + 0x00000000, // 227: + 0x00000000, // 228: + 0x00000000, // 229: + 0x00000000, // 230: + 0x00000000, // 231: + 0x00000000, // 232: + 0x00000000, // 233: + 0x00000000, // 234: + 0x00000000, // 235: + 0x00000000, // 236: + 0x00000000, // 237: + 0x00000000, // 238: + 0x00000000, // 239: + 0x00000000, // 240: + 0x00000000, // 241: + 0x00000000, // 242: + 0x00000000, // 243: + 0x00000000, // 244: + 0x00000000, // 245: + 0x00000000, // 246: + 0x00000000, // 247: + 0x00000000, // 248: + 0x00000000, // 249: + 0x00000000, // 250: + 0x00000000, // 251: + 0x00000000, // 252: + 0x00000000, // 253: + 0x00000000, // 254: + 0x00000000, // 255: + 0x000004F0, // 256: PHY_IO_PAD_DELAY_TIMING_BYPASS_1:RW:16:4:=0x00 PHY_CLK_WR_BYPASS_SLAVE_DELAY_1:RW:0:11:=0x04f0 + 0x00000000, // 257: PHY_WRITE_PATH_LAT_ADD_BYPASS_1:RW:16:3:=0x00 PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1:RW:0:10:=0x0000 + 0x00030200, // 258: PHY_CLK_BYPASS_OVERRIDE_1:RW:24:1:=0x00 PHY_BYPASS_TWO_CYC_PREAMBLE_1:RW:16:2:=0x03 PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1:RW:0:10:=0x0200 + 0x00000000, // 259: PHY_SW_WRDQ3_SHIFT_1:RW:24:6:=0x00 PHY_SW_WRDQ2_SHIFT_1:RW:16:6:=0x00 PHY_SW_WRDQ1_SHIFT_1:RW:8:6:=0x00 PHY_SW_WRDQ0_SHIFT_1:RW:0:6:=0x00 + 0x00000000, // 260: PHY_SW_WRDQ7_SHIFT_1:RW:24:6:=0x00 PHY_SW_WRDQ6_SHIFT_1:RW:16:6:=0x00 PHY_SW_WRDQ5_SHIFT_1:RW:8:6:=0x00 PHY_SW_WRDQ4_SHIFT_1:RW:0:6:=0x00 + 0x01030000, // 261: PHY_PER_CS_TRAINING_MULTICAST_EN_1:RW_D:24:1:=0x01 PHY_PER_RANK_CS_MAP_1:RW+:16:2:=0x03 PHY_SW_WRDQS_SHIFT_1:RW:8:4:=0x00 PHY_SW_WRDM_SHIFT_1:RW:0:6:=0x00 + 0x00010000, // 262: PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1:RW:24:5:=0x00 PHY_LP4_BOOT_RDDATA_EN_DLY_1:RW:16:5:=0x01 PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1:RW:8:2:=0x00 PHY_PER_CS_TRAINING_INDEX_1:RW+:0:1:=0x00 + 0x01030004, // 263: PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1:RW:24:5:=0x01 PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1:RW:16:2:=0x03 PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1:RW:8:4:=0x00 PHY_LP4_BOOT_RPTR_UPDATE_1:RW:0:4:=0x04 + 0x01000000, // 264: PHY_LPBK_DFX_TIMEOUT_EN_1:RW:24:1:=0x01 PHY_LPBK_CONTROL_1:RW:8:9:=0x0000 PHY_CTRL_LPBK_EN_1:RW:0:2:=0x00 + 0x00000000, // 265: PHY_AUTO_TIMING_MARGIN_CONTROL_1:RW:0:32:=0x00000000 + 0x00000000, // 266: PHY_AUTO_TIMING_MARGIN_OBS_1:RD:0:28:=0x00000000 + 0x01000001, // 267: PHY_RDLVL_MULTI_PATT_ENABLE_1:RW:24:1:=0x00 PHY_PRBS_PATTERN_MASK_1:RW:8:9:=0x0000 PHY_PRBS_PATTERN_START_1:RW_D:0:7:=0x01 + 0x00000400, // 268: PHY_VREF_TRAIN_OBS_1:RD:16:7:=0x00 PHY_VREF_INITIAL_STEPSIZE_1:RW:8:6:=0x04 PHY_RDLVL_MULTI_PATT_RST_DISABLE_1:RW:0:1:=0x00 + 0x000800C0, // 269: SC_PHY_SNAP_OBS_REGS_1:WR:24:1:=0x00 PHY_GATE_ERROR_DELAY_SELECT_1:RW:16:4:=0x08 PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1:RW:0:10:=0x00c0 + 0x060100CC, // 270: PHY_MEM_CLASS_1:RW:24:3:=0x06 PHY_LPDDR_1:RW:16:1:=0x01 PHY_GATE_SMPL1_SLAVE_DELAY_1:RW:0:9:=0x00cc + 0x00030066, // 271: ON_FLY_GATE_ADJUST_EN_1:RW:16:2:=0x03 PHY_GATE_SMPL2_SLAVE_DELAY_1:RW:0:9:=0x0066 + 0x00000000, // 272: PHY_GATE_TRACKING_OBS_1:RD:0:32:=0x00000000 + 0x00000001, // 273: PHY_LP4_PST_AMBLE_1:RW:8:2:=0x00 PHY_DFI40_POLARITY_1:RW:0:1:=0x01 + 0x0000AAAA, // 274: PHY_RDLVL_PATT8_1:RW:0:32:=0x0000AAAA + 0x00005555, // 275: PHY_RDLVL_PATT9_1:RW:0:32:=0x00005555 + 0x0000B5B5, // 276: PHY_RDLVL_PATT10_1:RW:0:32:=0x0000B5B5 + 0x00004A4A, // 277: PHY_RDLVL_PATT11_1:RW:0:32:=0x00004A4A + 0x00005656, // 278: PHY_RDLVL_PATT12_1:RW:0:32:=0x00005656 + 0x0000A9A9, // 279: PHY_RDLVL_PATT13_1:RW:0:32:=0x0000A9A9 + 0x0000A9A9, // 280: PHY_RDLVL_PATT14_1:RW:0:32:=0x0000A9A9 + 0x0000B5B5, // 281: PHY_RDLVL_PATT15_1:RW:0:32:=0x0000B5B5 + 0x00000000, // 282: PHY_RDDQ_ENC_OBS_SELECT_1:RW:24:3:=0x00 PHY_MASTER_DLY_LOCK_OBS_SELECT_1:RW:16:4:=0x00 PHY_SW_FIFO_PTR_RST_DISABLE_1:RW:8:1:=0x00 PHY_SLAVE_LOOP_CNT_UPDATE_1:RW:0:3:=0x00 + 0x00000000, // 283: PHY_FIFO_PTR_OBS_SELECT_1:RW:24:4:=0x00 PHY_WR_SHIFT_OBS_SELECT_1:RW:16:4:=0x00 PHY_WR_ENC_OBS_SELECT_1:RW:8:4:=0x00 PHY_RDDQS_DQ_ENC_OBS_SELECT_1:RW:0:4:=0x00 + 0x2A000000, // 284: PHY_WRLVL_PER_START_1:RW:24:8:=0x2A PHY_WRLVL_ALGO_1:RW:16:2:=0x00 SC_PHY_LVL_DEBUG_CONT_1:WR:8:1:=0x00 PHY_LVL_DEBUG_MODE_1:RW:0:1:=0x00 + 0x00000808, // 285: PHY_DQ_MASK_1:RW:16:8:=0x00 PHY_WRLVL_UPDT_WAIT_CNT_1:RW:8:4:=0x08 PHY_WRLVL_CAPTURE_CNT_1:RW:0:6:=0x08 + 0x04080000, // 286: PHY_GTLVL_UPDT_WAIT_CNT_1:RW:24:4:=0x04 PHY_GTLVL_CAPTURE_CNT_1:RW:16:6:=0x00 PHY_GTLVL_PER_START_1:RW:0:10:=0x0000 + 0x00000408, // 287: PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1:RW:24:5:=0x00 PHY_RDLVL_OP_MODE_1:RW:16:2:=0x00 PHY_RDLVL_UPDT_WAIT_CNT_1:RW:8:4:=0x04 PHY_RDLVL_CAPTURE_CNT_1:RW:0:6:=0x08 + 0x10300000, // 288: PHY_WDQLVL_BURST_CNT_1:RW:24:6:=0x10 PHY_WDQLVL_CLK_JITTER_TOLERANCE_1:RW:16:8:=0x20 PHY_RDLVL_DATA_MASK_1:RW:8:8:=0x00 PHY_RDLVL_PERIODIC_OBS_SELECT_1:RW:0:8:=0x00 + 0x0C002007, // 289: PHY_WDQLVL_UPDT_WAIT_CNT_1:RW:24:4:=0x0c PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1:RW:8:11:=0x0020 PHY_WDQLVL_PATT_1:RW:0:3:=0x07 + 0x00000000, // 290: SC_PHY_WDQLVL_CLR_PREV_RESULTS_1:WR:16:1:=0x00 PHY_WDQLVL_PERIODIC_OBS_SELECT_1:RW:8:8:=0x00 PHY_WDQLVL_DQDM_OBS_SELECT_1:RW:0:4:=0x00 + 0x00000100, // 291: PHY_WDQLVL_DATADM_MASK_1:RW:0:9:=0x0100 + 0x55555555, // 292: PHY_USER_PATT0_1:RW:0:32:=0x55555555 + 0xAAAAAAAA, // 293: PHY_USER_PATT1_1:RW:0:32:=0xAAAAAAAA + 0x55555555, // 294: PHY_USER_PATT2_1:RW:0:32:=0x55555555 + 0xAAAAAAAA, // 295: PHY_USER_PATT3_1:RW:0:32:=0xAAAAAAAA + 0x00005555, // 296: PHY_NTP_MULT_TRAIN_1:RW:16:1:=0x00 PHY_USER_PATT4_1:RW:0:16:=0x5555 + 0x01000100, // 297: PHY_NTP_PERIOD_THRESHOLD_1:RW:16:10:=0x0100 PHY_NTP_EARLY_THRESHOLD_1:RW:0:10:=0x0100 + 0x00800180, // 298: PHY_NTP_PERIOD_THRESHOLD_MAX_1:RW:16:10:=0x0080 PHY_NTP_PERIOD_THRESHOLD_MIN_1:RW:0:10:=0x0180 + 0x00000000, // 299: PHY_FIFO_PTR_OBS_1:RD:16:8:=0x00 SC_PHY_MANUAL_CLEAR_1:WR:8:6:=0x00 PHY_CALVL_VREF_DRIVING_SLICE_1:RW:0:1:=0x00 + 0x00000000, // 300: PHY_LPBK_RESULT_OBS_1:RD:0:32:=0x00000000 + 0x00000000, // 301: PHY_MASTER_DLY_LOCK_OBS_1:RD:16:11:=0x0000 PHY_LPBK_ERROR_COUNT_OBS_1:RD:0:16:=0x0000 + 0x00000000, // 302: PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1:RD:24:8:=0x00 PHY_MEAS_DLY_STEP_VALUE_1:RD:16:8:=0x00 PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1:RD:8:7:=0x00 PHY_RDDQ_SLV_DLY_ENC_OBS_1:RD:0:7:=0x00 + 0x00000000, // 303: PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1:RD:24:7:=0x00 PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1:RD:8:11:=0x0000 PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1:RD:0:8:=0x00 + 0x00000000, // 304: PHY_WR_SHIFT_OBS_1:RD:16:3:=0x00 PHY_WR_ADDER_SLV_DLY_ENC_OBS_1:RD:8:8:=0x00 PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1:RD:0:8:=0x00 + 0x00000000, // 305: PHY_WRLVL_HARD1_DELAY_OBS_1:RD:16:10:=0x0000 PHY_WRLVL_HARD0_DELAY_OBS_1:RD:0:10:=0x0000 + 0x00000000, // 306: PHY_WRLVL_STATUS_OBS_1:RD:0:17:=0x000000 + 0x00000000, // 307: PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1:RD:16:10:=0x0000 PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1:RD:0:10:=0x0000 + 0x00000000, // 308: PHY_GTLVL_HARD0_DELAY_OBS_1:RD:16:14:=0x0000 PHY_WRLVL_ERROR_OBS_1:RD:0:16:=0x0000 + 0x00000000, // 309: PHY_GTLVL_HARD1_DELAY_OBS_1:RD:0:14:=0x0000 + 0x00000000, // 310: PHY_GTLVL_STATUS_OBS_1:RD:0:18:=0x000000 + 0x00000000, // 311: PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1:RD:16:10:=0x0000 PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1:RD:0:10:=0x0000 + 0x00000000, // 312: PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1:RD:0:2:=0x00 + 0x00000000, // 313: PHY_RDLVL_STATUS_OBS_1:RD:0:32:=0x00000000 + 0x00000000, // 314: PHY_RDLVL_PERIODIC_OBS_1:RD:0:32:=0x00000000 + 0x00000000, // 315: PHY_WDQLVL_DQDM_TE_DLY_OBS_1:RD:16:11:=0x0000 PHY_WDQLVL_DQDM_LE_DLY_OBS_1:RD:0:11:=0x0000 + 0x00000000, // 316: PHY_WDQLVL_STATUS_OBS_1:RD:0:32:=0x00000000 + 0x00000000, // 317: PHY_WDQLVL_PERIODIC_OBS_1:RD:0:32:=0x00000000 + 0x00000000, // 318: PHY_DDL_MODE_1:RW:0:31:=0x00000000 + 0x00000000, // 319: PHY_DDL_MASK_1:RW:0:6:=0x00 + 0x00000000, // 320: PHY_DDL_TEST_OBS_1:RD:0:32:=0x00000000 + 0x00000000, // 321: PHY_DDL_TEST_MSTR_DLY_OBS_1:RD:0:32:=0x00000000 + 0x00000104, // 322: PHY_RX_CAL_OVERRIDE_1:RW:24:1:=0x00 SC_PHY_RX_CAL_START_1:WR:16:1:=0x00 PHY_LP4_WDQS_OE_EXTEND_1:RW:8:1:=0x00 PHY_DDL_TRACK_UPD_THRESHOLD_1:RW:0:8:=0x04 + 0x00000120, // 323: PHY_RX_CAL_DQ0_1:RW_D+:16:9:=0x0000 PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1:RW:8:1:=0x01 PHY_RX_CAL_SAMPLE_WAIT_1:RW:0:8:=0x20 + 0x00000000, // 324: PHY_RX_CAL_DQ2_1:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQ1_1:RW_D+:0:9:=0x0000 + 0x00000000, // 325: PHY_RX_CAL_DQ4_1:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQ3_1:RW_D+:0:9:=0x0000 + 0x00000000, // 326: PHY_RX_CAL_DQ6_1:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQ5_1:RW_D+:0:9:=0x0000 + 0x00000000, // 327: PHY_RX_CAL_DQ7_1:RW_D+:0:9:=0x0000 + 0x00000000, // 328: PHY_RX_CAL_DM_1:RW_D+:0:18:=0x000000 + 0x00000000, // 329: PHY_RX_CAL_FDBK_1:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQS_1:RW_D+:0:9:=0x0000 + 0x00000000, // 330: PHY_RX_CAL_LOCK_OBS_1:RD:16:9:=0x0000 PHY_RX_CAL_OBS_1:RD:0:11:=0x0000 + 0x00000001, // 331: PHY_RX_CAL_COMP_VAL_1:RW:24:1:=0x00 PHY_RX_CAL_DIFF_ADJUST_1:RW:16:7:=0x00 PHY_RX_CAL_SE_ADJUST_1:RW:8:7:=0x00 PHY_RX_CAL_DISABLE_1:RW_D:0:1:=0x01 + 0x07FF0000, // 332: PHY_PAD_RX_BIAS_EN_1:RW:16:11:=0x07ff PHY_RX_CAL_INDEX_MASK_1:RW:0:12:=0x0000 + 0x0080081F, // 333: PHY_DATA_DC_WEIGHT_1:RW:24:2:=0x00 PHY_DATA_DC_CAL_TIMEOUT_1:RW:16:8:=0x80 PHY_DATA_DC_CAL_SAMPLE_WAIT_1:RW:8:8:=0x08 PHY_STATIC_TOG_DISABLE_1:RW:0:5:=0x1f + 0x00081020, // 334: PHY_DATA_DC_ADJUST_DIRECT_1:RW:24:1:=0x00 PHY_DATA_DC_ADJUST_THRSHLD_1:RW:16:8:=0x08 PHY_DATA_DC_ADJUST_SAMPLE_CNT_1:RW:8:8:=0x10 PHY_DATA_DC_ADJUST_START_1:RW:0:6:=0x20 + 0x04010000, // 335: PHY_FDBK_PWR_CTRL_1:RW:24:3:=0x04 PHY_DATA_DC_SW_RANK_1:RW+:16:2:=0x01 PHY_DATA_DC_CAL_START_1:RW+:8:1:=0x00 PHY_DATA_DC_CAL_POLARITY_1:RW:0:1:=0x00 + 0x00000001, // 336: PHY_SLICE_PWR_RDC_DISABLE_1:RW:24:1:=0x00 PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1:RW_D:16:1:=0x00 PHY_RDPATH_GATE_DISABLE_1:RW_D:8:1:=0x00 PHY_SLV_DLY_CTRL_GATE_DISABLE_1:RW_D:0:1:=0x00 + 0x00000000, // 337: PHY_DS_FSM_ERROR_INFO_1:RD:16:14:=0x0000 PHY_PARITY_ERROR_REGIF_1:RW:0:11:=0x0000 + 0x00000000, // 338: SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1:WR:16:14:=0x0000 PHY_DS_FSM_ERROR_INFO_MASK_1:RW:0:14:=0x0000 + 0x00000100, // 339: SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1:WR:16:5:=0x00 PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1:RW:8:5:=0x01 PHY_DS_TRAIN_CALIB_ERROR_INFO_1:RD:0:5:=0x00 + 0x05CC0C05, // 340: PHY_DQS_TSEL_ENABLE_1:RW+:24:3:=0x01 PHY_DQ_TSEL_SELECT_1:RW+:8:16:=0x4408 PHY_DQ_TSEL_ENABLE_1:RW+:0:3:=0x01 + 0x1603CC0C, // 341: PHY_VREF_INITIAL_START_POINT_1:RW+:24:7:=0x20 PHY_TWO_CYC_PREAMBLE_1:RW+:16:2:=0x03 PHY_DQS_TSEL_SELECT_1:RW+:0:16:=0x4408 + 0x2000012F, // 342: PHY_NTP_WDQ_STEP_SIZE_1:RW+:24:8:=0x20 PHY_NTP_TRAIN_EN_1:RW+:16:1:=0x00 PHY_VREF_TRAINING_CTRL_1:RW+:8:2:=0x01 PHY_VREF_INITIAL_STOP_POINT_1:RW+:0:7:=0x25 + 0x07FF0200, // 343: PHY_NTP_WDQ_STOP_1:RW+:16:11:=0x07FF PHY_NTP_WDQ_START_1:RW+:0:11:=0x0200 + 0x0000DD01, // 344: PHY_SW_WDQLVL_DVW_MIN_EN_1:RW+:24:1:=0x00 PHY_WDQLVL_DVW_MIN_1:RW+:8:10:=0x00dd PHY_NTP_WDQ_BIT_EN_1:RW+:0:8:=0x01 + 0x00000303, // 345: PHY_PAD_RX_DCD_0_1:RW+:24:5:=0x00 PHY_PAD_TX_DCD_1:RW+:16:5:=0x00 PHY_FAST_LVL_EN_1:RW+:8:4:=0x03 PHY_WDQLVL_PER_START_OFFSET_1:RW+:0:6:=0x03 + 0x00000000, // 346: PHY_PAD_RX_DCD_4_1:RW+:24:5:=0x00 PHY_PAD_RX_DCD_3_1:RW+:16:5:=0x00 PHY_PAD_RX_DCD_2_1:RW+:8:5:=0x00 PHY_PAD_RX_DCD_1_1:RW+:0:5:=0x00 + 0x00000000, // 347: PHY_PAD_DM_RX_DCD_1:RW+:24:5:=0x00 PHY_PAD_RX_DCD_7_1:RW+:16:5:=0x00 PHY_PAD_RX_DCD_6_1:RW+:8:5:=0x00 PHY_PAD_RX_DCD_5_1:RW+:0:5:=0x00 + 0x00030000, // 348: PHY_PAD_DSLICE_IO_CFG_1:RW+:16:6:=0x00 PHY_PAD_FDBK_RX_DCD_1:RW+:8:5:=0x00 PHY_PAD_DQS_RX_DCD_1:RW+:0:5:=0x00 + 0x00000000, // 349: PHY_RDDQ1_SLAVE_DELAY_1:RW+:16:10:=0x0000 PHY_RDDQ0_SLAVE_DELAY_1:RW+:0:10:=0x0000 + 0x00000000, // 350: PHY_RDDQ3_SLAVE_DELAY_1:RW+:16:10:=0x0000 PHY_RDDQ2_SLAVE_DELAY_1:RW+:0:10:=0x0000 + 0x00000000, // 351: PHY_RDDQ5_SLAVE_DELAY_1:RW+:16:10:=0x0000 PHY_RDDQ4_SLAVE_DELAY_1:RW+:0:10:=0x0000 + 0x00000000, // 352: PHY_RDDQ7_SLAVE_DELAY_1:RW+:16:10:=0x0000 PHY_RDDQ6_SLAVE_DELAY_1:RW+:0:10:=0x0000 + 0x00050000, // 353: PHY_DATA_DC_CAL_CLK_SEL_1:RW+:16:3:=0x02 PHY_RDDM_SLAVE_DELAY_1:RW+:0:10:=0x0000 + 0x51515042, // 354: PHY_DQS_OE_TIMING_1:RW+:24:8:=0x51 PHY_DQ_TSEL_WR_TIMING_1:RW+:16:8:=0x51 PHY_DQ_TSEL_RD_TIMING_1:RW+:8:8:=0x50 PHY_DQ_OE_TIMING_1:RW+:0:8:=0x42 + 0x31C06000, // 355: PHY_DQS_TSEL_WR_TIMING_1:RW+:24:8:=0x31 PHY_DQS_OE_RD_TIMING_1:RW+:16:8:=0xc0 PHY_DQS_TSEL_RD_TIMING_1:RW+:8:8:=0x60 PHY_IO_PAD_DELAY_TIMING_1:RW+:0:4:=0x00 + 0x07A000A0, // 356: PHY_PAD_VREF_CTRL_DQ_1:RW+:16:12:=0x069f PHY_VREF_SETTING_TIME_1:RW+:0:16:=0x0004 + 0x00C0C001, // 357: PHY_RDDATA_EN_IE_DLY_1:RW+:24:2:=0x00 PHY_DQS_IE_TIMING_1:RW+:16:8:=0xc0 PHY_DQ_IE_TIMING_1:RW+:8:8:=0xc0 PHY_PER_CS_TRAINING_EN_1:RW+:0:1:=0x01 + 0x0E0D0100, // 358: PHY_RDDATA_EN_OE_DLY_1:RW+:24:5:=0x0e PHY_RDDATA_EN_TSEL_DLY_1:RW+:16:5:=0x0d PHY_DBI_MODE_1:RW+:8:1:=0x00 PHY_IE_MODE_1:RW+:0:2:=0x00 + 0x10001000, // 359: PHY_MASTER_DELAY_STEP_1:RW+:24:6:=0x10 PHY_MASTER_DELAY_START_1:RW+:8:11:=0x0010 PHY_SW_MASTER_MODE_1:RW+:0:4:=0x00 + 0x0C063E42, // 360: PHY_WRLVL_DLY_STEP_1:RW+:24:8:=0x0c PHY_RPTR_UPDATE_1:RW+:16:4:=0x06 PHY_MASTER_DELAY_HALF_MEASURE_1:RW+:8:8:=0x3e PHY_MASTER_DELAY_WAIT_1:RW+:0:8:=0x42 + 0x0F0C3701, // 361: PHY_GTLVL_RESP_WAIT_CNT_1:RW+:24:5:=0x0f PHY_GTLVL_DLY_STEP_1:RW+:16:4:=0x0c PHY_WRLVL_RESP_WAIT_CNT_1:RW+:8:6:=0x37 PHY_WRLVL_DLY_FINE_STEP_1:RW+:0:4:=0x01 + 0x01000140, // 362: PHY_GTLVL_FINAL_STEP_1:RW+:16:10:=0x0100 PHY_GTLVL_BACK_STEP_1:RW+:0:10:=0x0140 + 0x0C000120, // 363: PHY_RDLVL_DLY_STEP_1:RW+:24:4:=0x0c PHY_TOGGLE_PRE_SUPPORT_1:RW+:16:1:=0x00 PHY_WDQLVL_QTR_DLY_STEP_1:RW+:8:4:=0x01 PHY_WDQLVL_DLY_STEP_1:RW+:0:8:=0x20 + 0x00000322, // 364: PHY_RDLVL_MAX_EDGE_1:RW+:0:10:=0x0322 + 0x0A0000D0, // 365: PHY_RDLVL_PER_START_OFFSET_1:RW+:24:6:=0x0A PHY_SW_RDLVL_DVW_MIN_EN_1:RW+:16:1:=0x00 PHY_RDLVL_DVW_MIN_1:RW+:0:10:=0x00d0 + 0x00030200, // 366: PHY_DATA_DC_INIT_DISABLE_1:RW+:16:2:=0x00 PHY_WRPATH_GATE_TIMING_1:RW+:8:3:=0x02 PHY_WRPATH_GATE_DISABLE_1:RW+:0:2:=0x00 + 0x02800000, // 367: PHY_DATA_DC_DQ_INIT_SLV_DELAY_1:RW+:16:11:=0x0280 PHY_DATA_DC_DQS_INIT_SLV_DELAY_1:RW+:0:10:=0x0000 + 0x80800000, // 368: PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1:RW+:24:8:=0x80 PHY_DATA_DC_DM_CLK_SE_THRSHLD_1:RW+:16:8:=0x80 PHY_DATA_DC_WDQLVL_ENABLE_1:RW+:8:1:=0x01 PHY_DATA_DC_WRLVL_ENABLE_1:RW+:0:1:=0x01 + 0x000E2010, // 369: PHY_RDDATA_EN_DLY_1:RW+:16:5:=0x0e PHY_MEAS_DLY_STEP_ENABLE_1:RW+:8:6:=0x20 PHY_WDQ_OSC_DELTA_1:RW+:0:7:=0x10 + 0x52016437, // 370: PHY_DQ_DM_SWIZZLE0_1:RW+:0:32:=0x76543210 + 0x00000008, // 371: PHY_DQ_DM_SWIZZLE1_1:RW+:0:4:=0x08 + 0x02800280, // 372: PHY_CLK_WRDQ1_SLAVE_DELAY_1:RW+:16:11:=0x0280 PHY_CLK_WRDQ0_SLAVE_DELAY_1:RW+:0:11:=0x0280 + 0x02800280, // 373: PHY_CLK_WRDQ3_SLAVE_DELAY_1:RW+:16:11:=0x0280 PHY_CLK_WRDQ2_SLAVE_DELAY_1:RW+:0:11:=0x0280 + 0x02800280, // 374: PHY_CLK_WRDQ5_SLAVE_DELAY_1:RW+:16:11:=0x0280 PHY_CLK_WRDQ4_SLAVE_DELAY_1:RW+:0:11:=0x0280 + 0x02800280, // 375: PHY_CLK_WRDQ7_SLAVE_DELAY_1:RW+:16:11:=0x0280 PHY_CLK_WRDQ6_SLAVE_DELAY_1:RW+:0:11:=0x0280 + 0x00000280, // 376: PHY_CLK_WRDQS_SLAVE_DELAY_1:RW+:16:10:=0x0000 PHY_CLK_WRDM_SLAVE_DELAY_1:RW+:0:11:=0x0280 + 0x0000A000, // 377: PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1:RW+:8:10:=0x00a0 PHY_WRLVL_THRESHOLD_ADJUST_1:RW+:0:2:=0x00 + 0x00A000A0, // 378: PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0 + 0x00A000A0, // 379: PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0 + 0x00A000A0, // 380: PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0 + 0x00A000A0, // 381: PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0 + 0x00A000A0, // 382: PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0 + 0x00A000A0, // 383: PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0 + 0x00A000A0, // 384: PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0 + 0x00A000A0, // 385: PHY_RDDQS_DM_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0 + 0x01C200A0, // 386: PHY_RDDQS_GATE_SLAVE_DELAY_1:RW+:16:10:=0x01c2 PHY_RDDQS_DM_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0 + 0x01A00005, // 387: PHY_WRLVL_DELAY_EARLY_THRESHOLD_1:RW+:16:10:=0x01A0 PHY_WRITE_PATH_LAT_ADD_1:RW+:8:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_1:RW+:0:4:=0x05 + 0x00000000, // 388: PHY_WRLVL_EARLY_FORCE_ZERO_1:RW+:16:1:=0x00 PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1:RW+:0:10:=0x0000 + 0x00060000, // 389: PHY_GTLVL_LAT_ADJ_START_1:RW+:16:4:=0x06 PHY_GTLVL_RDDQS_SLV_DLY_START_1:RW+:0:10:=0x0000 + 0x00080200, // 390: PHY_NTP_PASS_1:RW+:24:1:=0x00 PHY_NTP_WRLAT_START_1:RW+:16:4:=0x08 PHY_WDQLVL_DQDM_SLV_DLY_START_1:RW+:0:11:=0x0200 + 0x00000000, // 391: PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1:RW+:0:10:=0x0000 + 0x20202020, // 392: PHY_DATA_DC_DQ2_CLK_ADJUST_1:RW+:24:8:=0x20 PHY_DATA_DC_DQ1_CLK_ADJUST_1:RW+:16:8:=0x20 PHY_DATA_DC_DQ0_CLK_ADJUST_1:RW+:8:8:=0x20 PHY_DATA_DC_DQS_CLK_ADJUST_1:RW+:0:8:=0x20 + 0x20202020, // 393: PHY_DATA_DC_DQ6_CLK_ADJUST_1:RW+:24:8:=0x20 PHY_DATA_DC_DQ5_CLK_ADJUST_1:RW+:16:8:=0x20 PHY_DATA_DC_DQ4_CLK_ADJUST_1:RW+:8:8:=0x20 PHY_DATA_DC_DQ3_CLK_ADJUST_1:RW+:0:8:=0x20 + 0xF0F02020, // 394: PHY_DSLICE_PAD_BOOSTPN_SETTING_1:RW+:16:16:=0x0000 PHY_DATA_DC_DM_CLK_ADJUST_1:RW+:8:8:=0x20 PHY_DATA_DC_DQ7_CLK_ADJUST_1:RW+:0:8:=0x20 + 0x00000000, // 395: PHY_DQS_FFE_1:RW+:16:2:=0x00 PHY_DQ_FFE_1:RW+:8:2:=0x00 PHY_DSLICE_PAD_RX_CTLE_SETTING_1:RW+:0:6:=0x00 + 0x00000000, // 396: + 0x00000000, // 397: + 0x00000000, // 398: + 0x00000000, // 399: + 0x00000000, // 400: + 0x00000000, // 401: + 0x00000000, // 402: + 0x00000000, // 403: + 0x00000000, // 404: + 0x00000000, // 405: + 0x00000000, // 406: + 0x00000000, // 407: + 0x00000000, // 408: + 0x00000000, // 409: + 0x00000000, // 410: + 0x00000000, // 411: + 0x00000000, // 412: + 0x00000000, // 413: + 0x00000000, // 414: + 0x00000000, // 415: + 0x00000000, // 416: + 0x00000000, // 417: + 0x00000000, // 418: + 0x00000000, // 419: + 0x00000000, // 420: + 0x00000000, // 421: + 0x00000000, // 422: + 0x00000000, // 423: + 0x00000000, // 424: + 0x00000000, // 425: + 0x00000000, // 426: + 0x00000000, // 427: + 0x00000000, // 428: + 0x00000000, // 429: + 0x00000000, // 430: + 0x00000000, // 431: + 0x00000000, // 432: + 0x00000000, // 433: + 0x00000000, // 434: + 0x00000000, // 435: + 0x00000000, // 436: + 0x00000000, // 437: + 0x00000000, // 438: + 0x00000000, // 439: + 0x00000000, // 440: + 0x00000000, // 441: + 0x00000000, // 442: + 0x00000000, // 443: + 0x00000000, // 444: + 0x00000000, // 445: + 0x00000000, // 446: + 0x00000000, // 447: + 0x00000000, // 448: + 0x00000000, // 449: + 0x00000000, // 450: + 0x00000000, // 451: + 0x00000000, // 452: + 0x00000000, // 453: + 0x00000000, // 454: + 0x00000000, // 455: + 0x00000000, // 456: + 0x00000000, // 457: + 0x00000000, // 458: + 0x00000000, // 459: + 0x00000000, // 460: + 0x00000000, // 461: + 0x00000000, // 462: + 0x00000000, // 463: + 0x00000000, // 464: + 0x00000000, // 465: + 0x00000000, // 466: + 0x00000000, // 467: + 0x00000000, // 468: + 0x00000000, // 469: + 0x00000000, // 470: + 0x00000000, // 471: + 0x00000000, // 472: + 0x00000000, // 473: + 0x00000000, // 474: + 0x00000000, // 475: + 0x00000000, // 476: + 0x00000000, // 477: + 0x00000000, // 478: + 0x00000000, // 479: + 0x00000000, // 480: + 0x00000000, // 481: + 0x00000000, // 482: + 0x00000000, // 483: + 0x00000000, // 484: + 0x00000000, // 485: + 0x00000000, // 486: + 0x00000000, // 487: + 0x00000000, // 488: + 0x00000000, // 489: + 0x00000000, // 490: + 0x00000000, // 491: + 0x00000000, // 492: + 0x00000000, // 493: + 0x00000000, // 494: + 0x00000000, // 495: + 0x00000000, // 496: + 0x00000000, // 497: + 0x00000000, // 498: + 0x00000000, // 499: + 0x00000000, // 500: + 0x00000000, // 501: + 0x00000000, // 502: + 0x00000000, // 503: + 0x00000000, // 504: + 0x00000000, // 505: + 0x00000000, // 506: + 0x00000000, // 507: + 0x00000000, // 508: + 0x00000000, // 509: + 0x00000000, // 510: + 0x00000000, // 511: + 0x000004F0, // 512: PHY_IO_PAD_DELAY_TIMING_BYPASS_2:RW:16:4:=0x00 PHY_CLK_WR_BYPASS_SLAVE_DELAY_2:RW:0:11:=0x04f0 + 0x00000000, // 513: PHY_WRITE_PATH_LAT_ADD_BYPASS_2:RW:16:3:=0x00 PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2:RW:0:10:=0x0000 + 0x00030200, // 514: PHY_CLK_BYPASS_OVERRIDE_2:RW:24:1:=0x00 PHY_BYPASS_TWO_CYC_PREAMBLE_2:RW:16:2:=0x03 PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2:RW:0:10:=0x0200 + 0x00000000, // 515: PHY_SW_WRDQ3_SHIFT_2:RW:24:6:=0x00 PHY_SW_WRDQ2_SHIFT_2:RW:16:6:=0x00 PHY_SW_WRDQ1_SHIFT_2:RW:8:6:=0x00 PHY_SW_WRDQ0_SHIFT_2:RW:0:6:=0x00 + 0x00000000, // 516: PHY_SW_WRDQ7_SHIFT_2:RW:24:6:=0x00 PHY_SW_WRDQ6_SHIFT_2:RW:16:6:=0x00 PHY_SW_WRDQ5_SHIFT_2:RW:8:6:=0x00 PHY_SW_WRDQ4_SHIFT_2:RW:0:6:=0x00 + 0x01030000, // 517: PHY_PER_CS_TRAINING_MULTICAST_EN_2:RW_D:24:1:=0x01 PHY_PER_RANK_CS_MAP_2:RW+:16:2:=0x03 PHY_SW_WRDQS_SHIFT_2:RW:8:4:=0x00 PHY_SW_WRDM_SHIFT_2:RW:0:6:=0x00 + 0x00010000, // 518: PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2:RW:24:5:=0x00 PHY_LP4_BOOT_RDDATA_EN_DLY_2:RW:16:5:=0x01 PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2:RW:8:2:=0x00 PHY_PER_CS_TRAINING_INDEX_2:RW+:0:1:=0x00 + 0x01030004, // 519: PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2:RW:24:5:=0x01 PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2:RW:16:2:=0x03 PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2:RW:8:4:=0x00 PHY_LP4_BOOT_RPTR_UPDATE_2:RW:0:4:=0x04 + 0x01000000, // 520: PHY_LPBK_DFX_TIMEOUT_EN_2:RW:24:1:=0x01 PHY_LPBK_CONTROL_2:RW:8:9:=0x0000 PHY_CTRL_LPBK_EN_2:RW:0:2:=0x00 + 0x00000000, // 521: PHY_AUTO_TIMING_MARGIN_CONTROL_2:RW:0:32:=0x00000000 + 0x00000000, // 522: PHY_AUTO_TIMING_MARGIN_OBS_2:RD:0:28:=0x00000000 + 0x01000001, // 523: PHY_RDLVL_MULTI_PATT_ENABLE_2:RW:24:1:=0x00 PHY_PRBS_PATTERN_MASK_2:RW:8:9:=0x0000 PHY_PRBS_PATTERN_START_2:RW_D:0:7:=0x01 + 0x00000400, // 524: PHY_VREF_TRAIN_OBS_2:RD:16:7:=0x00 PHY_VREF_INITIAL_STEPSIZE_2:RW:8:6:=0x04 PHY_RDLVL_MULTI_PATT_RST_DISABLE_2:RW:0:1:=0x00 + 0x000800C0, // 525: SC_PHY_SNAP_OBS_REGS_2:WR:24:1:=0x00 PHY_GATE_ERROR_DELAY_SELECT_2:RW:16:4:=0x08 PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2:RW:0:10:=0x00c0 + 0x060100CC, // 526: PHY_MEM_CLASS_2:RW:24:3:=0x06 PHY_LPDDR_2:RW:16:1:=0x01 PHY_GATE_SMPL1_SLAVE_DELAY_2:RW:0:9:=0x00cc + 0x00030066, // 527: ON_FLY_GATE_ADJUST_EN_2:RW:16:2:=0x03 PHY_GATE_SMPL2_SLAVE_DELAY_2:RW:0:9:=0x0066 + 0x00000000, // 528: PHY_GATE_TRACKING_OBS_2:RD:0:32:=0x00000000 + 0x00000001, // 529: PHY_LP4_PST_AMBLE_2:RW:8:2:=0x00 PHY_DFI40_POLARITY_2:RW:0:1:=0x01 + 0x0000AAAA, // 530: PHY_RDLVL_PATT8_2:RW:0:32:=0x0000AAAA + 0x00005555, // 531: PHY_RDLVL_PATT9_2:RW:0:32:=0x00005555 + 0x0000B5B5, // 532: PHY_RDLVL_PATT10_2:RW:0:32:=0x0000B5B5 + 0x00004A4A, // 533: PHY_RDLVL_PATT11_2:RW:0:32:=0x00004A4A + 0x00005656, // 534: PHY_RDLVL_PATT12_2:RW:0:32:=0x00005656 + 0x0000A9A9, // 535: PHY_RDLVL_PATT13_2:RW:0:32:=0x0000A9A9 + 0x0000A9A9, // 536: PHY_RDLVL_PATT14_2:RW:0:32:=0x0000A9A9 + 0x0000B5B5, // 537: PHY_RDLVL_PATT15_2:RW:0:32:=0x0000B5B5 + 0x00000000, // 538: PHY_RDDQ_ENC_OBS_SELECT_2:RW:24:3:=0x00 PHY_MASTER_DLY_LOCK_OBS_SELECT_2:RW:16:4:=0x00 PHY_SW_FIFO_PTR_RST_DISABLE_2:RW:8:1:=0x00 PHY_SLAVE_LOOP_CNT_UPDATE_2:RW:0:3:=0x00 + 0x00000000, // 539: PHY_FIFO_PTR_OBS_SELECT_2:RW:24:4:=0x00 PHY_WR_SHIFT_OBS_SELECT_2:RW:16:4:=0x00 PHY_WR_ENC_OBS_SELECT_2:RW:8:4:=0x00 PHY_RDDQS_DQ_ENC_OBS_SELECT_2:RW:0:4:=0x00 + 0x2A000000, // 540: PHY_WRLVL_PER_START_2:RW:24:8:=0x2A PHY_WRLVL_ALGO_2:RW:16:2:=0x00 SC_PHY_LVL_DEBUG_CONT_2:WR:8:1:=0x00 PHY_LVL_DEBUG_MODE_2:RW:0:1:=0x00 + 0x00000808, // 541: PHY_DQ_MASK_2:RW:16:8:=0x00 PHY_WRLVL_UPDT_WAIT_CNT_2:RW:8:4:=0x08 PHY_WRLVL_CAPTURE_CNT_2:RW:0:6:=0x08 + 0x04080000, // 542: PHY_GTLVL_UPDT_WAIT_CNT_2:RW:24:4:=0x04 PHY_GTLVL_CAPTURE_CNT_2:RW:16:6:=0x00 PHY_GTLVL_PER_START_2:RW:0:10:=0x0000 + 0x00000408, // 543: PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2:RW:24:5:=0x00 PHY_RDLVL_OP_MODE_2:RW:16:2:=0x00 PHY_RDLVL_UPDT_WAIT_CNT_2:RW:8:4:=0x04 PHY_RDLVL_CAPTURE_CNT_2:RW:0:6:=0x08 + 0x10300000, // 544: PHY_WDQLVL_BURST_CNT_2:RW:24:6:=0x10 PHY_WDQLVL_CLK_JITTER_TOLERANCE_2:RW:16:8:=0x20 PHY_RDLVL_DATA_MASK_2:RW:8:8:=0x00 PHY_RDLVL_PERIODIC_OBS_SELECT_2:RW:0:8:=0x00 + 0x0C002007, // 545: PHY_WDQLVL_UPDT_WAIT_CNT_2:RW:24:4:=0x0c PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2:RW:8:11:=0x0020 PHY_WDQLVL_PATT_2:RW:0:3:=0x07 + 0x00000000, // 546: SC_PHY_WDQLVL_CLR_PREV_RESULTS_2:WR:16:1:=0x00 PHY_WDQLVL_PERIODIC_OBS_SELECT_2:RW:8:8:=0x00 PHY_WDQLVL_DQDM_OBS_SELECT_2:RW:0:4:=0x00 + 0x00000100, // 547: PHY_WDQLVL_DATADM_MASK_2:RW:0:9:=0x0100 + 0x55555555, // 548: PHY_USER_PATT0_2:RW:0:32:=0x55555555 + 0xAAAAAAAA, // 549: PHY_USER_PATT1_2:RW:0:32:=0xAAAAAAAA + 0x55555555, // 550: PHY_USER_PATT2_2:RW:0:32:=0x55555555 + 0xAAAAAAAA, // 551: PHY_USER_PATT3_2:RW:0:32:=0xAAAAAAAA + 0x00005555, // 552: PHY_NTP_MULT_TRAIN_2:RW:16:1:=0x00 PHY_USER_PATT4_2:RW:0:16:=0x5555 + 0x01000100, // 553: PHY_NTP_PERIOD_THRESHOLD_2:RW:16:10:=0x0100 PHY_NTP_EARLY_THRESHOLD_2:RW:0:10:=0x0100 + 0x00800180, // 554: PHY_NTP_PERIOD_THRESHOLD_MAX_2:RW:16:10:=0x0080 PHY_NTP_PERIOD_THRESHOLD_MIN_2:RW:0:10:=0x0180 + 0x00000001, // 555: PHY_FIFO_PTR_OBS_2:RD:16:8:=0x00 SC_PHY_MANUAL_CLEAR_2:WR:8:6:=0x00 PHY_CALVL_VREF_DRIVING_SLICE_2:RW:0:1:=0x01 + 0x00000000, // 556: PHY_LPBK_RESULT_OBS_2:RD:0:32:=0x00000000 + 0x00000000, // 557: PHY_MASTER_DLY_LOCK_OBS_2:RD:16:11:=0x0000 PHY_LPBK_ERROR_COUNT_OBS_2:RD:0:16:=0x0000 + 0x00000000, // 558: PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2:RD:24:8:=0x00 PHY_MEAS_DLY_STEP_VALUE_2:RD:16:8:=0x00 PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2:RD:8:7:=0x00 PHY_RDDQ_SLV_DLY_ENC_OBS_2:RD:0:7:=0x00 + 0x00000000, // 559: PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2:RD:24:7:=0x00 PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2:RD:8:11:=0x0000 PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2:RD:0:8:=0x00 + 0x00000000, // 560: PHY_WR_SHIFT_OBS_2:RD:16:3:=0x00 PHY_WR_ADDER_SLV_DLY_ENC_OBS_2:RD:8:8:=0x00 PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2:RD:0:8:=0x00 + 0x00000000, // 561: PHY_WRLVL_HARD1_DELAY_OBS_2:RD:16:10:=0x0000 PHY_WRLVL_HARD0_DELAY_OBS_2:RD:0:10:=0x0000 + 0x00000000, // 562: PHY_WRLVL_STATUS_OBS_2:RD:0:17:=0x000000 + 0x00000000, // 563: PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2:RD:16:10:=0x0000 PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2:RD:0:10:=0x0000 + 0x00000000, // 564: PHY_GTLVL_HARD0_DELAY_OBS_2:RD:16:14:=0x0000 PHY_WRLVL_ERROR_OBS_2:RD:0:16:=0x0000 + 0x00000000, // 565: PHY_GTLVL_HARD1_DELAY_OBS_2:RD:0:14:=0x0000 + 0x00000000, // 566: PHY_GTLVL_STATUS_OBS_2:RD:0:18:=0x000000 + 0x00000000, // 567: PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2:RD:16:10:=0x0000 PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2:RD:0:10:=0x0000 + 0x00000000, // 568: PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2:RD:0:2:=0x00 + 0x00000000, // 569: PHY_RDLVL_STATUS_OBS_2:RD:0:32:=0x00000000 + 0x00000000, // 570: PHY_RDLVL_PERIODIC_OBS_2:RD:0:32:=0x00000000 + 0x00000000, // 571: PHY_WDQLVL_DQDM_TE_DLY_OBS_2:RD:16:11:=0x0000 PHY_WDQLVL_DQDM_LE_DLY_OBS_2:RD:0:11:=0x0000 + 0x00000000, // 572: PHY_WDQLVL_STATUS_OBS_2:RD:0:32:=0x00000000 + 0x00000000, // 573: PHY_WDQLVL_PERIODIC_OBS_2:RD:0:32:=0x00000000 + 0x00000000, // 574: PHY_DDL_MODE_2:RW:0:31:=0x00000000 + 0x00000000, // 575: PHY_DDL_MASK_2:RW:0:6:=0x00 + 0x00000000, // 576: PHY_DDL_TEST_OBS_2:RD:0:32:=0x00000000 + 0x00000000, // 577: PHY_DDL_TEST_MSTR_DLY_OBS_2:RD:0:32:=0x00000000 + 0x00000104, // 578: PHY_RX_CAL_OVERRIDE_2:RW:24:1:=0x00 SC_PHY_RX_CAL_START_2:WR:16:1:=0x00 PHY_LP4_WDQS_OE_EXTEND_2:RW:8:1:=0x00 PHY_DDL_TRACK_UPD_THRESHOLD_2:RW:0:8:=0x04 + 0x00000120, // 579: PHY_RX_CAL_DQ0_2:RW_D+:16:9:=0x0000 PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2:RW:8:1:=0x01 PHY_RX_CAL_SAMPLE_WAIT_2:RW:0:8:=0x20 + 0x00000000, // 580: PHY_RX_CAL_DQ2_2:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQ1_2:RW_D+:0:9:=0x0000 + 0x00000000, // 581: PHY_RX_CAL_DQ4_2:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQ3_2:RW_D+:0:9:=0x0000 + 0x00000000, // 582: PHY_RX_CAL_DQ6_2:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQ5_2:RW_D+:0:9:=0x0000 + 0x00000000, // 583: PHY_RX_CAL_DQ7_2:RW_D+:0:9:=0x0000 + 0x00000000, // 584: PHY_RX_CAL_DM_2:RW_D+:0:18:=0x000000 + 0x00000000, // 585: PHY_RX_CAL_FDBK_2:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQS_2:RW_D+:0:9:=0x0000 + 0x00000000, // 586: PHY_RX_CAL_LOCK_OBS_2:RD:16:9:=0x0000 PHY_RX_CAL_OBS_2:RD:0:11:=0x0000 + 0x00000001, // 587: PHY_RX_CAL_COMP_VAL_2:RW:24:1:=0x00 PHY_RX_CAL_DIFF_ADJUST_2:RW:16:7:=0x00 PHY_RX_CAL_SE_ADJUST_2:RW:8:7:=0x00 PHY_RX_CAL_DISABLE_2:RW_D:0:1:=0x01 + 0x07FF0000, // 588: PHY_PAD_RX_BIAS_EN_2:RW:16:11:=0x07ff PHY_RX_CAL_INDEX_MASK_2:RW:0:12:=0x0000 + 0x0080081F, // 589: PHY_DATA_DC_WEIGHT_2:RW:24:2:=0x00 PHY_DATA_DC_CAL_TIMEOUT_2:RW:16:8:=0x80 PHY_DATA_DC_CAL_SAMPLE_WAIT_2:RW:8:8:=0x08 PHY_STATIC_TOG_DISABLE_2:RW:0:5:=0x1f + 0x00081020, // 590: PHY_DATA_DC_ADJUST_DIRECT_2:RW:24:1:=0x00 PHY_DATA_DC_ADJUST_THRSHLD_2:RW:16:8:=0x08 PHY_DATA_DC_ADJUST_SAMPLE_CNT_2:RW:8:8:=0x10 PHY_DATA_DC_ADJUST_START_2:RW:0:6:=0x20 + 0x04010000, // 591: PHY_FDBK_PWR_CTRL_2:RW:24:3:=0x04 PHY_DATA_DC_SW_RANK_2:RW+:16:2:=0x01 PHY_DATA_DC_CAL_START_2:RW+:8:1:=0x00 PHY_DATA_DC_CAL_POLARITY_2:RW:0:1:=0x00 + 0x00000001, // 592: PHY_SLICE_PWR_RDC_DISABLE_2:RW:24:1:=0x00 PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2:RW_D:16:1:=0x00 PHY_RDPATH_GATE_DISABLE_2:RW_D:8:1:=0x00 PHY_SLV_DLY_CTRL_GATE_DISABLE_2:RW_D:0:1:=0x00 + 0x00000000, // 593: PHY_DS_FSM_ERROR_INFO_2:RD:16:14:=0x0000 PHY_PARITY_ERROR_REGIF_2:RW:0:11:=0x0000 + 0x00000000, // 594: SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2:WR:16:14:=0x0000 PHY_DS_FSM_ERROR_INFO_MASK_2:RW:0:14:=0x0000 + 0x00000100, // 595: SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2:WR:16:5:=0x00 PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2:RW:8:5:=0x01 PHY_DS_TRAIN_CALIB_ERROR_INFO_2:RD:0:5:=0x00 + 0x05CC0C05, // 596: PHY_DQS_TSEL_ENABLE_2:RW+:24:3:=0x01 PHY_DQ_TSEL_SELECT_2:RW+:8:16:=0x4408 PHY_DQ_TSEL_ENABLE_2:RW+:0:3:=0x01 + 0x1603CC0C, // 597: PHY_VREF_INITIAL_START_POINT_2:RW+:24:7:=0x20 PHY_TWO_CYC_PREAMBLE_2:RW+:16:2:=0x03 PHY_DQS_TSEL_SELECT_2:RW+:0:16:=0x4408 + 0x2000012F, // 598: PHY_NTP_WDQ_STEP_SIZE_2:RW+:24:8:=0x20 PHY_NTP_TRAIN_EN_2:RW+:16:1:=0x00 PHY_VREF_TRAINING_CTRL_2:RW+:8:2:=0x01 PHY_VREF_INITIAL_STOP_POINT_2:RW+:0:7:=0x25 + 0x07FF0200, // 599: PHY_NTP_WDQ_STOP_2:RW+:16:11:=0x07FF PHY_NTP_WDQ_START_2:RW+:0:11:=0x0200 + 0x0000DD01, // 600: PHY_SW_WDQLVL_DVW_MIN_EN_2:RW+:24:1:=0x00 PHY_WDQLVL_DVW_MIN_2:RW+:8:10:=0x00dd PHY_NTP_WDQ_BIT_EN_2:RW+:0:8:=0x01 + 0x00000303, // 601: PHY_PAD_RX_DCD_0_2:RW+:24:5:=0x00 PHY_PAD_TX_DCD_2:RW+:16:5:=0x00 PHY_FAST_LVL_EN_2:RW+:8:4:=0x03 PHY_WDQLVL_PER_START_OFFSET_2:RW+:0:6:=0x03 + 0x00000000, // 602: PHY_PAD_RX_DCD_4_2:RW+:24:5:=0x00 PHY_PAD_RX_DCD_3_2:RW+:16:5:=0x00 PHY_PAD_RX_DCD_2_2:RW+:8:5:=0x00 PHY_PAD_RX_DCD_1_2:RW+:0:5:=0x00 + 0x00000000, // 603: PHY_PAD_DM_RX_DCD_2:RW+:24:5:=0x00 PHY_PAD_RX_DCD_7_2:RW+:16:5:=0x00 PHY_PAD_RX_DCD_6_2:RW+:8:5:=0x00 PHY_PAD_RX_DCD_5_2:RW+:0:5:=0x00 + 0x00030000, // 604: PHY_PAD_DSLICE_IO_CFG_2:RW+:16:6:=0x00 PHY_PAD_FDBK_RX_DCD_2:RW+:8:5:=0x00 PHY_PAD_DQS_RX_DCD_2:RW+:0:5:=0x00 + 0x00000000, // 605: PHY_RDDQ1_SLAVE_DELAY_2:RW+:16:10:=0x0000 PHY_RDDQ0_SLAVE_DELAY_2:RW+:0:10:=0x0000 + 0x00000000, // 606: PHY_RDDQ3_SLAVE_DELAY_2:RW+:16:10:=0x0000 PHY_RDDQ2_SLAVE_DELAY_2:RW+:0:10:=0x0000 + 0x00000000, // 607: PHY_RDDQ5_SLAVE_DELAY_2:RW+:16:10:=0x0000 PHY_RDDQ4_SLAVE_DELAY_2:RW+:0:10:=0x0000 + 0x00000000, // 608: PHY_RDDQ7_SLAVE_DELAY_2:RW+:16:10:=0x0000 PHY_RDDQ6_SLAVE_DELAY_2:RW+:0:10:=0x0000 + 0x00050000, // 609: PHY_DATA_DC_CAL_CLK_SEL_2:RW+:16:3:=0x02 PHY_RDDM_SLAVE_DELAY_2:RW+:0:10:=0x0000 + 0x51515042, // 610: PHY_DQS_OE_TIMING_2:RW+:24:8:=0x51 PHY_DQ_TSEL_WR_TIMING_2:RW+:16:8:=0x51 PHY_DQ_TSEL_RD_TIMING_2:RW+:8:8:=0x50 PHY_DQ_OE_TIMING_2:RW+:0:8:=0x42 + 0x31C06000, // 611: PHY_DQS_TSEL_WR_TIMING_2:RW+:24:8:=0x31 PHY_DQS_OE_RD_TIMING_2:RW+:16:8:=0xc0 PHY_DQS_TSEL_RD_TIMING_2:RW+:8:8:=0x60 PHY_IO_PAD_DELAY_TIMING_2:RW+:0:4:=0x00 + 0x07A000A0, // 612: PHY_PAD_VREF_CTRL_DQ_2:RW+:16:12:=0x069f PHY_VREF_SETTING_TIME_2:RW+:0:16:=0x0004 + 0x00C0C001, // 613: PHY_RDDATA_EN_IE_DLY_2:RW+:24:2:=0x00 PHY_DQS_IE_TIMING_2:RW+:16:8:=0xc0 PHY_DQ_IE_TIMING_2:RW+:8:8:=0xc0 PHY_PER_CS_TRAINING_EN_2:RW+:0:1:=0x01 + 0x0E0D0100, // 614: PHY_RDDATA_EN_OE_DLY_2:RW+:24:5:=0x0e PHY_RDDATA_EN_TSEL_DLY_2:RW+:16:5:=0x0d PHY_DBI_MODE_2:RW+:8:1:=0x00 PHY_IE_MODE_2:RW+:0:2:=0x00 + 0x10001000, // 615: PHY_MASTER_DELAY_STEP_2:RW+:24:6:=0x10 PHY_MASTER_DELAY_START_2:RW+:8:11:=0x0010 PHY_SW_MASTER_MODE_2:RW+:0:4:=0x00 + 0x0C063E42, // 616: PHY_WRLVL_DLY_STEP_2:RW+:24:8:=0x0c PHY_RPTR_UPDATE_2:RW+:16:4:=0x06 PHY_MASTER_DELAY_HALF_MEASURE_2:RW+:8:8:=0x3e PHY_MASTER_DELAY_WAIT_2:RW+:0:8:=0x42 + 0x0F0C3701, // 617: PHY_GTLVL_RESP_WAIT_CNT_2:RW+:24:5:=0x0f PHY_GTLVL_DLY_STEP_2:RW+:16:4:=0x0c PHY_WRLVL_RESP_WAIT_CNT_2:RW+:8:6:=0x37 PHY_WRLVL_DLY_FINE_STEP_2:RW+:0:4:=0x01 + 0x01000140, // 618: PHY_GTLVL_FINAL_STEP_2:RW+:16:10:=0x0100 PHY_GTLVL_BACK_STEP_2:RW+:0:10:=0x0140 + 0x0C000120, // 619: PHY_RDLVL_DLY_STEP_2:RW+:24:4:=0x0c PHY_TOGGLE_PRE_SUPPORT_2:RW+:16:1:=0x00 PHY_WDQLVL_QTR_DLY_STEP_2:RW+:8:4:=0x01 PHY_WDQLVL_DLY_STEP_2:RW+:0:8:=0x20 + 0x00000322, // 620: PHY_RDLVL_MAX_EDGE_2:RW+:0:10:=0x0322 + 0x0A0000D0, // 621: PHY_RDLVL_PER_START_OFFSET_2:RW+:24:6:=0x0A PHY_SW_RDLVL_DVW_MIN_EN_2:RW+:16:1:=0x00 PHY_RDLVL_DVW_MIN_2:RW+:0:10:=0x00d0 + 0x00030200, // 622: PHY_DATA_DC_INIT_DISABLE_2:RW+:16:2:=0x00 PHY_WRPATH_GATE_TIMING_2:RW+:8:3:=0x02 PHY_WRPATH_GATE_DISABLE_2:RW+:0:2:=0x00 + 0x02800000, // 623: PHY_DATA_DC_DQ_INIT_SLV_DELAY_2:RW+:16:11:=0x0280 PHY_DATA_DC_DQS_INIT_SLV_DELAY_2:RW+:0:10:=0x0000 + 0x80800000, // 624: PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2:RW+:24:8:=0x80 PHY_DATA_DC_DM_CLK_SE_THRSHLD_2:RW+:16:8:=0x80 PHY_DATA_DC_WDQLVL_ENABLE_2:RW+:8:1:=0x01 PHY_DATA_DC_WRLVL_ENABLE_2:RW+:0:1:=0x01 + 0x000E2010, // 625: PHY_RDDATA_EN_DLY_2:RW+:16:5:=0x0e PHY_MEAS_DLY_STEP_ENABLE_2:RW+:8:6:=0x20 PHY_WDQ_OSC_DELTA_2:RW+:0:7:=0x10 + 0x21043576, // 626: PHY_DQ_DM_SWIZZLE0_2:RW+:0:32:=0x76543210 + 0x00000008, // 627: PHY_DQ_DM_SWIZZLE1_2:RW+:0:4:=0x08 + 0x02800280, // 628: PHY_CLK_WRDQ1_SLAVE_DELAY_2:RW+:16:11:=0x0280 PHY_CLK_WRDQ0_SLAVE_DELAY_2:RW+:0:11:=0x0280 + 0x02800280, // 629: PHY_CLK_WRDQ3_SLAVE_DELAY_2:RW+:16:11:=0x0280 PHY_CLK_WRDQ2_SLAVE_DELAY_2:RW+:0:11:=0x0280 + 0x02800280, // 630: PHY_CLK_WRDQ5_SLAVE_DELAY_2:RW+:16:11:=0x0280 PHY_CLK_WRDQ4_SLAVE_DELAY_2:RW+:0:11:=0x0280 + 0x02800280, // 631: PHY_CLK_WRDQ7_SLAVE_DELAY_2:RW+:16:11:=0x0280 PHY_CLK_WRDQ6_SLAVE_DELAY_2:RW+:0:11:=0x0280 + 0x00000280, // 632: PHY_CLK_WRDQS_SLAVE_DELAY_2:RW+:16:10:=0x0000 PHY_CLK_WRDM_SLAVE_DELAY_2:RW+:0:11:=0x0280 + 0x0000A000, // 633: PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2:RW+:8:10:=0x00a0 PHY_WRLVL_THRESHOLD_ADJUST_2:RW+:0:2:=0x00 + 0x00A000A0, // 634: PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0 + 0x00A000A0, // 635: PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0 + 0x00A000A0, // 636: PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0 + 0x00A000A0, // 637: PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0 + 0x00A000A0, // 638: PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0 + 0x00A000A0, // 639: PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0 + 0x00A000A0, // 640: PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0 + 0x00A000A0, // 641: PHY_RDDQS_DM_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0 + 0x01C200A0, // 642: PHY_RDDQS_GATE_SLAVE_DELAY_2:RW+:16:10:=0x01c2 PHY_RDDQS_DM_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0 + 0x01A00005, // 643: PHY_WRLVL_DELAY_EARLY_THRESHOLD_2:RW+:16:10:=0x01A0 PHY_WRITE_PATH_LAT_ADD_2:RW+:8:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_2:RW+:0:4:=0x05 + 0x00000000, // 644: PHY_WRLVL_EARLY_FORCE_ZERO_2:RW+:16:1:=0x00 PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2:RW+:0:10:=0x0000 + 0x00060000, // 645: PHY_GTLVL_LAT_ADJ_START_2:RW+:16:4:=0x06 PHY_GTLVL_RDDQS_SLV_DLY_START_2:RW+:0:10:=0x0000 + 0x00080200, // 646: PHY_NTP_PASS_2:RW+:24:1:=0x00 PHY_NTP_WRLAT_START_2:RW+:16:4:=0x08 PHY_WDQLVL_DQDM_SLV_DLY_START_2:RW+:0:11:=0x0200 + 0x00000000, // 647: PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2:RW+:0:10:=0x0000 + 0x20202020, // 648: PHY_DATA_DC_DQ2_CLK_ADJUST_2:RW+:24:8:=0x20 PHY_DATA_DC_DQ1_CLK_ADJUST_2:RW+:16:8:=0x20 PHY_DATA_DC_DQ0_CLK_ADJUST_2:RW+:8:8:=0x20 PHY_DATA_DC_DQS_CLK_ADJUST_2:RW+:0:8:=0x20 + 0x20202020, // 649: PHY_DATA_DC_DQ6_CLK_ADJUST_2:RW+:24:8:=0x20 PHY_DATA_DC_DQ5_CLK_ADJUST_2:RW+:16:8:=0x20 PHY_DATA_DC_DQ4_CLK_ADJUST_2:RW+:8:8:=0x20 PHY_DATA_DC_DQ3_CLK_ADJUST_2:RW+:0:8:=0x20 + 0xF0F02020, // 650: PHY_DSLICE_PAD_BOOSTPN_SETTING_2:RW+:16:16:=0x0000 PHY_DATA_DC_DM_CLK_ADJUST_2:RW+:8:8:=0x20 PHY_DATA_DC_DQ7_CLK_ADJUST_2:RW+:0:8:=0x20 + 0x00000000, // 651: PHY_DQS_FFE_2:RW+:16:2:=0x00 PHY_DQ_FFE_2:RW+:8:2:=0x00 PHY_DSLICE_PAD_RX_CTLE_SETTING_2:RW+:0:6:=0x00 + 0x00000000, // 652: + 0x00000000, // 653: + 0x00000000, // 654: + 0x00000000, // 655: + 0x00000000, // 656: + 0x00000000, // 657: + 0x00000000, // 658: + 0x00000000, // 659: + 0x00000000, // 660: + 0x00000000, // 661: + 0x00000000, // 662: + 0x00000000, // 663: + 0x00000000, // 664: + 0x00000000, // 665: + 0x00000000, // 666: + 0x00000000, // 667: + 0x00000000, // 668: + 0x00000000, // 669: + 0x00000000, // 670: + 0x00000000, // 671: + 0x00000000, // 672: + 0x00000000, // 673: + 0x00000000, // 674: + 0x00000000, // 675: + 0x00000000, // 676: + 0x00000000, // 677: + 0x00000000, // 678: + 0x00000000, // 679: + 0x00000000, // 680: + 0x00000000, // 681: + 0x00000000, // 682: + 0x00000000, // 683: + 0x00000000, // 684: + 0x00000000, // 685: + 0x00000000, // 686: + 0x00000000, // 687: + 0x00000000, // 688: + 0x00000000, // 689: + 0x00000000, // 690: + 0x00000000, // 691: + 0x00000000, // 692: + 0x00000000, // 693: + 0x00000000, // 694: + 0x00000000, // 695: + 0x00000000, // 696: + 0x00000000, // 697: + 0x00000000, // 698: + 0x00000000, // 699: + 0x00000000, // 700: + 0x00000000, // 701: + 0x00000000, // 702: + 0x00000000, // 703: + 0x00000000, // 704: + 0x00000000, // 705: + 0x00000000, // 706: + 0x00000000, // 707: + 0x00000000, // 708: + 0x00000000, // 709: + 0x00000000, // 710: + 0x00000000, // 711: + 0x00000000, // 712: + 0x00000000, // 713: + 0x00000000, // 714: + 0x00000000, // 715: + 0x00000000, // 716: + 0x00000000, // 717: + 0x00000000, // 718: + 0x00000000, // 719: + 0x00000000, // 720: + 0x00000000, // 721: + 0x00000000, // 722: + 0x00000000, // 723: + 0x00000000, // 724: + 0x00000000, // 725: + 0x00000000, // 726: + 0x00000000, // 727: + 0x00000000, // 728: + 0x00000000, // 729: + 0x00000000, // 730: + 0x00000000, // 731: + 0x00000000, // 732: + 0x00000000, // 733: + 0x00000000, // 734: + 0x00000000, // 735: + 0x00000000, // 736: + 0x00000000, // 737: + 0x00000000, // 738: + 0x00000000, // 739: + 0x00000000, // 740: + 0x00000000, // 741: + 0x00000000, // 742: + 0x00000000, // 743: + 0x00000000, // 744: + 0x00000000, // 745: + 0x00000000, // 746: + 0x00000000, // 747: + 0x00000000, // 748: + 0x00000000, // 749: + 0x00000000, // 750: + 0x00000000, // 751: + 0x00000000, // 752: + 0x00000000, // 753: + 0x00000000, // 754: + 0x00000000, // 755: + 0x00000000, // 756: + 0x00000000, // 757: + 0x00000000, // 758: + 0x00000000, // 759: + 0x00000000, // 760: + 0x00000000, // 761: + 0x00000000, // 762: + 0x00000000, // 763: + 0x00000000, // 764: + 0x00000000, // 765: + 0x00000000, // 766: + 0x00000000, // 767: + 0x000004F0, // 768: PHY_IO_PAD_DELAY_TIMING_BYPASS_3:RW:16:4:=0x00 PHY_CLK_WR_BYPASS_SLAVE_DELAY_3:RW:0:11:=0x04f0 + 0x00000000, // 769: PHY_WRITE_PATH_LAT_ADD_BYPASS_3:RW:16:3:=0x00 PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3:RW:0:10:=0x0000 + 0x00030200, // 770: PHY_CLK_BYPASS_OVERRIDE_3:RW:24:1:=0x00 PHY_BYPASS_TWO_CYC_PREAMBLE_3:RW:16:2:=0x03 PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3:RW:0:10:=0x0200 + 0x00000000, // 771: PHY_SW_WRDQ3_SHIFT_3:RW:24:6:=0x00 PHY_SW_WRDQ2_SHIFT_3:RW:16:6:=0x00 PHY_SW_WRDQ1_SHIFT_3:RW:8:6:=0x00 PHY_SW_WRDQ0_SHIFT_3:RW:0:6:=0x00 + 0x00000000, // 772: PHY_SW_WRDQ7_SHIFT_3:RW:24:6:=0x00 PHY_SW_WRDQ6_SHIFT_3:RW:16:6:=0x00 PHY_SW_WRDQ5_SHIFT_3:RW:8:6:=0x00 PHY_SW_WRDQ4_SHIFT_3:RW:0:6:=0x00 + 0x01030000, // 773: PHY_PER_CS_TRAINING_MULTICAST_EN_3:RW_D:24:1:=0x01 PHY_PER_RANK_CS_MAP_3:RW+:16:2:=0x03 PHY_SW_WRDQS_SHIFT_3:RW:8:4:=0x00 PHY_SW_WRDM_SHIFT_3:RW:0:6:=0x00 + 0x00010000, // 774: PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3:RW:24:5:=0x00 PHY_LP4_BOOT_RDDATA_EN_DLY_3:RW:16:5:=0x01 PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3:RW:8:2:=0x00 PHY_PER_CS_TRAINING_INDEX_3:RW+:0:1:=0x00 + 0x01030004, // 775: PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3:RW:24:5:=0x01 PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3:RW:16:2:=0x03 PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3:RW:8:4:=0x00 PHY_LP4_BOOT_RPTR_UPDATE_3:RW:0:4:=0x04 + 0x01000000, // 776: PHY_LPBK_DFX_TIMEOUT_EN_3:RW:24:1:=0x01 PHY_LPBK_CONTROL_3:RW:8:9:=0x0000 PHY_CTRL_LPBK_EN_3:RW:0:2:=0x00 + 0x00000000, // 777: PHY_AUTO_TIMING_MARGIN_CONTROL_3:RW:0:32:=0x00000000 + 0x00000000, // 778: PHY_AUTO_TIMING_MARGIN_OBS_3:RD:0:28:=0x00000000 + 0x01000001, // 779: PHY_RDLVL_MULTI_PATT_ENABLE_3:RW:24:1:=0x00 PHY_PRBS_PATTERN_MASK_3:RW:8:9:=0x0000 PHY_PRBS_PATTERN_START_3:RW_D:0:7:=0x01 + 0x00000400, // 780: PHY_VREF_TRAIN_OBS_3:RD:16:7:=0x00 PHY_VREF_INITIAL_STEPSIZE_3:RW:8:6:=0x04 PHY_RDLVL_MULTI_PATT_RST_DISABLE_3:RW:0:1:=0x00 + 0x000800C0, // 781: SC_PHY_SNAP_OBS_REGS_3:WR:24:1:=0x00 PHY_GATE_ERROR_DELAY_SELECT_3:RW:16:4:=0x08 PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3:RW:0:10:=0x00c0 + 0x060100CC, // 782: PHY_MEM_CLASS_3:RW:24:3:=0x06 PHY_LPDDR_3:RW:16:1:=0x01 PHY_GATE_SMPL1_SLAVE_DELAY_3:RW:0:9:=0x00cc + 0x00030066, // 783: ON_FLY_GATE_ADJUST_EN_3:RW:16:2:=0x03 PHY_GATE_SMPL2_SLAVE_DELAY_3:RW:0:9:=0x0066 + 0x00000000, // 784: PHY_GATE_TRACKING_OBS_3:RD:0:32:=0x00000000 + 0x00000001, // 785: PHY_LP4_PST_AMBLE_3:RW:8:2:=0x00 PHY_DFI40_POLARITY_3:RW:0:1:=0x01 + 0x0000AAAA, // 786: PHY_RDLVL_PATT8_3:RW:0:32:=0x0000AAAA + 0x00005555, // 787: PHY_RDLVL_PATT9_3:RW:0:32:=0x00005555 + 0x0000B5B5, // 788: PHY_RDLVL_PATT10_3:RW:0:32:=0x0000B5B5 + 0x00004A4A, // 789: PHY_RDLVL_PATT11_3:RW:0:32:=0x00004A4A + 0x00005656, // 790: PHY_RDLVL_PATT12_3:RW:0:32:=0x00005656 + 0x0000A9A9, // 791: PHY_RDLVL_PATT13_3:RW:0:32:=0x0000A9A9 + 0x0000A9A9, // 792: PHY_RDLVL_PATT14_3:RW:0:32:=0x0000A9A9 + 0x0000B5B5, // 793: PHY_RDLVL_PATT15_3:RW:0:32:=0x0000B5B5 + 0x00000000, // 794: PHY_RDDQ_ENC_OBS_SELECT_3:RW:24:3:=0x00 PHY_MASTER_DLY_LOCK_OBS_SELECT_3:RW:16:4:=0x00 PHY_SW_FIFO_PTR_RST_DISABLE_3:RW:8:1:=0x00 PHY_SLAVE_LOOP_CNT_UPDATE_3:RW:0:3:=0x00 + 0x00000000, // 795: PHY_FIFO_PTR_OBS_SELECT_3:RW:24:4:=0x00 PHY_WR_SHIFT_OBS_SELECT_3:RW:16:4:=0x00 PHY_WR_ENC_OBS_SELECT_3:RW:8:4:=0x00 PHY_RDDQS_DQ_ENC_OBS_SELECT_3:RW:0:4:=0x00 + 0x2A000000, // 796: PHY_WRLVL_PER_START_3:RW:24:8:=0x2A PHY_WRLVL_ALGO_3:RW:16:2:=0x00 SC_PHY_LVL_DEBUG_CONT_3:WR:8:1:=0x00 PHY_LVL_DEBUG_MODE_3:RW:0:1:=0x00 + 0x00000808, // 797: PHY_DQ_MASK_3:RW:16:8:=0x00 PHY_WRLVL_UPDT_WAIT_CNT_3:RW:8:4:=0x08 PHY_WRLVL_CAPTURE_CNT_3:RW:0:6:=0x08 + 0x04080000, // 798: PHY_GTLVL_UPDT_WAIT_CNT_3:RW:24:4:=0x04 PHY_GTLVL_CAPTURE_CNT_3:RW:16:6:=0x00 PHY_GTLVL_PER_START_3:RW:0:10:=0x0000 + 0x00000408, // 799: PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3:RW:24:5:=0x00 PHY_RDLVL_OP_MODE_3:RW:16:2:=0x00 PHY_RDLVL_UPDT_WAIT_CNT_3:RW:8:4:=0x04 PHY_RDLVL_CAPTURE_CNT_3:RW:0:6:=0x08 + 0x10300000, // 800: PHY_WDQLVL_BURST_CNT_3:RW:24:6:=0x10 PHY_WDQLVL_CLK_JITTER_TOLERANCE_3:RW:16:8:=0x20 PHY_RDLVL_DATA_MASK_3:RW:8:8:=0x00 PHY_RDLVL_PERIODIC_OBS_SELECT_3:RW:0:8:=0x00 + 0x0C002007, // 801: PHY_WDQLVL_UPDT_WAIT_CNT_3:RW:24:4:=0x0c PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3:RW:8:11:=0x0020 PHY_WDQLVL_PATT_3:RW:0:3:=0x07 + 0x00000000, // 802: SC_PHY_WDQLVL_CLR_PREV_RESULTS_3:WR:16:1:=0x00 PHY_WDQLVL_PERIODIC_OBS_SELECT_3:RW:8:8:=0x00 PHY_WDQLVL_DQDM_OBS_SELECT_3:RW:0:4:=0x00 + 0x00000100, // 803: PHY_WDQLVL_DATADM_MASK_3:RW:0:9:=0x0100 + 0x55555555, // 804: PHY_USER_PATT0_3:RW:0:32:=0x55555555 + 0xAAAAAAAA, // 805: PHY_USER_PATT1_3:RW:0:32:=0xAAAAAAAA + 0x55555555, // 806: PHY_USER_PATT2_3:RW:0:32:=0x55555555 + 0xAAAAAAAA, // 807: PHY_USER_PATT3_3:RW:0:32:=0xAAAAAAAA + 0x00005555, // 808: PHY_NTP_MULT_TRAIN_3:RW:16:1:=0x00 PHY_USER_PATT4_3:RW:0:16:=0x5555 + 0x01000100, // 809: PHY_NTP_PERIOD_THRESHOLD_3:RW:16:10:=0x0100 PHY_NTP_EARLY_THRESHOLD_3:RW:0:10:=0x0100 + 0x00800180, // 810: PHY_NTP_PERIOD_THRESHOLD_MAX_3:RW:16:10:=0x0080 PHY_NTP_PERIOD_THRESHOLD_MIN_3:RW:0:10:=0x0180 + 0x00000000, // 811: PHY_FIFO_PTR_OBS_3:RD:16:8:=0x00 SC_PHY_MANUAL_CLEAR_3:WR:8:6:=0x00 PHY_CALVL_VREF_DRIVING_SLICE_3:RW:0:1:=0x00 + 0x00000000, // 812: PHY_LPBK_RESULT_OBS_3:RD:0:32:=0x00000000 + 0x00000000, // 813: PHY_MASTER_DLY_LOCK_OBS_3:RD:16:11:=0x0000 PHY_LPBK_ERROR_COUNT_OBS_3:RD:0:16:=0x0000 + 0x00000000, // 814: PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3:RD:24:8:=0x00 PHY_MEAS_DLY_STEP_VALUE_3:RD:16:8:=0x00 PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3:RD:8:7:=0x00 PHY_RDDQ_SLV_DLY_ENC_OBS_3:RD:0:7:=0x00 + 0x00000000, // 815: PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3:RD:24:7:=0x00 PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3:RD:8:11:=0x0000 PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3:RD:0:8:=0x00 + 0x00000000, // 816: PHY_WR_SHIFT_OBS_3:RD:16:3:=0x00 PHY_WR_ADDER_SLV_DLY_ENC_OBS_3:RD:8:8:=0x00 PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3:RD:0:8:=0x00 + 0x00000000, // 817: PHY_WRLVL_HARD1_DELAY_OBS_3:RD:16:10:=0x0000 PHY_WRLVL_HARD0_DELAY_OBS_3:RD:0:10:=0x0000 + 0x00000000, // 818: PHY_WRLVL_STATUS_OBS_3:RD:0:17:=0x000000 + 0x00000000, // 819: PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3:RD:16:10:=0x0000 PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3:RD:0:10:=0x0000 + 0x00000000, // 820: PHY_GTLVL_HARD0_DELAY_OBS_3:RD:16:14:=0x0000 PHY_WRLVL_ERROR_OBS_3:RD:0:16:=0x0000 + 0x00000000, // 821: PHY_GTLVL_HARD1_DELAY_OBS_3:RD:0:14:=0x0000 + 0x00000000, // 822: PHY_GTLVL_STATUS_OBS_3:RD:0:18:=0x000000 + 0x00000000, // 823: PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3:RD:16:10:=0x0000 PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3:RD:0:10:=0x0000 + 0x00000000, // 824: PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3:RD:0:2:=0x00 + 0x00000000, // 825: PHY_RDLVL_STATUS_OBS_3:RD:0:32:=0x00000000 + 0x00000000, // 826: PHY_RDLVL_PERIODIC_OBS_3:RD:0:32:=0x00000000 + 0x00000000, // 827: PHY_WDQLVL_DQDM_TE_DLY_OBS_3:RD:16:11:=0x0000 PHY_WDQLVL_DQDM_LE_DLY_OBS_3:RD:0:11:=0x0000 + 0x00000000, // 828: PHY_WDQLVL_STATUS_OBS_3:RD:0:32:=0x00000000 + 0x00000000, // 829: PHY_WDQLVL_PERIODIC_OBS_3:RD:0:32:=0x00000000 + 0x00000000, // 830: PHY_DDL_MODE_3:RW:0:31:=0x00000000 + 0x00000000, // 831: PHY_DDL_MASK_3:RW:0:6:=0x00 + 0x00000000, // 832: PHY_DDL_TEST_OBS_3:RD:0:32:=0x00000000 + 0x00000000, // 833: PHY_DDL_TEST_MSTR_DLY_OBS_3:RD:0:32:=0x00000000 + 0x00000104, // 834: PHY_RX_CAL_OVERRIDE_3:RW:24:1:=0x00 SC_PHY_RX_CAL_START_3:WR:16:1:=0x00 PHY_LP4_WDQS_OE_EXTEND_3:RW:8:1:=0x00 PHY_DDL_TRACK_UPD_THRESHOLD_3:RW:0:8:=0x04 + 0x00000120, // 835: PHY_RX_CAL_DQ0_3:RW_D+:16:9:=0x0000 PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3:RW:8:1:=0x01 PHY_RX_CAL_SAMPLE_WAIT_3:RW:0:8:=0x20 + 0x00000000, // 836: PHY_RX_CAL_DQ2_3:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQ1_3:RW_D+:0:9:=0x0000 + 0x00000000, // 837: PHY_RX_CAL_DQ4_3:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQ3_3:RW_D+:0:9:=0x0000 + 0x00000000, // 838: PHY_RX_CAL_DQ6_3:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQ5_3:RW_D+:0:9:=0x0000 + 0x00000000, // 839: PHY_RX_CAL_DQ7_3:RW_D+:0:9:=0x0000 + 0x00000000, // 840: PHY_RX_CAL_DM_3:RW_D+:0:18:=0x000000 + 0x00000000, // 841: PHY_RX_CAL_FDBK_3:RW_D+:16:9:=0x0000 PHY_RX_CAL_DQS_3:RW_D+:0:9:=0x0000 + 0x00000000, // 842: PHY_RX_CAL_LOCK_OBS_3:RD:16:9:=0x0000 PHY_RX_CAL_OBS_3:RD:0:11:=0x0000 + 0x00000001, // 843: PHY_RX_CAL_COMP_VAL_3:RW:24:1:=0x00 PHY_RX_CAL_DIFF_ADJUST_3:RW:16:7:=0x00 PHY_RX_CAL_SE_ADJUST_3:RW:8:7:=0x00 PHY_RX_CAL_DISABLE_3:RW_D:0:1:=0x01 + 0x07FF0000, // 844: PHY_PAD_RX_BIAS_EN_3:RW:16:11:=0x07ff PHY_RX_CAL_INDEX_MASK_3:RW:0:12:=0x0000 + 0x0080081F, // 845: PHY_DATA_DC_WEIGHT_3:RW:24:2:=0x00 PHY_DATA_DC_CAL_TIMEOUT_3:RW:16:8:=0x80 PHY_DATA_DC_CAL_SAMPLE_WAIT_3:RW:8:8:=0x08 PHY_STATIC_TOG_DISABLE_3:RW:0:5:=0x1f + 0x00081020, // 846: PHY_DATA_DC_ADJUST_DIRECT_3:RW:24:1:=0x00 PHY_DATA_DC_ADJUST_THRSHLD_3:RW:16:8:=0x08 PHY_DATA_DC_ADJUST_SAMPLE_CNT_3:RW:8:8:=0x10 PHY_DATA_DC_ADJUST_START_3:RW:0:6:=0x20 + 0x04010000, // 847: PHY_FDBK_PWR_CTRL_3:RW:24:3:=0x04 PHY_DATA_DC_SW_RANK_3:RW+:16:2:=0x01 PHY_DATA_DC_CAL_START_3:RW+:8:1:=0x00 PHY_DATA_DC_CAL_POLARITY_3:RW:0:1:=0x00 + 0x00000001, // 848: PHY_SLICE_PWR_RDC_DISABLE_3:RW:24:1:=0x00 PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3:RW_D:16:1:=0x00 PHY_RDPATH_GATE_DISABLE_3:RW_D:8:1:=0x00 PHY_SLV_DLY_CTRL_GATE_DISABLE_3:RW_D:0:1:=0x00 + 0x00000000, // 849: PHY_DS_FSM_ERROR_INFO_3:RD:16:14:=0x0000 PHY_PARITY_ERROR_REGIF_3:RW:0:11:=0x0000 + 0x00000000, // 850: SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3:WR:16:14:=0x0000 PHY_DS_FSM_ERROR_INFO_MASK_3:RW:0:14:=0x0000 + 0x00000100, // 851: SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3:WR:16:5:=0x00 PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3:RW:8:5:=0x01 PHY_DS_TRAIN_CALIB_ERROR_INFO_3:RD:0:5:=0x00 + 0x05CC0C05, // 852: PHY_DQS_TSEL_ENABLE_3:RW+:24:3:=0x01 PHY_DQ_TSEL_SELECT_3:RW+:8:16:=0x4408 PHY_DQ_TSEL_ENABLE_3:RW+:0:3:=0x01 + 0x1603CC0C, // 853: PHY_VREF_INITIAL_START_POINT_3:RW+:24:7:=0x20 PHY_TWO_CYC_PREAMBLE_3:RW+:16:2:=0x03 PHY_DQS_TSEL_SELECT_3:RW+:0:16:=0x4408 + 0x2000012F, // 854: PHY_NTP_WDQ_STEP_SIZE_3:RW+:24:8:=0x20 PHY_NTP_TRAIN_EN_3:RW+:16:1:=0x00 PHY_VREF_TRAINING_CTRL_3:RW+:8:2:=0x01 PHY_VREF_INITIAL_STOP_POINT_3:RW+:0:7:=0x25 + 0x07FF0200, // 855: PHY_NTP_WDQ_STOP_3:RW+:16:11:=0x07FF PHY_NTP_WDQ_START_3:RW+:0:11:=0x0200 + 0x0000DD01, // 856: PHY_SW_WDQLVL_DVW_MIN_EN_3:RW+:24:1:=0x00 PHY_WDQLVL_DVW_MIN_3:RW+:8:10:=0x00dd PHY_NTP_WDQ_BIT_EN_3:RW+:0:8:=0x01 + 0x00000303, // 857: PHY_PAD_RX_DCD_0_3:RW+:24:5:=0x00 PHY_PAD_TX_DCD_3:RW+:16:5:=0x00 PHY_FAST_LVL_EN_3:RW+:8:4:=0x03 PHY_WDQLVL_PER_START_OFFSET_3:RW+:0:6:=0x03 + 0x00000000, // 858: PHY_PAD_RX_DCD_4_3:RW+:24:5:=0x00 PHY_PAD_RX_DCD_3_3:RW+:16:5:=0x00 PHY_PAD_RX_DCD_2_3:RW+:8:5:=0x00 PHY_PAD_RX_DCD_1_3:RW+:0:5:=0x00 + 0x00000000, // 859: PHY_PAD_DM_RX_DCD_3:RW+:24:5:=0x00 PHY_PAD_RX_DCD_7_3:RW+:16:5:=0x00 PHY_PAD_RX_DCD_6_3:RW+:8:5:=0x00 PHY_PAD_RX_DCD_5_3:RW+:0:5:=0x00 + 0x00030000, // 860: PHY_PAD_DSLICE_IO_CFG_3:RW+:16:6:=0x00 PHY_PAD_FDBK_RX_DCD_3:RW+:8:5:=0x00 PHY_PAD_DQS_RX_DCD_3:RW+:0:5:=0x00 + 0x00000000, // 861: PHY_RDDQ1_SLAVE_DELAY_3:RW+:16:10:=0x0000 PHY_RDDQ0_SLAVE_DELAY_3:RW+:0:10:=0x0000 + 0x00000000, // 862: PHY_RDDQ3_SLAVE_DELAY_3:RW+:16:10:=0x0000 PHY_RDDQ2_SLAVE_DELAY_3:RW+:0:10:=0x0000 + 0x00000000, // 863: PHY_RDDQ5_SLAVE_DELAY_3:RW+:16:10:=0x0000 PHY_RDDQ4_SLAVE_DELAY_3:RW+:0:10:=0x0000 + 0x00000000, // 864: PHY_RDDQ7_SLAVE_DELAY_3:RW+:16:10:=0x0000 PHY_RDDQ6_SLAVE_DELAY_3:RW+:0:10:=0x0000 + 0x00050000, // 865: PHY_DATA_DC_CAL_CLK_SEL_3:RW+:16:3:=0x02 PHY_RDDM_SLAVE_DELAY_3:RW+:0:10:=0x0000 + 0x51515042, // 866: PHY_DQS_OE_TIMING_3:RW+:24:8:=0x51 PHY_DQ_TSEL_WR_TIMING_3:RW+:16:8:=0x51 PHY_DQ_TSEL_RD_TIMING_3:RW+:8:8:=0x50 PHY_DQ_OE_TIMING_3:RW+:0:8:=0x42 + 0x31C06000, // 867: PHY_DQS_TSEL_WR_TIMING_3:RW+:24:8:=0x31 PHY_DQS_OE_RD_TIMING_3:RW+:16:8:=0xc0 PHY_DQS_TSEL_RD_TIMING_3:RW+:8:8:=0x60 PHY_IO_PAD_DELAY_TIMING_3:RW+:0:4:=0x00 + 0x07A000A0, // 868: PHY_PAD_VREF_CTRL_DQ_3:RW+:16:12:=0x069f PHY_VREF_SETTING_TIME_3:RW+:0:16:=0x0004 + 0x00C0C001, // 869: PHY_RDDATA_EN_IE_DLY_3:RW+:24:2:=0x00 PHY_DQS_IE_TIMING_3:RW+:16:8:=0xc0 PHY_DQ_IE_TIMING_3:RW+:8:8:=0xc0 PHY_PER_CS_TRAINING_EN_3:RW+:0:1:=0x01 + 0x0E0D0100, // 870: PHY_RDDATA_EN_OE_DLY_3:RW+:24:5:=0x0e PHY_RDDATA_EN_TSEL_DLY_3:RW+:16:5:=0x0d PHY_DBI_MODE_3:RW+:8:1:=0x00 PHY_IE_MODE_3:RW+:0:2:=0x00 + 0x10001000, // 871: PHY_MASTER_DELAY_STEP_3:RW+:24:6:=0x10 PHY_MASTER_DELAY_START_3:RW+:8:11:=0x0010 PHY_SW_MASTER_MODE_3:RW+:0:4:=0x00 + 0x0C063E42, // 872: PHY_WRLVL_DLY_STEP_3:RW+:24:8:=0x0c PHY_RPTR_UPDATE_3:RW+:16:4:=0x06 PHY_MASTER_DELAY_HALF_MEASURE_3:RW+:8:8:=0x3e PHY_MASTER_DELAY_WAIT_3:RW+:0:8:=0x42 + 0x0F0C3701, // 873: PHY_GTLVL_RESP_WAIT_CNT_3:RW+:24:5:=0x0f PHY_GTLVL_DLY_STEP_3:RW+:16:4:=0x0c PHY_WRLVL_RESP_WAIT_CNT_3:RW+:8:6:=0x37 PHY_WRLVL_DLY_FINE_STEP_3:RW+:0:4:=0x01 + 0x01000140, // 874: PHY_GTLVL_FINAL_STEP_3:RW+:16:10:=0x0100 PHY_GTLVL_BACK_STEP_3:RW+:0:10:=0x0140 + 0x0C000120, // 875: PHY_RDLVL_DLY_STEP_3:RW+:24:4:=0x0c PHY_TOGGLE_PRE_SUPPORT_3:RW+:16:1:=0x00 PHY_WDQLVL_QTR_DLY_STEP_3:RW+:8:4:=0x01 PHY_WDQLVL_DLY_STEP_3:RW+:0:8:=0x20 + 0x00000322, // 876: PHY_RDLVL_MAX_EDGE_3:RW+:0:10:=0x0322 + 0x0A0000D0, // 877: PHY_RDLVL_PER_START_OFFSET_3:RW+:24:6:=0x0A PHY_SW_RDLVL_DVW_MIN_EN_3:RW+:16:1:=0x00 PHY_RDLVL_DVW_MIN_3:RW+:0:10:=0x00d0 + 0x00030200, // 878: PHY_DATA_DC_INIT_DISABLE_3:RW+:16:2:=0x00 PHY_WRPATH_GATE_TIMING_3:RW+:8:3:=0x02 PHY_WRPATH_GATE_DISABLE_3:RW+:0:2:=0x00 + 0x02800000, // 879: PHY_DATA_DC_DQ_INIT_SLV_DELAY_3:RW+:16:11:=0x0280 PHY_DATA_DC_DQS_INIT_SLV_DELAY_3:RW+:0:10:=0x0000 + 0x80800000, // 880: PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3:RW+:24:8:=0x80 PHY_DATA_DC_DM_CLK_SE_THRSHLD_3:RW+:16:8:=0x80 PHY_DATA_DC_WDQLVL_ENABLE_3:RW+:8:1:=0x01 PHY_DATA_DC_WRLVL_ENABLE_3:RW+:0:1:=0x01 + 0x000E2010, // 881: PHY_RDDATA_EN_DLY_3:RW+:16:5:=0x0e PHY_MEAS_DLY_STEP_ENABLE_3:RW+:8:6:=0x20 PHY_WDQ_OSC_DELTA_3:RW+:0:7:=0x10 + 0x06173452, // 882: PHY_DQ_DM_SWIZZLE0_3:RW+:0:32:=0x76543210 + 0x00000008, // 883: PHY_DQ_DM_SWIZZLE1_3:RW+:0:4:=0x08 + 0x02800280, // 884: PHY_CLK_WRDQ1_SLAVE_DELAY_3:RW+:16:11:=0x0280 PHY_CLK_WRDQ0_SLAVE_DELAY_3:RW+:0:11:=0x0280 + 0x02800280, // 885: PHY_CLK_WRDQ3_SLAVE_DELAY_3:RW+:16:11:=0x0280 PHY_CLK_WRDQ2_SLAVE_DELAY_3:RW+:0:11:=0x0280 + 0x02800280, // 886: PHY_CLK_WRDQ5_SLAVE_DELAY_3:RW+:16:11:=0x0280 PHY_CLK_WRDQ4_SLAVE_DELAY_3:RW+:0:11:=0x0280 + 0x02800280, // 887: PHY_CLK_WRDQ7_SLAVE_DELAY_3:RW+:16:11:=0x0280 PHY_CLK_WRDQ6_SLAVE_DELAY_3:RW+:0:11:=0x0280 + 0x00000280, // 888: PHY_CLK_WRDQS_SLAVE_DELAY_3:RW+:16:10:=0x0000 PHY_CLK_WRDM_SLAVE_DELAY_3:RW+:0:11:=0x0280 + 0x0000A000, // 889: PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3:RW+:8:10:=0x00a0 PHY_WRLVL_THRESHOLD_ADJUST_3:RW+:0:2:=0x00 + 0x00A000A0, // 890: PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0 + 0x00A000A0, // 891: PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0 + 0x00A000A0, // 892: PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0 + 0x00A000A0, // 893: PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0 + 0x00A000A0, // 894: PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0 + 0x00A000A0, // 895: PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0 + 0x00A000A0, // 896: PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0 + 0x00A000A0, // 897: PHY_RDDQS_DM_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0 + 0x01C200A0, // 898: PHY_RDDQS_GATE_SLAVE_DELAY_3:RW+:16:10:=0x01c2 PHY_RDDQS_DM_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0 + 0x01A00005, // 899: PHY_WRLVL_DELAY_EARLY_THRESHOLD_3:RW+:16:10:=0x01A0 PHY_WRITE_PATH_LAT_ADD_3:RW+:8:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_3:RW+:0:4:=0x05 + 0x00000000, // 900: PHY_WRLVL_EARLY_FORCE_ZERO_3:RW+:16:1:=0x00 PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3:RW+:0:10:=0x0000 + 0x00060000, // 901: PHY_GTLVL_LAT_ADJ_START_3:RW+:16:4:=0x06 PHY_GTLVL_RDDQS_SLV_DLY_START_3:RW+:0:10:=0x0000 + 0x00080200, // 902: PHY_NTP_PASS_3:RW+:24:1:=0x00 PHY_NTP_WRLAT_START_3:RW+:16:4:=0x08 PHY_WDQLVL_DQDM_SLV_DLY_START_3:RW+:0:11:=0x0200 + 0x00000000, // 903: PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3:RW+:0:10:=0x0000 + 0x20202020, // 904: PHY_DATA_DC_DQ2_CLK_ADJUST_3:RW+:24:8:=0x20 PHY_DATA_DC_DQ1_CLK_ADJUST_3:RW+:16:8:=0x20 PHY_DATA_DC_DQ0_CLK_ADJUST_3:RW+:8:8:=0x20 PHY_DATA_DC_DQS_CLK_ADJUST_3:RW+:0:8:=0x20 + 0x20202020, // 905: PHY_DATA_DC_DQ6_CLK_ADJUST_3:RW+:24:8:=0x20 PHY_DATA_DC_DQ5_CLK_ADJUST_3:RW+:16:8:=0x20 PHY_DATA_DC_DQ4_CLK_ADJUST_3:RW+:8:8:=0x20 PHY_DATA_DC_DQ3_CLK_ADJUST_3:RW+:0:8:=0x20 + 0xF0F02020, // 906: PHY_DSLICE_PAD_BOOSTPN_SETTING_3:RW+:16:16:=0x0000 PHY_DATA_DC_DM_CLK_ADJUST_3:RW+:8:8:=0x20 PHY_DATA_DC_DQ7_CLK_ADJUST_3:RW+:0:8:=0x20 + 0x00000000, // 907: PHY_DQS_FFE_3:RW+:16:2:=0x00 PHY_DQ_FFE_3:RW+:8:2:=0x00 PHY_DSLICE_PAD_RX_CTLE_SETTING_3:RW+:0:6:=0x00 + 0x00000000, // 908: + 0x00000000, // 909: + 0x00000000, // 910: + 0x00000000, // 911: + 0x00000000, // 912: + 0x00000000, // 913: + 0x00000000, // 914: + 0x00000000, // 915: + 0x00000000, // 916: + 0x00000000, // 917: + 0x00000000, // 918: + 0x00000000, // 919: + 0x00000000, // 920: + 0x00000000, // 921: + 0x00000000, // 922: + 0x00000000, // 923: + 0x00000000, // 924: + 0x00000000, // 925: + 0x00000000, // 926: + 0x00000000, // 927: + 0x00000000, // 928: + 0x00000000, // 929: + 0x00000000, // 930: + 0x00000000, // 931: + 0x00000000, // 932: + 0x00000000, // 933: + 0x00000000, // 934: + 0x00000000, // 935: + 0x00000000, // 936: + 0x00000000, // 937: + 0x00000000, // 938: + 0x00000000, // 939: + 0x00000000, // 940: + 0x00000000, // 941: + 0x00000000, // 942: + 0x00000000, // 943: + 0x00000000, // 944: + 0x00000000, // 945: + 0x00000000, // 946: + 0x00000000, // 947: + 0x00000000, // 948: + 0x00000000, // 949: + 0x00000000, // 950: + 0x00000000, // 951: + 0x00000000, // 952: + 0x00000000, // 953: + 0x00000000, // 954: + 0x00000000, // 955: + 0x00000000, // 956: + 0x00000000, // 957: + 0x00000000, // 958: + 0x00000000, // 959: + 0x00000000, // 960: + 0x00000000, // 961: + 0x00000000, // 962: + 0x00000000, // 963: + 0x00000000, // 964: + 0x00000000, // 965: + 0x00000000, // 966: + 0x00000000, // 967: + 0x00000000, // 968: + 0x00000000, // 969: + 0x00000000, // 970: + 0x00000000, // 971: + 0x00000000, // 972: + 0x00000000, // 973: + 0x00000000, // 974: + 0x00000000, // 975: + 0x00000000, // 976: + 0x00000000, // 977: + 0x00000000, // 978: + 0x00000000, // 979: + 0x00000000, // 980: + 0x00000000, // 981: + 0x00000000, // 982: + 0x00000000, // 983: + 0x00000000, // 984: + 0x00000000, // 985: + 0x00000000, // 986: + 0x00000000, // 987: + 0x00000000, // 988: + 0x00000000, // 989: + 0x00000000, // 990: + 0x00000000, // 991: + 0x00000000, // 992: + 0x00000000, // 993: + 0x00000000, // 994: + 0x00000000, // 995: + 0x00000000, // 996: + 0x00000000, // 997: + 0x00000000, // 998: + 0x00000000, // 999: + 0x00000000, // 1000: + 0x00000000, // 1001: + 0x00000000, // 1002: + 0x00000000, // 1003: + 0x00000000, // 1004: + 0x00000000, // 1005: + 0x00000000, // 1006: + 0x00000000, // 1007: + 0x00000000, // 1008: + 0x00000000, // 1009: + 0x00000000, // 1010: + 0x00000000, // 1011: + 0x00000000, // 1012: + 0x00000000, // 1013: + 0x00000000, // 1014: + 0x00000000, // 1015: + 0x00000000, // 1016: + 0x00000000, // 1017: + 0x00000000, // 1018: + 0x00000000, // 1019: + 0x00000000, // 1020: + 0x00000000, // 1021: + 0x00000000, // 1022: + 0x00000000, // 1023: + 0x00000000, // 1024: SC_PHY_ADR_MANUAL_CLEAR_0:WR:24:3:=0x00 PHY_ADR_CLK_BYPASS_OVERRIDE_0:RW:16:1:=0x00 PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0:RW:0:11:=0x0000 + 0x00000000, // 1025: PHY_ADR_LPBK_RESULT_OBS_0:RD:0:32:=0x00000000 + 0x00000000, // 1026: PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0:RW:24:4:=0x00 PHY_ADR_MEAS_DLY_STEP_VALUE_0:RD:16:8:=0x00 PHY_ADR_LPBK_ERROR_COUNT_OBS_0:RD:0:16:=0x0000 + 0x00000000, // 1027: PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0:RD:24:8:=0x00 PHY_ADR_BASE_SLV_DLY_ENC_OBS_0:RD:16:7:=0x00 PHY_ADR_MASTER_DLY_LOCK_OBS_0:RD:0:11:=0x0000 + 0x00000000, // 1028: PHY_ADR_TSEL_ENABLE_0:RW:24:1:=0x00 SC_PHY_ADR_SNAP_OBS_REGS_0:WR:16:1:=0x00 PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0:RW:8:3:=0x00 PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0:RW:0:3:=0x00 + 0x00000100, // 1029: PHY_ADR_PWR_RDC_DISABLE_0:RW:24:1:=0x00 PHY_ADR_PRBS_PATTERN_MASK_0:RW:16:5:=0x00 PHY_ADR_PRBS_PATTERN_START_0:RW_D:8:7:=0x01 PHY_ADR_LPBK_CONTROL_0:RW:0:7:=0x00 + 0x00000201, // 1030: PHY_ADR_IE_MODE_0:RW:24:1:=0x00 PHY_ADR_WRADDR_SHIFT_OBS_0:RD:16:3:=0x00 PHY_ADR_TYPE_0:RW:8:2:=0x02 PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0:RW_D:0:1:=0x00 + 0x00000000, // 1031: PHY_ADR_DDL_MODE_0:RW:0:27:=0x00000000 + 0x00000000, // 1032: PHY_ADR_DDL_MASK_0:RW:0:6:=0x00 + 0x00000000, // 1033: PHY_ADR_DDL_TEST_OBS_0:RD:0:32:=0x00000000 + 0x00000000, // 1034: PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0:RD:0:32:=0x00000000 + 0x00400000, // 1035: PHY_ADR_CALVL_COARSE_DLY_0:RW:16:11:=0x0040 PHY_ADR_CALVL_START_0:RW:0:11:=0x0000 + 0x00000080, // 1036: PHY_ADR_CALVL_QTR_0:RW:0:11:=0x0080 + 0x00DCBA98, // 1037: PHY_ADR_CALVL_SWIZZLE0_0:RW:0:24:=0xdcba98 + 0x03000000, // 1038: PHY_ADR_CALVL_RANK_CTRL_0:RW:24:2:=0x03 PHY_ADR_CALVL_SWIZZLE1_0:RW:0:24:=0x000000 + 0x00200000, // 1039: PHY_ADR_CALVL_PERIODIC_START_OFFSET_0:RW:16:9:=0x0020 PHY_ADR_CALVL_RESP_WAIT_CNT_0:RW:8:4:=0x00 PHY_ADR_CALVL_NUM_PATTERNS_0:RW:0:2:=0x00 + 0x00000000, // 1040: PHY_ADR_CALVL_OBS_SELECT_0:RW:24:3:=0x00 SC_PHY_ADR_CALVL_ERROR_CLR_0:WR:16:1:=0x00 SC_PHY_ADR_CALVL_DEBUG_CONT_0:WR:8:1:=0x00 PHY_ADR_CALVL_DEBUG_MODE_0:RW:0:1:=0x00 + 0x00000000, // 1041: PHY_ADR_CALVL_CH0_OBS0_0:RD:0:32:=0x00000000 + 0x00000000, // 1042: PHY_ADR_CALVL_CH1_OBS0_0:RD:0:32:=0x00000000 + 0x00000000, // 1043: PHY_ADR_CALVL_OBS1_0:RD:0:32:=0x00000000 + 0x00000000, // 1044: PHY_ADR_CALVL_OBS2_0:RD:0:32:=0x00000000 + 0x0000002A, // 1045: PHY_ADR_CALVL_FG_0_0:RW:0:20:=0x00002a + 0x00000015, // 1046: PHY_ADR_CALVL_BG_0_0:RW:0:20:=0x000015 + 0x00000015, // 1047: PHY_ADR_CALVL_FG_1_0:RW:0:20:=0x000015 + 0x0000002A, // 1048: PHY_ADR_CALVL_BG_1_0:RW:0:20:=0x00002a + 0x00000033, // 1049: PHY_ADR_CALVL_FG_2_0:RW:0:20:=0x000033 + 0x0000000C, // 1050: PHY_ADR_CALVL_BG_2_0:RW:0:20:=0x00000c + 0x0000000C, // 1051: PHY_ADR_CALVL_FG_3_0:RW:0:20:=0x00000c + 0x00000033, // 1052: PHY_ADR_CALVL_BG_3_0:RW:0:20:=0x000033 + 0x00543210, // 1053: PHY_ADR_ADDR_SEL_0:RW:0:24:=0x543210 + 0x003F0000, // 1054: PHY_ADR_SEG_MASK_0:RW:24:6:=0x00 PHY_ADR_BIT_MASK_0:RW:16:6:=0x3f PHY_ADR_LP4_BOOT_SLV_DELAY_0:RW:0:10:=0x0000 + 0x000F013F, // 1055: PHY_ADR_SW_TXIO_CTRL_0:RW:24:6:=0x00 PHY_ADR_STATIC_TOG_DISABLE_0:RW:16:4:=0x0f PHY_ADR_CSLVL_TRAIN_MASK_0:RW:8:6:=0x01 PHY_ADR_CALVL_TRAIN_MASK_0:RW:0:6:=0x3f + 0x20202000, // 1056: PHY_ADR_DC_ADR2_CLK_ADJUST_0:RW+:24:8:=0x20 PHY_ADR_DC_ADR1_CLK_ADJUST_0:RW+:16:8:=0x20 PHY_ADR_DC_ADR0_CLK_ADJUST_0:RW+:8:8:=0x20 PHY_ADR_DC_INIT_DISABLE_0:RW+:0:2:=0x00 + 0x00202020, // 1057: PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0:RW_D:24:1:=0x00 PHY_ADR_DC_ADR5_CLK_ADJUST_0:RW+:16:8:=0x20 PHY_ADR_DC_ADR4_CLK_ADJUST_0:RW+:8:8:=0x20 PHY_ADR_DC_ADR3_CLK_ADJUST_0:RW+:0:8:=0x20 + 0x20008008, // 1058: PHY_ADR_DC_ADJUST_START_0:RW:24:6:=0x20 PHY_ADR_DC_WEIGHT_0:RW:16:2:=0x00 PHY_ADR_DC_CAL_TIMEOUT_0:RW:8:8:=0x80 PHY_ADR_DC_CAL_SAMPLE_WAIT_0:RW:0:8:=0x08 + 0x00000810, // 1059: PHY_ADR_DC_CAL_POLARITY_0:RW:24:1:=0x00 PHY_ADR_DC_ADJUST_DIRECT_0:RW:16:1:=0x00 PHY_ADR_DC_ADJUST_THRSHLD_0:RW:8:8:=0x08 PHY_ADR_DC_ADJUST_SAMPLE_CNT_0:RW:0:8:=0x10 + 0x00000F00, // 1060: PHY_PARITY_ERROR_REGIF_ADR_0:RW:16:11:=0x0000 PHY_ADR_SW_TXPWR_CTRL_0:RW:8:6:=0x0f PHY_ADR_DC_CAL_START_0:RW+:0:1:=0x00 + 0x00000000, // 1061: PHY_AS_FSM_ERROR_INFO_MASK_0:RW:16:9:=0x0000 PHY_AS_FSM_ERROR_INFO_0:RD:0:9:=0x0000 + 0x00000000, // 1062: PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0:RW:24:1:=0x00 PHY_AS_TRAIN_CALIB_ERROR_INFO_0:RD:16:1:=0x00 SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0:WR:0:9:=0x0000 + 0x00000000, // 1063: SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0:WR:0:1:=0x00 + 0x000604CC, // 1064: PHY_PAD_ADR_IO_CFG_0:RW+:16:11:=0x0000 PHY_ADR_DC_CAL_CLK_SEL_0:RW+:8:3:=0x02 PHY_ADR_TSEL_SELECT_0:RW+:0:8:=0x44 + 0x00030000, // 1065: PHY_ADR1_SW_WRADDR_SHIFT_0:RW+:24:5:=0x00 PHY_ADR0_CLK_WR_SLAVE_DELAY_0:RW+:8:11:=0x0300 PHY_ADR0_SW_WRADDR_SHIFT_0:RW+:0:5:=0x00 + 0x00000300, // 1066: PHY_ADR2_SW_WRADDR_SHIFT_0:RW+:16:5:=0x00 PHY_ADR1_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 + 0x00000300, // 1067: PHY_ADR3_SW_WRADDR_SHIFT_0:RW+:16:5:=0x00 PHY_ADR2_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 + 0x00000300, // 1068: PHY_ADR4_SW_WRADDR_SHIFT_0:RW+:16:5:=0x00 PHY_ADR3_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 + 0x00000300, // 1069: PHY_ADR5_SW_WRADDR_SHIFT_0:RW+:16:5:=0x00 PHY_ADR4_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 + 0x00000300, // 1070: PHY_ADR_SW_MASTER_MODE_0:RW+:16:4:=0x00 PHY_ADR5_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 + 0x42080010, // 1071: PHY_ADR_MASTER_DELAY_WAIT_0:RW+:24:8:=0x42 PHY_ADR_MASTER_DELAY_STEP_0:RW+:16:6:=0x08 PHY_ADR_MASTER_DELAY_START_0:RW+:0:11:=0x0010 + 0x0000803E, // 1072: PHY_ADR_SW_CALVL_DVW_MIN_EN_0:RW+:24:1:=0x00 PHY_ADR_SW_CALVL_DVW_MIN_0:RW+:8:10:=0x0080 PHY_ADR_MASTER_DELAY_HALF_MEASURE_0:RW+:0:8:=0x3e + 0x00000001, // 1073: PHY_ADR_CALVL_DLY_STEP_0:RW+:0:4:=0x01 + 0x01000102, // 1074: PHY_ADR_DC_INIT_SLV_DELAY_0:RW+:16:10:=0x0100 PHY_ADR_MEAS_DLY_STEP_ENABLE_0:RW+:8:1:=0x01 PHY_ADR_CALVL_CAPTURE_CNT_0:RW+:0:4:=0x02 + 0x00008000, // 1075: PHY_ADR_DC_DM_CLK_THRSHLD_0:RW+:8:8:=0x80 PHY_ADR_DC_CALVL_ENABLE_0:RW+:0:1:=0x01 + 0x00000000, // 1076: + 0x00000000, // 1077: + 0x00000000, // 1078: + 0x00000000, // 1079: + 0x00000000, // 1080: + 0x00000000, // 1081: + 0x00000000, // 1082: + 0x00000000, // 1083: + 0x00000000, // 1084: + 0x00000000, // 1085: + 0x00000000, // 1086: + 0x00000000, // 1087: + 0x00000000, // 1088: + 0x00000000, // 1089: + 0x00000000, // 1090: + 0x00000000, // 1091: + 0x00000000, // 1092: + 0x00000000, // 1093: + 0x00000000, // 1094: + 0x00000000, // 1095: + 0x00000000, // 1096: + 0x00000000, // 1097: + 0x00000000, // 1098: + 0x00000000, // 1099: + 0x00000000, // 1100: + 0x00000000, // 1101: + 0x00000000, // 1102: + 0x00000000, // 1103: + 0x00000000, // 1104: + 0x00000000, // 1105: + 0x00000000, // 1106: + 0x00000000, // 1107: + 0x00000000, // 1108: + 0x00000000, // 1109: + 0x00000000, // 1110: + 0x00000000, // 1111: + 0x00000000, // 1112: + 0x00000000, // 1113: + 0x00000000, // 1114: + 0x00000000, // 1115: + 0x00000000, // 1116: + 0x00000000, // 1117: + 0x00000000, // 1118: + 0x00000000, // 1119: + 0x00000000, // 1120: + 0x00000000, // 1121: + 0x00000000, // 1122: + 0x00000000, // 1123: + 0x00000000, // 1124: + 0x00000000, // 1125: + 0x00000000, // 1126: + 0x00000000, // 1127: + 0x00000000, // 1128: + 0x00000000, // 1129: + 0x00000000, // 1130: + 0x00000000, // 1131: + 0x00000000, // 1132: + 0x00000000, // 1133: + 0x00000000, // 1134: + 0x00000000, // 1135: + 0x00000000, // 1136: + 0x00000000, // 1137: + 0x00000000, // 1138: + 0x00000000, // 1139: + 0x00000000, // 1140: + 0x00000000, // 1141: + 0x00000000, // 1142: + 0x00000000, // 1143: + 0x00000000, // 1144: + 0x00000000, // 1145: + 0x00000000, // 1146: + 0x00000000, // 1147: + 0x00000000, // 1148: + 0x00000000, // 1149: + 0x00000000, // 1150: + 0x00000000, // 1151: + 0x00000000, // 1152: + 0x00000000, // 1153: + 0x00000000, // 1154: + 0x00000000, // 1155: + 0x00000000, // 1156: + 0x00000000, // 1157: + 0x00000000, // 1158: + 0x00000000, // 1159: + 0x00000000, // 1160: + 0x00000000, // 1161: + 0x00000000, // 1162: + 0x00000000, // 1163: + 0x00000000, // 1164: + 0x00000000, // 1165: + 0x00000000, // 1166: + 0x00000000, // 1167: + 0x00000000, // 1168: + 0x00000000, // 1169: + 0x00000000, // 1170: + 0x00000000, // 1171: + 0x00000000, // 1172: + 0x00000000, // 1173: + 0x00000000, // 1174: + 0x00000000, // 1175: + 0x00000000, // 1176: + 0x00000000, // 1177: + 0x00000000, // 1178: + 0x00000000, // 1179: + 0x00000000, // 1180: + 0x00000000, // 1181: + 0x00000000, // 1182: + 0x00000000, // 1183: + 0x00000000, // 1184: + 0x00000000, // 1185: + 0x00000000, // 1186: + 0x00000000, // 1187: + 0x00000000, // 1188: + 0x00000000, // 1189: + 0x00000000, // 1190: + 0x00000000, // 1191: + 0x00000000, // 1192: + 0x00000000, // 1193: + 0x00000000, // 1194: + 0x00000000, // 1195: + 0x00000000, // 1196: + 0x00000000, // 1197: + 0x00000000, // 1198: + 0x00000000, // 1199: + 0x00000000, // 1200: + 0x00000000, // 1201: + 0x00000000, // 1202: + 0x00000000, // 1203: + 0x00000000, // 1204: + 0x00000000, // 1205: + 0x00000000, // 1206: + 0x00000000, // 1207: + 0x00000000, // 1208: + 0x00000000, // 1209: + 0x00000000, // 1210: + 0x00000000, // 1211: + 0x00000000, // 1212: + 0x00000000, // 1213: + 0x00000000, // 1214: + 0x00000000, // 1215: + 0x00000000, // 1216: + 0x00000000, // 1217: + 0x00000000, // 1218: + 0x00000000, // 1219: + 0x00000000, // 1220: + 0x00000000, // 1221: + 0x00000000, // 1222: + 0x00000000, // 1223: + 0x00000000, // 1224: + 0x00000000, // 1225: + 0x00000000, // 1226: + 0x00000000, // 1227: + 0x00000000, // 1228: + 0x00000000, // 1229: + 0x00000000, // 1230: + 0x00000000, // 1231: + 0x00000000, // 1232: + 0x00000000, // 1233: + 0x00000000, // 1234: + 0x00000000, // 1235: + 0x00000000, // 1236: + 0x00000000, // 1237: + 0x00000000, // 1238: + 0x00000000, // 1239: + 0x00000000, // 1240: + 0x00000000, // 1241: + 0x00000000, // 1242: + 0x00000000, // 1243: + 0x00000000, // 1244: + 0x00000000, // 1245: + 0x00000000, // 1246: + 0x00000000, // 1247: + 0x00000000, // 1248: + 0x00000000, // 1249: + 0x00000000, // 1250: + 0x00000000, // 1251: + 0x00000000, // 1252: + 0x00000000, // 1253: + 0x00000000, // 1254: + 0x00000000, // 1255: + 0x00000000, // 1256: + 0x00000000, // 1257: + 0x00000000, // 1258: + 0x00000000, // 1259: + 0x00000000, // 1260: + 0x00000000, // 1261: + 0x00000000, // 1262: + 0x00000000, // 1263: + 0x00000000, // 1264: + 0x00000000, // 1265: + 0x00000000, // 1266: + 0x00000000, // 1267: + 0x00000000, // 1268: + 0x00000000, // 1269: + 0x00000000, // 1270: + 0x00000000, // 1271: + 0x00000000, // 1272: + 0x00000000, // 1273: + 0x00000000, // 1274: + 0x00000000, // 1275: + 0x00000000, // 1276: + 0x00000000, // 1277: + 0x00000000, // 1278: + 0x00000000, // 1279: + 0x00000000, // 1280: PHY_FREQ_SEL:RW:0:2:=0x00 + 0x00000100, // 1281: PHY_SW_GRP0_SHIFT_0:RW+:24:5:=0x00 PHY_FREQ_SEL_INDEX:RW+:16:2:=0x00 PHY_FREQ_SEL_MULTICAST_EN:RW+:8:1:=0x01 PHY_FREQ_SEL_FROM_REGIF:RW_D:0:1:=0x00 + 0x00000000, // 1282: PHY_SW_GRP0_SHIFT_1:RW+:24:5:=0x00 PHY_SW_GRP3_SHIFT_0:RW+:16:5:=0x00 PHY_SW_GRP2_SHIFT_0:RW+:8:5:=0x00 PHY_SW_GRP1_SHIFT_0:RW+:0:5:=0x00 + 0x00000000, // 1283: PHY_SW_GRP3_SHIFT_1:RW+:16:5:=0x00 PHY_SW_GRP2_SHIFT_1:RW+:8:5:=0x00 PHY_SW_GRP1_SHIFT_1:RW+:0:5:=0x00 + 0x00050000, // 1284: PHY_GRP_BYPASS_OVERRIDE:RW:24:1:=0x00 PHY_SW_GRP_BYPASS_SHIFT:RW:16:5:=0x05 PHY_GRP_BYPASS_SLAVE_DELAY:RW:0:11:=0x0000 + 0x04000000, // 1285: PHY_CSLVL_START:RW:16:11:=0x0400 PHY_MANUAL_UPDATE_PHYUPD_ENABLE:RW_D:8:1:=0x00 SC_PHY_MANUAL_UPDATE:WR:0:1:=0x00 + 0x00000055, // 1286: SC_PHY_CSLVL_DEBUG_CONT:WR:24:1:=0x00 PHY_CSLVL_DEBUG_MODE:RW:16:1:=0x00 PHY_CSLVL_COARSE_DLY:RW:0:11:=0x0055 + 0x00000000, // 1287: SC_PHY_CSLVL_ERROR_CLR:WR:0:1:=0x00 + 0x00000000, // 1288: PHY_CSLVL_OBS0:RD:0:32:=0x00000000 + 0x00000000, // 1289: PHY_CSLVL_OBS1:RD:0:32:=0x00000000 + 0x00000000, // 1290: PHY_CSLVL_OBS2:RD:0:32:=0x00000000 + 0x00002001, // 1291: PHY_LP4_BOOT_DISABLE:RW:24:1:=0x00 PHY_CSLVL_PERIODIC_START_OFFSET:RW:8:9:=0x0020 PHY_CSLVL_ENABLE:RW:0:1:=0x01 + 0x0000400F, // 1292: PHY_CSLVL_QTR:RW:8:11:=0x0040 PHY_CSLVL_CS_MAP:RW:0:4:=0x0f + 0x50020028, // 1293: PHY_CALVL_CS_MAP:RW:24:8:=0x50 PHY_CSLVL_COARSE_CAPTURE_CNT:RW:16:4:=0x02 PHY_CSLVL_COARSE_CHK:RW:0:11:=0x0028 + 0x01010000, // 1294: PHY_ADRCTL_LPDDR:RW:24:1:=0x01 PHY_DFI_PHYUPD_TYPE:RW:16:2:=0x01 PHY_ADRCTL_SNAP_OBS_REGS:WR:8:1:=0x00 PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE:RW:0:3:=0x00 + 0x80080001, // 1295: PHY_CLK_DC_CAL_TIMEOUT:RW:24:8:=0x80 PHY_CLK_DC_CAL_SAMPLE_WAIT:RW:16:8:=0x08 PHY_LPDDR3_CS:RW_D:8:1:=0x00 PHY_LP4_ACTIVE:RW:0:1:=0x01 + 0x10200000, // 1296: PHY_CLK_DC_ADJUST_SAMPLE_CNT:RW:24:8:=0x10 PHY_CLK_DC_ADJUST_START:RW:16:6:=0x20 PHY_CLK_DC_FREQ_CHG_ADJ:RW:8:1:=0x00 PHY_CLK_DC_WEIGHT:RW:0:2:=0x00 + 0x00000008, // 1297: PHY_CLK_DC_CAL_START:RW+:24:1:=0x00 PHY_CLK_DC_CAL_POLARITY:RW:16:1:=0x00 PHY_CLK_DC_ADJUST_DIRECT:RW:8:1:=0x00 PHY_CLK_DC_ADJUST_THRSHLD:RW:0:8:=0x08 + 0x00000100, // 1298: PHY_SW_TXIO_CTRL_1:RW:24:4:=0x00 PHY_SW_TXIO_CTRL_0:RW:16:4:=0x00 PHY_CONTINUOUS_CLK_CAL_UPDATE:RW:8:1:=0x00 SC_PHY_UPDATE_CLK_CAL_VALUES:WR:0:1:=0x00 + 0x01090E00, // 1299: PHY_MEMCLK_SW_TXPWR_CTRL:RW:24:1:=0x01 PHY_ADRCTL_SW_TXPWR_CTRL_1:RW:16:4:=0x09 PHY_ADRCTL_SW_TXPWR_CTRL_0:RW:8:4:=0x0e PHY_MEMCLK_SW_TXIO_CTRL:RW:0:1:=0x00 + 0x00040101, // 1300: PHY_STATIC_TOG_CONTROL:RW:16:16:=0x0004 PHY_BYTE_DISABLE_STATIC_TOG_DISABLE:RW:8:1:=0x01 PHY_TOP_STATIC_TOG_DISABLE:RW:0:1:=0x01 + 0x0000010F, // 1301: PHY_LP4_BOOT_PLL_BYPASS:RW:16:1:=0x00 PHY_MEMCLK_STATIC_TOG_DISABLE:RW:8:1:=0x01 PHY_ADRCTL_STATIC_TOG_DISABLE:RW:0:4:=0x0f + 0x00000000, // 1302: PHY_CLK_SWITCH_OBS:RD:0:32:=0x00000000 + 0x00000064, // 1303: PHY_PLL_WAIT:RW:0:16:=0x0064 + 0x00000000, // 1304: PHY_SW_PLL_BYPASS:RW+:0:1:=0x00 + 0x01010000, // 1305: PHY_CS_ACS_ALLOCATION_BIT1_0:RW:24:4:=0x01 PHY_CS_ACS_ALLOCATION_BIT0_0:RW:16:4:=0x01 PHY_SET_DFI_INPUT_1:RW_D:8:4:=0x00 PHY_SET_DFI_INPUT_0:RW_D:0:4:=0x00 + 0x01080402, // 1306: PHY_CS_ACS_ALLOCATION_BIT1_1:RW:24:4:=0x01 PHY_CS_ACS_ALLOCATION_BIT0_1:RW:16:4:=0x08 PHY_CS_ACS_ALLOCATION_BIT3_0:RW:8:4:=0x04 PHY_CS_ACS_ALLOCATION_BIT2_0:RW:0:4:=0x02 + 0x01200F02, // 1307: PHY_CLK_DC_INIT_DISABLE:RW+:24:1:=0x00 PHY_CLK_DC_ADJUST_0:RW+:16:8:=0x20 PHY_CS_ACS_ALLOCATION_BIT3_1:RW:8:4:=0x0f PHY_CS_ACS_ALLOCATION_BIT2_1:RW:0:4:=0x02 + 0x001B4280, // 1308: PHY_LP4_BOOT_PLL_CTRL:RW:8:13:=0x1b42 PHY_CLK_DC_DM_THRSHLD:RW+:0:8:=0x80 + 0x00010004, // 1309: PHY_USE_PLL_DSKEWCALLOCK:RW:16:1:=0x01 PHY_PLL_CTRL_OVERRIDE:RW:0:16:=0x0004 + 0x00050000, // 1310: SC_PHY_PLL_SPO_CAL_SNAP_OBS:WR:24:2:=0x00 PHY_PLL_SPO_CAL_CTRL:RW:0:19:=0x050000 + 0x00000000, // 1311: SC_PHY_PLL_CAL_CLK_MEAS:WR:16:2:=0x00 PHY_PLL_CAL_CLK_MEAS_CYCLES:RW:0:10:=0x0000 + 0x00000000, // 1312: PHY_PLL_OBS_0:RD:0:16:=0x0000 + 0x00000000, // 1313: PHY_PLL_SPO_CAL_OBS_0:RD:0:17:=0x000000 + 0x00000000, // 1314: PHY_PLL_CAL_CLK_MEAS_OBS_0:RD:0:18:=0x000000 + 0x00000000, // 1315: PHY_PLL_OBS_1:RD:0:16:=0x0000 + 0x00000000, // 1316: PHY_PLL_SPO_CAL_OBS_1:RD:0:17:=0x000000 + 0x01000000, // 1317: PHY_LP4_BOOT_LOW_FREQ_SEL:RW:24:1:=0x01 PHY_PLL_CAL_CLK_MEAS_OBS_1:RD:0:18:=0x000000 + 0x00000705, // 1318: PHY_LS_IDLE_EN:RW:16:1:=0x01 PHY_LP_WAKEUP:RW:8:8:=0x07 PHY_TCKSRE_WAIT:RW:0:4:=0x05 + 0x00000054, // 1319: PHY_TDFI_PHY_WRDELAY:RW:16:1:=0x00 PHY_LP_CTRLUPD_CNTR_CFG:RW:0:10:=0x0054 + 0x00024410, // 1320: PHY_PAD_FDBK_TERM:RW+:0:18:=0x004410 + 0x00004410, // 1321: PHY_PAD_DATA_TERM:RW+:0:17:=0x004410 + 0x00004410, // 1322: PHY_PAD_DQS_TERM:RW+:0:17:=0x004410 + 0x00004410, // 1323: PHY_PAD_ADDR_TERM:RW+:0:18:=0x004410 + 0x00004410, // 1324: PHY_PAD_CLK_TERM:RW+:0:18:=0x004410 + 0x00004410, // 1325: PHY_PAD_CKE_TERM:RW+:0:18:=0x004410 + 0x00004410, // 1326: PHY_PAD_RST_TERM:RW+:0:18:=0x004410 + 0x00004410, // 1327: PHY_PAD_CS_TERM:RW+:0:18:=0x004410 + 0x00004410, // 1328: PHY_PAD_ODT_TERM:RW+:0:18:=0x004410 + 0x00000000, // 1329: PHY_ADRCTL_LP3_RX_CAL:RW:16:13:=0x0000 PHY_ADRCTL_RX_CAL:RW:0:10:=0x0000 + 0x00000076, // 1330: PHY_CAL_START_0:WR:24:1:=0x00 PHY_CAL_CLEAR_0:WR:16:1:=0x00 PHY_CAL_MODE_0:RW:0:13:=0x0064 + 0x00001000, // 1331: PHY_CAL_INTERVAL_COUNT_0:RW:0:32:=0x00000000 + 0x00000108, // 1332: PHY_LP4_BOOT_CAL_CLK_SELECT_0:RW:8:3:=0x01 PHY_CAL_SAMPLE_WAIT_0:RW:0:8:=0x08 + 0x00000000, // 1333: PHY_CAL_RESULT_OBS_0:RD:0:24:=0x000000 + 0x00000000, // 1334: PHY_CAL_RESULT2_OBS_0:RD:0:24:=0x000000 + 0x00000000, // 1335: PHY_CAL_RESULT4_OBS_0:RD:0:24:=0x000000 + 0x00000000, // 1336: PHY_CAL_RESULT5_OBS_0:RD:0:24:=0x000000 + 0x00000000, // 1337: PHY_CAL_RESULT6_OBS_0:RD:0:24:=0x000000 + 0x03000000, // 1338: PHY_CAL_CPTR_CNT_0:RW:24:7:=0x03 PHY_CAL_RESULT7_OBS_0:RD:0:24:=0x000000 + 0x00000000, // 1339: PHY_CAL_DBG_CFG_0:RW:24:1:=0x00 PHY_CAL_RCV_FINE_ADJ_0:RW:16:8:=0x00 PHY_CAL_PD_FINE_ADJ_0:RW:8:8:=0x00 PHY_CAL_PU_FINE_ADJ_0:RW:0:8:=0x00 + 0x00000000, // 1340: SC_PHY_PAD_DBG_CONT_0:WR:0:1:=0x00 + 0x00000000, // 1341: PHY_CAL_RESULT3_OBS_0:RD:0:32:=0x00000000 + 0x04102006, // 1342: PHY_CAL_SLOPE_ADJ_0:RW_D:8:20:=0x041020 PHY_ADRCTL_PVT_MAP_0:RW:0:7:=0x35 + 0x00041020, // 1343: PHY_CAL_SLOPE_ADJ_PASS2_0:RW_D:0:20:=0x041020 + 0x01C98C98, // 1344: PHY_CAL_TWO_PASS_CFG_0:RW_D:0:25:=0x01c98c98 + 0x3F400000, // 1345: PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0:RW_D:24:6:=0x3f PHY_CAL_SW_CAL_CFG_0:RW:0:23:=0x400000 + 0x3F3F1F3F, // 1346: PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0:RW_D:24:6:=0x3f PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0:RW_D:16:6:=0x3f PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0:RW_D:8:5:=0x1f PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0:RW_D:0:6:=0x3f + 0x0000001F, // 1347: PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0:RW:24:5:=0x1f PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0:RW:16:6:=0x3f PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0:RW:8:6:=0x3f PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0:RW_D:0:5:=0x1f + 0x00000000, // 1348: PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0:RW:16:5:=0x1f PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0:RW:8:6:=0x3f PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0:RW:0:6:=0x3f + 0x00000000, // 1349: PHY_PARITY_ERROR_REGIF_AC:RW:16:11:=0x0000 PHY_PAD_ATB_CTRL:RW:0:16:=0x0000 + 0x00000000, // 1350: PHY_AC_LPBK_ENABLE:RW:24:2:=0x00 PHY_AC_LPBK_OBS_SELECT:RW:16:1:=0x00 PHY_AC_LPBK_ERR_CLEAR:WR:8:1:=0x00 PHY_ADRCTL_MANUAL_UPDATE:WR:0:1:=0x00 + 0x00010000, // 1351: PHY_AC_PRBS_PATTERN_MASK:RW:24:4:=0x00 PHY_AC_PRBS_PATTERN_START:RW_D:16:7:=0x01 PHY_AC_LPBK_CONTROL:RW:0:9:=0x0000 + 0x00000000, // 1352: PHY_AC_LPBK_RESULT_OBS:RD:0:32:=0x00000000 + 0x00000000, // 1353: PHY_AC_CLK_LPBK_CONTROL:RW:16:6:=0x00 PHY_AC_CLK_LPBK_ENABLE:RW:8:1:=0x00 PHY_AC_CLK_LPBK_OBS_SELECT:RW:0:1:=0x00 + 0x00000000, // 1354: PHY_TOP_PWR_RDC_DISABLE:RW_D:24:1:=0x00 PHY_AC_PWR_RDC_DISABLE:RW:16:1:=0x00 PHY_AC_CLK_LPBK_RESULT_OBS:RD:0:16:=0x0000 + 0x00000001, // 1355: PHY_AC_SLV_DLY_CTRL_GATE_DISABLE:RW_D:0:1:=0x00 + 0x76543210, // 1356: PHY_DATA_BYTE_ORDER_SEL:RW:0:32:=0x76543210 + 0x00010198, // 1357: PHY_ADRCTL_MSTR_DLY_ENC_SEL_0:RW:24:2:=0x00 PHY_CALVL_DEVICE_MAP:RW:16:5:=0x01 PHY_LPDDR4_CONNECT:RW:8:1:=0x01 PHY_DATA_BYTE_ORDER_SEL_HIGH:RW:0:8:=0x98 + 0x00000000, // 1358: PHY_ADRCTL_MSTR_DLY_ENC_SEL_1:RW:0:2:=0x00 + 0x00000000, // 1359: PHY_DDL_AC_ENABLE:RW:0:32:=0x00000000 + 0x00000000, // 1360: PHY_DDL_AC_MODE:RW:0:26:=0x00000000 + 0x00040700, // 1361: PHY_ERR_MASK_EN:RW:24:3:=0x00 PHY_DDL_TRACK_UPD_THRESHOLD_AC:RW:16:8:=0x04 PHY_INIT_UPDATE_CONFIG:RW:8:3:=0x07 PHY_DDL_AC_MASK:RW:0:6:=0x00 + 0x00000000, // 1362: PHY_ERR_STATUS:RW+:0:3:=0x00 + 0x00000000, // 1363: PHY_DS0_DQS_ERR_COUNTER:RD:0:32:=0x00000000 + 0x00000000, // 1364: PHY_DS1_DQS_ERR_COUNTER:RD:0:32:=0x00000000 + 0x00000000, // 1365: PHY_DS2_DQS_ERR_COUNTER:RD:0:32:=0x00000000 + 0x00000000, // 1366: PHY_DS3_DQS_ERR_COUNTER:RD:0:32:=0x00000000 + 0x00000002, // 1367: PHY_DS_INIT_COMPLETE_OBS:RD:24:4:=0x00 PHY_AC_INIT_COMPLETE_OBS:RD:8:10:=0x0000 PHY_DLL_RST_EN:RW_D:0:2:=0x02 + 0x00000000, // 1368: PHY_GRP_SHIFT_OBS_SELECT:RW:24:3:=0x00 PHY_GRP_SLV_DLY_ENC_OBS_SELECT:RW:16:4:=0x00 PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE:RW_D:8:1:=0x00 PHY_UPDATE_MASK:RW:0:1:=0x00 + 0x00000000, // 1369: PHY_GRP_SHIFT_OBS:RD:16:3:=0x00 PHY_GRP_SLV_DLY_ENC_OBS:RD:0:11:=0x0000 + 0x00000000, // 1370: PHY_PLL_LOCK_DEASSERT_MASK:RW:24:3:=0x00 PHY_PARITY_ERROR_REGIF_PS:RW:8:11:=0x0000 PHY_PARITY_ERROR_INJECTION_ENABLE:RW:0:1:=0x00 + 0x00000000, // 1371: SC_PHY_PARITY_ERROR_INFO_WOCLR:WR:16:7:=0x00 PHY_PARITY_ERROR_INFO_MASK:RW:8:7:=0x00 PHY_PARITY_ERROR_INFO:RD:0:7:=0x00 + 0x00000000, // 1372: PHY_TIMEOUT_ERROR_INFO_MASK:RW:16:14:=0x0000 PHY_TIMEOUT_ERROR_INFO:RD:0:14:=0x0000 + 0x00000000, // 1373: PHY_PLL_FREQUENCY_ERROR_MASK:RW:24:6:=0x00 PHY_PLL_FREQUENCY_ERROR:RD:16:4:=0x00 SC_PHY_TIMEOUT_ERROR_INFO_WOCLR:WR:0:14:=0x0000 + 0x00080000, // 1374: PHY_PLL_DSKEWCALOUT_MIN:RW:8:12:=0x0800 SC_PHY_PLL_FREQUENCY_ERROR_WOCLR:WR:0:6:=0x00 + 0x000007FF, // 1375: PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK:RW:24:2:=0x00 PHY_PLL_DSKEWCALOUT_ERROR_INFO:RD:16:2:=0x00 PHY_PLL_DSKEWCALOUT_MAX:RW:0:12:=0x07ff + 0x00000000, // 1376: PHY_TOP_FSM_ERROR_INFO:RD:8:9:=0x0000 SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR:WR:0:2:=0x00 + 0x00000000, // 1377: SC_PHY_TOP_FSM_ERROR_INFO_WOCLR:WR:16:9:=0x0000 PHY_TOP_FSM_ERROR_INFO_MASK:RW:0:9:=0x0000 + 0x00000000, // 1378: PHY_FSM_TRANSIENT_ERROR_INFO_MASK:RW:16:10:=0x0000 PHY_FSM_TRANSIENT_ERROR_INFO:RD:0:10:=0x0000 + 0x00000000, // 1379: PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK:RW:24:2:=0x00 PHY_TOP_TRAIN_CALIB_ERROR_INFO:RD:16:2:=0x00 SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR:WR:0:10:=0x0000 + 0x00000000, // 1380: SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR:WR:24:7:=0x00 PHY_TRAIN_CALIB_ERROR_INFO_MASK:RW:16:7:=0x00 PHY_TRAIN_CALIB_ERROR_INFO:RD:8:7:=0x00 SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR:WR:0:2:=0x00 + 0x00000000, // 1381: PHY_GLOBAL_ERROR_INFO_MASK:RW:8:6:=0x00 PHY_GLOBAL_ERROR_INFO:RD:0:6:=0x00 + 0x000FFFFF, // 1382: PHY_TRAINING_TIMEOUT_VALUE:RW:0:20:=0x0fffff + 0x000FFFFF, // 1383: PHY_INIT_TIMEOUT_VALUE:RW:0:20:=0x0fffff + 0x0000FFFF, // 1384: PHY_LP_TIMEOUT_VALUE:RW:0:16:=0xffff + 0xFFFFFFF0, // 1385: PHY_PHYUPD_TIMEOUT_VALUE:RW:0:32:=0xFFFFFFF0 + 0x030FFFFF, // 1386: PHY_PLL_LOCK_0_MIN_VALUE:RW:24:5:=0x03 PHY_PHYMSTR_TIMEOUT_VALUE:RW:0:20:=0x0fffff + 0x01FFFFFF, // 1387: PHY_PLL_FREQUENCY_DELTA:RW:24:4:=0x01 PHY_RDDATA_VALID_TIMEOUT_VALUE:RW:16:8:=0xff PHY_PLL_LOCK_TIMEOUT_VALUE:RW:0:16:=0xffff + 0x0000FFFF, // 1388: PHY_ADRCTL_FSM_ERROR_INFO_0:RD:16:14:=0x0000 PHY_PLL_FREQUENCY_COMPARE_INTERVAL:RW:0:16:=0xffff + 0x00000000, // 1389: SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0:WR:16:14:=0x0000 PHY_ADRCTL_FSM_ERROR_INFO_MASK_0:RW:0:14:=0x0000 + 0x00000000, // 1390: PHY_ADRCTL_FSM_ERROR_INFO_MASK_1:RW:16:14:=0x0000 PHY_ADRCTL_FSM_ERROR_INFO_1:RD:0:14:=0x0000 + 0x00000000, // 1391: PHY_MEMCLK_FSM_ERROR_INFO_0:RD:16:14:=0x0000 SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1:WR:0:14:=0x0000 + 0x00000000, // 1392: SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0:WR:16:14:=0x0000 PHY_MEMCLK_FSM_ERROR_INFO_MASK_0:RW:0:14:=0x0000 + 0x0001F7C6, // 1393: PHY_PAD_CAL_IO_CFG_0:RW+:0:18:=0x000000 + 0x00000006, // 1394: PHY_PAD_ACS_IO_CFG:RW+:0:14:=0x0000 + 0x00000000, // 1395: PHY_PLL_BYPASS:RW+:0:1:=0x00 + 0x00001142, // 1396: PHY_LOW_FREQ_SEL:RW+:16:1:=0x00 PHY_PLL_CTRL:RW+:0:13:=0x1142 + 0x010207AE, // 1397: PHY_CSLVL_DLY_STEP:RW+:24:4:=0x01 PHY_CSLVL_CAPTURE_CNT:RW+:16:4:=0x02 PHY_PAD_VREF_CTRL_AC:RW:0:12:=0x0600 + 0x01000080, // 1398: PHY_LVL_MEAS_DLY_STEP_ENABLE:RW+:24:1:=0x01 PHY_SW_CSLVL_DVW_MIN_EN:RW+:16:1:=0x00 PHY_SW_CSLVL_DVW_MIN:RW+:0:9:=0x0080 + 0x03000300, // 1399: PHY_GRP1_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_GRP0_SLAVE_DELAY_0:RW+:0:11:=0x0300 + 0x03000300, // 1400: PHY_GRP3_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_GRP2_SLAVE_DELAY_0:RW+:0:11:=0x0300 + 0x00000300, // 1401: PHY_GRP0_SLAVE_DELAY_1:RW+:0:11:=0x0300 + 0x00000300, // 1402: PHY_GRP1_SLAVE_DELAY_1:RW+:0:11:=0x0300 + 0x00000300, // 1403: PHY_GRP2_SLAVE_DELAY_1:RW+:0:11:=0x0300 + 0x00000300, // 1404: PHY_GRP3_SLAVE_DELAY_1:RW+:0:11:=0x0300 + 0x00000005, // 1405: PHY_CLK_DC_CAL_CLK_SEL:RW+:0:3:=0x02 + 0x3183BFCC, // 1406: PHY_PAD_FDBK_DRIVE:RW+:0:30:=0x00030044 + 0x0003000B, // 1407: PHY_PAD_FDBK_DRIVE2:RW+:0:18:=0x030008 + 0x0C000DFF, // 1408: PHY_PAD_DATA_DRIVE:RW+:0:31:=0x00000180 + 0x30000DFF, // 1409: PHY_PAD_DQS_DRIVE:RW+:0:32:=0x00000180 + 0x300DFF11, // 1410: PHY_PAD_ADDR_DRIVE:RW+:0:30:=0x00018011 + 0x01990000, // 1411: PHY_PAD_ADDR_DRIVE2:RW+:0:27:=0x0089ff00 + 0x000DFFCC, // 1412: PHY_PAD_CLK_DRIVE:RW+:0:32:=0x00018044 + 0x00004C11, // 1413: PHY_PAD_CLK_DRIVE2:RW+:0:18:=0x004011 + 0x300DFF11, // 1414: PHY_PAD_CKE_DRIVE:RW+:0:30:=0x00018011 + 0x01990000, // 1415: PHY_PAD_CKE_DRIVE2:RW+:0:27:=0x0089ff00 + 0x300DFF11, // 1416: PHY_PAD_RST_DRIVE:RW+:0:30:=0x00018011 + 0x01990000, // 1417: PHY_PAD_RST_DRIVE2:RW+:0:27:=0x0089ff00 + 0x300DFF11, // 1418: PHY_PAD_CS_DRIVE:RW+:0:30:=0x00018011 + 0x01990000, // 1419: PHY_PAD_CS_DRIVE2:RW+:0:27:=0x0089ff00 + 0x00018011, // 1420: PHY_PAD_ODT_DRIVE:RW+:0:30:=0x00018011 + 0x0199FF00, // 1421: PHY_PAD_ODT_DRIVE2:RW+:0:27:=0x0089ff00 + 0x20040006 // 1422: PHY_CAL_SETTLING_PRD_0:RW+:24:7:=0x20 PHY_CAL_VREF_SWITCH_TIMER_0:RW+:8:16:=0x0400 PHY_CAL_CLK_SELECT_0:RW+:0:3:=0x01 +}; + +#endif /* _DDR_CONFIGURATION_H_ */ + diff --git a/meta-hailo-bsp/recipes-bsp/hailo-ddr-configuration-native/hailo-ddr-configuration-native.bb b/meta-hailo-bsp/recipes-bsp/hailo-ddr-configuration-native/hailo-ddr-configuration-native.bb new file mode 100644 index 0000000..aedb1e9 --- /dev/null +++ b/meta-hailo-bsp/recipes-bsp/hailo-ddr-configuration-native/hailo-ddr-configuration-native.bb @@ -0,0 +1,73 @@ +DESCRIPTION = "Generate DDR regconfig for Hailo SoC" +LICENSE = "MIT" +LIC_FILES_CHKSUM = "file://LICENSE;md5=8349eaff29531f0a3c4f4c8b31185958" + +DEPENDS = "openssl-native" + +inherit deploy native + +# set this variable to your board's regconfig file (generated by hailo tools) +# this file is added to the SRC_URI, so it has to be located in the FILESPATH or FILESEXTRAPATHS +HAILO_DDR_REGCONFIG_FILE ?= "hailo15_evb_MT53E1G32D2FW-046.h" + +# ECC mode. +# Possible values: +# "disabled" +# "enabled": ECC enabled, detection disabled, correction disabled +# "detection": ECC enabled, detection enabled, correction disabled +# "correction": ECC enabled, detection enabled, correction enabled +HAILO_DDR_ECC_MODE ?= "${@bb.utils.contains('MACHINE_FEATURES', 'ddr_ecc_en', 'correction', 'disabled', d)}" + +# BIST mode. +# controls enabling or disable the BIST procedure that run at every boot +# Possible values: +# "enabled" +# "disabled" +HAILO_DDR_BIST_ENABLE ?= "enabled" + +# Operational frequency. +# controls the operational frequency of the DDR after training. +# Possible values: +# "f0" (50Mhz, xtal mode) +# "f1" +# "f2" +HAILO_DDR_OPERATIONAL_FREQUENCY_INDEX ?= "f1" + +# F1, F2 frequency Hz. +# controls the frequency of the DDR in F1 and F2. +# Note: this value is half the transfer rate (MT/s) value because it is double data-rate. +# Possible values: +# 50000000, 100000000, 1598000000, 200000000, +# 400000000, 800000000, 1200000000, 1600000000, +# 2000000000, 2130000000, 2132000000, 2133000000 +HAILO_DDR_F1_FREQUENCY_HZ ?= "1600000000" +HAILO_DDR_F2_FREQUENCY_HZ ?= "2000000000" + + +HAILO_DDR_CONFIGURATION_FILENAME = "hailo_ddr_configuration.bin" + +SRC_URI = "file://build_ddr_configuration.c \ + file://${HAILO_DDR_REGCONFIG_FILE} \ + file://LICENSE" + +S = "${WORKDIR}" + +CFLAGS:append = " -Werror" +LDFLAGS:append = " -lssl -lcrypto" + +do_compile () { + ${CC} ${CFLAGS} build_ddr_configuration.c -DREGCONFIG_FILENAME=\"${HAILO_DDR_REGCONFIG_FILE}\" -o build_ddr_configuration ${LDFLAGS} + ./build_ddr_configuration \ + ${HAILO_DDR_ECC_MODE} \ + ${HAILO_DDR_BIST_ENABLE} \ + ${HAILO_DDR_OPERATIONAL_FREQUENCY_INDEX} \ + ${HAILO_DDR_F1_FREQUENCY_HZ} \ + ${HAILO_DDR_F2_FREQUENCY_HZ} \ + ${HAILO_DDR_CONFIGURATION_FILENAME} +} + +do_deploy () { + install -m 644 -D ${B}/${HAILO_DDR_CONFIGURATION_FILENAME} ${DEPLOYDIR}/${HAILO_DDR_CONFIGURATION_FILENAME} +} + +addtask deploy after do_compile diff --git a/meta-hailo-bsp/recipes-bsp/hailo-secureboot-assets/hailo-secureboot-assets.bb b/meta-hailo-bsp/recipes-bsp/hailo-secureboot-assets/hailo-secureboot-assets.bb new file mode 100644 index 0000000..910cdb9 --- /dev/null +++ b/meta-hailo-bsp/recipes-bsp/hailo-secureboot-assets/hailo-secureboot-assets.bb @@ -0,0 +1,25 @@ +DESCRIPTION = "Crypto assets for Hailo secure boot" +LICENSE = "Proprietary" +DEPENDS = "openssl-native" +LIC_FILES_CHKSUM = "file://../LICENSE;md5=263ee034adc02556d59ab1ebdaea2cda" +inherit deploy + +CUSTOMER_CERT = "development_customer_cert_chain.bin" +CUSTOMER_KEY = "development_customer_keypair.pem" + +BASE_URI = "https://hailo-hailort.s3.eu-west-2.amazonaws.com/Hailo15/SecureBoot" +SRC_URI = "${BASE_URI}/${CUSTOMER_CERT};name=cert \ + ${BASE_URI}/${CUSTOMER_KEY};name=key \ + ${BASE_URI}/LICENSE;name=lic" + +SRC_URI[cert.sha256sum] = "4e878fb261dbdb46e9f31a9c195b1171916fcaa79b09ec394fee302135d2ac70" +SRC_URI[key.sha256sum] = "1a3c0142934da9164ec599a5677104cd1a1df2ece1a3f4bb2448a9ccf08cd351" +SRC_URI[lic.sha256sum] = "ca96445e6e33ae0a82170ea847b0925c864492f0cbb6342d42c54fd647133608" + +do_deploy() { + install -m 644 -D ${WORKDIR}/${CUSTOMER_CERT} ${DEPLOYDIR}/customer_certificate.bin + install -m 644 -D ${WORKDIR}/${CUSTOMER_KEY} ${DEPLOYDIR}/customer.key + openssl req -batch -new -x509 -key ${DEPLOYDIR}/customer.key -out ${DEPLOYDIR}/customer.crt +} + +addtask deploy after do_compile diff --git a/meta-hailo-bsp/recipes-bsp/recovery-fw/recovery-fw.bb b/meta-hailo-bsp/recipes-bsp/recovery-fw/recovery-fw.bb new file mode 100644 index 0000000..10fd4b0 --- /dev/null +++ b/meta-hailo-bsp/recipes-bsp/recovery-fw/recovery-fw.bb @@ -0,0 +1,22 @@ +DESCRIPTION = "Hailo Recovery FW. \ + This recipe will download the Recovery firmware binary from AWS and add it to deploy" + +inherit deploy + +LICENSE = "Proprietary" +LIC_FILES_CHKSUM = "file://../LICENSE;md5=263ee034adc02556d59ab1ebdaea2cda" + +BASE_URI = "https://hailo-hailort.s3.eu-west-2.amazonaws.com/Hailo15/1.1.0/recovery-fw" +FW = "hailo15_uart_recovery_fw.bin" +LICENSE_FILE = "LICENSE" +SRC_URI = "${BASE_URI}/${FW};name=fw \ + ${BASE_URI}/${LICENSE_FILE};name=lic" + +SRC_URI[fw.sha256sum] = "f0a69fdf2a9b8da4dd1641de62828a94288613349925282298df740fbc35b142" +SRC_URI[lic.sha256sum] = "ca96445e6e33ae0a82170ea847b0925c864492f0cbb6342d42c54fd647133608" + +do_deploy() { + install -m 644 -D ${WORKDIR}/${FW} ${DEPLOYDIR}/${FW} +} + +addtask deploy after do_compile diff --git a/meta-hailo-bsp/recipes-bsp/scu-fw/scu-fw.bb b/meta-hailo-bsp/recipes-bsp/scu-fw/scu-fw.bb new file mode 100644 index 0000000..acf9b59 --- /dev/null +++ b/meta-hailo-bsp/recipes-bsp/scu-fw/scu-fw.bb @@ -0,0 +1,22 @@ +DESCRIPTION = "Hailo SCU. \ + This recipe will download the SCU firmware binary from AWS and add it to deploy" + +inherit deploy + +LICENSE = "Proprietary" +LIC_FILES_CHKSUM = "file://../LICENSE;md5=263ee034adc02556d59ab1ebdaea2cda" + +BASE_URI = "https://hailo-hailort.s3.eu-west-2.amazonaws.com/Hailo15/1.1.0/scu-fw" +FW = "hailo15_scu_fw.bin" +LICENSE_FILE = "LICENSE" +SRC_URI = "${BASE_URI}/${FW};name=fw \ + ${BASE_URI}/${LICENSE_FILE};name=lic" + +SRC_URI[fw.sha256sum] = "977efaad7b742647bccda8d0a62fa7c06cd072346a99460585f9b0b53102d408" +SRC_URI[lic.sha256sum] = "ca96445e6e33ae0a82170ea847b0925c864492f0cbb6342d42c54fd647133608" + +do_deploy() { + install -m 644 -D ${WORKDIR}/${FW} ${DEPLOYDIR}/${FW} +} + +addtask deploy after do_compile diff --git a/meta-hailo-bsp/recipes-bsp/sensors-config-file/files/COPYING.MIT b/meta-hailo-bsp/recipes-bsp/sensors-config-file/files/COPYING.MIT new file mode 100644 index 0000000..cd5290f --- /dev/null +++ b/meta-hailo-bsp/recipes-bsp/sensors-config-file/files/COPYING.MIT @@ -0,0 +1,19 @@ +Copyright (c) 2023 Hailo Technologies Ltd. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY kIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. \ No newline at end of file diff --git a/meta-hailo-bsp/recipes-bsp/sensors-config-file/files/hailo15-evb/ina231_precise-i2c-1.conf b/meta-hailo-bsp/recipes-bsp/sensors-config-file/files/hailo15-evb/ina231_precise-i2c-1.conf new file mode 100644 index 0000000..08ed72c --- /dev/null +++ b/meta-hailo-bsp/recipes-bsp/sensors-config-file/files/hailo15-evb/ina231_precise-i2c-1.conf @@ -0,0 +1,79 @@ +bus "i2c-1" "Synopsys DesignWare I2C adapter" + +chip "ina231_precise-i2c-1-41" + label in0 "MPP_AVDDH Shunt voltage" + label in1 "MPP_AVDDH Bus voltage" + label curr1 "MPP_AVDDH Current" + label power1 "MPP_AVDDH Power" + +chip "ina231_precise-i2c-1-42" + label in0 "DDR_PHY_1v1 Shunt voltage" + label in1 "DDR_PHY_1v1 Bus voltage" + label curr1 "DDR_PHY_1v1 Current" + label power1 "DDR_PHY_1v1 Power" + +chip "ina231_precise-i2c-1-43" + label in0 "ALL_PLL Shunt voltage" + label in1 "ALL_PLL Bus voltage" + label curr1 "ALL_PLL Current" + label power1 "ALL_PLL Power" + +chip "ina231_precise-i2c-1-44" + label in0 "MIPI_AVDDH Shunt voltage" + label in1 "MIPI_AVDDH Bus voltage" + label curr1 "MIPI_AVDDH Current" + label power1 "MIPI_AVDDH Power" + +chip "ina231_precise-i2c-1-45" + label in0 "USB_AVDDIO_HV Shunt voltage" + label in1 "USB_AVDDIO_HV Bus voltage" + label curr1 "USB_AVDDIO_HV Current" + label power1 "USB_AVDDIO_HV Power" + +chip "ina231_precise-i2c-1-46" + label in0 "DDR_1v8 Shunt voltage" + label in1 "DDR_1v8 Bus voltage" + label curr1 "DDR_1v8 Current" + label power1 "DDR_1v8 Power" + +chip "ina231_precise-i2c-1-47" + label in0 "DDR_PHY_0v8 Shunt voltage" + label in1 "DDR_PHY_0v8 Bus voltage" + label curr1 "DDR_PHY_0v8 Current" + label power1 "DDR_PHY_0v8 Power" + +chip "ina231_precise-i2c-1-49" + label in0 "5V_PERIPH Shunt voltage" + label in1 "5V_PERIPH Bus voltage" + label curr1 "5V_PERIPH Current" + label power1 "5V_PERIPH Power" + +chip "ina231_precise-i2c-1-4a" + label in0 "SOC_and_DRAM_5V_SRC Shunt voltage" + label in1 "SOC_and_DRAM_5V_SRC Bus voltage" + label curr1 "SOC_and_DRAM_5V_SRC Current" + label power1 "SOC_and_DRAM_5V_SRC Power" + +chip "ina231_precise-i2c-1-4c" + label in0 "DDR_PHY_0v6 Shunt voltage" + label in1 "DDR_PHY_0v6 Bus voltage" + label curr1 "DDR_PHY_0v6 Current" + label power1 "DDR_PHY_0v6 Power" + +chip "ina231_precise-i2c-1-4d" + label in0 "IO_1v8 Shunt voltage" + label in1 "IO_1v8 Bus voltage" + label curr1 "IO_1v8 Current" + label power1 "IO_1v8 Power" + +chip "ina231_precise-i2c-1-4e" + label in0 "VDD Shunt voltage" + label in1 "VDD Bus voltage" + label curr1 "VDD Current" + label power1 "VDD Power" + +chip "ina231_precise-i2c-1-4f" + label in0 "MIPI_MPP_USB_AVDD Shunt voltage" + label in1 "MIPI_MPP_USB_AVDD Bus voltage" + label curr1 "MIPI_MPP_USB_AVDD Current" + label power1 "MIPI_MPP_USB_AVDD Power" \ No newline at end of file diff --git a/meta-hailo-bsp/recipes-bsp/sensors-config-file/files/hailo15-evb/tmp175-i2c-1.conf b/meta-hailo-bsp/recipes-bsp/sensors-config-file/files/hailo15-evb/tmp175-i2c-1.conf new file mode 100644 index 0000000..09f006e --- /dev/null +++ b/meta-hailo-bsp/recipes-bsp/sensors-config-file/files/hailo15-evb/tmp175-i2c-1.conf @@ -0,0 +1,13 @@ +bus "i2c-1" "Synopsys DesignWare I2C adapter" + +chip "tmp175-i2c-1-2d" + label temp1 "NEAR_TOP_POWER temperature" + +chip "tmp175-i2c-1-2f" + label temp1 "NEAR_DDR temperature" + +chip "tmp175-i2c-1-2e" + label temp1 "NEAR_H15_SOC_0 temperature" + +chip "tmp175-i2c-1-2c" + label temp1 "NEAR_H15_SOC_1 temperature" diff --git a/meta-hailo-bsp/recipes-bsp/sensors-config-file/files/hailo15-sbc/ina231_precise-i2c-1.conf b/meta-hailo-bsp/recipes-bsp/sensors-config-file/files/hailo15-sbc/ina231_precise-i2c-1.conf new file mode 100644 index 0000000..e454777 --- /dev/null +++ b/meta-hailo-bsp/recipes-bsp/sensors-config-file/files/hailo15-sbc/ina231_precise-i2c-1.conf @@ -0,0 +1,19 @@ +bus "i2c-1" "Synopsys DesignWare I2C adapter" + +chip "ina231_precise-i2c-1-40" + label in0 "1v8 Shunt voltage" + label in1 "1v8 Bus voltage" + label curr1 "1v8 Current" + label power1 "1v8 Power" + +chip "ina231_precise-i2c-1-42" + label in0 "DDR_VDDQX Shunt voltage" + label in1 "DDR_VDDQX Bus voltage" + label curr1 "DDR_VDDQX Current" + label power1 "DDR_VDDQX Power" + +chip "ina231_precise-i2c-1-43" + label in0 "0v8 Shunt voltage" + label in1 "0v8 Bus voltage" + label curr1 "0v8 Current" + label power1 "0v8 Power" \ No newline at end of file diff --git a/meta-hailo-bsp/recipes-bsp/sensors-config-file/files/hailo15-sbc/tmp175-i2c-1.conf b/meta-hailo-bsp/recipes-bsp/sensors-config-file/files/hailo15-sbc/tmp175-i2c-1.conf new file mode 100644 index 0000000..268fa60 --- /dev/null +++ b/meta-hailo-bsp/recipes-bsp/sensors-config-file/files/hailo15-sbc/tmp175-i2c-1.conf @@ -0,0 +1,4 @@ +bus "i2c-1" "Synopsys DesignWare I2C adapter" + +chip "tmp175-i2c-1-2c" + label temp1 "NEAR_H15_SOC temperature" diff --git a/meta-hailo-bsp/recipes-bsp/sensors-config-file/files/hailo15-scmi.conf b/meta-hailo-bsp/recipes-bsp/sensors-config-file/files/hailo15-scmi.conf new file mode 100644 index 0000000..53477ad --- /dev/null +++ b/meta-hailo-bsp/recipes-bsp/sensors-config-file/files/hailo15-scmi.conf @@ -0,0 +1,3 @@ +chip "scmi_sensors-virtual-0" + label temp1 "H15 temperature 1" + label temp2 "H15 temperature 2" diff --git a/meta-hailo-bsp/recipes-bsp/sensors-config-file/sensors-config-file.bb b/meta-hailo-bsp/recipes-bsp/sensors-config-file/sensors-config-file.bb new file mode 100644 index 0000000..4f175bb --- /dev/null +++ b/meta-hailo-bsp/recipes-bsp/sensors-config-file/sensors-config-file.bb @@ -0,0 +1,30 @@ +DESCRIPTION = "Add sensor config files into Linux image" +SECTION = "apps" +LICENSE = "MIT" +SRC_URI = "file://COPYING.MIT" +LIC_FILES_CHKSUM = "file://../COPYING.MIT;md5=aa7321c8e0df442b97243c2e1d64c9ee" +targetdir = "/etc/sensors.d" + +SENSOR_CONF_FILES:append:hailo15-sbc = " hailo15-sbc/ina231_precise-i2c-1.conf" +SENSOR_CONF_FILES:append:hailo15-sbc = " hailo15-sbc/tmp175-i2c-1.conf" +SENSOR_CONF_FILES:append:hailo15-evb = " hailo15-evb/ina231_precise-i2c-1.conf" +SENSOR_CONF_FILES:append:hailo15-evb = " hailo15-evb/tmp175-i2c-1.conf" +SENSOR_CONF_FILES:append = " hailo15-scmi.conf" + +python () { + import os + sensor_files = d.getVar('SENSOR_CONF_FILES') + if not sensor_files: + return + for sensor_file in sensor_files.split(): + d.appendVar('SRC_URI', ' file://' + sensor_file) + d.appendVar('FILES:' + d.getVar('PN'), ' ${targetdir}/' + os.path.basename(sensor_file)) +} + +do_install() { + install -m 0755 -d ${D}${targetdir} + + for f in ${SENSOR_CONF_FILES}; do + install -m 0644 ${WORKDIR}/${f} ${D}${targetdir} + done +} diff --git a/meta-hailo-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-hailo.bb b/meta-hailo-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-hailo.bb new file mode 100644 index 0000000..054dd30 --- /dev/null +++ b/meta-hailo-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-hailo.bb @@ -0,0 +1,12 @@ +require recipes-bsp/trusted-firmware-a/trusted-firmware-a.inc + +BRANCH = "1.1.0" +SRCREV = "a3f0bdc789ccddc95479423c4633a5e8f0d32b47" +SRC_URI := "git://git@github.com/hailo-ai/arm-trusted-firmware.git;protocol=https;branch=${BRANCH}" + +LIC_FILES_CHKSUM += "file://docs/license.rst;md5=b2c740efedc159745b9b31f88ff03dde" +LICENSE = "BSD-3-Clause" + +COMPATIBLE_MACHINE:hailo15 = ".*" +TFA_PLATFORM:hailo15 = "hailo15" +TFA_BUILD_TARGET = "bl31" diff --git a/meta-hailo-bsp/recipes-bsp/u-boot-tfa-image/files/COPYING.MIT b/meta-hailo-bsp/recipes-bsp/u-boot-tfa-image/files/COPYING.MIT new file mode 100644 index 0000000..cd5290f --- /dev/null +++ b/meta-hailo-bsp/recipes-bsp/u-boot-tfa-image/files/COPYING.MIT @@ -0,0 +1,19 @@ +Copyright (c) 2023 Hailo Technologies Ltd. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY kIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. \ No newline at end of file diff --git a/meta-hailo-bsp/recipes-bsp/u-boot-tfa-image/files/u-boot-tfa.its b/meta-hailo-bsp/recipes-bsp/u-boot-tfa-image/files/u-boot-tfa.its new file mode 100644 index 0000000..f22c6a8 --- /dev/null +++ b/meta-hailo-bsp/recipes-bsp/u-boot-tfa-image/files/u-boot-tfa.its @@ -0,0 +1,45 @@ +/dts-v1/; + +/ { + description = "U-Boot & Trusted firmware bundle"; + + images { + atf { + description = "ARM TrustedFirmware-A"; + data = /incbin/("bl31.bin"); + type = "firmware"; + os = "arm-trusted-firmware"; + arch = "arm64"; + compression = "none"; + load = <0x80000000>; + entry = <0x80000000>; + signature { + algo = "sha256,rsa3072"; + key-name-hint = "customer"; + }; + }; + uboot { + description = "U-Boot"; + data = /incbin/("u-boot.bin"); + type = "firmware"; + os = "u-boot"; + arch = "arm64"; + compression = "none"; + load = <0x83000000>; + entry = <0x83000000>; + signature { + algo = "sha256,rsa3072"; + key-name-hint = "customer"; + }; + }; + }; + configurations { + default = "config_1"; + + config_1 { + description = "H15-uboot-atf"; + firmware = "atf"; + loadables = "uboot"; + }; + }; +}; \ No newline at end of file diff --git a/meta-hailo-bsp/recipes-bsp/u-boot-tfa-image/u-boot-tfa-image.bb b/meta-hailo-bsp/recipes-bsp/u-boot-tfa-image/u-boot-tfa-image.bb new file mode 100644 index 0000000..6284e26 --- /dev/null +++ b/meta-hailo-bsp/recipes-bsp/u-boot-tfa-image/u-boot-tfa-image.bb @@ -0,0 +1,33 @@ +DESCRIPTION = "U-Boot & TrustedFirmware-A image" + +PACKAGE_ARCH = "${MACHINE_ARCH}" +LICENSE = "MIT" +LIC_FILES_CHKSUM = "file://../COPYING.MIT;md5=aa7321c8e0df442b97243c2e1d64c9ee" +inherit deploy hailo-cc312-sign +SRC_URI = "file://u-boot-tfa.its \ + file://COPYING.MIT" + +HAILO_CC312_SIGNED_BINARY = "${B}/u-boot-spl.bin" +HAILO_CC312_UNSIGNED_BINARY = "${B}/u-boot-spl-unsigned.bin" + +DEPENDS += " dtc-native u-boot-tools-native u-boot" +do_compile[depends] += " u-boot:do_deploy trusted-firmware-a-hailo:do_deploy hailo-secureboot-assets:do_deploy" + +do_compile() { + ln -sf ${DEPLOY_DIR_IMAGE}/u-boot.bin ${WORKDIR}/u-boot.bin + ln -sf ${DEPLOY_DIR_IMAGE}/bl31.bin ${WORKDIR}/bl31.bin + uboot-mkimage -f ${WORKDIR}/u-boot-tfa.its ${B}/u-boot-tfa.itb + cp ${STAGING_DATADIR}/u-boot-spl.dtb ${B}/u-boot-spl.dtb + # sign u-boot-tfa with customer key + uboot-mkimage -F -k ${SPL_SIGN_KEYDIR} -K ${B}/u-boot-spl.dtb -r ${B}/u-boot-tfa.itb + # concat u-boot-spl with dtb containing key + cat ${STAGING_DATADIR}/u-boot-spl-nodtb.bin ${B}/u-boot-spl.dtb > ${B}/u-boot-spl-unsigned.bin + # sign u-boot-spl-unsigned.bin, generate u-boot-spl.bin + do_hailo_cc312_sign +} + +do_deploy() { + install -m 0644 ${B}/u-boot-spl.bin ${B}/u-boot-tfa.itb ${DEPLOYDIR}/ +} + +addtask deploy after do_compile diff --git a/meta-hailo-bsp/recipes-bsp/u-boot/cfg/hailo15_ddr_ecc_disabled.cfg b/meta-hailo-bsp/recipes-bsp/u-boot/cfg/hailo15_ddr_ecc_disabled.cfg new file mode 100644 index 0000000..7553dc0 --- /dev/null +++ b/meta-hailo-bsp/recipes-bsp/u-boot/cfg/hailo15_ddr_ecc_disabled.cfg @@ -0,0 +1,2 @@ +CONFIG_HAILO15_DDR_ENABLE_ECC=n +CONFIG_NR_DRAM_BANKS=1 diff --git a/meta-hailo-bsp/recipes-bsp/u-boot/cfg/hailo15_ddr_ecc_enable.cfg b/meta-hailo-bsp/recipes-bsp/u-boot/cfg/hailo15_ddr_ecc_enable.cfg new file mode 100644 index 0000000..966c7dc --- /dev/null +++ b/meta-hailo-bsp/recipes-bsp/u-boot/cfg/hailo15_ddr_ecc_enable.cfg @@ -0,0 +1,2 @@ +CONFIG_HAILO15_DDR_ENABLE_ECC=y +CONFIG_NR_DRAM_BANKS=2 diff --git a/meta-hailo-bsp/recipes-bsp/u-boot/fw_env.config b/meta-hailo-bsp/recipes-bsp/u-boot/fw_env.config new file mode 100644 index 0000000..6c9f7b4 --- /dev/null +++ b/meta-hailo-bsp/recipes-bsp/u-boot/fw_env.config @@ -0,0 +1,2 @@ +# MTD device name Device offset Env. size Flash sector size Number of sectors +/dev/mtd2 0x0000 0x4000 0x4000 1 diff --git a/meta-hailo-bsp/recipes-bsp/u-boot/u-boot-hailo.inc b/meta-hailo-bsp/recipes-bsp/u-boot/u-boot-hailo.inc new file mode 100644 index 0000000..0fcac2d --- /dev/null +++ b/meta-hailo-bsp/recipes-bsp/u-boot/u-boot-hailo.inc @@ -0,0 +1,6 @@ +UBOOT_HAILO_URI ??= "git://git@github.com/hailo-ai/hailo-u-boot.git;protocol=https;branch=${BRANCH}" +UBOOT_HAILO_BRANCH ??= "1.1.0" +UBOOT_HAILO_SRCREV ??= "155ad431e3681be7fd9ac1a2a08d21a26f8a268f" +BRANCH = "${UBOOT_HAILO_BRANCH}" +SRCREV = "${UBOOT_HAILO_SRCREV}" +SRC_URI = "${UBOOT_HAILO_URI}" diff --git a/meta-hailo-bsp/recipes-bsp/u-boot/u-boot-tools_%.bbappend b/meta-hailo-bsp/recipes-bsp/u-boot/u-boot-tools_%.bbappend new file mode 100644 index 0000000..88fc661 --- /dev/null +++ b/meta-hailo-bsp/recipes-bsp/u-boot/u-boot-tools_%.bbappend @@ -0,0 +1 @@ +require u-boot-hailo.inc \ No newline at end of file diff --git a/meta-hailo-bsp/recipes-bsp/u-boot/u-boot_%.bbappend b/meta-hailo-bsp/recipes-bsp/u-boot/u-boot_%.bbappend new file mode 100644 index 0000000..22f8bf5 --- /dev/null +++ b/meta-hailo-bsp/recipes-bsp/u-boot/u-boot_%.bbappend @@ -0,0 +1,29 @@ +FILESEXTRAPATHS:prepend := "${THISDIR}/:" + +DEPENDS += "u-boot-mkenvimage-native" + +require u-boot-hailo.inc + +SPL_BINARY = "spl/u-boot-spl.bin" + +SRC_URI:append = " file://fw_env.config" +SRC_URI:append = "${@bb.utils.contains('MACHINE_FEATURES', 'ddr_ecc_en', ' file://cfg/hailo15_ddr_ecc_enable.cfg', '', d)}" + +UBOOT_ENV_SIZE = "0x4000" + +do_compile:append() { + uboot-mkenvimage -s ${UBOOT_ENV_SIZE} -o u-boot-initial-env.bin u-boot-initial-env +} + +do_install:append() { + install -Dm 0644 ${SPL_DIR}/${SPL_DTB_BINARY} ${D}${datadir}/${SPL_DTB_BINARY} + install -Dm 0644 ${SPL_DIR}/${SPL_NODTB_BINARY} ${D}${datadir}/${SPL_NODTB_BINARY} +} + +do_deploy:append() { + install -m 0644 ${B}/u-boot-initial-env.bin ${DEPLOYDIR}/u-boot-initial-env.bin + install -m 0644 ${B}/spl/u-boot-spl ${DEPLOYDIR}/u-boot-spl.elf + + # do not deploy SPL related binaries here, we do it in the u-boot-tfa-image recipe + rm -f ${DEPLOYDIR}/u-boot-spl* +} diff --git a/meta-hailo-bsp/recipes-kernel/linux/linux-yocto-hailo.bb b/meta-hailo-bsp/recipes-kernel/linux/linux-yocto-hailo.bb new file mode 100644 index 0000000..adc9e73 --- /dev/null +++ b/meta-hailo-bsp/recipes-kernel/linux/linux-yocto-hailo.bb @@ -0,0 +1,32 @@ +DESCRIPTION = "Linux kernel" +SECTION = "kernel" +LICENSE = "GPLv2" +LIC_FILES_CHKSUM = "file://COPYING;md5=6bc538ed5bd9a7fc9398086aedcd7e46" + +LINUX_VERSION = "5.15.32" +PV = "${LINUX_VERSION}" + +LINUX_YOCTO_HAILO_URI ??= "git@github.com/hailo-ai/linux-yocto-hailo.git" +LINUX_YOCTO_HAILO_BRANCH ??= "1.1.0" +LINUX_YOCTO_HAILO_SRCREV ??= "46b2521b4eb097b489d5f6056f8b02adbede2fa0" +LINUX_YOCTO_HAILO_BOARD_VENDOR ?= "hailo" + +KBRANCH = "${LINUX_YOCTO_HAILO_BRANCH}" +SRCREV = "${LINUX_YOCTO_HAILO_SRCREV}" + +SRC_URI = "git://${LINUX_YOCTO_HAILO_URI};protocol=https;branch=${KBRANCH} \ + file://defconfig \ + file://cfg/;destsuffix=cfg;type=kmeta" +SRC_URI:append = "${@bb.utils.contains('MACHINE_FEATURES', 'thermal_debug_en', ' file://cfg/thermal-configuration.cfg', '', d)}" +SRC_URI:append = "${@bb.utils.contains('MACHINE_FEATURES', 'kernel_debug_en', ' file://cfg/debug-configuration.cfg', '', d)}" + +SDIO0_POSTFIX = "${@bb.utils.contains('MACHINE_FEATURES', 'sdio0', '-sdio0', '', d)}" +KERNEL_DEVICETREE = "${LINUX_YOCTO_HAILO_BOARD_VENDOR}/${MACHINE}${SDIO0_POSTFIX}.dtb" + +KCONFIG_MODE="--alldefconfig" + +# customer certificate is deployed by the hailo-secureboot-assets +# and used for signing the fitimage +do_assemble_fitimage[depends] += "hailo-secureboot-assets:do_deploy" + +require recipes-kernel/linux/linux-yocto.inc diff --git a/meta-hailo-bsp/recipes-kernel/linux/linux-yocto-hailo/cfg/debug-configuration.cfg b/meta-hailo-bsp/recipes-kernel/linux/linux-yocto-hailo/cfg/debug-configuration.cfg new file mode 100644 index 0000000..7cd1a90 --- /dev/null +++ b/meta-hailo-bsp/recipes-kernel/linux/linux-yocto-hailo/cfg/debug-configuration.cfg @@ -0,0 +1,5 @@ +CONFIG_DEBUG_INFO_REDUCED=n +CONFIG_RANDOMIZE_BASE=n +CONFIG_PID_IN_CONTEXTIDR=y +CONFIG_FTRACE=y +CONFIG_BOOTTIME_TRACING=y diff --git a/meta-hailo-bsp/recipes-kernel/linux/linux-yocto-hailo/cfg/thermal-configuration.cfg b/meta-hailo-bsp/recipes-kernel/linux/linux-yocto-hailo/cfg/thermal-configuration.cfg new file mode 100644 index 0000000..a0a8924 --- /dev/null +++ b/meta-hailo-bsp/recipes-kernel/linux/linux-yocto-hailo/cfg/thermal-configuration.cfg @@ -0,0 +1 @@ +CONFIG_THERMAL_WRITABLE_TRIPS=y diff --git a/meta-hailo-bsp/recipes-kernel/linux/linux-yocto-hailo/defconfig b/meta-hailo-bsp/recipes-kernel/linux/linux-yocto-hailo/defconfig new file mode 100644 index 0000000..9564c71 --- /dev/null +++ b/meta-hailo-bsp/recipes-kernel/linux/linux-yocto-hailo/defconfig @@ -0,0 +1,575 @@ +CONFIG_WERROR=y +CONFIG_LOCALVERSION="-yocto-standard" +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_AUDIT=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_JIT=y +CONFIG_PREEMPT=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +# CONFIG_COMPAT_BRK is not set +CONFIG_PROFILING=y +CONFIG_ARCH_HAILO15=y +# CONFIG_ARM64_ERRATUM_832075 is not set +# CONFIG_ARM64_ERRATUM_1024718 is not set +# CONFIG_ARM64_ERRATUM_1418040 is not set +# CONFIG_ARM64_ERRATUM_1165522 is not set +# CONFIG_ARM64_ERRATUM_1319367 is not set +# CONFIG_ARM64_ERRATUM_1530923 is not set +# CONFIG_ARM64_ERRATUM_1286807 is not set +# CONFIG_ARM64_ERRATUM_1463225 is not set +# CONFIG_ARM64_ERRATUM_1542419 is not set +# CONFIG_ARM64_ERRATUM_1508412 is not set +# CONFIG_CAVIUM_ERRATUM_22375 is not set +# CONFIG_CAVIUM_ERRATUM_23154 is not set +# CONFIG_CAVIUM_ERRATUM_27456 is not set +# CONFIG_CAVIUM_ERRATUM_30115 is not set +# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set +# CONFIG_FUJITSU_ERRATUM_010001 is not set +# CONFIG_HISILICON_ERRATUM_161600802 is not set +# CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set +# CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set +# CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set +# CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set +# CONFIG_NVIDIA_CARMEL_CNP_ERRATUM is not set +# CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set +CONFIG_ARM64_VA_BITS_48=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y +CONFIG_KEXEC=y +CONFIG_KEXEC_FILE=y +CONFIG_CRASH_DUMP=y +CONFIG_FORCE_MAX_ZONEORDER=14 +# CONFIG_RODATA_FULL_DEFAULT_ENABLED is not set +CONFIG_COMPAT=y +CONFIG_RANDOMIZE_BASE=y +# CONFIG_EFI is not set +CONFIG_HIBERNATION=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +CONFIG_ENERGY_MODEL=y +CONFIG_CPU_IDLE=y +CONFIG_ARM_CPUIDLE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=m +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m +CONFIG_CPUFREQ_DT=y +CONFIG_ARM_SCMI_CPUFREQ=y +CONFIG_ARM64_CRYPTO=y +CONFIG_CRYPTO_SHA1_ARM64_CE=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_SHA512_ARM64_CE=m +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_CHACHA20_NEON=m +CONFIG_CRYPTO_AES_ARM64_BS=m +CONFIG_JUMP_LABEL=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_BLK_DEV_INTEGRITY=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_PAGE_REPORTING=y +CONFIG_KSM=y +CONFIG_MEMORY_FAILURE=y +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_CMA=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IPV6_SIT=m +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_NET_DSA=m +CONFIG_NET_DSA_TAG_OCELOT=m +CONFIG_NET_DSA_TAG_OCELOT_8021Q=m +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_CBS=m +CONFIG_NET_SCH_ETF=m +CONFIG_NET_SCH_TAPRIO=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_GACT=m +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_GATE=m +CONFIG_BT=m +CONFIG_BT_HIDP=m +# CONFIG_BT_LE is not set +CONFIG_BT_LEDS=y +# CONFIG_BT_DEBUGFS is not set +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_QCA=y +CONFIG_CFG80211=m +CONFIG_MAC80211=m +CONFIG_MAC80211_LEDS=y +CONFIG_RFKILL=m +CONFIG_RFKILL_INPUT=y +CONFIG_PCI=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCI_IOV=y +CONFIG_PCI_PASID=y +CONFIG_HOTPLUG_PCI=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCIE_CADENCE_PLAT_HOST=y +CONFIG_PCIE_CADENCE_PLAT_EP=y +CONFIG_PCI_ENDPOINT=y +CONFIG_PCI_ENDPOINT_CONFIGFS=y +CONFIG_PCI_EPF_TEST=m +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_FW_LOADER_USER_HELPER=y +CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y +CONFIG_ARM_SCMI_PROTOCOL=y +# CONFIG_ARM_SCMI_TRANSPORT_SMC is not set +# CONFIG_ARM_SMCCC_SOC_ID is not set +CONFIG_HAILO_SCU_LOG=y +CONFIG_MTD=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_RAM=y +CONFIG_MTD_ROM=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_DATAFLASH=y +CONFIG_MTD_SST25L=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_UBI=m +CONFIG_OF_OVERLAY=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=1 +CONFIG_VIRTIO_BLK=y +CONFIG_BLK_DEV_NVME=m +CONFIG_SRAM=y +CONFIG_PCI_ENDPOINT_TEST=m +CONFIG_EEPROM_AT24=m +CONFIG_EEPROM_AT25=m +CONFIG_UACCE=m +CONFIG_NETDEVICES=y +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_TUN=y +CONFIG_VETH=m +CONFIG_VIRTIO_NET=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_AGERE is not set +# CONFIG_NET_VENDOR_ALACRITECH is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AMD is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +CONFIG_MACB=y +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_GOOGLE is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MICROSOFT is not set +# CONFIG_NET_VENDOR_LITEX is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETERION is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_NET_VENDOR_PACKET_ENGINES is not set +# CONFIG_NET_VENDOR_PENSANDO is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_SOCIONEXT is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_NET_VENDOR_XILINX is not set +CONFIG_MARVELL_PHY=m +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y +CONFIG_MDIO_BUS_MUX_MMIOREG=y +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_LAN78XX=m +CONFIG_USB_USBNET=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_ATH10K=m +CONFIG_ATH10K_PCI=m +CONFIG_BRCMFMAC=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_PCIE=m +CONFIG_WL18XX=m +CONFIG_WLCORE_SDIO=m +CONFIG_INPUT_MATRIXKMAP=y +CONFIG_INPUT_EVDEV=y +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO_SERPORT is not set +CONFIG_LEGACY_PTY_COUNT=16 +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_VIRTIO_CONSOLE=y +# CONFIG_HW_RANDOM_CAVIUM is not set +# CONFIG_HW_RANDOM_ARM_SMCCC_TRNG is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_GPIO=m +CONFIG_I2C_SLAVE=y +CONFIG_SPI=y +CONFIG_SPI_BITBANG=m +CONFIG_SPI_CADENCE_QUADSPI=y +CONFIG_SPI_SPIDEV=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_HAILO15=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_CMSDK=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_POWER_RESET_HAILO15=y +CONFIG_SENSORS_ARM_SCMI=y +CONFIG_SENSORS_LM75=y +CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_INA2XX_PRECISE=y +CONFIG_SENSORS_INA3221=m +CONFIG_THERMAL=y +CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y +CONFIG_CPU_THERMAL=y +CONFIG_THERMAL_EMULATION=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_SYSFS=y +CONFIG_ARM_SP805_WATCHDOG=y +CONFIG_MFD_MAX77620=y +CONFIG_MFD_SYSCON=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_VCTRL=m +CONFIG_MEDIA_SUPPORT=m +CONFIG_MEDIA_SUPPORT_FILTER=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_DVB_NET is not set +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_SDR_PLATFORM_DRIVERS=y +CONFIG_DRM=m +CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m +CONFIG_DRM_PANEL_LVDS=m +CONFIG_DRM_PANEL_SIMPLE=m +CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m +CONFIG_DRM_PANEL_RAYDIUM_RM67191=m +CONFIG_DRM_PANEL_SITRONIX_ST7703=m +CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m +CONFIG_DRM_DISPLAY_CONNECTOR=m +CONFIG_DRM_LONTIUM_LT9611UXC=m +CONFIG_DRM_SIMPLE_BRIDGE=m +CONFIG_FB=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=m +CONFIG_BACKLIGHT_LP855X=m +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_DYNAMIC_MINORS=y +# CONFIG_SND_PCI is not set +# CONFIG_SND_SPI is not set +# CONFIG_SND_USB is not set +CONFIG_SND_SOC=y +CONFIG_SND_DESIGNWARE_I2S=y +CONFIG_SND_DESIGNWARE_PCM=y +CONFIG_SND_SOC_TLV320AIC3X_I2C=y +CONFIG_SND_SIMPLE_CARD=y +CONFIG_SND_AUDIO_GRAPH_CARD=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_EZKEY=y +CONFIG_HID_ITE=y +CONFIG_HID_KENSINGTON=y +CONFIG_HID_LOGITECH=y +CONFIG_HID_REDRAGON=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_MULTITOUCH=m +CONFIG_I2C_HID_OF=m +CONFIG_USB_ULPI_BUS=y +CONFIG_USB_CONN_GPIO=y +CONFIG_USB=y +CONFIG_USB_OTG=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI_RENESAS=m +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_ACM=m +CONFIG_USB_CDNS_SUPPORT=y +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_HSIC_USB3503=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_TYPEC=m +CONFIG_TYPEC_TCPM=m +CONFIG_TYPEC_TCPCI=m +CONFIG_TYPEC_FUSB302=m +CONFIG_TYPEC_TPS6598X=m +CONFIG_TYPEC_HD3SS3220=m +CONFIG_MMC=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_ARMMMCI=y +# CONFIG_MMC_STM32_SDMMC is not set +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SPI=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_SYSCON=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_EDAC=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1307=m +CONFIG_RTC_DRV_HYM8563=m +CONFIG_RTC_DRV_MAX77686=y +CONFIG_RTC_DRV_PCF85363=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_RX8581=m +CONFIG_RTC_DRV_RV3028=m +CONFIG_RTC_DRV_RV8803=m +CONFIG_RTC_DRV_DS3232=y +CONFIG_RTC_DRV_PCF2127=m +CONFIG_DMADEVICES=y +CONFIG_VFIO=y +CONFIG_VFIO_PCI=y +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +CONFIG_STAGING=y +CONFIG_STAGING_MEDIA=y +CONFIG_COMMON_CLK_SCMI=y +CONFIG_COMMON_CLK_PWM=y +CONFIG_HWSPINLOCK=y +CONFIG_MAILBOX=y +CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y +CONFIG_ARM_SMMU=y +CONFIG_ARM_SMMU_V3=y +CONFIG_REMOTEPROC=y +CONFIG_PM_DEVFREQ=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_DEVFREQ_GOV_USERSPACE=m +CONFIG_EXTCON_USB_GPIO=y +CONFIG_MEMORY=y +CONFIG_IIO=y +CONFIG_IIO_BUFFER=y +CONFIG_IIO_TRIGGERED_BUFFER=m +CONFIG_PWM=y +CONFIG_PWM_HAILO15=y +CONFIG_RESET_CONTROLLER=y +CONFIG_PHY_CADENCE_DPHY=m +CONFIG_NVMEM_RMEM=m +CONFIG_TEE=y +CONFIG_MUX_MMIO=y +CONFIG_INTERCONNECT=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_QUOTA=y +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_VFAT_FS=y +CONFIG_EXFAT_FS=m +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_HUGETLBFS=y +CONFIG_SQUASHFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_SECURITY=y +CONFIG_SECURITYFS=y +CONFIG_CRYPTO_DH=m +CONFIG_CRYPTO_ECDSA=m +CONFIG_CRYPTO_CURVE25519=m +CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_DEV_CCREE=m +CONFIG_INDIRECT_PIO=y +CONFIG_CRC_CCITT=m +CONFIG_CRC_T10DIF=y +CONFIG_CRC8=y +# CONFIG_XZ_DEC_X86 is not set +# CONFIG_XZ_DEC_POWERPC is not set +# CONFIG_XZ_DEC_IA64 is not set +# CONFIG_XZ_DEC_SPARC is not set +CONFIG_DMA_RESTRICTED_POOL=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=32 +CONFIG_IRQ_POLL=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_INFO_REDUCED=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_FTRACE is not set +CONFIG_MEMTEST=y diff --git a/meta-hailo-bsp/wic/sd.wks b/meta-hailo-bsp/wic/sd.wks new file mode 100644 index 0000000..905fb68 --- /dev/null +++ b/meta-hailo-bsp/wic/sd.wks @@ -0,0 +1,6 @@ +# short-description: Create SD card image for Hailo +# long-description: Creates a partitioned SD card image for Hailo. +# Boot files are located in the first vfat partition. + +part /boot --source bootimg-partition --ondisk mmcblk0 --fstype=vfat --label boot --active --align 4 --size 16 --use-uuid +part / --source rootfs --ondisk mmcblk --fstype=ext4 --label root --align 4 --use-uuid diff --git a/meta-hailo-dsp/conf/layer.conf b/meta-hailo-dsp/conf/layer.conf new file mode 100644 index 0000000..6f1b1ee --- /dev/null +++ b/meta-hailo-dsp/conf/layer.conf @@ -0,0 +1,15 @@ +# We have a conf and classes directory, add to BBPATH +BBPATH .= ":${LAYERDIR}" + +# We have recipes-* directories, add to BBFILES +BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \ + ${LAYERDIR}/recipes-*/*/*.bbappend" + +BBFILE_COLLECTIONS += "meta-hailo-dsp" +BBFILE_PATTERN_meta-hailo-dsp = "^${LAYERDIR}/" +BBFILE_PRIORITY_meta-hailo-dsp = "6" + +LAYERDEPENDS_meta-hailo-dsp = "core meta-hailo-bsp" +LAYERSERIES_COMPAT_meta-hailo-dsp = "kirkstone" + +IMAGE_INSTALL:append = " libhailodsp-dev dsp-fw" diff --git a/meta-hailo-dsp/recipes-fw/dsp-fw/dsp-fw.bb b/meta-hailo-dsp/recipes-fw/dsp-fw/dsp-fw.bb new file mode 100644 index 0000000..9074c4d --- /dev/null +++ b/meta-hailo-dsp/recipes-fw/dsp-fw/dsp-fw.bb @@ -0,0 +1,28 @@ +DESCRIPTION = "Hailo DSP FW. \ + # This recipe downloads and installs the DSP firmware" +LICENSE = "LICENSE" +LIC_FILES_CHKSUM = "file://LICENSE;md5=263ee034adc02556d59ab1ebdaea2cda" +S3_URI = "https://hailo-hailort.s3.eu-west-2.amazonaws.com/Hailo15/1.1.0/dsp-fw" +FW = "dsp-fw.elf" + +SRC_URI = "${S3_URI}/${FW};name=fw \ + ${S3_URI}/LICENSE;name=lic" + +SRC_URI[fw.sha256sum] = "1c57d4b810536353a507fea772f86766cebc2de1d5d66bd9cd78c3363a8300be" +SRC_URI[lic.sha256sum] = "ca96445e6e33ae0a82170ea847b0925c864492f0cbb6342d42c54fd647133608" + +# elf is compiled for 32bit (DSP), while target (A53) is Aarch64 +INSANE_SKIP:${PN} += " arch" + +FW_PATH = "${S}/${FW}" +FIRMWARE_INSTALL_DIR = "/lib/firmware" +ROOTFS_FIRMWARE_DIR = "${D}${FIRMWARE_INSTALL_DIR}" + +S = "${WORKDIR}" +do_install() { + install -d ${ROOTFS_FIRMWARE_DIR} + install -m 0644 ${FW_PATH} ${ROOTFS_FIRMWARE_DIR} +} + +FILES:${PN} += "${FIRMWARE_INSTALL_DIR}/${FW}" + diff --git a/meta-hailo-dsp/recipes-kernel/linux-yocto-hailo/cfg/enable-xrp-release.cfg b/meta-hailo-dsp/recipes-kernel/linux-yocto-hailo/cfg/enable-xrp-release.cfg new file mode 100644 index 0000000..1e80edc --- /dev/null +++ b/meta-hailo-dsp/recipes-kernel/linux-yocto-hailo/cfg/enable-xrp-release.cfg @@ -0,0 +1,2 @@ +CONFIG_HAILO_XRP=y +CONFIG_HAILO_XRP_DEBUG=n \ No newline at end of file diff --git a/meta-hailo-dsp/recipes-kernel/linux-yocto-hailo/cfg/enable-xrp.cfg b/meta-hailo-dsp/recipes-kernel/linux-yocto-hailo/cfg/enable-xrp.cfg new file mode 100644 index 0000000..428a4b6 --- /dev/null +++ b/meta-hailo-dsp/recipes-kernel/linux-yocto-hailo/cfg/enable-xrp.cfg @@ -0,0 +1,2 @@ +CONFIG_HAILO_XRP=y +CONFIG_HAILO_XRP_DEBUG=y \ No newline at end of file diff --git a/meta-hailo-dsp/recipes-kernel/linux-yocto-hailo/linux-yocto-hailo.bbappend b/meta-hailo-dsp/recipes-kernel/linux-yocto-hailo/linux-yocto-hailo.bbappend new file mode 100644 index 0000000..5f5bdf4 --- /dev/null +++ b/meta-hailo-dsp/recipes-kernel/linux-yocto-hailo/linux-yocto-hailo.bbappend @@ -0,0 +1,6 @@ +FILESEXTRAPATHS:prepend := "${THISDIR}:" + +DSP_COMPILATION_MODE ??= "release" +ENABLE_XRP_FILE = "${@bb.utils.contains('DSP_COMPILATION_MODE', 'release', 'enable-xrp-release.cfg', 'enable-xrp.cfg', d)}" + +SRC_URI:append = " file://cfg/${ENABLE_XRP_FILE}" diff --git a/meta-hailo-dsp/recipes-libhailodsp/libhailodsp/libhailodsp_0.1.bb b/meta-hailo-dsp/recipes-libhailodsp/libhailodsp/libhailodsp_0.1.bb new file mode 100644 index 0000000..94b153f --- /dev/null +++ b/meta-hailo-dsp/recipes-libhailodsp/libhailodsp/libhailodsp_0.1.bb @@ -0,0 +1,20 @@ +DESCRIPTION = "libhailodsp - Hailo's API for DSP" +LICENSE = "MIT" +LIC_FILES_CHKSUM = "file://LICENSE;md5=2740b88bd0ffad7eda222e6f5cd097f4" + +BRANCH = "1.1.0" +SRCREV = "8462de82aac612e692bf33276e110af326fd9dff" + +SRC_URI = "git://git@github.com/hailo-ai/hailodsp.git;protocol=https;branch=${BRANCH}" +S = "${WORKDIR}/git" +OECMAKE_SOURCEPATH = "${S}/libhailodsp" + +DSP_COMPILATION_MODE ??= "release" +DEPENDS:prepend := "catch2 spdlog " +BUILD_TYPE = "${@bb.utils.contains('DSP_COMPILATION_MODE', 'release', 'Release', 'Debug', d)}" +EXTRA_OECMAKE:append = "-DCMAKE_BUILD_TYPE=${BUILD_TYPE}" +inherit cmake + +# Seperate tests executable to seperate package +PACKAGES:prepend = "${PN}-tests " +FILES:${PN}-tests += "${bindir}/dsp-test*" diff --git a/meta-hailo-imaging/COPYING.MIT b/meta-hailo-imaging/COPYING.MIT new file mode 100644 index 0000000..fb950dc --- /dev/null +++ b/meta-hailo-imaging/COPYING.MIT @@ -0,0 +1,17 @@ +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. diff --git a/meta-hailo-imaging/README b/meta-hailo-imaging/README new file mode 100644 index 0000000..3a26f8f --- /dev/null +++ b/meta-hailo-imaging/README @@ -0,0 +1,41 @@ +This README file contains information on the contents of the meta-hailo-imaging layer. + +Please see the corresponding sections below for details. + +Dependencies +============ + + URI: + branch: + + URI: + branch: + + . + . + . + +Patches +======= + +Please submit any patches against the meta-hailo-imaging layer to the xxxx mailing list (xxxx@zzzz.org) +and cc: the maintainer: + +Maintainer: XXX YYYYYY + +Table of Contents +================= + + I. Adding the meta-hailo-imaging layer to your build + II. Misc + + +I. Adding the meta-hailo-imaging layer to your build +================================================= + +Run 'bitbake-layers add-layer meta-hailo-imaging' + +II. Misc +======== + +--- replace with specific information about the meta-hailo-imaging layer --- diff --git a/meta-hailo-imaging/conf/layer.conf b/meta-hailo-imaging/conf/layer.conf new file mode 100644 index 0000000..0d05dd7 --- /dev/null +++ b/meta-hailo-imaging/conf/layer.conf @@ -0,0 +1,22 @@ +# We have a conf and classes directory, add to BBPATH +BBPATH .= ":${LAYERDIR}" + +# We have recipes-* directories, add to BBFILES +BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \ + ${LAYERDIR}/recipes-*/*/*.bbappend" + +BBFILE_COLLECTIONS += "meta-hailo-imaging" +BBFILE_PATTERN_meta-hailo-imaging = "^${LAYERDIR}/" +BBFILE_PRIORITY_meta-hailo-imaging = "6" + +LAYERDEPENDS_meta-hailo-imaging = "core" +LAYERSERIES_COMPAT_meta-hailo-imaging = "kirkstone" + +# For vc8000e encoder +CORE_IMAGE_EXTRA_INSTALL += "video-encoder video-encoder-kernel-modules" +KERNEL_MODULE_AUTOLOAD += "hx280enc" + +CORE_IMAGE_EXTRA_INSTALL += "imaging-sub-system" +MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "kernel-module-cdns-csi2rx kernel-module-hailo15-pixel-mux kernel-module-hailo15-rxwrapper kernel-module-hailo15-isp kernel-module-hailo15-video-cap" +MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "${@bb.utils.contains('MACHINE_FEATURES', 'imx334', 'kernel-module-imx334', '', d)}" +MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "${@bb.utils.contains('MACHINE_FEATURES', 'imx678', 'kernel-module-imx678', '', d)}" diff --git a/meta-hailo-imaging/conf/machine/mercury-ginger-imaging.conf b/meta-hailo-imaging/conf/machine/mercury-ginger-imaging.conf new file mode 100644 index 0000000..c4c3fed --- /dev/null +++ b/meta-hailo-imaging/conf/machine/mercury-ginger-imaging.conf @@ -0,0 +1,7 @@ +require conf/machine/hailo15-base.inc + +UBOOT_MACHINE = "hailo15_ginger_imaging_defconfig" + +CORE_IMAGE_EXTRA_INSTALL += "vision-subsystem imaging-sub-system imaging-sub-system-kernel-modules" + +MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "kernel-module-ov2775 kernel-module-cdns-csi2rx kernel-module-hailo15-pixel-mux kernel-module-imx334 kernel-module-hailo15-rxwrapper" diff --git a/meta-hailo-imaging/conf/machine/mercury-lavender-encoder.conf b/meta-hailo-imaging/conf/machine/mercury-lavender-encoder.conf new file mode 100644 index 0000000..4055268 --- /dev/null +++ b/meta-hailo-imaging/conf/machine/mercury-lavender-encoder.conf @@ -0,0 +1,5 @@ +require conf/machine/hailo15-base.inc + +UBOOT_MACHINE = "hailo15_lavender_encoder_defconfig" + +CORE_IMAGE_EXTRA_INSTALL += "imaging-sub-system imaging-sub-system-kernel-modules" diff --git a/meta-hailo-imaging/recipes-imaging/imaging-sub-system/imaging-sub-system.bb b/meta-hailo-imaging/recipes-imaging/imaging-sub-system/imaging-sub-system.bb new file mode 100644 index 0000000..4d37209 --- /dev/null +++ b/meta-hailo-imaging/recipes-imaging/imaging-sub-system/imaging-sub-system.bb @@ -0,0 +1,106 @@ +SUMMARY = "Verisilicon vivante SW package user space code build" +LICENSE = "MIT & Proprietary-VSI" +LIC_FILES_CHKSUM = "file://${B}/LICENSE;md5=805d1be5d56ae9500316a754de03ab5f \ + file://${S}/LICENSE;md5=8349eaff29531f0a3c4f4c8b31185958" +inherit externalsrc ccache qmake5_paths + +RDEPENDS:${PN} += " qtmultimedia" +DEPENDS += "qtbase-native ninja-native libdrm bash cmake-native qwt-qt5 qtbase qtdeclarative qtmultimedia qmllive boost" + +SRC_URI = "https://hailo-hailort.s3.eu-west-2.amazonaws.com/Hailo15/1.1.0/imaging-sub-system.tar.gz" +SRC_URI[sha256sum] = "8b74431c095b67a897d5f5762086b56476dff78f8ae96876159b45bf8da6ac70" + +B = "${WORKDIR}/imaging-sub-system/build" +S = "${WORKDIR}/imaging-sub-system/scripts" + +do_install() { + install -d ${D}/lib + install -d ${D}/etc + install -d ${D}/etc/init.d + install -d ${D}/etc/rc5.d + install -d ${D}${bindir} + cp -R --no-dereference --preserve=mode,links -v ${B}/dist/lib/* ${D}/lib + cp -R --no-dereference --preserve=mode,links -v ${B}/dist/release/lib/* ${D}/lib + + install -m 0755 -D ${B}/dist/bin/tuning-server ${D}${bindir} + install -m 0755 -D ${B}/dist/bin/tuning-lite ${D}${bindir} + install -m 0755 -D ${B}/dist/release/bin/isp_media_server ${D}${bindir} + + install -m 0755 -D ${S}/hailo_cfg/isp_media_server ${D}/etc/init.d + ln -s -r ${D}/etc/init.d/isp_media_server ${D}/etc/rc5.d/S20isp_media_server + + install -m 0755 -D ${B}/dist/bin/tuning-enable ${D}${bindir} + install -m 0755 -D ${B}/dist/bin/tuning-yuv-capture ${D}${bindir} + + install -m 0644 -D ${B}/dist/bin/sony_imx334.xml ${D}${bindir} + install -m 0644 -D ${B}/dist/bin/HAILO_IMX334*.xml ${D}${bindir} + install -m 0644 -D ${B}/dist/bin/sony_imx678.xml ${D}${bindir} + install -m 0644 -D ${B}/dist/bin/HAILO_IMX678*.xml ${D}${bindir} + install -m 0755 -D ${B}/dist/bin/*.so ${D}${bindir} + install -m 0755 -D ${B}/dist/release/bin/*.json ${D}${bindir} + install -m 0755 -D ${B}/dist/release/bin/*.cfg ${D}${bindir} + + install -m 0755 -D ${B}/dist/bin/raw_image_capture ${D}${bindir} + install -m 0755 -D ${B}/dist/bin/v4l_stream_example ${D}${bindir} + install -m 0755 -D ${B}/dist/bin/v4l_ctrl_example ${D}${bindir} + install -m 0755 -D ${B}/dist/bin/fps ${D}${bindir} + + install -m 0755 -D ${S}/mediacontrol/server/media_server_cfg.json ${D}${bindir} + + install -d ${D}${includedir}/imaging + install -d ${D}${includedir}/imaging/cam_device + install -d ${D}${includedir}/imaging/ebase + install -d ${D}${includedir}/imaging/scmi + install -d ${D}${includedir}/imaging/bufferpool + install -d ${D}${includedir}/imaging/json + install -d ${D}${includedir}/imaging/common + install -d ${D}${includedir}/imaging/hal + install -d ${D}${includedir}/imaging/oslayer + install -d ${D}${includedir}/imaging/fpga + install -d ${D}${includedir}/imaging/isi + install -d ${D}${includedir}/imaging/cameric_drv + + cp -R --no-dereference --preserve=mode,links -v ${B}/dist/include/* ${D}${includedir}/imaging + install -m 0755 -D ${S}/scripts/hailo_tuning_server.sh ${D}${bindir} + #install -m 0755 -D ${S}/scripts/* ${D}${TARGET_SBIN_DIR}/scripts + + cp ${S}/units/cam_device/include/cam_device_2dnr/* ${D}${includedir}/imaging + cp ${S}/units/cam_device/include/cam_device_3dnr/* ${D}${includedir}/imaging + cp ${S}/units/cam_device/include/cam_device_gc2/* ${D}${includedir}/imaging + cp ${S}/units/cam_device/include/cam_device_demosaic2/* ${D}${includedir}/imaging + cp ${S}/units/cam_device/include/cam_device_wdr4/* ${D}${includedir}/imaging + cp -R ${S}/units/common/include/* ${D}${includedir}/imaging + cp ${S}/units/isi/include/* ${D}${includedir}/imaging + cp ${S}/units/isi/include_priv/* ${D}${includedir}/imaging + cp ${S}/units/3av2/include/* ${D}${includedir}/imaging + cp -R ${S}/tuning-common/include/* ${D}${includedir}/imaging + cp -R ${S}/utils3rd/include/* ${D}${includedir}/imaging + cp -R ${S}/vvcam/v4l2/common/* ${D}${includedir}/imaging + cp ${S}/vvcam/common/vvsensor.h ${D}${includedir}/imaging + cp ${S}/vvcam/common/viv_video_kevent.h ${D}${includedir}/imaging + cp -R ${S}/units/cam_device/include/* ${D}${includedir}/imaging/cam_device + cp ${S}/units/ebase/include/* ${D}${includedir}/imaging/ebase + cp ${S}/units/scmi/include/* ${D}${includedir}/imaging/scmi + cp ${S}/units/bufferpool/include/* ${D}${includedir}/imaging/bufferpool + cp ${S}/utils3rd/3rd/jsoncpp/include/json/* ${D}${includedir}/imaging/json + cp ${S}/appshell/common/include/* ${D}${includedir}/imaging/common + cp ${S}/units/hal/include/* ${D}${includedir}/imaging/hal + cp ${S}/units/oslayer/include/* ${D}${includedir}/imaging/oslayer + cp ${S}/units/fpga/fpga/include/* ${D}${includedir}/imaging/fpga + cp ${S}/units/isi/include/* ${D}${includedir}/imaging/isi + cp ${S}/units/cameric_drv/include/cameric_drv_common.h ${D}${includedir}/imaging/cameric_drv + + ln -s -r ${D}/lib/libHAILO_IMX334.so ${D}${bindir}/HAILO_IMX334.drv + ln -s -r ${D}/lib/libHAILO_IMX678.so ${D}${bindir}/HAILO_IMX678.drv +} + +PACKAGES = "${PN} ${PN}-dev" +INSANE_SKIP:${PN}-dev = "file-rpaths dev-so debug-files rpaths staticdev installed-vs-shipped" +INSANE_SKIP:${PN} = "file-rpaths dev-so debug-files rpaths staticdev installed-vs-shipped" + +# FIXME: why? arch? +do_package_qa[noexec] = "1" +EXCLUDE_FROM_SHLIBS = "1" + +FILES:${PN} += "/lib/* /lib/*/*" +FILES:${PN} += "${bindir}/*" diff --git a/meta-hailo-imaging/recipes-imaging/video-encoder/video-encoder-kernel-modules.bb b/meta-hailo-imaging/recipes-imaging/video-encoder/video-encoder-kernel-modules.bb new file mode 100644 index 0000000..b2f6084 --- /dev/null +++ b/meta-hailo-imaging/recipes-imaging/video-encoder/video-encoder-kernel-modules.bb @@ -0,0 +1,29 @@ +SUMMARY = "Verisilicon vivante SW package Linux kernel modules" +LICENSE = "GPLv2" +LIC_FILES_CHKSUM = "file://${S}/software/linux_reference/kernel_module/LICENSE;md5=2b2755b2924328c8efe5adbf9eca4dd9" + +inherit module + +VIDEO_ENCODER_BRANCH = "1.1.0" + +SRCREV = "7074857caff5796c7dc2b4d62b86e67871414f99" +SRC_URI = "git://git@github.com/hailo-ai/hailo-vision.git;protocol=https;branch=${VIDEO_ENCODER_BRANCH}" + +# Source code +S = "${WORKDIR}/git/imaging-encoder" +# Build directory +B = "${WORKDIR}/build" + +EXTRA_OEMAKE = "KDIR=${STAGING_KERNEL_DIR}" + +do_compile() { + oe_runmake -C ${S}/software/linux_reference/kernel_module +} + +do_install() { + #create the directories + install -d ${D}${base_libdir}/modules/${KERNEL_VERSION}/kernel/drivers/imaging + #installing + install -m 555 ${S}/software/linux_reference/kernel_module/*.ko ${D}${base_libdir}/modules/${KERNEL_VERSION}/kernel/drivers/imaging/ +} + diff --git a/meta-hailo-imaging/recipes-imaging/video-encoder/video-encoder.bb b/meta-hailo-imaging/recipes-imaging/video-encoder/video-encoder.bb new file mode 100644 index 0000000..52fd7fa --- /dev/null +++ b/meta-hailo-imaging/recipes-imaging/video-encoder/video-encoder.bb @@ -0,0 +1,48 @@ +SUMMARY = "Verisilicon vivante SW package user space code build" + +LICENSE = "Proprietary-VSI" +LIC_FILES_CHKSUM = "file://${S}/software/LICENSE;md5=2c81b04b9390e9d08d51eea41d622b4e" + +INSANE_SKIP:${PN} += "already-stripped" + +SO_TARGET_NAME = "libhantro_vc8000e" +SW_INC_PATH = "software/inc" +SW_SRC_COMMON_PATH = "software/source/common" +SW_LINUX_TEST_HEVC = "software/linux_reference/test/hevc" +SW_LINUX_REFS = "software/linux_reference" +APP_FILE_NAME = "hevc_testenc" + +SRC_URI = "https://hailo-hailort.s3.eu-west-2.amazonaws.com/Hailo15/1.1.0/video-encoder.tar.gz" +SRC_URI[sha256sum] = "3705b8e45f0a4b462353df7799c6c6c96214ab5fdb35090dab34163ad883f7fa" + +S = "${WORKDIR}/video-encoder" + +SOURCE_DEPLOY_LIB = "${S}/${SW_LINUX_REFS}" +SOURCE_DEPLOY_INC = "${S}/${SW_INC_PATH}" +SOURCE_COMMON_DEPLOY_INC = "${S}/${SW_SRC_COMMON_PATH}" +SOURCE_DEPLOY_BIN = "${S}/${SW_LINUX_TEST_HEVC}" + +RDEPENDS:video-encoder += "bash" + +do_install () { + # create the directories + install -d ${D}${libdir} + install -d ${D}${includedir} + install -d ${D}${includedir}/video_encoder + install -d ${D}${bindir} + + # deploy artifacts + install -m 0755 -D ${SOURCE_DEPLOY_LIB}/${SO_TARGET_NAME}.so ${D}${libdir} + install -m 0755 -D ${SOURCE_DEPLOY_INC}/*.h ${D}${includedir}/video_encoder + install -m 0755 -D ${SOURCE_COMMON_DEPLOY_INC}/*.h ${D}${includedir}/video_encoder + install -m 0755 -D ${SOURCE_DEPLOY_BIN}/${APP_FILE_NAME} ${D}${bindir} +} + +FILES:${PN} = "${libdir}/*" +FILES:${PN} += "${includedir}/*" +FILES:${PN} += "${includedir}/video_encoder/*" +FILES:${PN} += "${bindir}/*" + +# For non versioned libraries - https://docs.yoctoproject.org/dev-manual/common-tasks.html#non-versioned-libraries +SOLIBS = ".so" +FILES_SOLIBSDEV = "" diff --git a/meta-hailo-imaging/recipes-kernel/linux-yocto-hailo/cfg/csi-configuration.cfg b/meta-hailo-imaging/recipes-kernel/linux-yocto-hailo/cfg/csi-configuration.cfg new file mode 100644 index 0000000..d0d5bdf --- /dev/null +++ b/meta-hailo-imaging/recipes-kernel/linux-yocto-hailo/cfg/csi-configuration.cfg @@ -0,0 +1,3 @@ +CONFIG_VIDEO_CADENCE=y +CONFIG_VIDEO_CADENCE_CSI2RX=m +CONFIG_VIDEO_CADENCE_CSI2TX=m \ No newline at end of file diff --git a/meta-hailo-imaging/recipes-kernel/linux-yocto-hailo/cfg/imx334-sensor-conf.cfg b/meta-hailo-imaging/recipes-kernel/linux-yocto-hailo/cfg/imx334-sensor-conf.cfg new file mode 100644 index 0000000..3acf1f1 --- /dev/null +++ b/meta-hailo-imaging/recipes-kernel/linux-yocto-hailo/cfg/imx334-sensor-conf.cfg @@ -0,0 +1 @@ +CONFIG_VIDEO_IMX334=m diff --git a/meta-hailo-imaging/recipes-kernel/linux-yocto-hailo/cfg/imx678-sensor-conf.cfg b/meta-hailo-imaging/recipes-kernel/linux-yocto-hailo/cfg/imx678-sensor-conf.cfg new file mode 100644 index 0000000..2d08051 --- /dev/null +++ b/meta-hailo-imaging/recipes-kernel/linux-yocto-hailo/cfg/imx678-sensor-conf.cfg @@ -0,0 +1 @@ +CONFIG_VIDEO_IMX678=m diff --git a/meta-hailo-imaging/recipes-kernel/linux-yocto-hailo/cfg/isp-conf.cfg b/meta-hailo-imaging/recipes-kernel/linux-yocto-hailo/cfg/isp-conf.cfg new file mode 100644 index 0000000..46fdcc5 --- /dev/null +++ b/meta-hailo-imaging/recipes-kernel/linux-yocto-hailo/cfg/isp-conf.cfg @@ -0,0 +1,2 @@ +CONFIG_VIDEO_HAILO15=y +CONFIG_VIDEO_HAILO15_ISP=m diff --git a/meta-hailo-imaging/recipes-kernel/linux-yocto-hailo/cfg/media-conf.cfg b/meta-hailo-imaging/recipes-kernel/linux-yocto-hailo/cfg/media-conf.cfg new file mode 100644 index 0000000..8644896 --- /dev/null +++ b/meta-hailo-imaging/recipes-kernel/linux-yocto-hailo/cfg/media-conf.cfg @@ -0,0 +1 @@ +CONFIG_MEDIA_SUPPORT=y diff --git a/meta-hailo-imaging/recipes-kernel/linux-yocto-hailo/cfg/pix-mux-conf.cfg b/meta-hailo-imaging/recipes-kernel/linux-yocto-hailo/cfg/pix-mux-conf.cfg new file mode 100644 index 0000000..4fac980 --- /dev/null +++ b/meta-hailo-imaging/recipes-kernel/linux-yocto-hailo/cfg/pix-mux-conf.cfg @@ -0,0 +1,2 @@ +CONFIG_VIDEO_HAILO15=y +CONFIG_VIDEO_HAILO15_PIX_MUX=m diff --git a/meta-hailo-imaging/recipes-kernel/linux-yocto-hailo/cfg/rxwrapper-conf.cfg b/meta-hailo-imaging/recipes-kernel/linux-yocto-hailo/cfg/rxwrapper-conf.cfg new file mode 100644 index 0000000..b1c1850 --- /dev/null +++ b/meta-hailo-imaging/recipes-kernel/linux-yocto-hailo/cfg/rxwrapper-conf.cfg @@ -0,0 +1,2 @@ +CONFIG_VIDEO_HAILO15=y +CONFIG_VIDEO_HAILO15_RXWRAPPER=m diff --git a/meta-hailo-imaging/recipes-kernel/linux-yocto-hailo/cfg/video-conf.cfg b/meta-hailo-imaging/recipes-kernel/linux-yocto-hailo/cfg/video-conf.cfg new file mode 100644 index 0000000..3461fc4 --- /dev/null +++ b/meta-hailo-imaging/recipes-kernel/linux-yocto-hailo/cfg/video-conf.cfg @@ -0,0 +1,2 @@ +CONFIG_VIDEO_HAILO15=y +CONFIG_VIDEO_HAILO15_VIDEO_CAPTURE=m diff --git a/meta-hailo-imaging/recipes-kernel/linux-yocto-hailo/linux-yocto-hailo.bbappend b/meta-hailo-imaging/recipes-kernel/linux-yocto-hailo/linux-yocto-hailo.bbappend new file mode 100644 index 0000000..85ae38d --- /dev/null +++ b/meta-hailo-imaging/recipes-kernel/linux-yocto-hailo/linux-yocto-hailo.bbappend @@ -0,0 +1,23 @@ +FILESEXTRAPATHS:prepend := "${THISDIR}:" + +SRC_URI:append = " file://cfg/media-conf.cfg" +SRC_URI:append = " file://cfg/csi-configuration.cfg" +SRC_URI:append = " file://cfg/pix-mux-conf.cfg" +SRC_URI:append = " file://cfg/rxwrapper-conf.cfg" +SRC_URI:append = " file://cfg/isp-conf.cfg" +SRC_URI:append = " file://cfg/video-conf.cfg" +SRC_URI:append = " ${@bb.utils.contains('MACHINE_FEATURES', 'imx334', 'file://cfg/imx334-sensor-conf.cfg', '', d)}" +SRC_URI:append = " ${@bb.utils.contains('MACHINE_FEATURES', 'imx678', 'file://cfg/imx678-sensor-conf.cfg', '', d)}" + +USE_SENSOR_IMX678 = "${@bb.utils.contains('MACHINE_FEATURES', 'imx678', '1', '', d)}" +SENSOR_H_PATH = "arch/arm64/boot/dts/hailo/hailo15-evb-security-camera-sensor.h" +do_compile:prepend() { + echo "USE_SENSOR_IMX678 is: ${USE_SENSOR_IMX678}" + if [ "${USE_SENSOR_IMX678}" -eq 1 ]; then + echo "using sensor imx678" + echo "#define SENSOR_IMX678" > "${S}/${SENSOR_H_PATH}" + else + echo "using sensor imx334" + echo "#define SENSOR_IMX334" > "${S}/${SENSOR_H_PATH}" + fi +} diff --git a/meta-hailo-linux/COPYING.MIT b/meta-hailo-linux/COPYING.MIT new file mode 100644 index 0000000..fb950dc --- /dev/null +++ b/meta-hailo-linux/COPYING.MIT @@ -0,0 +1,17 @@ +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. diff --git a/meta-hailo-linux/README b/meta-hailo-linux/README new file mode 100644 index 0000000..7a7ee7d --- /dev/null +++ b/meta-hailo-linux/README @@ -0,0 +1,32 @@ +This README file contains information on the contents of the meta-hailo-linux layer. + +Please see the corresponding sections below for details. + +Dependencies +============ + + Nothing + +Table of Contents +================= + + I. Adding the meta-hailo-linux layer to your build + II. Misc + + +I. Adding the meta-hailo-linux layer to your build +================================================= + +Run 'bitbake-layers add-layer meta-hailo-linux' + +II. Misc +======== + This layer defines Hailo’s distribution from the generic Linux OS perspective. + + Packages: + lrzsz phytool v4l-utils glibc-binary-localedata-en-us + fuse-exfat + openssl openssl-bin + ethtool tmux tcpdump ssmtp vsftpd + + Recipes: busybox, vsftpd diff --git a/meta-hailo-linux/conf/layer.conf b/meta-hailo-linux/conf/layer.conf new file mode 100644 index 0000000..4ba4cb9 --- /dev/null +++ b/meta-hailo-linux/conf/layer.conf @@ -0,0 +1,50 @@ +# We have a conf and classes directory, add to BBPATH +BBPATH .= ":${LAYERDIR}" + +# We have recipes-* directories, add to BBFILES +BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \ + ${LAYERDIR}/recipes-*/*/*.bbappend" + +BBFILE_COLLECTIONS += "meta-hailo-linux" +BBFILE_PATTERN_meta-hailo-linux = "^${LAYERDIR}/" +BBFILE_PRIORITY_meta-hailo-linux = "6" + +LAYERDEPENDS_meta-hailo-linux = "core" +LAYERSERIES_COMPAT_meta-hailo-linux = "kirkstone" + + + + +CORE_IMAGE_EXTRA_INSTALL += " lrzsz phytool v4l-utils glibc-binary-localedata-en-us" +CORE_IMAGE_EXTRA_INSTALL += " fuse-exfat" +CORE_IMAGE_EXTRA_INSTALL += " exfat-utils" +CORE_IMAGE_EXTRA_INSTALL += " openssl openssl-bin" +CORE_IMAGE_EXTRA_INSTALL += " ethtool tmux tcpdump ssmtp vsftpd" +CORE_IMAGE_EXTRA_INSTALL += " libgpiod libgpiod-tools" +CORE_IMAGE_EXTRA_INSTALL += " kmod" +CORE_IMAGE_EXTRA_INSTALL += " lmsensors-libsensors lmsensors-sensors sensors-config-file" +CORE_IMAGE_EXTRA_INSTALL += " e2fsprogs dosfstools gptfdisk" +CORE_IMAGE_EXTRA_INSTALL += " util-linux" +CORE_IMAGE_EXTRA_INSTALL += " os-release" +CORE_IMAGE_EXTRA_INSTALL += " mmc-utils" +CORE_IMAGE_EXTRA_INSTALL += " edac-utils" +CORE_IMAGE_EXTRA_INSTALL += " mtd-utils" +CORE_IMAGE_EXTRA_INSTALL += " nfs-utils-client" +CORE_IMAGE_EXTRA_INSTALL += " tree" +CORE_IMAGE_EXTRA_INSTALL += " htop sysstat" +CORE_IMAGE_EXTRA_INSTALL += " alsa-tools alsa-plugins alsa-topology-conf alsa-utils alsa-lib alsa-utils-scripts alsa-state" +CORE_IMAGE_EXTRA_INSTALL += " openssh-sftp-server" + +PREFERRED_VERSION_gstreamer1.0 = "1.20.2" +PREFERRED_VERSION_gstreamer1.0-plugins-base = "1.20.2" +# Adding gstreamer to image only if env var ADD_GSTREAMER_TO_IMAGE is set to "true" +GSTREAMER_VERSIONS = " gstreamer1.0 gstreamer1.0-plugins-base gstreamer1.0-plugins-good gstreamer1.0-plugins-bad gstreamer1.0-rtsp-server" +CORE_IMAGE_EXTRA_INSTALL:append = "${@d.getVar('GSTREAMER_VERSIONS') if d.getVar('ADD_GSTREAMER_TO_IMAGE') == 'true' else ''}" + +# Adding python to image only if env var ADD_PYTHON_TO_IMAGE is set to "true" +CORE_IMAGE_EXTRA_INSTALL:append = "${@ ' python3' if d.getVar('ADD_PYTHON_TO_IMAGE') == 'true' else ''}" + +# Adding default user/password +INHERIT += "extrausers" +PASSWD = "\$5\$5bZLqb1IqC\$WqgDM7KNoNcQF4IUwvYWZG15NXQ6tTpvbBvyq.4BQZ3" +EXTRA_USERS_PARAMS = "usermod -p '${PASSWD}' root;" diff --git a/meta-hailo-linux/licenses/LICENSE b/meta-hailo-linux/licenses/LICENSE new file mode 100644 index 0000000..d351a21 --- /dev/null +++ b/meta-hailo-linux/licenses/LICENSE @@ -0,0 +1,13 @@ +Software License +---------------- + +Copyright 2020 (C) Hailo Technologies Ltd. +All rights reserved. + +Hailo Technologies Ltd. (“Hailo”) disclaims any warranties, including, but not limited to, +the implied warranties of merchantability and fitness for a particular purpose. +This software is provided on an "AS IS" basis, and Hailo has no obligation to provide maintenance, +support, updates, enhancements, or modifications. + +You may use this software in the development of any project. +You shall not reproduce, modify or distribute this software without prior written permission. diff --git a/meta-hailo-linux/recipes-core/hailo-base-config/files/bashrc b/meta-hailo-linux/recipes-core/hailo-base-config/files/bashrc new file mode 100644 index 0000000..8097a66 --- /dev/null +++ b/meta-hailo-linux/recipes-core/hailo-base-config/files/bashrc @@ -0,0 +1,27 @@ +# ~/.bashrc: executed by bash(1) for non-login shells. + +# Terminal color +# export PS1='${debian_chroot:+($debian_chroot)}\[\033[01;32m\]\u@\h\[\033[00m\]:\[\033[01;34m\]\w\[\033[00m\]\$ ' + +umask 022 + +# You may uncomment the following lines if you want `ls' to be colorized: +export LS_OPTIONS='--color=auto' +alias ls='ls $LS_OPTIONS' +alias ll='ls $LS_OPTIONS -l' +alias l='ls $LS_OPTIONS -lA' + +# Set locale +export LC_ALL=en_US.UTF-8 +export LANG=en_US.UTF-8 +export LANGUAGE=en_US.UTF-8 + +# Immediately persist commands across terminal sessions +export PROMPT_COMMAND='history -a' + +# Include timestamps +export HISTTIMEFORMAT="%F %T " + +# Modify the buffers size +export HISTSIZE=11000 +export HISTFILESIZE=11000 diff --git a/meta-hailo-linux/recipes-core/hailo-base-config/files/inputrc b/meta-hailo-linux/recipes-core/hailo-base-config/files/inputrc new file mode 100644 index 0000000..7288cb1 --- /dev/null +++ b/meta-hailo-linux/recipes-core/hailo-base-config/files/inputrc @@ -0,0 +1,6 @@ +"\e[1;5C": forward-word +"\e[1;5D": backward-word +"\e[5C": forward-word +"\e[5D": backward-word +"\e\e[C": forward-word +"\e\e[D": backward-word diff --git a/meta-hailo-linux/recipes-core/hailo-base-config/files/profile b/meta-hailo-linux/recipes-core/hailo-base-config/files/profile new file mode 100644 index 0000000..ff37183 --- /dev/null +++ b/meta-hailo-linux/recipes-core/hailo-base-config/files/profile @@ -0,0 +1,7 @@ +# ~/.profile: executed by Bourne-compatible login shells. + +if [ -f ~/.bashrc ]; then + . ~/.bashrc +fi + +mesg n diff --git a/meta-hailo-linux/recipes-core/hailo-base-config/hailo-base-config_0.1.bb b/meta-hailo-linux/recipes-core/hailo-base-config/hailo-base-config_0.1.bb new file mode 100644 index 0000000..c000bd7 --- /dev/null +++ b/meta-hailo-linux/recipes-core/hailo-base-config/hailo-base-config_0.1.bb @@ -0,0 +1,17 @@ +DESCRIPTION = "Basic bash configuration for hailo images" +LICENSE = "CLOSED" + +S = "${WORKDIR}" + +FILESEXTRAPATHS:prepend:hailo15 := "${THISDIR}/files/:" +SRC_URI:append:hailo15 = "file://inputrc;striplevel=3 file://bashrc;striplevel=3 file://profile;striplevel=3" + +do_install:append () { + install -d ${D}${ROOT_HOME} + install -m 0755 ${S}/bashrc ${D}${ROOT_HOME}/.bashrc + install -m 0755 ${S}/profile ${D}${ROOT_HOME}/.profile + install -m 0600 ${S}/inputrc ${D}${ROOT_HOME}/.inputrc +} + +FILES:${PN} += "/home/root /home/root/.bashrc /home/root/.profile /home/root/.inputrc" + diff --git a/meta-hailo-linux/recipes-core/images/core-image-minimal.bbappend b/meta-hailo-linux/recipes-core/images/core-image-minimal.bbappend new file mode 100644 index 0000000..6d52805 --- /dev/null +++ b/meta-hailo-linux/recipes-core/images/core-image-minimal.bbappend @@ -0,0 +1 @@ +EXTRA_IMAGE_FEATURES += "ssh-server-openssh allow-root-login" diff --git a/meta-hailo-linux/recipes-core/init-ifupdown/files/interfaces b/meta-hailo-linux/recipes-core/init-ifupdown/files/interfaces new file mode 100644 index 0000000..0bb4d3b --- /dev/null +++ b/meta-hailo-linux/recipes-core/init-ifupdown/files/interfaces @@ -0,0 +1,13 @@ +# /etc/network/interfaces -- configuration file for ifup(8), ifdown(8) + +# The loopback interface +auto lo +iface lo inet loopback + +# Wired or wireless interfaces +auto eth0 +iface eth0 inet static + address 10.0.0.1 + netmask 255.255.255.0 + +iface eth1 inet dhcp diff --git a/meta-hailo-linux/recipes-core/init-ifupdown/init-ifupdown_%.bbappend b/meta-hailo-linux/recipes-core/init-ifupdown/init-ifupdown_%.bbappend new file mode 100644 index 0000000..41f6400 --- /dev/null +++ b/meta-hailo-linux/recipes-core/init-ifupdown/init-ifupdown_%.bbappend @@ -0,0 +1,11 @@ + +FILESEXTRAPATHS:prepend := "${THISDIR}/files:" +SRC_URI += "file://interfaces" + +S = "${WORKDIR}" + +do_install:append() { + install -m 0644 ${WORKDIR}/interfaces ${D}${sysconfdir}/network/interfaces +} + +FILES:${PN} += " /etc /etc/network /etc/network/interfaces " diff --git a/meta-hailo-linux/recipes-core/os-release/os-release.bbappend b/meta-hailo-linux/recipes-core/os-release/os-release.bbappend new file mode 100644 index 0000000..8b53a08 --- /dev/null +++ b/meta-hailo-linux/recipes-core/os-release/os-release.bbappend @@ -0,0 +1,7 @@ +OS_RELEASE_FIELDS = "\ + NAME VERSION RELEASE_REV_METADATA \ +" + +NAME = "HAILO Hailo-15" +VERSION = "1.1.0" +RELEASE_REV_METADATA = "/etc/hailo-rev" diff --git a/meta-hailo-linux/recipes-daemons/vsftpd/vsftpd/0001-re-added-ssl-patch.patch b/meta-hailo-linux/recipes-daemons/vsftpd/vsftpd/0001-re-added-ssl-patch.patch new file mode 100644 index 0000000..579f2fa --- /dev/null +++ b/meta-hailo-linux/recipes-daemons/vsftpd/vsftpd/0001-re-added-ssl-patch.patch @@ -0,0 +1,22 @@ +From 5e68ee0b6e71a2b4e25918b0437ad3f1135cd4e0 Mon Sep 17 00:00:00 2001 +From: Hailo Tech +Date: Sun, 29 May 2022 16:57:42 +0300 +Subject: [PATCH] re-added ssl patch + +--- + builddefs.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/builddefs.h b/builddefs.h +index f48a568..a28cfe3 100644 +--- a/builddefs.h ++++ b/builddefs.h +@@ -3,7 +3,7 @@ + + #define VSF_BUILD_TCPWRAPPERS + #undef VSF_BUILD_PAM +-#undef VSF_BUILD_SSL ++#define VSF_BUILD_SSL + + #endif /* VSF_BUILDDEFS_H */ + diff --git a/meta-hailo-linux/recipes-daemons/vsftpd/vsftpd_%.bbappend b/meta-hailo-linux/recipes-daemons/vsftpd/vsftpd_%.bbappend new file mode 100644 index 0000000..59bd346 --- /dev/null +++ b/meta-hailo-linux/recipes-daemons/vsftpd/vsftpd_%.bbappend @@ -0,0 +1,5 @@ +FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:" + +SRC_URI += "file://0001-re-added-ssl-patch.patch" + +LDFLAGS:append = " -I/usr/include/openssl/ -lcrypto -lssl" diff --git a/meta-hailo-linux/recipes-hailo/busybox/busybox/enable-base64.cfg b/meta-hailo-linux/recipes-hailo/busybox/busybox/enable-base64.cfg new file mode 100644 index 0000000..0a372b8 --- /dev/null +++ b/meta-hailo-linux/recipes-hailo/busybox/busybox/enable-base64.cfg @@ -0,0 +1 @@ +CONFIG_BASE64=y diff --git a/meta-hailo-linux/recipes-hailo/busybox/busybox/enable-dd-third-status-line.cfg b/meta-hailo-linux/recipes-hailo/busybox/busybox/enable-dd-third-status-line.cfg new file mode 100644 index 0000000..c95784f --- /dev/null +++ b/meta-hailo-linux/recipes-hailo/busybox/busybox/enable-dd-third-status-line.cfg @@ -0,0 +1 @@ +CONFIG_FEATURE_DD_THIRD_STATUS_LINE=y \ No newline at end of file diff --git a/meta-hailo-linux/recipes-hailo/busybox/busybox/enable-devmem.cfg b/meta-hailo-linux/recipes-hailo/busybox/busybox/enable-devmem.cfg new file mode 100644 index 0000000..174a3f2 --- /dev/null +++ b/meta-hailo-linux/recipes-hailo/busybox/busybox/enable-devmem.cfg @@ -0,0 +1 @@ +CONFIG_DEVMEM=y diff --git a/meta-hailo-linux/recipes-hailo/busybox/busybox/enable-i2c-tools.cfg b/meta-hailo-linux/recipes-hailo/busybox/busybox/enable-i2c-tools.cfg new file mode 100644 index 0000000..c69e10a --- /dev/null +++ b/meta-hailo-linux/recipes-hailo/busybox/busybox/enable-i2c-tools.cfg @@ -0,0 +1,5 @@ +CONFIG_I2CGET=y +CONFIG_I2CSET=y +CONFIG_I2CDUMP=y +CONFIG_I2CDETECT=y +CONFIG_I2CTRANSFER=y diff --git a/meta-hailo-linux/recipes-hailo/busybox/busybox/enable-nc-server.cfg b/meta-hailo-linux/recipes-hailo/busybox/busybox/enable-nc-server.cfg new file mode 100644 index 0000000..2fcfd8f --- /dev/null +++ b/meta-hailo-linux/recipes-hailo/busybox/busybox/enable-nc-server.cfg @@ -0,0 +1,3 @@ +CONFIG_NC_SERVER=y +CONFIG_NC_EXTRA=y +CONFIG_NC_110_COMPAT=y \ No newline at end of file diff --git a/meta-hailo-linux/recipes-hailo/busybox/busybox/enable-reverse-search.cfg b/meta-hailo-linux/recipes-hailo/busybox/busybox/enable-reverse-search.cfg new file mode 100644 index 0000000..5641a2e --- /dev/null +++ b/meta-hailo-linux/recipes-hailo/busybox/busybox/enable-reverse-search.cfg @@ -0,0 +1 @@ +CONFIG_FEATURE_REVERSE_SEARCH=y \ No newline at end of file diff --git a/meta-hailo-linux/recipes-hailo/busybox/busybox/enable-telentd.cfg b/meta-hailo-linux/recipes-hailo/busybox/busybox/enable-telentd.cfg new file mode 100644 index 0000000..6dc8392 --- /dev/null +++ b/meta-hailo-linux/recipes-hailo/busybox/busybox/enable-telentd.cfg @@ -0,0 +1 @@ +CONFIG_TELNETD=y \ No newline at end of file diff --git a/meta-hailo-linux/recipes-hailo/busybox/busybox/enable-tftp-progressbar.cfg b/meta-hailo-linux/recipes-hailo/busybox/busybox/enable-tftp-progressbar.cfg new file mode 100644 index 0000000..1c58bce --- /dev/null +++ b/meta-hailo-linux/recipes-hailo/busybox/busybox/enable-tftp-progressbar.cfg @@ -0,0 +1,2 @@ +CONFIG_FEATURE_TFTP_PROGRESS_BAR=y +CONFIG_FEATURE_TFTP_BLOCKSIZE=y diff --git a/meta-hailo-linux/recipes-hailo/busybox/busybox_%.bbappend b/meta-hailo-linux/recipes-hailo/busybox/busybox_%.bbappend new file mode 100644 index 0000000..33876c4 --- /dev/null +++ b/meta-hailo-linux/recipes-hailo/busybox/busybox_%.bbappend @@ -0,0 +1,8 @@ +FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:" +SRC_URI += "file://enable-devmem.cfg" +SRC_URI += "file://enable-nc-server.cfg" +SRC_URI += "file://enable-dd-third-status-line.cfg" +SRC_URI += "file://enable-reverse-search.cfg" +SRC_URI += "file://enable-base64.cfg" +SRC_URI += "file://enable-tftp-progressbar.cfg" +SRC_URI += "file://enable-i2c-tools.cfg" diff --git a/meta-hailo-linux/recipes-support/rng-tools/rng-tools_%.bbappend b/meta-hailo-linux/recipes-support/rng-tools/rng-tools_%.bbappend new file mode 100644 index 0000000..ec5700f --- /dev/null +++ b/meta-hailo-linux/recipes-support/rng-tools/rng-tools_%.bbappend @@ -0,0 +1,4 @@ +# INITSCRIPT_PARAMS define when start and stop the system-V services +# overriding the INITSCRIPT_PARAMS by removing the auto start of rng-tools +INITSCRIPT_PARAMS="stop 30 0 6 1 ." + diff --git a/meta-hailo-media-library/classes/media-library-base.bbclass b/meta-hailo-media-library/classes/media-library-base.bbclass new file mode 100644 index 0000000..90631c3 --- /dev/null +++ b/meta-hailo-media-library/classes/media-library-base.bbclass @@ -0,0 +1,16 @@ +# media-library base class - setting the base configuration for meson (target, type, includes etc...) +# depends on + +inherit meson pkgconfig + +S = "${WORKDIR}/git" + +MEDIA_LIBRARY_BUILD_TARGET = "all" +MEDIA_LIBRARY_BUILD_TYPE = "release" +PARALLEL_MAKE = "-j 4" + +EXTRA_OEMESON += " \ + -Dcpp_std='c++17' \ + -Dtargets='${MEDIA_LIBRARY_BUILD_TARGET}' \ + --buildtype='${MEDIA_LIBRARY_BUILD_TYPE}' \ + " diff --git a/meta-hailo-media-library/conf/layer.conf b/meta-hailo-media-library/conf/layer.conf new file mode 100644 index 0000000..aaded30 --- /dev/null +++ b/meta-hailo-media-library/conf/layer.conf @@ -0,0 +1,15 @@ +# We have a conf and classes directory, add to BBPATH +BBPATH .= ":${LAYERDIR}" + +# We have recipes-* directories, add to BBFILES +BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \ + ${LAYERDIR}/recipes-*/*/*.bbappend" + +BBFILE_COLLECTIONS += "meta-hailo-media-library" +BBFILE_PATTERN_meta-hailo-media-library = "^${LAYERDIR}/" +BBFILE_PRIORITY_meta-hailo-media-library = "8" + +LAYERDEPENDS_meta-hailo-media-library = "core" +LAYERSERIES_COMPAT_meta-hailo-media-library = "kirkstone" + +TOOLCHAIN_TARGET_TASK:append = " expected" diff --git a/meta-hailo-media-library/recipes-gstreamer/gstreamer/files/get_vsm_from_v4l_buffer.patch b/meta-hailo-media-library/recipes-gstreamer/gstreamer/files/get_vsm_from_v4l_buffer.patch new file mode 100644 index 0000000..6185156 --- /dev/null +++ b/meta-hailo-media-library/recipes-gstreamer/gstreamer/files/get_vsm_from_v4l_buffer.patch @@ -0,0 +1,348 @@ +diff --git a/subprojects/gst-plugins-good/sys/v4l2/gstv4l2.c b/subprojects/gst-plugins-good/sys/v4l2/gstv4l2.c +index ec53bc9e83..25cbeace71 100644 +--- a/subprojects/gst-plugins-good/sys/v4l2/gstv4l2.c ++++ b/subprojects/gst-plugins-good/sys/v4l2/gstv4l2.c +@@ -57,6 +57,7 @@ + #include "gstv4l2vp8enc.h" + #include "gstv4l2vp9enc.h" + #include "gstv4l2transform.h" ++#include "hailo_vsm/hailo_vsm_meta.h" + + GST_DEBUG_CATEGORY_EXTERN (v4l2_debug); + #define GST_CAT_DEFAULT v4l2_debug +@@ -267,6 +268,9 @@ plugin_init (GstPlugin * plugin) + ret |= GST_ELEMENT_REGISTER (v4l2radio, plugin); + ret |= GST_DEVICE_PROVIDER_REGISTER (v4l2deviceprovider, plugin); + ++ gst_hailo_vsm_meta_get_info(); ++ gst_hailo_vsm_meta_get_type(); ++ + return ret; + } + +diff --git a/subprojects/gst-plugins-good/sys/v4l2/gstv4l2src.c b/subprojects/gst-plugins-good/sys/v4l2/gstv4l2src.c +index d00f7a80dc..3c5dfa6ca7 100644 +--- a/subprojects/gst-plugins-good/sys/v4l2/gstv4l2src.c ++++ b/subprojects/gst-plugins-good/sys/v4l2/gstv4l2src.c +@@ -57,6 +57,10 @@ + #include "gstv4l2elements.h" + #include "gstv4l2src.h" + ++#include "hailo_vsm/hailo_vsm_meta.h" ++#include "hailo_vsm/hailo_vsm.h" ++#include "gst/allocators/gstdmabuf.h" ++ + #include "gstv4l2colorbalance.h" + #include "gstv4l2tuner.h" + #include "gstv4l2vidorient.h" +@@ -67,6 +71,7 @@ GST_DEBUG_CATEGORY (v4l2src_debug); + #define GST_CAT_DEFAULT v4l2src_debug + + #define DEFAULT_PROP_DEVICE "/dev/video0" ++#define VIDEO_GET_VSM_IOC 0x1337face + + enum + { +@@ -924,6 +929,51 @@ gst_v4l2src_change_state (GstElement * element, GstStateChange transition) + return ret; + } + ++static gboolean ++gst_v4l2_get_vsm_metadata(GstV4l2Src *v4l2src, GstV4l2Object *obj, GstBuffer *buf) ++{ ++ struct hailo15_get_vsm_params vsm_params; ++ guint v4l2_index; ++ ++ GstMemory *mem; ++ GstV4l2Memory *vmem; ++ GstV4l2MemoryGroup *group; ++ ++ // Get V4l2 memory group from buffer - taken from gstv4l2bufferpool.c (gst_v4l2_is_buffer_valid) ++ mem = gst_buffer_peek_memory(buf, 0); ++ ++ if (GST_BUFFER_FLAG_IS_SET(buf, GST_BUFFER_FLAG_TAG_MEMORY)) ++ return FALSE; ++ ++ if (gst_is_dmabuf_memory (mem)) ++ mem = gst_mini_object_get_qdata (GST_MINI_OBJECT (mem), ++ GST_V4L2_MEMORY_QUARK); ++ ++ if (!mem || !gst_is_v4l2_memory(mem)){ ++ GST_WARNING_OBJECT(v4l2src, "Failed to get v4l2memory from buffer (buffer may copied). skip adding VSM metadata"); ++ return TRUE; ++ } ++ ++ vmem = (GstV4l2Memory *) mem; ++ group = vmem->group; ++ ++ // Get the v4l2 buffer index from the memory group ++ v4l2_index = group->buffer.index; ++ vsm_params.index = v4l2_index; ++ ++ // Get the VSM params (motion vector) from the video device ++ if(obj->ioctl(obj->video_fd, VIDEO_GET_VSM_IOC, &vsm_params)){ ++ GST_ERROR_OBJECT (v4l2src, "Failed to get vsm params for index %d", v4l2_index); ++ return FALSE; ++ } ++ ++ GST_DEBUG_OBJECT(v4l2src, "Got vsm params for index %d, x = %d , y=%d", v4l2_index, vsm_params.vsm.dx, vsm_params.vsm.dy); ++ ++ // Add the VSM params to the buffer as metadata ++ gst_buffer_add_hailo_vsm_meta(buf, v4l2_index, vsm_params.vsm); ++ return TRUE; ++} ++ + static GstFlowReturn + gst_v4l2src_create (GstPushSrc * src, GstBuffer ** buf) + { +@@ -973,6 +1023,9 @@ gst_v4l2src_create (GstPushSrc * src, GstBuffer ** buf) + if (G_UNLIKELY (ret != GST_FLOW_OK)) + goto error; + ++ if (!gst_v4l2_get_vsm_metadata(v4l2src, obj, *buf)) ++ goto error; ++ + timestamp = GST_BUFFER_TIMESTAMP (*buf); + duration = obj->duration; + +diff --git a/subprojects/gst-plugins-good/sys/v4l2/hailo_vsm/hailo_vsm.h b/subprojects/gst-plugins-good/sys/v4l2/hailo_vsm/hailo_vsm.h +new file mode 100644 +index 0000000000..f93334497c +--- /dev/null ++++ b/subprojects/gst-plugins-good/sys/v4l2/hailo_vsm/hailo_vsm.h +@@ -0,0 +1,12 @@ ++#pragma once ++// hailo_vsm name ++ ++struct hailo15_vsm{ ++ int dx; ++ int dy; ++}; ++ ++struct hailo15_get_vsm_params{ ++ int index; ++ struct hailo15_vsm vsm; ++}; +\ No newline at end of file +diff --git a/subprojects/gst-plugins-good/sys/v4l2/hailo_vsm/hailo_vsm_meta.c b/subprojects/gst-plugins-good/sys/v4l2/hailo_vsm/hailo_vsm_meta.c +new file mode 100644 +index 0000000000..7002f5e502 +--- /dev/null ++++ b/subprojects/gst-plugins-good/sys/v4l2/hailo_vsm/hailo_vsm_meta.c +@@ -0,0 +1,153 @@ ++/** ++ * Copyright (c) 2021-2022 Hailo Technologies Ltd. All rights reserved. ++ * Distributed under the LGPL license (https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt) ++ **/ ++#include "hailo_vsm_meta.h" ++ ++#include ++#include ++#include ++#include ++ ++static gboolean gst_hailo_vsm_meta_init(GstMeta *meta, gpointer params, GstBuffer *buffer); ++static void gst_hailo_vsm_meta_free(GstMeta *meta, GstBuffer *buffer); ++static gboolean gst_hailo_vsm_meta_transform(GstBuffer *transbuf, GstMeta *meta, GstBuffer *buffer, ++ GQuark type, gpointer data); ++ ++// Register metadata type and returns Gtype ++// https://gstreamer.freedesktop.org/data/doc/gstreamer/head/gstreamer/html/gstreamer-GstMeta.html#gst-meta-api-type-register ++GType gst_hailo_vsm_meta_get_type(void) ++{ ++ static const gchar *tags[] = {NULL}; ++ static GType type; ++ if (g_once_init_enter(&type)) ++ { ++ GType _type = gst_meta_api_type_register("GstHailoVsmMetaAPI", tags); ++ g_once_init_leave(&type, _type); ++ } ++ return type; ++} ++ ++// GstMetaInfo provides info for specific metadata implementation ++// https://gstreamer.freedesktop.org/data/doc/gstreamer/head/gstreamer/html/gstreamer-GstMeta.html#GstMetaInfo ++const GstMetaInfo *gst_hailo_vsm_meta_get_info(void) ++{ ++ static const GstMetaInfo *gst_hailo_vsm_meta_info = NULL; ++ ++ if (g_once_init_enter(&gst_hailo_vsm_meta_info)) ++ { ++ // Explanation of fields ++ // https://gstreamer.freedesktop.org/documentation/design/meta.html#gstmeta1 ++ const GstMetaInfo *meta = gst_meta_register(GST_HAILO_VSM_META_API_TYPE, /* api type */ ++ "GstHailoVsmMeta", /* implementation type */ ++ sizeof(GstHailoVsmMeta), /* size of the structure */ ++ gst_hailo_vsm_meta_init, ++ (GstMetaFreeFunction)gst_hailo_vsm_meta_free, ++ gst_hailo_vsm_meta_transform); ++ g_once_init_leave(&gst_hailo_vsm_meta_info, meta); ++ } ++ return gst_hailo_vsm_meta_info; ++} ++ ++// Meta init function ++// Fourth field in GstMetaInfo ++// https://gstreamer.freedesktop.org/data/doc/gstreamer/head/gstreamer/html/gstreamer-GstMeta.html#GstMetaInitFunction ++static gboolean gst_hailo_vsm_meta_init(GstMeta *meta, gpointer params, GstBuffer *buffer) ++{ ++ GstHailoVsmMeta *gst_hailo_vsm_meta = (GstHailoVsmMeta *)meta; ++ // GStreamer is allocating the GstHailoVsmMeta struct with POD allocation (like malloc) when ++ // it holds non POD type (shared_ptr). The memset assures there is no garbage data in this address. ++ // This is a temporary solution because memset to non POD type is undefined behavior. ++ // https://stackoverflow.com/questions/59747240/is-it-okay-to-memset-a-struct-which-has-an-another-struct-with-smart-pointer-mem?rq=1 ++ // Opened an issue to replace this line with right initialization - MAD-1158. ++ gst_hailo_vsm_meta->v4l2_index = 0; ++ gst_hailo_vsm_meta->vsm.dx = 0; ++ gst_hailo_vsm_meta->vsm.dy = 0; ++ return TRUE; ++} ++ ++// Meta free function ++// Fifth field in GstMetaInfo ++// https://gstreamer.freedesktop.org/data/doc/gstreamer/head/gstreamer/html/gstreamer-GstMeta.html#GstMetaFreeFunction ++static void gst_hailo_vsm_meta_free(GstMeta *meta, GstBuffer *buffer) ++{ ++ GstHailoVsmMeta *hailo_vsm_meta = (GstHailoVsmMeta *)meta; ++ hailo_vsm_meta->v4l2_index = 0; ++ hailo_vsm_meta->vsm.dx = 0; ++ hailo_vsm_meta->vsm.dy = 0; ++} ++ ++// Meta transform function ++// Sixth field in GstMetaInfo ++// https://gstreamer.freedesktop.org/data/doc/gstreamer/head/gstreamer/html/gstreamer-GstMeta.html#GstMetaTransformFunction ++static gboolean gst_hailo_vsm_meta_transform(GstBuffer *transbuf, GstMeta *meta, GstBuffer *buffer, ++ GQuark type, gpointer data) ++{ ++ GstHailoVsmMeta *gst_hailo_vsm_meta = (GstHailoVsmMeta *)meta; ++ ++ GstHailoVsmMeta *new_hailo_vsm_meta = gst_buffer_add_hailo_vsm_meta(transbuf, gst_hailo_vsm_meta->v4l2_index, gst_hailo_vsm_meta->vsm); ++ if(!new_hailo_vsm_meta) ++ { ++ GST_ERROR("gst_hailo_vsm_meta_transform: failed to transform hailo_vsm_meta"); ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++ ++GstHailoVsmMeta *gst_buffer_get_hailo_vsm_meta(GstBuffer *buffer) ++{ ++ // https://gstreamer.freedesktop.org/data/doc/gstreamer/head/gstreamer/html/GstBuffer.html#gst-buffer-get-meta ++ GstHailoVsmMeta *meta = (GstHailoVsmMeta *)gst_buffer_get_meta((buffer), GST_HAILO_VSM_META_API_TYPE); ++ return meta; ++} ++/** ++ * @brief Addes a new GstHailoVsmMeta to a given buffer, this meta is initialized with a given index. ++ * ++ * @param buffer Buffer to add the metadata on. ++ * @param guint v4l2_index ++ * @return GstHailoVsmMeta* The meta structure that was added to the buffer. ++ */ ++GstHailoVsmMeta *gst_buffer_add_hailo_vsm_meta(GstBuffer *buffer, guint v4l2_index, struct hailo15_vsm vsm) ++{ ++ GstHailoVsmMeta *gst_hailo_vsm_meta = NULL; ++ ++ // check that gst_buffer valid ++ g_return_val_if_fail((int)GST_IS_BUFFER(buffer), NULL); ++ ++ // check that gst_buffer writable ++ if (!gst_buffer_is_writable(buffer)) ++ return gst_hailo_vsm_meta; ++ ++ // https://gstreamer.freedesktop.org/data/doc/gstreamer/head/gstreamer/html/GstBuffer.html#gst-buffer-add-meta ++ gst_hailo_vsm_meta = (GstHailoVsmMeta *)gst_buffer_add_meta(buffer, GST_HAILO_VSM_META_INFO, NULL); ++ ++ gst_hailo_vsm_meta->v4l2_index = v4l2_index; ++ gst_hailo_vsm_meta->vsm = vsm; ++ ++ return gst_hailo_vsm_meta; ++} ++ ++/** ++ * @brief Removes GstHailoVsmMeta from a given buffer. ++ * ++ * @param buffer A buffer to remove meta from. ++ * @return gboolean whether removal was successfull (TRUE if there isn't GstHailoVsmMeta). ++ * @note Removes only the first GstHailoVsmMeta in this buffer. ++ */ ++gboolean gst_buffer_remove_hailo_vsm_meta(GstBuffer *buffer) ++{ ++ GstHailoVsmMeta *meta; ++ g_return_val_if_fail((int)GST_IS_BUFFER(buffer), false); ++ ++ meta = (GstHailoVsmMeta *)gst_buffer_get_meta((buffer), GST_HAILO_VSM_META_API_TYPE); ++ ++ if (meta == NULL) ++ return TRUE; ++ ++ if (!gst_buffer_is_writable(buffer)) ++ return FALSE; ++ ++ // https://gstreamer.freedesktop.org/data/doc/gstreamer/head/gstreamer/html/GstBuffer.html#gst-buffer-remove-meta ++ return gst_buffer_remove_meta(buffer, &meta->meta); ++} +\ No newline at end of file +diff --git a/subprojects/gst-plugins-good/sys/v4l2/hailo_vsm/hailo_vsm_meta.h b/subprojects/gst-plugins-good/sys/v4l2/hailo_vsm/hailo_vsm_meta.h +new file mode 100644 +index 0000000000..8661fcc1ad +--- /dev/null ++++ b/subprojects/gst-plugins-good/sys/v4l2/hailo_vsm/hailo_vsm_meta.h +@@ -0,0 +1,41 @@ ++#include ++#include "hailo_vsm.h" ++ ++G_BEGIN_DECLS ++ ++// Api Type ++// First field of gst_meta_register (which returns GstMetaInfo) ++// https://gstreamer.freedesktop.org/documentation/gstreamer/gstmeta.html?gi-language=c#gst_meta_register ++#define GST_HAILO_VSM_META_API_TYPE (gst_hailo_vsm_meta_get_type()) ++#define GST_HAILO_VSM_META_INFO (gst_hailo_vsm_meta_get_info()) ++ ++#define HAILO_VSM_META_API_NAME "GstHailoVsmMetaAPI" ++ ++typedef struct _GstHailoVsmMeta GstHailoVsmMeta; ++ ++struct _GstHailoVsmMeta ++{ ++ // Gstreamer Metadata for passing the VSM (motion vector) through hailo15 pipeline ++ ++ GstMeta meta; ++ // V4L2 buffer index ++ guint v4l2_index; ++ // VSM ++ struct hailo15_vsm vsm; ++}; ++ ++GType gst_hailo_vsm_meta_get_type(void); ++ ++GST_EXPORT ++const GstMetaInfo *gst_hailo_vsm_meta_get_info(void); ++ ++GST_EXPORT ++GstHailoVsmMeta *gst_buffer_add_hailo_vsm_meta(GstBuffer *buffer, guint v4l2_index, struct hailo15_vsm vsm); ++ ++GST_EXPORT ++gboolean gst_buffer_remove_hailo_vsm_meta(GstBuffer *buffer); ++ ++GST_EXPORT ++GstHailoVsmMeta *gst_buffer_get_hailo_vsm_meta(GstBuffer *b); ++ ++G_END_DECLS +\ No newline at end of file +diff --git a/subprojects/gst-plugins-good/sys/v4l2/meson.build b/subprojects/gst-plugins-good/sys/v4l2/meson.build +index 65f551fb64..bfde728cad 100644 +--- a/subprojects/gst-plugins-good/sys/v4l2/meson.build ++++ b/subprojects/gst-plugins-good/sys/v4l2/meson.build +@@ -33,7 +33,8 @@ v4l2_sources = [ + 'v4l2-utils.c', + 'tuner.c', + 'tunerchannel.c', +- 'tunernorm.c' ++ 'tunernorm.c', ++ 'hailo_vsm/hailo_vsm_meta.c' + ] + + v4l2 = get_option('v4l2') diff --git a/meta-hailo-media-library/recipes-gstreamer/gstreamer/gstreamer1.0-plugins-good_%.bbappend b/meta-hailo-media-library/recipes-gstreamer/gstreamer/gstreamer1.0-plugins-good_%.bbappend new file mode 100644 index 0000000..a54b5cd --- /dev/null +++ b/meta-hailo-media-library/recipes-gstreamer/gstreamer/gstreamer1.0-plugins-good_%.bbappend @@ -0,0 +1,12 @@ +FILESEXTRAPATHS:prepend:hailo15 := "${THISDIR}/files/:" + +SRC_URI:append:hailo15 = "file://get_vsm_from_v4l_buffer.patch;striplevel=3;md5=1939fc95b44a4e82f97aad4a1c60d73f" + +do_install:append(){ + install -d ${D}${includedir}/ + install -d ${D}${includedir}/v4l2_vsm/ + + install -m 0644 ${S}/sys/v4l2/hailo_vsm/*.h ${D}${includedir}/v4l2_vsm/ +} + +FILES:${PN}-dev += "${includedir}/v4l2_vsm ${includedir}/v4l2_vsm/*" \ No newline at end of file diff --git a/meta-hailo-media-library/recipes-gstreamer/libgstmedialib/libgstmedialib_0.1.0.bb b/meta-hailo-media-library/recipes-gstreamer/libgstmedialib/libgstmedialib_0.1.0.bb new file mode 100644 index 0000000..2a898fc --- /dev/null +++ b/meta-hailo-media-library/recipes-gstreamer/libgstmedialib/libgstmedialib_0.1.0.bb @@ -0,0 +1,34 @@ +DESCRIPTION = "Media Library GStreamer plugin \ + compiles the medialibrary gstreamer plugin \ + and copies it to usr/lib/gstreamer-1.0 (gstreamer's plugins directory) " + +LICENSE = "MIT" +LIC_FILES_CHKSUM = "file://LICENSE;md5=8349eaff29531f0a3c4f4c8b31185958" + +S = "${S}/hailo-media-library" +SRC_URI = "git://git@github.com/hailo-ai/hailo-media-library.git;protocol=https;branch=1.1.0" +SRCREV = "df61fbcf11b4885e6df452c3841610943a41b433" + +inherit media-library-base + +MEDIA_LIBRARY_BUILD_TARGET = "gst" + +do_install:append() { + rm -f ${D}/${libdir}/gstreamer-1.0/libgstmedialib.so + find ${D}/${libdir}/gstreamer-1.0/ -name 'libgstmedialib.so.[0-9]' -delete + mv -f ${D}/${libdir}/gstreamer-1.0/libgstmedialib.so.${PV} ${D}/${libdir}/gstreamer-1.0/libgstmedialib.so +} + +# Gstreamer Dependencies +DEPENDS:append = " glib-2.0-native glib-2.0 gstreamer1.0 gstreamer1.0-plugins-base gstreamer1.0-plugins-good" +# Hailo-15 Dependencies +DEPENDS:append = " libhailodsp libmedialib" +# Other Dependencies +DEPENDS:append = " opencv spdlog" + + +FILES:${PN} += "${libdir}/gstreamer-1.0/libgstmedialib.so" +FILES:${PN}-lib += "${libdir}/gstreamer-1.0/libgstmedialib.so" +RDEPENDS:${PN}-staticdev = "" +RDEPENDS:${PN}-dev = "" +RDEPENDS:${PN}-dbg = "" diff --git a/meta-hailo-media-library/recipes-media-library/expected/expected_1.1.0.bb b/meta-hailo-media-library/recipes-media-library/expected/expected_1.1.0.bb new file mode 100644 index 0000000..b0f1661 --- /dev/null +++ b/meta-hailo-media-library/recipes-media-library/expected/expected_1.1.0.bb @@ -0,0 +1,25 @@ +SUMMARY = "expected : Single header implementation of std::expected with functional-style extensions." + +LICENSE = "CC0 1.0 Universal" +LIC_FILES_CHKSUM = "file://COPYING;md5=65d3616852dbf7b1a6d4b53b00626032" + +SRC_URI = "git://github.com/TartanLlama/expected.git;protocol=https;branch=master" + +PV = "1.0+git${SRCPV}" +SRCREV = "292eff8bd8ee230a7df1d6a1c00c4ea0eb2f0362" + +S = "${WORKDIR}/git" + +# expected is a header-only C++ library, so the main package will be empty. +ALLOW_EMPTY:${PN} = "1" +ALLOW_EMPTY:${PN}-dev = "1" + +do_install(){ + install -d ${D}${includedir} + install -d ${D}${includedir}/tl + + install -m 0644 ${S}/include/tl/*.hpp ${D}${includedir}/tl/ +} + +FILES:${PN} += "${includedir}/* ${includedir}/TL ${includedir}/tl/*.hpp" +FILES:${PN}-dev += "${includedir}/* ${includedir}/tl ${includedir}/tl/*" diff --git a/meta-hailo-media-library/recipes-media-library/libencoderosd/libencoderosd_0.1.0.bb b/meta-hailo-media-library/recipes-media-library/libencoderosd/libencoderosd_0.1.0.bb new file mode 100644 index 0000000..76c11b0 --- /dev/null +++ b/meta-hailo-media-library/recipes-media-library/libencoderosd/libencoderosd_0.1.0.bb @@ -0,0 +1,29 @@ +DESCRIPTION = "Media Library Encoder OSD API \ + compiles the medialibrary encoder osd API \ + and copies it to usr/lib/ " + +LICENSE = "MIT" +LIC_FILES_CHKSUM = "file://LICENSE;md5=8349eaff29531f0a3c4f4c8b31185958" + +SRC_URI = "git://git@github.com/hailo-ai/hailo-media-library.git;protocol=https;branch=1.1.0" +SRCREV = "df61fbcf11b4885e6df452c3841610943a41b433" + +inherit media-library-base + +MEDIA_LIBRARY_BUILD_TARGET = "api" + +# Gstreamer Dependencies +DEPENDS:append = " glib-2.0-native glib-2.0 gstreamer1.0 gstreamer1.0-plugins-base gstreamer1.0-plugins-good json-schema-validator" +# Hailo-15 Dependencies +DEPENDS:append = " libgstmedialib" + +do_install:append(){ + install -d ${D}/${bindir} + install -m 0644 ${S}/api/examples/*.json ${D}/${bindir} +} + +FILES:${PN} += "${libdir}/libencoderosd.so ${bindir}/vision_preproc_example ${bindir}/*.json ${incdir}/medialibrary/*.hpp" +FILES:${PN}-lib += "${libdir}/libencoderosd.so" +RDEPENDS:${PN}-staticdev = "" +RDEPENDS:${PN}-dev = "" +RDEPENDS:${PN}-dbg = "" diff --git a/meta-hailo-media-library/recipes-media-library/libmedialib/libmedialib_0.1.0.bb b/meta-hailo-media-library/recipes-media-library/libmedialib/libmedialib_0.1.0.bb new file mode 100644 index 0000000..2ff35ce --- /dev/null +++ b/meta-hailo-media-library/recipes-media-library/libmedialib/libmedialib_0.1.0.bb @@ -0,0 +1,20 @@ +DESCRIPTION = "Media Library package recipe \ + compiles medialibrary vision_pre_proc shared object and copies it to usr/lib/ " + +LICENSE = "MIT" +LIC_FILES_CHKSUM = "file://LICENSE;md5=8349eaff29531f0a3c4f4c8b31185958" + +SRC_URI = "git://git@github.com/hailo-ai/hailo-media-library.git;protocol=https;branch=1.1.0" +SRCREV = "df61fbcf11b4885e6df452c3841610943a41b433" + +inherit media-library-base + +MEDIA_LIBRARY_BUILD_TARGET = "core" + +DEPENDS:append = " gstreamer1.0-plugins-good rapidjson spdlog json-schema-validator expected" + +# Hailo-15 Dependencies +DEPENDS:append = " video-encoder libhailodsp" + +FILES:${PN} += "${libdir}/libdis_library.so ${libdir}/libhailo_media_library_common.so ${libdir}/libhailo_media_library_frontend.so ${libdir}/libhailo_media_library_encoder.so ${libdir}/libhailo_encoder.so ${incdir}/medialibrary/*.hpp" +FILES:${PN}-lib += "${libdir}/libdis_library.so ${libdir}/libhailo_media_library_common.so ${libdir}/libhailo_media_library_frontend.so ${libdir}/libhailo_media_library_encoder.so ${libdir}/libhailo_encoder.so"