Tri-State data type

[HWoidt]

Issue by HWoidt
Saturday Jul 11, 2015 at 13:01 GMT
Originally opened as https://gits-15.sys.kth.se/ingo/forsyde-deep/issues/12

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Reported by [email protected], Apr 23, 2008

In order to model for instance buses a tri-state data type is needed.

std_logic in VHDL provides 9 different values, the most important are '1',
'0', 'Z' (high resistance) and 'X' (unknown).

How difficult would it be to implement it?

Apr 24, 2008
Project Member [email protected]

OK, sounds reasonable. On the other hand ... wouldn't it be better to just have one
type (e.g. StdLogic) instead of two (Bit + StdLogic)? Actually, Bit is currently
translated to std_logic.

I never really understood why VHDL makes use of both.

Apr 24, 2008
Project Member [email protected]

Let's think a little bit more about it. The full std_logic data type is not needed
for synthesis. One should have 'Z' and maybe 'X' is also used (for don't care, but we
have to check this further).