Schematic Cleanup, PCB stackup, Trace Rerouting

[fabianmuehlberger]

Hi,

[EDIT] 18.11.2024

The schematic should follow general guidelines like:

• Symbol naming/numbering from left top to right bottom,
• Upper left Power, IO
• right side MCU, peripherals (flash, crystal)
• do not cross lines if possible
• PWR labels always Up, GND labels always down
• labels on symbols should sit on the line

I found this guide with basic recommendations for the schematic.

Elegant schematics
schematic checklist

A best practices regarding ground can be found here

I have not checked if the left and right side have significant functional differences, if so, making hierarchical sheets for duplicates would be suggested too, e.g. keys, LEDs, MCU on separate sheets and references to them for left and right side if the components are the same.

Regarding the PCB, I would suggest switching to a 4 layer PCB. Since ground pour is only on the top side with a high number of traces on the top and bottom, as well as layer changes of signal lines, current return paths are VERY restricted. A 4 layer PCB with 2 ground inner layers would make routing easier and improve the board overall.

I made some example changes in the corne chocolate schematic on my fork
Please let me know if you are interested in a redesign, if there is interest, I am happy to contribute.

Best Fabian

[foostan]

Thank you for your suggestion. Please provide evidence to evaluate the validity of your proposal. thank you.

[fabianmuehlberger]

Deleted

[foostan]

Thank you for sharing. I'll confirm the guide and fix them.

About 4 layer, could you tell me your opinion more. Could you share Pros/Cons?

[fabianmuehlberger]

Hey, It's not about the guide, these enhancements can be separately applied.

1. Schematic rearrangement/refactor is to make it more concise. The goal is to make it easier to read and debug if there are problems. Following basic guidelines will help adapt and improve the design in the future and make it more portable.

2. PCB stackup is a big topic itself, and I am not an expert. But 4 layer PCBs are the norm nowadays and have gotten cheap to produce; therefore we can get the advantages over a 2 layer board with basically no downsides. I see no reason for not using a 4 layer board
   These are:

• Inner ground layers: generally speaking, you want all traces separated by a ground layer. This helps with crosstalk and provides a solid current return path. With 2 layers, this is only possible when using one side for traces and the other for ground. Obviously, this can only be done on low density boards (low component count; space for routing).
• Easier Routing: With a 4 layer board, it is much simpler since you can use the 2 inner layers for GND and the PWR bus and use the outer layers for the signal traces. This makes routing easier, since you simply have more space to do so.
• EMI: For commercial products in the EU an EMI/EMC test is mandatory. So far, I have not produced a PCB for the market, but it's a big topic. Following the industry norm wherever you can helps comply with those standards.
  https://www.protoexpress.com/blog/7-pcb-design-tips-solve-emi-emc-issues/

Best

[foostan]

Thank you for sharing. I'll read the docs you shared.

[fabianmuehlberger]

From your answer, I assume that you are not interested in me contributing to the project.
I close this issue then.

[fabianmuehlberger]

Since there is an ongoing discussion regarding EMI problems, #265 I decided to reopen this issue.
It seems that the concerns in this issue are directly related with the current issues of the hardware.

[willpuckett]

@fabianmuehlberger it seems like your discussion of stackup and improved return path could be relevant to the EMI issues.

I do think there's a value in producing 2 layer boards though especially ones used by hobbyists. 4 layers are sometimes quite a bit more expensive in short runs.

[foostan]

I'm currently prototyping with 2 layers at https://github.com/foostan/crkbd/tree/v4_1_1. If this proves stable enough, It'll continue with 2 layers. If this doesn't work, I may redesign with 4 layers as 4.1.2.

[fabianmuehlberger]

Hey @foostan great to see you are making progress!

I will take a look at your design, maybe I can help improve it here and there.
One thing that I noticed first was the VLED and LED traces intersecting the board south->north and running parallel to the USB lines. There are 2 things to note here. I highlighted those traces.
I took a look at the LEFT board, but the same principle applies to the right side

1. Crosstalk: High-speed signal lines can have crosstalk on parallel signal traces. Since you have some USB issues, you might want to reduce the chance as much as possible.
2. Current return path. Since your USB Connection and therefore your GND is in the upper-right corner (left board), you want a current return path from your IC to that area, that is not intersected by traces.

VLED: you could try routing the VLED from the down and left. Making a circle clockwise around the board instead of cutting through the middle,
LED: I am not sure if the order of attached LEDs is important: if not, you could do the same for the LED line, instead of routing top to bottom, you could try to attach the LEDs from the left side.

This would give you a chance to have a solid copper GND from the IC to the USB port, as well as a solid ground layer under the USB lines. Which should help with the EMI issues you are experiencing.

Best

[foostan]

@fabianmuehlberger Thank you for your suggestion! I'll check later and update it 👍 Thank you!