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Make register categories not translatable (#870)
* Make register categories and names not translatable Categories are not user-visible, only used as ids for searching, so translation is an unnecessary complication that can break things. And the names of registers were never supposed to be translatable. Fixes #868 * These strings are not to be translated The register view relies on these strings to keep the right geometry, and sometimes even for functionality, so they shouldn't be translated.
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-41
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2 files changed

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plugins/ODbgRegisterView/arch/x86-generic/x86Groups.cpp

+27-27
Original file line numberDiff line numberDiff line change
@@ -37,10 +37,10 @@ namespace {
3737
const BitFieldDescription fpuTagDescription = {
3838
7,
3939
{
40-
tr("valid"),
41-
tr("zero"),
42-
tr("special"),
43-
tr("empty"),
40+
"valid",
41+
"zero",
42+
"special",
43+
"empty",
4444
},
4545
{
4646
tr("Tag as used"),
@@ -56,10 +56,10 @@ const BitFieldDescription fpuTagDescription = {
5656
const BitFieldDescription roundControlDescription = {
5757
4,
5858
{
59-
tr("NEAR"),
60-
tr("DOWN"),
61-
tr(" UP"),
62-
tr("ZERO"),
59+
"NEAR",
60+
"DOWN",
61+
" UP",
62+
"ZERO",
6363
},
6464
{
6565
tr("Round to nearest"),
@@ -72,10 +72,10 @@ const BitFieldDescription roundControlDescription = {
7272
const BitFieldDescription precisionControlDescription = {
7373
2,
7474
{
75-
tr("24"),
76-
tr("??"),
77-
tr("53"),
78-
tr("64"),
75+
"24",
76+
"??",
77+
"53",
78+
"64",
7979
},
8080
{
8181
tr("Set 24-bit precision"),
@@ -88,10 +88,10 @@ const BitFieldDescription precisionControlDescription = {
8888
const BitFieldDescription debugRWDescription = {
8989
5,
9090
{
91-
tr("EXEC"),
92-
tr("WRITE"),
93-
tr(" IO"),
94-
tr(" R/W"),
91+
"EXEC",
92+
"WRITE",
93+
" IO",
94+
" R/W",
9595
},
9696
{
9797
tr("Break on execution"),
@@ -104,10 +104,10 @@ const BitFieldDescription debugRWDescription = {
104104
const BitFieldDescription debugLenDescription = {
105105
1,
106106
{
107-
tr("1"),
108-
tr("2"),
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tr("8"),
110-
tr("4"),
107+
"1",
108+
"2",
109+
"8",
110+
"4",
111111
},
112112
{
113113
tr("Set 1-byte length"),
@@ -152,7 +152,7 @@ void add_precision_mode(RegisterGroup *group, const QModelIndex &index, int row,
152152

153153
void add_puozdi(RegisterGroup *group, const QModelIndex &excRegIndex, const QModelIndex &maskRegIndex, int startRow, int startColumn) {
154154

155-
static const QString exceptions = tr("PUOZDI");
155+
static const QString exceptions = "PUOZDI";
156156

157157
static const std::unordered_map<char, QString> excNames = {
158158
{'P', tr("Precision")},
@@ -192,14 +192,14 @@ void add_puozdi(RegisterGroup *group, const QModelIndex &excRegIndex, const QMod
192192
}
193193

194194
RegisterGroup *create_eflags(RegisterViewModelBase::Model *model, QWidget *parent) {
195-
const auto catIndex = find_model_category(model, tr("General Status"));
195+
const auto catIndex = find_model_category(model, "General Status");
196196
if (!catIndex.isValid()) {
197197
return nullptr;
198198
}
199199

200-
auto nameIndex = find_model_register(catIndex, tr("RFLAGS"));
200+
auto nameIndex = find_model_register(catIndex, "RFLAGS");
201201
if (!nameIndex.isValid()) {
202-
nameIndex = find_model_register(catIndex, tr("EFLAGS"));
202+
nameIndex = find_model_register(catIndex, "EFLAGS");
203203
}
204204

205205
if (!nameIndex.isValid()) {
@@ -209,7 +209,7 @@ RegisterGroup *create_eflags(RegisterViewModelBase::Model *model, QWidget *paren
209209
const auto group = new RegisterGroup(tr("EFL"), parent);
210210
constexpr int NameWidth = 3;
211211
int column = 0;
212-
group->insert(0, column, new FieldWidget(tr("EFL"), group));
212+
group->insert(0, column, new FieldWidget("EFL", group));
213213

214214
constexpr int ValueWidth = 8;
215215
const auto valueIndex = nameIndex.sibling(nameIndex.row(), ModelValueColumn);
@@ -228,7 +228,7 @@ RegisterGroup *create_eflags(RegisterViewModelBase::Model *model, QWidget *paren
228228
}
229229

230230
RegisterGroup *create_expanded_eflags(RegisterViewModelBase::Model *model, QWidget *parent) {
231-
const auto catIndex = find_model_category(model, tr("General Status"));
231+
const auto catIndex = find_model_category(model, "General Status");
232232
if (!catIndex.isValid()) {
233233
return nullptr;
234234
}
@@ -318,7 +318,7 @@ RegisterGroup *create_fpu_data(RegisterViewModelBase::Model *model, QWidget *par
318318
constexpr int TagWidth = 7;
319319
const auto fsrIndex = valid_index(find_model_register(catIndex, FsrName));
320320

321-
const QPersistentModelIndex topIndex = valid_index(find_model_register(fsrIndex, tr("TOP"), ModelValueColumn));
321+
const QPersistentModelIndex topIndex = valid_index(find_model_register(fsrIndex, "TOP", ModelValueColumn));
322322

323323
for (int row = 0; row < FpuRegCount; ++row) {
324324
int column = 0;

src/arch/x86-generic/RegisterViewModel.cpp

+14-14
Original file line numberDiff line numberDiff line change
@@ -380,20 +380,20 @@ QVariant RegisterViewModel::data(const QModelIndex &index, int role) const {
380380
*/
381381
RegisterViewModel::RegisterViewModel(int cpuSuppFlags, QObject *parent)
382382
: RegisterViewModelBase::Model(parent),
383-
gprs32(addCategory(tr("General Purpose"))),
384-
gprs64(addCategory(tr("General Purpose"))),
385-
genStatusRegs32(addCategory(tr("General Status"))),
386-
genStatusRegs64(addCategory(tr("General Status"))),
387-
segRegs(addCategory(tr("Segment"))),
388-
dbgRegs32(addCategory(tr("Debug"))),
389-
dbgRegs64(addCategory(tr("Debug"))),
390-
fpuRegs32(addFPUCategory(tr("FPU"))),
391-
fpuRegs64(addFPUCategory(tr("FPU"))),
392-
mmxRegs(addSIMDCategory(tr("MMX"), MMXFormats)),
393-
sseRegs32(addSIMDCategory(tr("SSE"), SSEAVXFormats)),
394-
sseRegs64(addSIMDCategory(tr("SSE"), SSEAVXFormats)),
395-
avxRegs32(addSIMDCategory(tr("AVX"), SSEAVXFormats)),
396-
avxRegs64(addSIMDCategory(tr("AVX"), SSEAVXFormats)) {
383+
gprs32(addCategory("General Purpose")),
384+
gprs64(addCategory("General Purpose")),
385+
genStatusRegs32(addCategory("General Status")),
386+
genStatusRegs64(addCategory("General Status")),
387+
segRegs(addCategory("Segment")),
388+
dbgRegs32(addCategory("Debug")),
389+
dbgRegs64(addCategory("Debug")),
390+
fpuRegs32(addFPUCategory("FPU")),
391+
fpuRegs64(addFPUCategory("FPU")),
392+
mmxRegs(addSIMDCategory("MMX", MMXFormats)),
393+
sseRegs32(addSIMDCategory("SSE", SSEAVXFormats)),
394+
sseRegs64(addSIMDCategory("SSE", SSEAVXFormats)),
395+
avxRegs32(addSIMDCategory("AVX", SSEAVXFormats)),
396+
avxRegs64(addSIMDCategory("AVX", SSEAVXFormats)) {
397397
addGPRs32(gprs32);
398398
addGPRs64(gprs64);
399399

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