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| 1 | +diff --git a/components/esp_driver_i2c/i2c_master.c b/components/esp_driver_i2c/i2c_master.c |
| 2 | +index 8859998eb4..c2571f3d0d 100644 |
| 3 | +--- a/components/esp_driver_i2c/i2c_master.c |
| 4 | ++++ b/components/esp_driver_i2c/i2c_master.c |
| 5 | +@@ -197,22 +197,7 @@ static bool s_i2c_write_command(i2c_master_bus_handle_t i2c_master, i2c_operatio |
| 6 | + i2c_ll_master_write_cmd_reg(hal->dev, hw_cmd, i2c_master->cmd_idx); |
| 7 | + portEXIT_CRITICAL_SAFE(&handle->spinlock); |
| 8 | + i2c_master->w_r_size = data_fill; |
| 9 | +-#if SOC_I2C_STOP_INDEPENDENT |
| 10 | +- i2c_ll_master_write_cmd_reg(hal->dev, hw_end_cmd, i2c_master->cmd_idx + 1); |
| 11 | +- i2c_master->cmd_idx = 0; |
| 12 | +- if (i2c_master->i2c_trans.ops[i2c_master->trans_idx].total_bytes == i2c_master->i2c_trans.ops[i2c_master->trans_idx].bytes_used) { |
| 13 | +- i2c_master->i2c_trans.cmd_count--; |
| 14 | +- i2c_master->trans_idx++; |
| 15 | +- } |
| 16 | +- portENTER_CRITICAL_SAFE(&handle->spinlock); |
| 17 | +- if (i2c_master->async_trans == false) { |
| 18 | +- i2c_hal_master_trans_start(hal); |
| 19 | +- } else { |
| 20 | +- i2c_master->async_break = true; |
| 21 | +- } |
| 22 | +- portEXIT_CRITICAL_SAFE(&handle->spinlock); |
| 23 | + |
| 24 | +-#else |
| 25 | + // If data cannot be sent in one time, send data out. Otherwise, continue configuring command. |
| 26 | + if ((remaining_bytes - data_fill) != 0) { |
| 27 | + portENTER_CRITICAL_SAFE(&handle->spinlock); |
| 28 | +@@ -252,7 +237,6 @@ static bool s_i2c_write_command(i2c_master_bus_handle_t i2c_master, i2c_operatio |
| 29 | + } |
| 30 | + } |
| 31 | + } |
| 32 | +-#endif |
| 33 | + *fifo_fill = data_fill; |
| 34 | + |
| 35 | + return i2c_master->async_break; |
| 36 | +@@ -287,7 +271,6 @@ static bool s_i2c_read_command(i2c_master_bus_handle_t i2c_master, i2c_operation |
| 37 | + hw_cmd.byte_num = *fifo_fill; |
| 38 | + |
| 39 | + i2c_master->contains_read = true; |
| 40 | +-#if !SOC_I2C_STOP_INDEPENDENT |
| 41 | + if (remaining_bytes < I2C_FIFO_LEN(i2c_master->base->port_num) - 1) { |
| 42 | + if (i2c_operation->hw_cmd.ack_val == I2C_ACK_VAL) { |
| 43 | + if (remaining_bytes != 0) { |
| 44 | +@@ -328,29 +311,6 @@ static bool s_i2c_read_command(i2c_master_bus_handle_t i2c_master, i2c_operation |
| 45 | + } |
| 46 | + portEXIT_CRITICAL_SAFE(&handle->spinlock); |
| 47 | + } |
| 48 | +-#else |
| 49 | +- portENTER_CRITICAL_SAFE(&handle->spinlock); |
| 50 | +- // If the read command work with ack_val, but no bytes to read, we skip |
| 51 | +- // this command, and run next command directly. |
| 52 | +- if (hw_cmd.ack_val == I2C_ACK_VAL) { |
| 53 | +- if (i2c_operation->total_bytes == 0) { |
| 54 | +- i2c_master->trans_idx++; |
| 55 | +- hw_cmd = i2c_master->i2c_trans.ops[i2c_master->trans_idx].hw_cmd; |
| 56 | +- i2c_master->i2c_trans.cmd_count--; |
| 57 | +- } |
| 58 | +- } |
| 59 | +- i2c_ll_master_write_cmd_reg(hal->dev, hw_cmd, i2c_master->cmd_idx); |
| 60 | +- i2c_ll_master_write_cmd_reg(hal->dev, hw_end_cmd, i2c_master->cmd_idx + 1); |
| 61 | +- portEXIT_CRITICAL_SAFE(&handle->spinlock); |
| 62 | +- atomic_store(&i2c_master->status, I2C_STATUS_READ); |
| 63 | +- portENTER_CRITICAL_SAFE(&handle->spinlock); |
| 64 | +- if (i2c_master->async_trans == false) { |
| 65 | +- i2c_hal_master_trans_start(hal); |
| 66 | +- } else { |
| 67 | +- i2c_master->async_break = true; |
| 68 | +- } |
| 69 | +- portEXIT_CRITICAL_SAFE(&handle->spinlock); |
| 70 | +-#endif |
| 71 | + |
| 72 | + return i2c_master->async_break; |
| 73 | + } |
| 74 | +@@ -679,9 +639,7 @@ I2C_MASTER_ISR_ATTR static void i2c_isr_receive_handler(i2c_master_bus_t *i2c_ma |
| 75 | + i2c_operation->bytes_used = 0; |
| 76 | + } |
| 77 | + portEXIT_CRITICAL_ISR(&i2c_master->base->spinlock); |
| 78 | +- } |
| 79 | +-#if !SOC_I2C_STOP_INDEPENDENT |
| 80 | +- else { |
| 81 | ++ } else { |
| 82 | + i2c_operation_t *i2c_operation = &i2c_master->i2c_trans.ops[i2c_master->read_buf_pos]; |
| 83 | + portENTER_CRITICAL_ISR(&i2c_master->base->spinlock); |
| 84 | + i2c_ll_read_rxfifo(hal->dev, i2c_operation->data + i2c_operation->bytes_used, i2c_master->read_len_static); |
| 85 | +@@ -693,7 +651,6 @@ I2C_MASTER_ISR_ATTR static void i2c_isr_receive_handler(i2c_master_bus_t *i2c_ma |
| 86 | + i2c_master->contains_read = false; |
| 87 | + portEXIT_CRITICAL_ISR(&i2c_master->base->spinlock); |
| 88 | + } |
| 89 | +-#endif |
| 90 | + } |
| 91 | + |
| 92 | + static void i2c_master_isr_handler_default(void *arg) |
| 93 | +diff --git a/components/soc/esp32/include/soc/Kconfig.soc_caps.in b/components/soc/esp32/include/soc/Kconfig.soc_caps.in |
| 94 | +index 0ba999f747..22c2c0a407 100644 |
| 95 | +--- a/components/soc/esp32/include/soc/Kconfig.soc_caps.in |
| 96 | ++++ b/components/soc/esp32/include/soc/Kconfig.soc_caps.in |
| 97 | +@@ -391,10 +391,6 @@ config SOC_I2C_SUPPORT_10BIT_ADDR |
| 98 | + bool |
| 99 | + default y |
| 100 | + |
| 101 | +-config SOC_I2C_STOP_INDEPENDENT |
| 102 | +- bool |
| 103 | +- default y |
| 104 | +- |
| 105 | + config SOC_I2S_NUM |
| 106 | + int |
| 107 | + default 2 |
| 108 | +diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h |
| 109 | +index 1937908170..f7f4c16949 100644 |
| 110 | +--- a/components/soc/esp32/include/soc/soc_caps.h |
| 111 | ++++ b/components/soc/esp32/include/soc/soc_caps.h |
| 112 | +@@ -208,9 +208,6 @@ |
| 113 | + #define SOC_I2C_SUPPORT_APB (1) |
| 114 | + #define SOC_I2C_SUPPORT_10BIT_ADDR (1) |
| 115 | + |
| 116 | +-// On ESP32, the stop bit should be independent, we can't put trans data and stop command together |
| 117 | +-#define SOC_I2C_STOP_INDEPENDENT (1) |
| 118 | +- |
| 119 | + /*-------------------------- I2S CAPS ----------------------------------------*/ |
| 120 | + // ESP32 has 2 I2S |
| 121 | + #define SOC_I2S_NUM (2U) |
| 122 | +-- |
| 123 | +2.39.5 (Apple Git-154) |
| 124 | + |
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