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erhankurerhankur
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feat: add xtensa trax memory helpers
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‎CMakeLists.txt‎

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@@ -34,7 +34,9 @@ target_include_directories(${ESP_STUB_LIB}
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INTERFACE include
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PRIVATE include/esp-stub-lib
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)
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# Public within the library
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include_directories(include)
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include_directories(include/esp-stub-lib)
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# STUB_COMPILE_DEFS is optional definitions coming from the parent CMakeLists.txt
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target_compile_definitions(${ESP_STUB_LIB} PRIVATE ${STUB_COMPILE_DEFS})

‎include/esp-stub-lib/bit_utils.h‎

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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef BIT
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#define BIT(nr) (1UL << (nr))
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#endif
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#ifndef BIT64
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#define BIT64(nr) (1ULL << (nr))
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#endif
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#ifndef ALIGN_MASK
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#define ALIGN_MASK(x, mask) \
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({ \
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typeof(mask) _mask = (mask); \
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((x) + _mask) & ~_mask; \
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})
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#endif
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#ifndef ALIGN_UP
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#define ALIGN_UP(x, a) ALIGN_MASK(x, (typeof(x))(a) - 1)
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#endif
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#ifndef ALIGN_DOWN
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#define ALIGN_DOWN(x, a) ((x) & ~((typeof(x))(a) - 1))
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#endif
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#ifndef IS_ALIGNED
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#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0)
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#endif
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#ifndef MIN
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#define MIN(a, b) ((a) < (b) ? (a) : (b))
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#endif
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#ifndef MAX
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#define MAX(a, b) ((a) > (b) ? (a) : (b))
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#endif
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#ifdef __cplusplus
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}
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#endif

‎include/esp-stub-lib/trax_mem.h‎

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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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#pragma once
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#include <stdint.h>
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#define ERI_DEBUG_OFFSET 0x100000
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#define ERI_TRAX_OFFSET (ERI_DEBUG_OFFSET + 0x0)
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#define ERI_TRAX_TRAXCTRL (ERI_TRAX_OFFSET + 0x4)
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#define ERI_TRAX_TRIGGERPC (ERI_TRAX_OFFSET + 0x14)
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#define ERI_TRAX_DELAYCNT (ERI_TRAX_OFFSET + 0x1C)
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#define TRAXCTRL_TRSTP (1 << 1) // Trace Stop. Make 1 to stop trace.
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#define TRAXCTRL_TMEN (1 << 7) // Trace Memory Enable. Always set.
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern void stub_target_trax_mem_enable(void);
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extern void stub_target_trax_select_mem_block(int block);
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static inline uint32_t eri_read(int addr)
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{
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uint32_t ret;
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asm volatile(
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"RER %0,%1"
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:"=r"(ret):"r"(addr)
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);
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return ret;
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}
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static inline void eri_write(int addr, uint32_t data)
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{
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asm volatile(
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"WER %0,%1"
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::"r"(data), "r"(addr)
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);
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}
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/*
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* Enable the TRAX memory. For ESP32 only.
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*/
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static inline void esp_stub_lib_trax_mem_enable(void)
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{
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stub_target_trax_mem_enable();
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}
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/*
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* Select the memory block (0 or 1) to use.
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*/
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static inline void esp_stub_lib_trax_select_mem_block(int block)
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{
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stub_target_trax_select_mem_block(block);
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}
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/*
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* Read a TRAX register using ERI.
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*/
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static inline uint32_t esp_stub_lib_trax_reg_read(int addr)
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{
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return eri_read(addr);
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}
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/*
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* Write a TRAX register using ERI.
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*/
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static inline void esp_stub_lib_trax_reg_write(int addr, uint32_t data)
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{
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eri_write(addr, data);
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}
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#ifdef __cplusplus
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}
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#endif

‎include/private/soc_utils.h‎

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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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#pragma once
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#define ETS_UNCACHED_ADDR(addr) (addr)
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#define ETS_CACHED_ADDR(addr) (addr)
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//write value to register
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#define REG_WRITE(_r, _v) do { \
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(*(volatile uint32_t *)(_r)) = (_v); \
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} while(0)
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//read value from register
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#define REG_READ(_r) ({ \
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(*(volatile uint32_t *)(_r)); \
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})
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//get bit or get bits from register
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#define REG_GET_BIT(_r, _b) ({ \
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(*(volatile uint32_t*)(_r) & (_b)); \
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})
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//set bit or set bits to register
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#define REG_SET_BIT(_r, _b) do { \
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*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) | (_b); \
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} while(0)
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//clear bit or clear bits of register
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#define REG_CLR_BIT(_r, _b) do { \
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*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) & (~(_b)); \
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} while(0)
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//set bits of register controlled by mask
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#define REG_SET_BITS(_r, _b, _m) do { \
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*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)); \
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} while(0)
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//get field from register, uses field _S & _V to determine mask
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#define REG_GET_FIELD(_r, _f) ({ \
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((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \
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})
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//set field of a register from variable, uses field _S & _V to determine mask
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#define REG_SET_FIELD(_r, _f, _v) do { \
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REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))); \
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} while(0)
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//get field value from a variable, used when _f is not left shifted by _f##_S
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#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
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//get field value from a variable, used when _f is left shifted by _f##_S
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#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
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//set field value to a variable, used when _f is not left shifted by _f##_S
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#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
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//set field value to a variable, used when _f is left shifted by _f##_S
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#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
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//generate a value from a field value, used when _f is not left shifted by _f##_S
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#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
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//generate a value from a field value, used when _f is left shifted by _f##_S
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#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
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//read value from register
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#define READ_PERI_REG(addr) ({ \
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(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \
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})
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//write value to register
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#define WRITE_PERI_REG(addr, val) do { \
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(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \
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} while(0)
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//clear bits of register controlled by mask
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#define CLEAR_PERI_REG_MASK(reg, mask) do { \
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WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \
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} while(0)
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//set bits of register controlled by mask
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#define SET_PERI_REG_MASK(reg, mask) do { \
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WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \
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} while(0)
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//get bits of register controlled by mask
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#define GET_PERI_REG_MASK(reg, mask) ({ \
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(READ_PERI_REG(reg) & (mask)); \
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})
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//get bits of register controlled by highest bit and lowest bit
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#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \
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((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \
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})
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//set bits of register controlled by mask and shift
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#define SET_PERI_REG_BITS(reg,bit_map,value,shift) do { \
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WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift)) ); \
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} while(0)
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//get field of register
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#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \
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((READ_PERI_REG(reg)>>(shift))&(mask)); \
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})

‎src/esp32/CMakeLists.txt‎

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set(srcs
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src/uart.c
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src/flash.c
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src/trax.c
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)
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add_library(${ESP_TARGET_LIB} STATIC ${srcs})

‎src/esp32/src/trax.c‎

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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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#include <stdint.h>
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#include <private/soc_utils.h>
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#include "reg_base.h"
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#define TRACEMEM_MUX_MODE_REG (DR_REG_DPORT_BASE + 0x070)
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#define TRACEMEM_ENA_REG (DR_REG_DPORT_BASE + 0x074)
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#define TRACEMEM_ENA_M (0x1)
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#define TRACEMEM_MUX_BLK0_ONLY 1
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#define TRACEMEM_MUX_BLK1_ONLY 2
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void stub_target_trax_mem_enable(void)
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{
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WRITE_PERI_REG(TRACEMEM_ENA_REG, TRACEMEM_ENA_M);
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}
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void stub_target_trax_select_mem_block(int block)
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{
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WRITE_PERI_REG(TRACEMEM_MUX_MODE_REG, block ? TRACEMEM_MUX_BLK0_ONLY : TRACEMEM_MUX_BLK1_ONLY);
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}

‎src/esp32s2/CMakeLists.txt‎

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set(srcs
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src/uart.c
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src/flash.c
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src/trax.c
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)
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add_library(${ESP_TARGET_LIB} STATIC ${srcs})

‎src/esp32s2/src/trax.c‎

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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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#include <stdint.h>
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#include <bit_utils.h>
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#include <private/soc_utils.h>
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#include "reg_base.h"
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#define PMS_OCCUPY_3_REG (DR_REG_SENSITIVE_BASE + 0x0E0)
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#define TRACEMEM_MUX_BLK0_NUM 19
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#define TRACEMEM_MUX_BLK1_NUM 20
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void stub_target_trax_mem_enable(void)
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{
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/* nothing to do for ESP32S2 */
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}
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void stub_target_trax_select_mem_block(int block)
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{
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WRITE_PERI_REG(PMS_OCCUPY_3_REG, block ? BIT(TRACEMEM_MUX_BLK0_NUM - 4) : BIT(TRACEMEM_MUX_BLK1_NUM - 4));
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}

‎src/esp32s3/CMakeLists.txt‎

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set(srcs
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src/uart.c
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src/flash.c
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src/trax.c
45
)
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add_library(${ESP_TARGET_LIB} STATIC ${srcs})

‎src/esp32s3/src/trax.c‎

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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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#include <stdint.h>
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#include <bit_utils.h>
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#include <private/soc_utils.h>
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#include "reg_base.h"
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#define SENSITIVE_INTERNAL_SRAM_USAGE_2_REG (DR_REG_SENSITIVE_BASE + 0x18)
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#define TRACEMEM_MUX_BLK0_NUM 22
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#define TRACEMEM_MUX_BLK1_NUM 26
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#define TRACEMEM_MUX_BLK_ALLOC(_n_) (((_n_) - 2UL) % 4UL)
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#define TRACEMEM_CORE0_MUX_BLK_BITS(_n_) (BIT(((_n_) - 2UL) / 4UL) | (TRACEMEM_MUX_BLK_ALLOC(_n_) << 14))
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#define TRACEMEM_CORE1_MUX_BLK_BITS(_n_) (BIT(7UL + ((_n_) - 2UL) / 4UL) | (TRACEMEM_MUX_BLK_ALLOC(_n_) << 16))
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void stub_target_trax_mem_enable(void)
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{
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/* nothing to do for ESP32S3 */
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}
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void stub_target_trax_select_mem_block(int block)
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{
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uint32_t block_bits = block ? TRACEMEM_CORE0_MUX_BLK_BITS(TRACEMEM_MUX_BLK0_NUM)
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: TRACEMEM_CORE0_MUX_BLK_BITS(TRACEMEM_MUX_BLK1_NUM);
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block_bits |= block ? TRACEMEM_CORE1_MUX_BLK_BITS(TRACEMEM_MUX_BLK0_NUM)
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: TRACEMEM_CORE1_MUX_BLK_BITS(TRACEMEM_MUX_BLK1_NUM);
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WRITE_PERI_REG(SENSITIVE_INTERNAL_SRAM_USAGE_2_REG, block_bits);
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}

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