Teach rustc about the Xtensa arch.

Author: MabezDev

compiler/rustc_llvm/build.rs

@@ -85,6 +85,7 @@ fn main() {
         "sparc",
         "nvptx",
         "hexagon",
+        "xtensa",
         "riscv",
     ];
 

compiler/rustc_llvm/llvm-wrapper/PassWrapper.cpp

@@ -231,6 +231,12 @@ void LLVMRustAddLastExtensionPasses(
 #define SUBTARGET_SPARC
 #endif
 
+#ifdef LLVM_COMPONENT_XTENSA
+#define SUBTARGET_XTENSA SUBTARGET(XTENSA)
+#else
+#define SUBTARGET_XTENSA
+#endif
+
 #ifdef LLVM_COMPONENT_HEXAGON
 #define SUBTARGET_HEXAGON SUBTARGET(Hexagon)
 #else
@@ -248,6 +254,7 @@ void LLVMRustAddLastExtensionPasses(
   SUBTARGET_MSP430                                                             \
   SUBTARGET_SPARC                                                              \
   SUBTARGET_HEXAGON                                                            \
+  SUBTARGET_XTENSA                                                             \
   SUBTARGET_RISCV                                                              \
 
 #define SUBTARGET(x)                                                           \

compiler/rustc_llvm/src/lib.rs

@@ -162,6 +162,14 @@ pub fn initialize_available_targets() {
         LLVMInitializeHexagonAsmPrinter,
         LLVMInitializeHexagonAsmParser
     );
+    init_target!(
+        llvm_component = "xtensa",
+        LLVMInitializeXtensaTargetInfo,
+        LLVMInitializeXtensaTarget,
+        LLVMInitializeXtensaTargetMC,
+        LLVMInitializeXtensaAsmPrinter,
+        LLVMInitializeXtensaAsmParser
+    );
     init_target!(
         llvm_component = "webassembly",
         LLVMInitializeWebAssemblyTargetInfo,