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use std:: { io, os:: fd:: AsRawFd } ;
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use std:: { thread:: sleep, time:: Duration } ;
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+ use bitflags:: bitflags;
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#[ cfg( unix) ]
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use libc:: ioctl;
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use log:: debug;
@@ -208,7 +209,7 @@ trait RtcWdtReset {
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impl RtcWdtReset for crate :: targets:: esp32c3:: Esp32c3 {
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fn wdt_wprotect ( & self ) -> u32 {
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- 0x6000_8000 + 0x00B0
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+ 0x6000_8000 + 0x00A0
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}
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fn wdt_wkey ( & self ) -> u32 {
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0x50D8_3AA1
@@ -223,16 +224,16 @@ impl RtcWdtReset for crate::targets::esp32c3::Esp32c3 {
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impl RtcWdtReset for crate :: targets:: esp32s2:: Esp32s2 {
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fn wdt_wprotect ( & self ) -> u32 {
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- 0x6000_F000 + 0x00B0
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+ 0x3F40_8000 + 0x00AC
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}
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fn wdt_wkey ( & self ) -> u32 {
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- 0xA123_B456
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+ 0x50D8_3AA1
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}
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fn wdt_config0 ( & self ) -> u32 {
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- 0x6000_F000 + 0x0090
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+ 0x3F40_8000 + 0x0094
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}
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fn wdt_config1 ( & self ) -> u32 {
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- 0x6000_F000 + 0x0094
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+ 0x3F40_8000 + 0x0098
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}
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}
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@@ -241,13 +242,13 @@ impl RtcWdtReset for crate::targets::esp32s3::Esp32s3 {
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0x6000_E000 + 0x00B0
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}
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fn wdt_wkey ( & self ) -> u32 {
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- 0xB987_C654
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+ 0x50D8_3AA1
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}
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fn wdt_config0 ( & self ) -> u32 {
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- 0x6000_E000 + 0x0090
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+ 0x6000_E000 + 0x0098
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}
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fn wdt_config1 ( & self ) -> u32 {
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- 0x6000_E000 + 0x0094
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+ 0x6000_E000 + 0x009C
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}
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}
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@@ -346,6 +347,15 @@ pub fn soft_reset(
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Ok ( ( ) )
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}
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+ bitflags ! {
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+ struct WdtConfig0Flags : u32 {
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+ const EN = 1 << 31 ;
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+ const STAGE0 = 5 << 28 ; // 5 (binary: 101) in bits 28-30
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+ const CHIP_RESET_EN = 1 << 8 ; // 8th bit
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+ const CHIP_RESET_WIDTH = 1 << 2 ; // 1st bit
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+ }
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+ }
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+
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/// Perform Watchdog reset
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pub fn wdt_reset ( chip : Chip , connection : & mut Connection ) -> Result < ( ) , Error > {
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debug ! ( "Resetting with RTC WDT" ) ;
@@ -358,14 +368,19 @@ pub fn wdt_reset(chip: Chip, connection: &mut Connection) -> Result<(), Error> {
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} ;
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connection. write_reg ( chip. wdt_wprotect ( ) , chip. wdt_wkey ( ) , None ) ?;
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- connection. write_reg ( chip. wdt_config1 ( ) , 5000 , None ) ?;
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+ connection. write_reg ( chip. wdt_config1 ( ) , 2000 , None ) ?;
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connection. write_reg (
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chip. wdt_config0 ( ) ,
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- ( 1 << 31 ) | ( 5 << 28 ) | ( 1 << 8 ) | 2 ,
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+ ( WdtConfig0Flags :: EN . bits ( ) ) // enable RTC watchdog
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+ | ( WdtConfig0Flags :: STAGE0 . bits ( ) ) // enable at the interrupt/system and RTC stage
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+ | ( WdtConfig0Flags :: CHIP_RESET_EN . bits ( ) ) // enable chip reset
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+ | WdtConfig0Flags :: CHIP_RESET_WIDTH . bits ( ) , // set chip reset width
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None ,
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) ?;
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connection. write_reg ( chip. wdt_wprotect ( ) , 0 , None ) ?;
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+ sleep ( Duration :: from_millis ( 50 ) ) ;
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+
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Ok ( ( ) )
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}
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