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author
Blaise Tine
committed
cocogfx fixes and refactoring
1 parent a671e1a commit b995843

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44 files changed

+339
-3921
lines changed

‎Makefile

+2-1
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,11 @@
11
all:
2+
$(MAKE) -C third_party
23
$(MAKE) -C hw
34
$(MAKE) -C sim
45
$(MAKE) -C driver
56
$(MAKE) -C runtime
67
$(MAKE) -C tests
7-
8+
89
clean:
910
$(MAKE) -C hw clean
1011
$(MAKE) -C sim clean

‎hw/rtl/tex_unit/VX_tex_define.vh

+6-5
Original file line numberDiff line numberDiff line change
@@ -24,11 +24,12 @@
2424
`define TEX_BLEND_FRAC 8
2525
`define TEX_BLEND_ONE (2 ** `TEX_BLEND_FRAC)
2626

27-
`define TEX_FORMAT_R8G8B8A8 `TEX_FORMAT_BITS'(0)
27+
`define TEX_FORMAT_A8R8G8B8 `TEX_FORMAT_BITS'(0)
2828
`define TEX_FORMAT_R5G6B5 `TEX_FORMAT_BITS'(1)
29-
`define TEX_FORMAT_R4G4B4A4 `TEX_FORMAT_BITS'(2)
30-
`define TEX_FORMAT_L8A8 `TEX_FORMAT_BITS'(3)
31-
`define TEX_FORMAT_L8 `TEX_FORMAT_BITS'(4)
32-
`define TEX_FORMAT_A8 `TEX_FORMAT_BITS'(5)
29+
`define TEX_FORMAT_A1R5G5B5 `TEX_FORMAT_BITS'(2)
30+
`define TEX_FORMAT_A4R4G4B4 `TEX_FORMAT_BITS'(3)
31+
`define TEX_FORMAT_A8L8 `TEX_FORMAT_BITS'(4)
32+
`define TEX_FORMAT_L8 `TEX_FORMAT_BITS'(5)
33+
`define TEX_FORMAT_A8 `TEX_FORMAT_BITS'(6)
3334

3435
`endif

‎hw/rtl/tex_unit/VX_tex_format.sv

+16-10
Original file line numberDiff line numberDiff line change
@@ -13,25 +13,31 @@ module VX_tex_format #(
1313

1414
always @(*) begin
1515
case (format)
16-
`TEX_FORMAT_R8G8B8A8: begin
16+
`TEX_FORMAT_A8R8G8B8: begin
1717
texel_out_r[07:00] = texel_in[7:0];
1818
texel_out_r[15:08] = texel_in[15:8];
1919
texel_out_r[23:16] = texel_in[23:16];
2020
texel_out_r[31:24] = texel_in[31:24];
2121
end
2222
`TEX_FORMAT_R5G6B5: begin
23-
texel_out_r[07:00] = {texel_in[15:11], texel_in[15:13]};
23+
texel_out_r[07:00] = {texel_in[4:0], texel_in[4:2]};
2424
texel_out_r[15:08] = {texel_in[10:5], texel_in[10:9]};
25-
texel_out_r[23:16] = {texel_in[4:0], texel_in[4:2]};
25+
texel_out_r[23:16] = {texel_in[15:11], texel_in[15:13]};
2626
texel_out_r[31:24] = 8'hff;
2727
end
28-
`TEX_FORMAT_R4G4B4A4: begin
29-
texel_out_r[07:00] = {texel_in[11:8], texel_in[15:12]};
28+
`TEX_FORMAT_A1R5G5B5: begin
29+
texel_out_r[07:00] = {texel_in[4:0], texel_in[4:2]};
30+
texel_out_r[15:08] = {texel_in[9:5], texel_in[9:7]};
31+
texel_out_r[23:16] = {texel_in[14:10], texel_in[14:12]};
32+
texel_out_r[31:24] = {8{texel_in[15]}};
33+
end
34+
`TEX_FORMAT_A4R4G4B4: begin
35+
texel_out_r[07:00] = {2{texel_in[3:0]}};
3036
texel_out_r[15:08] = {2{texel_in[7:4]}};
31-
texel_out_r[23:16] = {2{texel_in[3:0]}};
37+
texel_out_r[23:16] = {2{texel_in[11:8]}};
3238
texel_out_r[31:24] = {2{texel_in[15:12]}};
3339
end
34-
`TEX_FORMAT_L8A8: begin
40+
`TEX_FORMAT_A8L8: begin
3541
texel_out_r[07:00] = texel_in[7:0];
3642
texel_out_r[15:08] = texel_in[7:0];
3743
texel_out_r[23:16] = texel_in[7:0];
@@ -45,9 +51,9 @@ module VX_tex_format #(
4551
end
4652
//`TEX_FORMAT_A8
4753
default: begin
48-
texel_out_r[07:00] = 0;
49-
texel_out_r[15:08] = 0;
50-
texel_out_r[23:16] = 0;
54+
texel_out_r[07:00] = 8'hff;
55+
texel_out_r[15:08] = 8'hff;
56+
texel_out_r[23:16] = 8'hff;
5157
texel_out_r[31:24] = texel_in[7:0];
5258
end
5359
endcase

‎hw/rtl/tex_unit/VX_tex_stride.sv

+8-7
Original file line numberDiff line numberDiff line change
@@ -12,13 +12,14 @@ module VX_tex_stride #(
1212

1313
always @(*) begin
1414
case (format)
15-
`TEX_FORMAT_A8: log_stride_r = 0;
16-
`TEX_FORMAT_L8: log_stride_r = 0;
17-
`TEX_FORMAT_L8A8: log_stride_r = 1;
18-
`TEX_FORMAT_R5G6B5: log_stride_r = 1;
19-
`TEX_FORMAT_R4G4B4A4: log_stride_r = 1;
20-
//`TEX_FORMAT_R8G8B8A8
21-
default: log_stride_r = 2;
15+
`TEX_FORMAT_A8R8G8B8: log_stride_r = 2;
16+
`TEX_FORMAT_R5G6B5,
17+
`TEX_FORMAT_A1R5G5B5,
18+
`TEX_FORMAT_A4R4G4B4,
19+
`TEX_FORMAT_A8L8: log_stride_r = 1;
20+
// `TEX_FORMAT_L8:
21+
// `TEX_FORMAT_A8:
22+
default: log_stride_r = 0;
2223
endcase
2324
end
2425

‎hw/syn/quartus/core/Makefile

+2-1
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@ PROJECT = Core
22
TOP_LEVEL_ENTITY = VX_core
33
SRC_FILE = VX_core.v
44
RTL_DIR = ../../../../rtl
5+
THIRD_PARTY_DIR = ../../../../../third_party
56

67
FAMILY = "Arria 10"
78
DEVICE = 10AX115N3F40E2SG
@@ -11,7 +12,7 @@ FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
1112
#DEVICE = 1SX280HN2F43E2VG
1213
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
1314

14-
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
15+
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
1516
TEX_INCLUDE = $(RTL_DIR)/tex_unit
1617
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(FPU_INCLUDE);$(TEX_INCLUDE)
1718

‎hw/syn/quartus/fpu_core/Makefile

+2-1
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@ PROJECT = VX_fpu_fpga
22
TOP_LEVEL_ENTITY = VX_fpu_fpga
33
SRC_FILE = VX_fpu_fpga.v
44
RTL_DIR = ../../../../rtl
5+
THIRD_PARTY_DIR = ../../../../../third_party
56

67
FAMILY = "Arria 10"
78
DEVICE = 10AX115N3F40E2SG
@@ -11,7 +12,7 @@ FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
1112
#DEVICE = 1SX280HN2F43E2VG
1213
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
1314

14-
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
15+
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
1516
RTL_INCLUDE = $(FPU_INCLUDE);$(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces
1617
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
1718

‎hw/syn/quartus/pipeline/Makefile

+2-1
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@ PROJECT = VX_pipeline
22
TOP_LEVEL_ENTITY = VX_pipeline
33
SRC_FILE = VX_pipeline.v
44
RTL_DIR = ../../../../rtl
5+
THIRD_PARTY_DIR = ../../../../../third_party
56

67
FAMILY = "Arria 10"
78
DEVICE = 10AX115N3F40E2SG
@@ -11,7 +12,7 @@ FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
1112
#DEVICE = 1SX280HN2F43E2VG
1213
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
1314

14-
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
15+
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
1516
TEX_INCLUDE = $(RTL_DIR)/tex_unit
1617
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(FPU_INCLUDE);$(TEX_INCLUDE)
1718

‎hw/syn/quartus/top1/Makefile

+2-1
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@ PROJECT = vortex_afu
22
TOP_LEVEL_ENTITY = vortex_afu
33
SRC_FILE = vortex_afu.sv
44
RTL_DIR = ../../../../rtl
5+
THIRD_PARTY_DIR = ../../../../../third_party
56

67
FAMILY = "Arria 10"
78
DEVICE = 10AX115N3F40E2SG
@@ -11,7 +12,7 @@ FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
1112
#DEVICE = 1SX280HN2F43E2VG
1213
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
1314

14-
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
15+
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
1516
TEX_INCLUDE = $(RTL_DIR)/tex_unit
1617
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE)
1718

‎hw/syn/quartus/top16/Makefile

+2-1
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@ PROJECT = vortex_afu
22
TOP_LEVEL_ENTITY = vortex_afu
33
SRC_FILE = vortex_afu.sv
44
RTL_DIR = ../../../../rtl
5+
THIRD_PARTY_DIR = ../../../../../third_party
56

67
FAMILY = "Arria 10"
78
DEVICE = 10AX115N3F40E2SG
@@ -11,7 +12,7 @@ FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
1112
#DEVICE = 1SX280HN2F43E2VG
1213
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
1314

14-
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
15+
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
1516
TEX_INCLUDE = $(RTL_DIR)/tex_unit
1617
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE)
1718

‎hw/syn/quartus/top2/Makefile

+2-1
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@ PROJECT = vortex_afu
22
TOP_LEVEL_ENTITY = vortex_afu
33
SRC_FILE = vortex_afu.sv
44
RTL_DIR = ../../../../rtl
5+
THIRD_PARTY_DIR = ../../../../../third_party
56

67
FAMILY = "Arria 10"
78
DEVICE = 10AX115N3F40E2SG
@@ -11,7 +12,7 @@ FPU_CORE_PATH=$(RTL_DIR)/fp_cores/altera/arria10
1112
#DEVICE = 1SX280HN2F43E2VG
1213
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
1314

14-
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
15+
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
1516
TEX_INCLUDE = $(RTL_DIR)/tex_unit
1617
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE)
1718

‎hw/syn/quartus/top32/Makefile

+2-1
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@ PROJECT = vortex_afu
22
TOP_LEVEL_ENTITY = vortex_afu
33
SRC_FILE = vortex_afu.sv
44
RTL_DIR = ../../../../rtl
5+
THIRD_PARTY_DIR = ../../../../../third_party
56

67
FAMILY = "Arria 10"
78
DEVICE = 10AX115N3F40E2SG
@@ -11,7 +12,7 @@ FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
1112
#DEVICE = 1SX280HN2F43E2VG
1213
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
1314

14-
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
15+
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
1516
TEX_INCLUDE = $(RTL_DIR)/tex_unit
1617
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE)
1718

‎hw/syn/quartus/top4/Makefile

+2-1
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@ PROJECT = vortex_afu
22
TOP_LEVEL_ENTITY = vortex_afu
33
SRC_FILE = vortex_afu.sv
44
RTL_DIR = ../../../../rtl
5+
THIRD_PARTY_DIR = ../../../../../third_party
56

67
FAMILY = "Arria 10"
78
DEVICE = 10AX115N3F40E2SG
@@ -11,7 +12,7 @@ FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
1112
#DEVICE = 1SX280HN2F43E2VG
1213
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
1314

14-
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
15+
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
1516
TEX_INCLUDE = $(RTL_DIR)/tex_unit
1617
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE)
1718

‎hw/syn/quartus/top64/Makefile

+3-2
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,8 @@
11
PROJECT = vortex_afu
22
TOP_LEVEL_ENTITY = vortex_afu
33
SRC_FILE = vortex_afu.sv
4-
RTL_DIR=../../../../rtl
4+
RTL_DIR = ../../../../rtl
5+
THIRD_PARTY_DIR = ../../../../../third_party
56

67
#FAMILY = "Arria 10"
78
#DEVICE = 10AX115N3F40E2SG
@@ -11,7 +12,7 @@ FAMILY = "Stratix 10"
1112
DEVICE = 1SX280HN2F43E2VG
1213
FPU_CORE_PATH=$(RTL_DIR)/fp_cores/altera/stratix10
1314

14-
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
15+
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
1516
TEX_INCLUDE = $(RTL_DIR)/tex_unit
1617
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE)
1718

‎hw/syn/quartus/top8/Makefile

+2-1
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@ PROJECT = vortex_afu
22
TOP_LEVEL_ENTITY = vortex_afu
33
SRC_FILE = vortex_afu.sv
44
RTL_DIR = ../../../../rtl
5+
THIRD_PARTY_DIR = ../../../../../third_party
56

67
FAMILY = "Arria 10"
78
DEVICE = 10AX115N3F40E2SG
@@ -11,7 +12,7 @@ FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
1112
#DEVICE = 1SX280HN2F43E2VG
1213
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
1314

14-
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
15+
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
1516
TEX_INCLUDE = $(RTL_DIR)/tex_unit
1617
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE)
1718

‎hw/syn/quartus/unittest/Makefile

+2-1
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@ PROJECT = Unittest
22
TOP_LEVEL_ENTITY = VX_core_req_bank_sel
33
SRC_FILE = VX_core_req_bank_sel.v
44
RTL_DIR = ../../../../rtl
5+
THIRD_PARTY_DIR = ../../../../../third_party
56

67
FAMILY = "Arria 10"
78
DEVICE = 10AX115N3F40E2SG
@@ -11,7 +12,7 @@ FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
1112
#DEVICE = 1SX280HN2F43E2VG
1213
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
1314

14-
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
15+
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
1516
TEX_INCLUDE = $(RTL_DIR)/tex_unit
1617
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(FPU_INCLUDE);$(TEX_INCLUDE)
1718

‎hw/syn/quartus/vortex/Makefile

+2-1
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@ PROJECT = Vortex
22
TOP_LEVEL_ENTITY = Vortex
33
SRC_FILE = Vortex.sv
44
RTL_DIR = ../../../../rtl
5+
THIRD_PARTY_DIR = ../../../../../third_party
56

67
FAMILY = "Arria 10"
78
DEVICE = 10AX115N3F40E2SG
@@ -11,7 +12,7 @@ FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
1112
#DEVICE = 1SX280HN2F43E2VG
1213
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
1314

14-
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
15+
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
1516
TEX_INCLUDE = $(RTL_DIR)/tex_unit
1617
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(FPU_INCLUDE);$(TEX_INCLUDE)
1718

‎runtime/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ $(PROJECT).dump: $(PROJECT).a
2626
$(CC) $(CFLAGS) -c $< -o $@
2727

2828
$(PROJECT).a: $(OBJS)
29-
$(AR) rcs $(PROJECT).a $^
29+
$(AR) rcs $@ $^
3030

3131
.depend: $(SRCS)
3232
$(CC) $(CFLAGS) -MM $^ > .depend;

‎sim/Makefile

-2
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,9 @@
11
all:
2-
$(MAKE) -C common
32
$(MAKE) -C simX
43
$(MAKE) -C rtlsim
54
$(MAKE) -C vlsim
65

76
clean:
8-
$(MAKE) -C common clean
97
$(MAKE) -C simX clean
108
$(MAKE) -C rtlsim clean
119
$(MAKE) -C vlsim clean

‎sim/common/Makefile

-5
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