Problem with delay chip.

[RufiS]

After designing a jk flip flop counter with set and reset pins on the jk flipflops(needed for my program counter) out of srnor, and, not, gates from your plugin, I noticed I needed a propagation delay between my Q and R pin and Q' and S pin. Used the delay chip, set to 20hz. IT WORKED! For a little bit, approximately 20 - 120, 10hz, 0 pulse width clock cycles. At which point, the delay chips would read input=0 or 1, and output=1 or 0, respectivly. they essentially "jam" up, and must be deactivated, then reactivated again. disconnecting the delay chip from all surrounding chips does not effect the "jammed" i/o state of the delay chip. delays of 10hz, 5hz were also tried, accompanied by 5hz and 2.5hz clock cycles, both default and 0 pulse widths were tested with all configurations

[eisental]

Why do you need a propagation delay for? It's usually not necessary.
Upload a WorldEdit schematic of the problematic circuit and I'll try to look at it.

[RufiS]

https://www.dropbox.com/s/92m4iyxgwmjreqo/JkSyncroCounterTest.schematic?m

I need propagation delay between the Q and K and Q' and J, without some sort of delay, the instant propagation your chips offer seems to be preventing the JK from functioning. Add a 20hz delay, and it toggles as expected. Try testing by replace the delays with repeaters. The delay chips work fine for the job, until they "jam" or you could say "lock" up.

[RufiS]

https://www.dropbox.com/s/x1a8u2yy9ki70jd/FlipflopBasedSyncCounter.schematic

Here is a design using the FLIPFLOP chip combined with AND and DELAY. using REPEATERs in the place of the DELAY causes the counter to count improperly for the first two clock cycles, after which it will count down instead of up, in the sequence -2, +1, -2, +1, -2, +1. The DELAYs are getting jammed as well in this design. Video in next comment.

[RufiS]

https://www.youtube.com/watch?v=p_g-THG8ck0&feature=youtube_gdata_player

After setting all outputs to 1, all DELAY chips should have power running through them. On the next clock cycle, all outputs should toggle to off. As you will see, DELAY chips will have non changing outputs, and opposite i/o.