Core1 / CYW43 not usable when powered via VSYS pin? #2869
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I'd recommend posting this on the RPI forums directly because it's not really core related if the CYW43 init routine itself if wonky. That said, I don't understand exactly the symptom you're describing. Or at least, it doesn't seem possible to me. Core1 is started from arduino-pico/cores/rp2040/main.cpp Line 180 in 49397a7 If the CYW43 init hangs (as part of the variant initialization) arduino-pico/cores/rp2040/main.cpp Line 133 in 49397a7 Then the app won't ever progress past line 133 there to start either core0 or core1. WiFi radio processing is all done on the external chip, and all LWIP/Ethernet polling and injection are done on core0 under IRQ control. So If the CYW43 chip goes out to lunch, core0 will freeze and not core1... |
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Hi,
I came across the issue that when powering the RP Pico (2) W from a LiPo battery via the VSYS pin,
Core1 does not run and the wireless functions cannot be used. It seems that the initialization code of the CYW43 chip (which is partly proprietary) checks for the presence of VBUS using WL_GPIO2 and hangs (!) if VBUS is not present. Even a simple blinky-code in setup1() does not run, although core0 runs normally...
When powering the system via a battery (using VSYS as recommended in the datasheet), VBUS can of course not be present because of the protection diode D1. Does this mean that BT (and effectively, Core1) cannot be used in a battery-powered configuration?
To verify my assumption, I directly connected WL_GPIO2 (at the point of the voltage divider R1/R10) to 3V3(out).
With this HW-patch, Core1 / BT starts normally, also when the system is powered via battery / VSYS.
Is there a function (or SW patch) to disable the check for VBUS in the initialization routine of the CYW chip?
Or another strategy to make BT and core 1 work when powered via the VSYS pin?
thanks!
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