Skip to content

Commit 3f322a2

Browse files
committed
update home
1 parent 5772b47 commit 3f322a2

File tree

1 file changed

+6
-8
lines changed

1 file changed

+6
-8
lines changed

index.md

+6-8
Original file line numberDiff line numberDiff line change
@@ -14,23 +14,21 @@ This is where I keep my notes, my thoughts, my experiences or anything interesti
1414

1515
---
1616

17-
## Getting started
18-
19-
### Who I am
17+
## Who am I
2018
Well, you know I'm a design verification engineer and I've been in this industry for quite a while. It's long enough to make me feel that I should share what I know, but also not enough to say that everything on this site are 100 percent correctly. I work with Systemverilog, uvm everyday and these are what I know the most. However, now and then, I also find myself struggling with formal verification, design, STA timing, =)) and the list goes on with synthesis, ECO logic, and also scripting. Talking about scripting, I have been using csh and perl for a long time before switching to zsh/bash and python recently. And I love vim, gosh, it is the best.
2119

2220

23-
### What you'll find here
21+
## What you'll find here
2422

2523

26-
#### 1. You find my notes :)
27-
##### The first reason makes me
24+
### 1. You find my notes :)
25+
#### The first reason makes me
2826

2927

30-
#### 2.You find my thoughts
28+
### 2.You find my thoughts
3129

3230

33-
#### 3.And you find my random
31+
### 3.And you find my random
3432

3533
---
3634

0 commit comments

Comments
 (0)