Add SCB_CCSELR register

Signed-off-by: Jean Pierre Dudey <[email protected]>

Author: jeandudey

src/map/reg/mod.rs

@@ -40,7 +40,7 @@ reg::tokens! {
     /// System control block.
     pub mod SCB {
         CPUID; ICSR; VTOR; AIRCR; SCR; CCR; SHPR1; SHPR2; SHPR3; SHCSR; MMFSR;
-        BFSR; UFSR; HFSR; DFSR; MMFAR; BFAR; AFSR; DEMCR;
+        BFSR; UFSR; HFSR; DFSR; MMFAR; BFAR; AFSR; DEMCR; CSSELR;
     }
 
     /// SysTick timer.

src/map/reg/scb.rs

@@ -464,3 +464,20 @@ reg! {
         };
     };
 }
+
+reg! {
+    /// Cache Size Selection Register
+    pub SCB CSSELR => {
+        address => 0xE000_ED84;
+        size => 0x20;
+        reset => 0x0000_0000;
+        traits => { RReg WReg };
+        fields => {
+            /// Cache level of required cache. Permitted values are from `0b000`,
+            /// indicating Level 1 cache, to `0b110` indicating Level 7 cache.
+            Level => { offset => 1; width => 3; traits => { RRRegField } };
+            /// Instruction not data bit.
+            InD => { offset => 0; width => 1; traits => { RRRegField WWRegField } };
+        };
+    };
+}