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[llvm-mca][scheduler-stats] Print issued micro opcodes per cycle. NFCI
It makes more sense to print out the number of micro opcodes that are issued every cycle rather than the number of instructions issued per cycle. This behavior is also consistent with the dispatch-stats: numbers from the two views can now be easily compared. llvm-svn: 357919
1 parent 5058ca6 commit f6a60f1

13 files changed

+44
-46
lines changed

‎llvm/docs/CommandGuide/llvm-mca.rst

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -498,7 +498,7 @@ sections.
498498
2, 314 (51.5%)
499499
500500
501-
Schedulers - number of cycles where we saw N instructions issued:
501+
Schedulers - number of cycles where we saw N micro opcodes issued:
502502
[# issued], [# cycles]
503503
0, 7 (1.1%)
504504
1, 306 (50.2%)
@@ -552,9 +552,9 @@ dispatch statistics are displayed by either using the command option
552552
``-all-stats`` or ``-dispatch-stats``.
553553

554554
The next table, *Schedulers*, presents a histogram displaying a count,
555-
representing the number of instructions issued on some number of cycles. In
556-
this case, of the 610 simulated cycles, single instructions were issued 306
557-
times (50.2%) and there were 7 cycles where no instructions were issued.
555+
representing the number of micro opcodes issued on some number of cycles. In
556+
this case, of the 610 simulated cycles, single opcodes were issued 306 times
557+
(50.2%) and there were 7 cycles where no opcodes were issued.
558558

559559
The *Scheduler's queue usage* table shows that the average and maximum number of
560560
buffer entries (i.e., scheduler queue entries) used at runtime. Resource JFPU01

‎llvm/test/tools/llvm-mca/AArch64/Exynos/scheduler-queue-usage.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@
2525
# M4-NEXT: IPC: 0.50
2626
# M4-NEXT: Block RThroughput: 0.2
2727

28-
# ALL: Schedulers - number of cycles where we saw N instructions issued:
28+
# ALL: Schedulers - number of cycles where we saw N micro opcodes issued:
2929
# ALL-NEXT: [# issued], [# cycles]
3030
# ALL-NEXT: 0, 1 (50.0%)
3131
# ALL-NEXT: 1, 1 (50.0%)

‎llvm/test/tools/llvm-mca/X86/BdVer2/load-throughput.s

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -90,7 +90,7 @@ vmovaps (%rbx), %ymm3
9090
# CHECK-NEXT: 2, 172 (83.1%)
9191
# CHECK-NEXT: 4, 14 (6.8%)
9292

93-
# CHECK: Schedulers - number of cycles where we saw N instructions issued:
93+
# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
9494
# CHECK-NEXT: [# issued], [# cycles]
9595
# CHECK-NEXT: 0, 7 (3.4%)
9696
# CHECK-NEXT: 2, 200 (96.6%)
@@ -203,7 +203,7 @@ vmovaps (%rbx), %ymm3
203203
# CHECK-NEXT: 2, 172 (83.1%)
204204
# CHECK-NEXT: 4, 14 (6.8%)
205205

206-
# CHECK: Schedulers - number of cycles where we saw N instructions issued:
206+
# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
207207
# CHECK-NEXT: [# issued], [# cycles]
208208
# CHECK-NEXT: 0, 7 (3.4%)
209209
# CHECK-NEXT: 2, 200 (96.6%)
@@ -316,7 +316,7 @@ vmovaps (%rbx), %ymm3
316316
# CHECK-NEXT: 2, 172 (83.1%)
317317
# CHECK-NEXT: 4, 14 (6.8%)
318318

319-
# CHECK: Schedulers - number of cycles where we saw N instructions issued:
319+
# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
320320
# CHECK-NEXT: [# issued], [# cycles]
321321
# CHECK-NEXT: 0, 7 (3.4%)
322322
# CHECK-NEXT: 2, 200 (96.6%)
@@ -429,7 +429,7 @@ vmovaps (%rbx), %ymm3
429429
# CHECK-NEXT: 2, 172 (83.1%)
430430
# CHECK-NEXT: 4, 14 (6.8%)
431431

432-
# CHECK: Schedulers - number of cycles where we saw N instructions issued:
432+
# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
433433
# CHECK-NEXT: [# issued], [# cycles]
434434
# CHECK-NEXT: 0, 7 (3.4%)
435435
# CHECK-NEXT: 2, 200 (96.6%)
@@ -542,7 +542,7 @@ vmovaps (%rbx), %ymm3
542542
# CHECK-NEXT: 2, 172 (83.1%)
543543
# CHECK-NEXT: 4, 14 (6.8%)
544544

545-
# CHECK: Schedulers - number of cycles where we saw N instructions issued:
545+
# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
546546
# CHECK-NEXT: [# issued], [# cycles]
547547
# CHECK-NEXT: 0, 7 (3.4%)
548548
# CHECK-NEXT: 2, 200 (96.6%)
@@ -655,7 +655,7 @@ vmovaps (%rbx), %ymm3
655655
# CHECK-NEXT: 2, 172 (83.1%)
656656
# CHECK-NEXT: 4, 14 (6.8%)
657657

658-
# CHECK: Schedulers - number of cycles where we saw N instructions issued:
658+
# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
659659
# CHECK-NEXT: [# issued], [# cycles]
660660
# CHECK-NEXT: 0, 7 (3.4%)
661661
# CHECK-NEXT: 2, 200 (96.6%)
@@ -767,10 +767,10 @@ vmovaps (%rbx), %ymm3
767767
# CHECK-NEXT: 0, 7 (3.4%)
768768
# CHECK-NEXT: 4, 200 (96.6%)
769769

770-
# CHECK: Schedulers - number of cycles where we saw N instructions issued:
770+
# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
771771
# CHECK-NEXT: [# issued], [# cycles]
772772
# CHECK-NEXT: 0, 7 (3.4%)
773-
# CHECK-NEXT: 2, 200 (96.6%)
773+
# CHECK-NEXT: 4, 200 (96.6%)
774774

775775
# CHECK: Scheduler's queue usage:
776776
# CHECK-NEXT: [1] Resource name.

‎llvm/test/tools/llvm-mca/X86/BdVer2/scheduler-queue-usage.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ add %rsi, %rsi
2626
# CHECK-NEXT: 1 10 1.00 * vmulps (%rsi), %xmm0, %xmm0
2727
# CHECK-NEXT: 1 1 0.50 addq %rsi, %rsi
2828

29-
# CHECK: Schedulers - number of cycles where we saw N instructions issued:
29+
# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
3030
# CHECK-NEXT: [# issued], [# cycles]
3131
# CHECK-NEXT: 0, 12 (92.3%)
3232
# CHECK-NEXT: 2, 1 (7.7%)

‎llvm/test/tools/llvm-mca/X86/BdVer2/store-throughput.s

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -91,7 +91,7 @@ vmovaps %ymm3, (%rbx)
9191
# CHECK-NEXT: 2, 1 (0.2%)
9292
# CHECK-NEXT: 4, 7 (1.7%)
9393

94-
# CHECK: Schedulers - number of cycles where we saw N instructions issued:
94+
# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
9595
# CHECK-NEXT: [# issued], [# cycles]
9696
# CHECK-NEXT: 0, 3 (0.7%)
9797
# CHECK-NEXT: 1, 400 (99.3%)
@@ -205,7 +205,7 @@ vmovaps %ymm3, (%rbx)
205205
# CHECK-NEXT: 2, 1 (0.2%)
206206
# CHECK-NEXT: 4, 7 (1.7%)
207207

208-
# CHECK: Schedulers - number of cycles where we saw N instructions issued:
208+
# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
209209
# CHECK-NEXT: [# issued], [# cycles]
210210
# CHECK-NEXT: 0, 3 (0.7%)
211211
# CHECK-NEXT: 1, 400 (99.3%)
@@ -319,7 +319,7 @@ vmovaps %ymm3, (%rbx)
319319
# CHECK-NEXT: 2, 1 (0.2%)
320320
# CHECK-NEXT: 4, 7 (1.7%)
321321

322-
# CHECK: Schedulers - number of cycles where we saw N instructions issued:
322+
# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
323323
# CHECK-NEXT: [# issued], [# cycles]
324324
# CHECK-NEXT: 0, 3 (0.7%)
325325
# CHECK-NEXT: 1, 400 (99.3%)
@@ -433,7 +433,7 @@ vmovaps %ymm3, (%rbx)
433433
# CHECK-NEXT: 2, 1 (0.2%)
434434
# CHECK-NEXT: 4, 7 (1.7%)
435435

436-
# CHECK: Schedulers - number of cycles where we saw N instructions issued:
436+
# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
437437
# CHECK-NEXT: [# issued], [# cycles]
438438
# CHECK-NEXT: 0, 3 (0.7%)
439439
# CHECK-NEXT: 1, 400 (99.3%)
@@ -547,7 +547,7 @@ vmovaps %ymm3, (%rbx)
547547
# CHECK-NEXT: 2, 1 (0.1%)
548548
# CHECK-NEXT: 4, 6 (0.7%)
549549

550-
# CHECK: Schedulers - number of cycles where we saw N instructions issued:
550+
# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
551551
# CHECK-NEXT: [# issued], [# cycles]
552552
# CHECK-NEXT: 0, 403 (50.2%)
553553
# CHECK-NEXT: 1, 400 (49.8%)
@@ -662,7 +662,7 @@ vmovaps %ymm3, (%rbx)
662662
# CHECK-NEXT: 2, 1 (0.2%)
663663
# CHECK-NEXT: 4, 7 (1.7%)
664664

665-
# CHECK: Schedulers - number of cycles where we saw N instructions issued:
665+
# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
666666
# CHECK-NEXT: [# issued], [# cycles]
667667
# CHECK-NEXT: 0, 3 (0.7%)
668668
# CHECK-NEXT: 1, 400 (99.3%)
@@ -774,10 +774,10 @@ vmovaps %ymm3, (%rbx)
774774
# CHECK-NEXT: 0, 3 (0.7%)
775775
# CHECK-NEXT: 4, 400 (99.3%)
776776

777-
# CHECK: Schedulers - number of cycles where we saw N instructions issued:
777+
# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
778778
# CHECK-NEXT: [# issued], [# cycles]
779779
# CHECK-NEXT: 0, 3 (0.7%)
780-
# CHECK-NEXT: 1, 400 (99.3%)
780+
# CHECK-NEXT: 4, 400 (99.3%)
781781

782782
# CHECK: Scheduler's queue usage:
783783
# CHECK-NEXT: [1] Resource name.

‎llvm/test/tools/llvm-mca/X86/BtVer2/scheduler-queue-usage.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ add %rsi, %rsi
2626
# CHECK-NEXT: 1 7 1.00 * vmulps (%rsi), %xmm0, %xmm0
2727
# CHECK-NEXT: 1 1 0.50 addq %rsi, %rsi
2828

29-
# CHECK: Schedulers - number of cycles where we saw N instructions issued:
29+
# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
3030
# CHECK-NEXT: [# issued], [# cycles]
3131
# CHECK-NEXT: 0, 9 (90.0%)
3232
# CHECK-NEXT: 2, 1 (10.0%)

‎llvm/test/tools/llvm-mca/X86/option-all-stats-1.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@ add %eax, %eax
4141
# FULLREPORT-NEXT: 1, 62 (60.2%)
4242
# FULLREPORT-NEXT: 2, 19 (18.4%)
4343

44-
# FULLREPORT: Schedulers - number of cycles where we saw N instructions issued:
44+
# FULLREPORT: Schedulers - number of cycles where we saw N micro opcodes issued:
4545
# FULLREPORT-NEXT: [# issued], [# cycles]
4646
# FULLREPORT-NEXT: 0, 3 (2.9%)
4747
# FULLREPORT-NEXT: 1, 100 (97.1%)

‎llvm/test/tools/llvm-mca/X86/option-all-stats-2.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@ add %eax, %eax
4242
# FULL-NEXT: 1, 62 (60.2%)
4343
# FULL-NEXT: 2, 19 (18.4%)
4444

45-
# ALL: Schedulers - number of cycles where we saw N instructions issued:
45+
# ALL: Schedulers - number of cycles where we saw N micro opcodes issued:
4646
# ALL-NEXT: [# issued], [# cycles]
4747
# ALL-NEXT: 0, 3 (2.9%)
4848
# ALL-NEXT: 1, 100 (97.1%)

‎llvm/test/tools/llvm-mca/X86/option-all-views-1.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,7 @@ add %eax, %eax
4343
# FULLREPORT-NEXT: 1, 62 (60.2%)
4444
# FULLREPORT-NEXT: 2, 19 (18.4%)
4545

46-
# FULLREPORT: Schedulers - number of cycles where we saw N instructions issued:
46+
# FULLREPORT: Schedulers - number of cycles where we saw N micro opcodes issued:
4747
# FULLREPORT-NEXT: [# issued], [# cycles]
4848
# FULLREPORT-NEXT: 0, 3 (2.9%)
4949
# FULLREPORT-NEXT: 1, 100 (97.1%)

‎llvm/test/tools/llvm-mca/X86/option-all-views-2.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@ add %eax, %eax
4242
# ALL-NEXT: 1, 62 (60.2%)
4343
# ALL-NEXT: 2, 19 (18.4%)
4444

45-
# ALL: Schedulers - number of cycles where we saw N instructions issued:
45+
# ALL: Schedulers - number of cycles where we saw N micro opcodes issued:
4646
# ALL-NEXT: [# issued], [# cycles]
4747
# ALL-NEXT: 0, 3 (2.9%)
4848
# ALL-NEXT: 1, 100 (97.1%)

‎llvm/test/tools/llvm-mca/X86/scheduler-queue-usage.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@
1313

1414
xor %eax, %ebx
1515

16-
# ALL: Schedulers - number of cycles where we saw N instructions issued:
16+
# ALL: Schedulers - number of cycles where we saw N micro opcodes issued:
1717
# ALL-NEXT: [# issued], [# cycles]
1818
# ALL-NEXT: 0, 3 (75.0%)
1919
# ALL-NEXT: 1, 1 (25.0%)

‎llvm/tools/llvm-mca/Views/SchedulerStatistics.cpp

Lines changed: 13 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,6 @@ SchedulerStatistics::SchedulerStatistics(const llvm::MCSubtargetInfo &STI)
2222
: SM(STI.getSchedModel()), LQResourceID(0), SQResourceID(0), NumIssued(0),
2323
NumCycles(0), MostRecentLoadDispatched(~0U),
2424
MostRecentStoreDispatched(~0U),
25-
IssuedPerCycle(STI.getSchedModel().NumProcResourceKinds, 0),
2625
Usage(STI.getSchedModel().NumProcResourceKinds, {0, 0, 0}) {
2726
if (SM.hasExtraProcessorInfo()) {
2827
const MCExtraProcessorInfo &EPI = SM.getExtraProcessorInfo();
@@ -43,9 +42,10 @@ SchedulerStatistics::SchedulerStatistics(const llvm::MCSubtargetInfo &STI)
4342
// In future we should add a new "memory queue" event type, so that we stop
4443
// making assumptions on how LSUnit internally works (See PR39828).
4544
void SchedulerStatistics::onEvent(const HWInstructionEvent &Event) {
46-
if (Event.Type == HWInstructionEvent::Issued)
47-
++NumIssued;
48-
else if (Event.Type == HWInstructionEvent::Dispatched) {
45+
if (Event.Type == HWInstructionEvent::Issued) {
46+
const Instruction &Inst = *Event.IR.getInstruction();
47+
NumIssued += Inst.getDesc().NumMicroOps;
48+
} else if (Event.Type == HWInstructionEvent::Dispatched) {
4949
const Instruction &Inst = *Event.IR.getInstruction();
5050
const unsigned Index = Event.IR.getSourceIndex();
5151
if (LQResourceID && Inst.getDesc().MayLoad &&
@@ -95,29 +95,25 @@ void SchedulerStatistics::updateHistograms() {
9595
BU.MaxUsedSlots = std::max(BU.MaxUsedSlots, BU.SlotsInUse);
9696
}
9797

98-
IssuedPerCycle[NumIssued]++;
98+
IssueWidthPerCycle[NumIssued]++;
9999
NumIssued = 0;
100100
}
101101

102102
void SchedulerStatistics::printSchedulerStats(raw_ostream &OS) const {
103103
OS << "\n\nSchedulers - "
104-
<< "number of cycles where we saw N instructions issued:\n";
104+
<< "number of cycles where we saw N micro opcodes issued:\n";
105105
OS << "[# issued], [# cycles]\n";
106106

107-
const auto It =
108-
std::max_element(IssuedPerCycle.begin(), IssuedPerCycle.end());
109-
unsigned Index = std::distance(IssuedPerCycle.begin(), It);
110-
111107
bool HasColors = OS.has_colors();
112-
for (unsigned I = 0, E = IssuedPerCycle.size(); I < E; ++I) {
113-
unsigned IPC = IssuedPerCycle[I];
114-
if (!IPC)
115-
continue;
116-
117-
if (I == Index && HasColors)
108+
const auto It =
109+
std::max_element(IssueWidthPerCycle.begin(), IssueWidthPerCycle.end());
110+
for (const std::pair<unsigned, unsigned> &Entry : IssueWidthPerCycle) {
111+
unsigned NumIssued = Entry.first;
112+
if (NumIssued == It->first && HasColors)
118113
OS.changeColor(raw_ostream::SAVEDCOLOR, true, false);
119114

120-
OS << " " << I << ", " << IPC << " ("
115+
unsigned IPC = Entry.second;
116+
OS << " " << NumIssued << ", " << IPC << " ("
121117
<< format("%.1f", ((double)IPC / NumCycles) * 100) << "%)\n";
122118
if (HasColors)
123119
OS.resetColor();

‎llvm/tools/llvm-mca/Views/SchedulerStatistics.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -62,7 +62,9 @@ class SchedulerStatistics final : public View {
6262
uint64_t CumulativeNumUsedSlots;
6363
};
6464

65-
std::vector<unsigned> IssuedPerCycle;
65+
using Histogram = std::map<unsigned, unsigned>;
66+
Histogram IssueWidthPerCycle;
67+
6668
std::vector<BufferUsage> Usage;
6769

6870
void updateHistograms();

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