[RISC-V] Contain GT_CALL constant controlExpr to move lower 12 bits to JALR offset (#114728)

* Contain GT_CALL constant controlExpr to move lower 12 bits to JALR offset

* Remove duplicate assertion

Co-authored-by: Tomasz Sowiński <[email protected]>

* Correct typo in comment

Co-authored-by: Bruce Forstall <[email protected]>

---------

Co-authored-by: Tomasz Sowiński <[email protected]>
Co-authored-by: Bruce Forstall <[email protected]>

Author: 3 people

src/coreclr/jit/codegenriscv64.cpp

@@ -6176,18 +6176,37 @@ void CodeGen::genCallInstruction(GenTreeCall* call)
         // For fast tailcall we have already consumed the target. We ensure in
         // RA that the target was allocated into a volatile register that will
         // not be messed up by epilog sequence.
-        if (!call->IsFastTailCall())
+        if (!call->IsFastTailCall() && !target->isContainedIntOrIImmed())
         {
             genConsumeReg(target);
         }
 
+        regNumber targetReg;
+        ssize_t   jalrOffset = 0;
+
+        if (target->isContainedIntOrIImmed())
+        {
+            // Load upper (64-12) bits to a temporary register. Lower 12 bits will be put inside JALR's instruction as
+            // offset.
+            targetReg   = internalRegisters.GetSingle(call);
+            ssize_t imm = target->AsIntCon()->IconValue();
+            jalrOffset  = (imm << (64 - 12)) >> (64 - 12);
+            imm -= jalrOffset;
+            GetEmitter()->emitLoadImmediate(EA_PTRSIZE, targetReg, imm);
+        }
+        else
+        {
+            targetReg = target->GetRegNum();
+        }
+
         // We have already generated code for gtControlExpr evaluating it into a register.
         // We just need to emit "call reg" in this case.
         //
-        assert(genIsValidIntReg(target->GetRegNum()));
+        assert(genIsValidIntReg(targetReg));
 
         params.callType = EC_INDIR_R;
-        params.ireg     = target->GetRegNum();
+        params.ireg     = targetReg;
+        params.addr     = (jalrOffset == 0) ? nullptr : (void*)jalrOffset; // We use addr to pass offset value
 
         genEmitCallWithCurrentGC(params);
     }

src/coreclr/jit/emitriscv64.cpp

@@ -1620,7 +1620,7 @@ void emitter::emitIns_Call(const EmitCallParams& params)
     assert(params.callType < EC_COUNT);
     assert((params.callType != EC_FUNC_TOKEN) ||
            (params.ireg == REG_NA && params.xreg == REG_NA && params.xmul == 0 && params.disp == 0));
-    assert(params.callType < EC_INDIR_R || params.addr == NULL);
+    assert(params.callType < EC_INDIR_R || params.addr == nullptr || isValidSimm12((ssize_t)params.addr));
     assert(params.callType != EC_INDIR_R ||
            (params.ireg < REG_COUNT && params.xreg == REG_NA && params.xmul == 0 && params.disp == 0));
 
@@ -1726,7 +1726,7 @@ void emitter::emitIns_Call(const EmitCallParams& params)
 
     // INS_OPTS_C: placeholders.  1/2/4-ins:
     //   if (callType == EC_INDIR_R)
-    //      jalr REG_R0/REG_RA, ireg, 0   <---- 1-ins
+    //      jalr REG_R0/REG_RA, ireg, offset   <---- 1-ins
     //   else if (callType == EC_FUNC_TOKEN || callType == EC_FUNC_ADDR)
     //     if reloc:
     //             //pc + offset_38bits       # only when reloc.
@@ -1750,6 +1750,12 @@ void emitter::emitIns_Call(const EmitCallParams& params)
         regNumber reg_jalr = params.isJump ? REG_R0 : REG_RA;
         id->idReg4(reg_jalr);
         id->idReg3(params.ireg); // NOTE: for EC_INDIR_R, using idReg3.
+        id->idSmallCns(0);       // SmallCns will contain JALR's offset.
+        if (params.addr != nullptr)
+        {
+            // If addr is not NULL, it must contain JALR's offset, which is set to the lower 12 bits of address.
+            id->idSmallCns((size_t)params.addr);
+        }
         assert(params.xreg == REG_NA);
 
         id->idCodeSize(4);
@@ -1853,10 +1859,12 @@ unsigned emitter::emitOutputCall(const insGroup* ig, BYTE* dst, instrDesc* id, c
     assert(id->idIns() == INS_jalr);
     if (id->idIsCallRegPtr())
     { // EC_INDIR_R
+        ssize_t offset = id->idSmallCns();
+        assert(isValidSimm12(offset));
         code = emitInsCode(id->idIns());
         code |= (code_t)id->idReg4() << 7;
         code |= (code_t)id->idReg3() << 15;
-        // the offset default is 0;
+        code |= (code_t)offset << 20;
         emitOutput_Instr(dst, code);
     }
     else if (id->idIsReloc())

src/coreclr/jit/lower.cpp

@@ -2744,6 +2744,15 @@ GenTree* Lowering::LowerCall(GenTree* node)
 
         BlockRange().InsertBefore(call, std::move(controlExprRange));
         call->gtControlExpr = controlExpr;
+
+#ifdef TARGET_RISCV64
+        // If controlExpr is a constant, we should contain it inside the call so that we can move the lower 12-bits of
+        // the value to call instruction's (JALR) offset.
+        if (controlExpr->IsCnsIntOrI() && !controlExpr->AsIntCon()->ImmedValNeedsReloc(comp) && !call->IsFastTailCall())
+        {
+            MakeSrcContained(call, controlExpr);
+        }
+#endif // TARGET_RISCV64
     }
 
     if (comp->opts.IsCFGEnabled())

src/coreclr/jit/lsrariscv64.cpp

@@ -957,6 +957,12 @@ int LinearScan::BuildCall(GenTreeCall* call)
             }
             assert(ctrlExprCandidates != RBM_NONE);
         }
+
+        // In case ctrlExpr is a contained constant, we need a register to store the value.
+        if (ctrlExpr->isContainedIntOrIImmed())
+        {
+            buildInternalIntRegisterDefForNode(call);
+        }
     }
     else if (call->IsR2ROrVirtualStubRelativeIndir())
     {
@@ -994,7 +1000,7 @@ int LinearScan::BuildCall(GenTreeCall* call)
 
     srcCount += BuildCallArgUses(call);
 
-    if (ctrlExpr != nullptr)
+    if (ctrlExpr != nullptr && !ctrlExpr->isContainedIntOrIImmed())
     {
         BuildUse(ctrlExpr, ctrlExprCandidates);
         srcCount++;