AIG generation: ignore Verilog named blocks

kroening · kroening · commit 493be127a0df · 2025-12-01T09:04:46.000-08:00
Verilog named blocks do not need to be allocated AIG nodes.
diff --git a/src/trans-netlist/trans_to_netlist.cpp b/src/trans-netlist/trans_to_netlist.cpp
@@ -229,6 +229,10 @@ void convert_trans_to_netlistt::map_vars(
     {
       return; // ignore modules
     }
+    else if(symbol.type.id() == ID_named_block)
+    {
+      return; // ignore Verilog named blocks
+    }
     else if(symbol.is_type)
       return; // ignore types
     else if (symbol.is_input)

Original file line number	Diff line number	Diff line change
`@@ -229,6 +229,10 @@ void convert_trans_to_netlistt::map_vars(`
`229`	`229`	`{`
`230`	`230`	`return; // ignore modules`
`231`	`231`	`}`
	`232`	`+ else if(symbol.type.id() == ID_named_block)`
	`233`	`+ {`
	`234`	`+ return; // ignore Verilog named blocks`
	`235`	`+ }`
`232`	`236`	`else if(symbol.is_type)`
`233`	`237`	`return; // ignore types`
`234`	`238`	`else if (symbol.is_input)`