added MSI implementation

Author: dgiantsidi

MSI.cpp

@@ -0,0 +1,51 @@
+#include <stdlib.h>
+#include <iostream>
+#include "MSI.h"
+
+MSI::MSI (int processorsNum, Processor **p) {
+    processors = p;
+    procNum = processorsNum;
+}
+
+void MSI::readRequest(int processorId, int address) {
+    std::cout<<"1 " << processorId << " " << address <<"\n";
+    int cacheLine = processors[processorId]->cache->findCacheLine(address);
+    std::cout<<"2\n";
+    int tag = processors[processorId]->cache->findTag(address);
+    std::cout<<"3 " <<cacheLine<< " "<<address<< " " <<tag<<"\n";
+    int word = processors[processorId]->cache->retWord(cacheLine, tag);
+    std::cout<<"4\n";
+
+    
+    if (word != address || processors[processorId]->cache->retStateOfLine(cacheLine) == 0) {
+        // set this block as Shared (state == 1)
+        processors[processorId]->cache->setStateOfLine(cacheLine, 1); 
+        processors[processorId]->cache->cacheWord(cacheLine, tag, address);
+    }
+    else {
+        std::cout<< "Hit\n";
+    }
+
+}
+
+void MSI::writeRequest(int processorId, int address) {
+    int cacheLine = processors[processorId]->cache->findCacheLine(address);
+    int tag = processors[processorId]->cache->findTag(address);
+    int word = processors[processorId]->cache->retWord(cacheLine, tag);
+
+    // set this block as Modified
+    processors[processorId]->cache->setStateOfLine(cacheLine, 2); 
+    processors[processorId]->cache->cacheWord(cacheLine, tag, address);
+    for (int i = 0; i < procNum; i++){
+        if (i != processorId) {
+            int line = processors[i]->cache->findCacheLine(address);
+            int tag = processors[i]->cache->findTag(address);
+            if (processors[i]->cache->retWord(line, tag) == address){
+                processors[i]->cache->setStateOfLine(cacheLine, 0); 
+            }
+        }
+    }
+    // invalidate other blocks in other caches that may have this word
+    // cached.
+
+}

MSI.h

@@ -1,5 +1,15 @@
-class MSI {
+#pragma once
+#include "processor.h"
 
+class MSI {
+    public:
+        MSI (int processorsNum, Processor **p);
+        ~MSI (){};
+        void readRequest(int processorId, int address);
+        void writeRequest(int processorId, int address);
+        Processor **processors;
 
+    private:
+        int procNum;
 
-}
+};

Main.cpp

@@ -1,6 +1,7 @@
 #include <iostream>
 #include "processor.h"
 #include "parser.h"
+#include "MSI.h"
 #include <stdlib.h>     /* atoi */
 int main (int argc, char* argv[]) {
     int lineSize = 1024;
@@ -9,35 +10,45 @@ int main (int argc, char* argv[]) {
 
     if (argc < 4) {
         std::cout << "Not enough arguments\n";
+        std::cout << "Provide cache line size, lines' number and processors' number\n";
         exit(1);
     }
 
     lineSize = atoi(argv[1]);
     linesNumber = atoi(argv[2]);
     procNumber = atoi(argv[3]);
-    
+
     Processor **procTable = new Processor*[procNumber];
+    Cache **cacheTable = new Cache*[procNumber];
     for (int i = 0; i < procNumber; i++) {
-        Cache cache(lineSize, linesNumber);
-        procTable[i] = new Processor(i, &cache);
-        std::cout << "Cache line size: " << cache.retLineSize() << std::endl;
-        std::cout << "Cache lines number: " << cache.retLinesNumber() << std::endl;
-        std::cout << "cache Line of 17: " << cache.findCacheLine(17) << std::endl;
-        std::cout << "cache tag of 17: " << cache.findTag(17) << std::endl;
-        cache.cacheWord(cache.findCacheLine(17), cache.findTag(17), 17);
-        std::cout << "address: " << cache.retWord(cache.findCacheLine(17), cache.findTag(17)) << std::endl;
+        cacheTable[i] = new Cache(lineSize, linesNumber);
+        procTable[i] = new Processor(i, cacheTable[i]);
     }
 
+    MSI coherence_protocol(procNumber, procTable);
+    
+    std::cout << procTable[0]->cache->retLineSize() << "---\n";
+    std::cout << coherence_protocol.processors[0]->cache->retLineSize() << "+++\n";
     Parser p;
     int ret;
     ret = p.parse();
     int pId;
     int adr;
+    std::string opr;
     while (ret) {
         // here cache coherence should be implemented
         pId = p.getProcessor();
         adr = p.getAddress();
-        std::cout << pId << " " << adr << std::endl;
+        opr = p.getOper();
+        if (opr.compare("R") == 0) {
+            std::cout<<"READ\n";
+            // std::cout << "Processor: " << pId <<  " "  << opr << " " << adr << std::endl;
+            coherence_protocol.readRequest(pId, adr);
+        }
+        else  {
+            std::cout<<"WRITE\n";
+            coherence_protocol.writeRequest(pId, adr);
+        }
         ret = p.parse();
     }
 }

cache.cpp

@@ -7,8 +7,14 @@ Cache::Cache(int size, int number) {
     linesNumber = number;
     statePerLine = new int[linesNumber];
     addrPerLine = new int*[linesNumber];
-    for (int i = 0; i < lineSize; i ++) 
+    for (int i = 0; i < linesNumber; i ++) 
         addrPerLine[i] = new int[lineSize];
+    for (int i = 0; i < linesNumber; i ++) 
+        statePerLine[i] = 0;
+    int i;
+    for (i = 0; i < linesNumber; i ++) 
+            for (int j = 0; j < lineSize; j++)
+                addrPerLine[i][j] = -1;
 }
 
 Cache::~Cache(){
@@ -35,11 +41,12 @@ int Cache::findCacheLine(int wordAddress) {
     if (wordAddress >= linesNumber) {
         return findCacheLine(wordAddress/linesNumber);
     }
-    return wordAddress-1;
+
+    return wordAddress;
 }
 
 int Cache::findTag(int wordAddress) {
-    return wordAddress%linesNumber;
+    return wordAddress%lineSize;
 }
 
 int Cache::retWord(int cacheLine, int tag) {

cache.h

@@ -1,3 +1,5 @@
+#pragma once
+
 class Cache {
     public:
         Cache(int size, int number);

parser.h

@@ -15,9 +15,8 @@ class Parser{
 
         int parse() {
             std::string line;    
-
             if (std::getline(infile, line)) {
-                // std::cout << line << std::endl;
+                std::cout << line << std::endl;
                 processLine(line);
                 return 1;
             }

processor.h

@@ -1,11 +1,12 @@
+#pragma once
 #include "cache.h"
 
 class Processor {
     public:
         Processor(int processorId, Cache *privateCache);
         void request();
+        Cache *cache;
 
     private:
         int id;
-        Cache *cache;
 };