From 34826f189267cd3658bbdd172bd0bb8ba1463720 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Fri, 12 Nov 2021 16:44:30 +0000 Subject: [PATCH] tests: Replace master/slave terminology from tests scripts Signed-off-by: Giacomo Travaglini Change-Id: Id7aafc082c7e4cfc977e807141e63a3feb5a6348 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52863 Tested-by: kokoro Maintainer: Bobby R. Bruce Reviewed-by: Bobby R. Bruce --- tests/configs/gpu-randomtest-ruby.py | 6 +++--- tests/configs/gpu-ruby.py | 6 +++--- tests/configs/memtest-filter.py | 10 +++++----- tests/configs/memtest-ruby.py | 2 +- tests/configs/memtest.py | 10 +++++----- tests/configs/o3-timing-mp-ruby.py | 4 ++-- tests/configs/o3-timing-ruby.py | 4 ++-- tests/configs/pc-simple-timing-ruby.py | 2 +- tests/configs/rubytest-ruby.py | 6 +++--- tests/configs/simple-atomic-mp-ruby.py | 4 ++-- tests/configs/t1000-simple-atomic.py | 2 +- tests/gem5/configs/base_config.py | 16 +++++++-------- tests/gem5/cpu_tests/run.py | 20 +++++++++---------- .../m5threads_test_atomic/atomic_system.py | 4 ++-- tests/gem5/m5threads_test_atomic/caches.py | 6 +++--- tests/gem5/memory/memtest-run.py | 10 +++++----- tests/gem5/memory/simple-run.py | 8 ++++---- 17 files changed, 60 insertions(+), 60 deletions(-) diff --git a/tests/configs/gpu-randomtest-ruby.py b/tests/configs/gpu-randomtest-ruby.py index 0d1171c7c4..03d31fe113 100644 --- a/tests/configs/gpu-randomtest-ruby.py +++ b/tests/configs/gpu-randomtest-ruby.py @@ -125,11 +125,11 @@ # Tie the ruby tester ports to the ruby cpu read and write ports # if ruby_port.support_data_reqs and ruby_port.support_inst_reqs: - tester.cpuInstDataPort = ruby_port.slave + tester.cpuInstDataPort = ruby_port.in_ports elif ruby_port.support_data_reqs: - tester.cpuDataPort = ruby_port.slave + tester.cpuDataPort = ruby_port.in_ports elif ruby_port.support_inst_reqs: - tester.cpuInstPort = ruby_port.slave + tester.cpuInstPort = ruby_port.in_ports # Do not automatically retry stalled Ruby requests ruby_port.no_retry_on_stall = True diff --git a/tests/configs/gpu-ruby.py b/tests/configs/gpu-ruby.py index 18641566c8..2f57779b06 100644 --- a/tests/configs/gpu-ruby.py +++ b/tests/configs/gpu-ruby.py @@ -305,7 +305,7 @@ def run_test(root): system.ruby._cpu_ports[0].in_ports, system.ruby._cpu_ports[0].in_ports, system.ruby._cpu_ports[0].interrupt_out_port) -system.ruby._cpu_ports[0].mem_master_port = system.piobus.slave +system.ruby._cpu_ports[0].mem_request_port = system.piobus.cpu_side_ports # attach CU ports to Ruby # Because of the peculiarities of the CP core, you may have 1 CPU but 2 @@ -338,8 +338,8 @@ def run_test(root): assert(args.num_cp == 0) # connect dispatcher to the system.piobus -dispatcher.pio = system.piobus.master -dispatcher.dma = system.piobus.slave +dispatcher.pio = system.piobus.mem_side_ports +dispatcher.dma = system.piobus.cpu_side_ports ################# Connect the CPU and GPU via GPU Dispatcher ################### # CPU rings the GPU doorbell to notify a pending task diff --git a/tests/configs/memtest-filter.py b/tests/configs/memtest-filter.py index cce73970ab..042b3cda3a 100644 --- a/tests/configs/memtest-filter.py +++ b/tests/configs/memtest-filter.py @@ -50,10 +50,10 @@ system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain, snoop_filter = SnoopFilter()) system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.master +system.l2c.cpu_side = system.toL2Bus.mem_side_ports # connect l2c to membus -system.l2c.mem_side = system.membus.slave +system.l2c.mem_side = system.membus.cpu_side_ports # add L1 caches for cpu in cpus: @@ -61,12 +61,12 @@ cpu.clk_domain = system.cpu_clk_domain cpu.l1c = L1Cache(size = '32kB', assoc = 4) cpu.l1c.cpu_side = cpu.port - cpu.l1c.mem_side = system.toL2Bus.slave + cpu.l1c.mem_side = system.toL2Bus.cpu_side_ports -system.system_port = system.membus.slave +system.system_port = system.membus.cpu_side_ports # connect memory to membus -system.physmem.port = system.membus.master +system.physmem.port = system.membus.mem_side_ports # ----------------------- diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py index f8fbd10639..d6e1cf4f8d 100644 --- a/tests/configs/memtest-ruby.py +++ b/tests/configs/memtest-ruby.py @@ -100,7 +100,7 @@ # Tie the cpu port to the ruby cpu ports and # physmem, respectively # - cpus[i].port = ruby_port.slave + cpus[i].port = ruby_port.in_ports # # Since the memtester is incredibly bursty, increase the deadlock diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py index a957674667..01a5a46f09 100644 --- a/tests/configs/memtest.py +++ b/tests/configs/memtest.py @@ -49,10 +49,10 @@ system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain) system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.master +system.l2c.cpu_side = system.toL2Bus.mem_side_ports # connect l2c to membus -system.l2c.mem_side = system.membus.slave +system.l2c.mem_side = system.membus.cpu_side_ports # add L1 caches for cpu in cpus: @@ -60,12 +60,12 @@ cpu.clk_domain = system.cpu_clk_domain cpu.l1c = L1Cache(size = '32kB', assoc = 4) cpu.l1c.cpu_side = cpu.port - cpu.l1c.mem_side = system.toL2Bus.slave + cpu.l1c.mem_side = system.toL2Bus.cpu_side_ports -system.system_port = system.membus.slave +system.system_port = system.membus.cpu_side_ports # connect memory to membus -system.physmem.port = system.membus.master +system.physmem.port = system.membus.mem_side_ports # ----------------------- diff --git a/tests/configs/o3-timing-mp-ruby.py b/tests/configs/o3-timing-mp-ruby.py index b17502f0d9..bd7f07f996 100644 --- a/tests/configs/o3-timing-mp-ruby.py +++ b/tests/configs/o3-timing-mp-ruby.py @@ -50,10 +50,10 @@ cpu.clk_domain = system.cpu_clk_domain # connect memory to membus -system.physmem.port = system.membus.master +system.physmem.port = system.membus.mem_side_ports # Connect the system port for loading of binaries etc -system.system_port = system.membus.slave +system.system_port = system.membus.cpu_side_ports # ----------------------- # run simulation diff --git a/tests/configs/o3-timing-ruby.py b/tests/configs/o3-timing-ruby.py index 719eedb4ad..f06fe93bc3 100644 --- a/tests/configs/o3-timing-ruby.py +++ b/tests/configs/o3-timing-ruby.py @@ -42,12 +42,12 @@ # CPUs frequency system.cpu.clk_domain = SrcClockDomain(clock = '2GHz') -system.physmem.port = system.membus.master +system.physmem.port = system.membus.mem_side_ports # create the interrupt controller cpu.createInterruptController() cpu.connectBus(system.membus) # Connect the system port for loading of binaries etc -system.system_port = system.membus.slave +system.system_port = system.membus.cpu_side_ports root = Root(full_system = False, system = system) diff --git a/tests/configs/pc-simple-timing-ruby.py b/tests/configs/pc-simple-timing-ruby.py index 16dc72806e..9f73da9f2b 100644 --- a/tests/configs/pc-simple-timing-ruby.py +++ b/tests/configs/pc-simple-timing-ruby.py @@ -72,7 +72,7 @@ # Connect the ruby io port to the PIO bus, # assuming that there is just one such port. -system.iobus.master = system.ruby._io_port.slave +system.iobus.mem_side_ports = system.ruby._io_port.in_ports for (i, cpu) in enumerate(system.cpu): # create the interrupt controller diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py index 409278d72d..b68ff92ad1 100644 --- a/tests/configs/rubytest-ruby.py +++ b/tests/configs/rubytest-ruby.py @@ -107,11 +107,11 @@ # Tie the ruby tester ports to the ruby cpu read and write ports # if ruby_port.support_data_reqs and ruby_port.support_inst_reqs: - tester.cpuInstDataPort = ruby_port.slave + tester.cpuInstDataPort = ruby_port.in_ports elif ruby_port.support_data_reqs: - tester.cpuDataPort = ruby_port.slave + tester.cpuDataPort = ruby_port.in_ports elif ruby_port.support_inst_reqs: - tester.cpuInstPort = ruby_port.slave + tester.cpuInstPort = ruby_port.in_ports # Do not automatically retry stalled Ruby requests ruby_port.no_retry_on_stall = True diff --git a/tests/configs/simple-atomic-mp-ruby.py b/tests/configs/simple-atomic-mp-ruby.py index a14bf30ac7..117787a7dd 100644 --- a/tests/configs/simple-atomic-mp-ruby.py +++ b/tests/configs/simple-atomic-mp-ruby.py @@ -48,10 +48,10 @@ cpu.clk_domain = system.cpu_clk_domain # connect memory to membus -system.physmem.port = system.membus.master +system.physmem.port = system.membus.mem_side_ports # Connect the system port for loading of binaries etc -system.system_port = system.membus.slave +system.system_port = system.membus.cpu_side_ports # ----------------------- # run simulation diff --git a/tests/configs/t1000-simple-atomic.py b/tests/configs/t1000-simple-atomic.py index 4152a6cca1..99697212cc 100644 --- a/tests/configs/t1000-simple-atomic.py +++ b/tests/configs/t1000-simple-atomic.py @@ -50,7 +50,7 @@ system.physmem = [SimpleMemory(range = r) for r in system.mem_ranges] for i in range(len(system.physmem)): - system.physmem[i].port = system.membus.master + system.physmem[i].port = system.membus.mem_side_ports root = Root(full_system=True, system=system) diff --git a/tests/gem5/configs/base_config.py b/tests/gem5/configs/base_config.py index 9496f41516..e148467151 100644 --- a/tests/gem5/configs/base_config.py +++ b/tests/gem5/configs/base_config.py @@ -108,8 +108,8 @@ def create_caches_shared(self, system): system.toL2Bus = L2XBar(clk_domain=system.cpu_clk_domain) system.l2c = L2Cache(clk_domain=system.cpu_clk_domain, size='4MB', assoc=8) - system.l2c.cpu_side = system.toL2Bus.master - system.l2c.mem_side = system.membus.slave + system.l2c.cpu_side = system.toL2Bus.mem_side_ports + system.l2c.mem_side = system.membus.cpu_side_ports return system.toL2Bus def init_cpu(self, system, cpu, sha_bus): @@ -250,8 +250,8 @@ def create_system(self): mem_mode = self.mem_mode, multi_thread = (self.num_threads > 1)) if not self.use_ruby: - system.system_port = system.membus.slave - system.physmem.port = system.membus.master + system.system_port = system.membus.cpu_side_ports + system.physmem.port = system.membus.mem_side_ports self.init_system(system) return system @@ -293,7 +293,7 @@ def init_system(self, system): if self.use_ruby: # Connect the ruby io port to the PIO bus, # assuming that there is just one such port. - system.iobus.master = system.ruby._io_port.slave + system.iobus.mem_side_ports = system.ruby._io_port.in_ports else: # create the memory controllers and connect them, stick with # the physmem name to avoid bumping all the reference stats @@ -308,12 +308,12 @@ def init_system(self, system): system.physmem = [self.mem_class(range = r) for r in system.mem_ranges] for i in range(len(system.physmem)): - system.physmem[i].port = system.membus.master + system.physmem[i].port = system.membus.mem_side_ports # create the iocache, which by default runs at the system clock system.iocache = IOCache(addr_ranges=system.mem_ranges) - system.iocache.cpu_side = system.iobus.master - system.iocache.mem_side = system.membus.slave + system.iocache.cpu_side = system.iobus.mem_side_ports + system.iocache.mem_side = system.membus.cpu_side_ports def create_root(self): system = self.create_system() diff --git a/tests/gem5/cpu_tests/run.py b/tests/gem5/cpu_tests/run.py index f6a1cf6658..c17956ee87 100644 --- a/tests/gem5/cpu_tests/run.py +++ b/tests/gem5/cpu_tests/run.py @@ -43,7 +43,7 @@ class L1Cache(Cache): def connectBus(self, bus): """Connect this cache to a memory-side bus""" - self.mem_side = bus.slave + self.mem_side = bus.cpu_side_ports def connectCPU(self, cpu): """Connect this cache's port to a CPU-side port @@ -83,10 +83,10 @@ class L2Cache(Cache): tgts_per_mshr = 12 def connectCPUSideBus(self, bus): - self.cpu_side = bus.master + self.cpu_side = bus.mem_side_ports def connectMemSideBus(self, bus): - self.mem_side = bus.slave + self.mem_side = bus.cpu_side_ports class MySimpleMemory(SimpleMemory): @@ -134,8 +134,8 @@ class MySimpleMemory(SimpleMemory): if args.cpu == "AtomicSimpleCPU": system.membus = SystemXBar() - system.cpu.icache_port = system.membus.slave - system.cpu.dcache_port = system.membus.slave + system.cpu.icache_port = system.membus.cpu_side_ports + system.cpu.dcache_port = system.membus.cpu_side_ports else: system.cpu.l1d = L1DCache() system.cpu.l1i = L1ICache() @@ -151,14 +151,14 @@ class MySimpleMemory(SimpleMemory): system.cpu.createInterruptController() if m5.defines.buildEnv['TARGET_ISA'] == "x86": - system.cpu.interrupts[0].pio = system.membus.master - system.cpu.interrupts[0].int_master = system.membus.slave - system.cpu.interrupts[0].int_slave = system.membus.master + system.cpu.interrupts[0].pio = system.membus.mem_side_ports + system.cpu.interrupts[0].int_master = system.membus.cpu_side_ports + system.cpu.interrupts[0].int_slave = system.membus.mem_side_ports system.mem_ctrl = valid_mem[args.mem]() system.mem_ctrl.range = system.mem_ranges[0] -system.mem_ctrl.port = system.membus.master -system.system_port = system.membus.slave +system.mem_ctrl.port = system.membus.mem_side_ports +system.system_port = system.membus.cpu_side_ports process = Process() process.cmd = [args.binary] diff --git a/tests/gem5/m5threads_test_atomic/atomic_system.py b/tests/gem5/m5threads_test_atomic/atomic_system.py index f5c53e530a..a7c6535b59 100644 --- a/tests/gem5/m5threads_test_atomic/atomic_system.py +++ b/tests/gem5/m5threads_test_atomic/atomic_system.py @@ -62,7 +62,7 @@ root.system.membus.badaddr_responder = BadAddr() root.system.membus.default = root.system.membus.badaddr_responder.pio -root.system.system_port = root.system.membus.slave +root.system.system_port = root.system.membus.cpu_side_ports process = Process(executable = args.cmd, cmd = [args.cmd, str(args.num_cores)]) @@ -96,7 +96,7 @@ root.system.mem_ctrl = DDR3_1600_8x8() root.system.mem_ctrl.range = root.system.mem_ranges[0] -root.system.mem_ctrl.port = root.system.membus.master +root.system.mem_ctrl.port = root.system.membus.mem_side_ports m5.instantiate() exit_event = m5.simulate() diff --git a/tests/gem5/m5threads_test_atomic/caches.py b/tests/gem5/m5threads_test_atomic/caches.py index d2d9e62c95..af303a171c 100755 --- a/tests/gem5/m5threads_test_atomic/caches.py +++ b/tests/gem5/m5threads_test_atomic/caches.py @@ -56,7 +56,7 @@ def __init__(self, options=None): def connectBus(self, bus): """Connect this cache to a memory-side bus""" - self.mem_side = bus.slave + self.mem_side = bus.cpu_side_ports def connectCPU(self, cpu): """Connect this cache's port to a CPU-side port @@ -106,7 +106,7 @@ def __init__(self, opts=None): super(L2Cache, self).__init__(opts) def connectCPUSideBus(self, bus): - self.cpu_side = bus.master + self.cpu_side = bus.mem_side_ports def connectMemSideBus(self, bus): - self.mem_side = bus.slave + self.mem_side = bus.cpu_side_ports diff --git a/tests/gem5/memory/memtest-run.py b/tests/gem5/memory/memtest-run.py index 0cae42d873..9b6625c09d 100644 --- a/tests/gem5/memory/memtest-run.py +++ b/tests/gem5/memory/memtest-run.py @@ -50,10 +50,10 @@ system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain) system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.master +system.l2c.cpu_side = system.toL2Bus.mem_side_ports # connect l2c to membus -system.l2c.mem_side = system.membus.slave +system.l2c.mem_side = system.membus.cpu_side_ports # add L1 caches for cpu in cpus: @@ -61,12 +61,12 @@ cpu.clk_domain = system.cpu_clk_domain cpu.l1c = L1Cache(size = '32kB', assoc = 4) cpu.l1c.cpu_side = cpu.port - cpu.l1c.mem_side = system.toL2Bus.slave + cpu.l1c.mem_side = system.toL2Bus.cpu_side_ports -system.system_port = system.membus.slave +system.system_port = system.membus.cpu_side_ports # connect memory to membus -system.physmem.port = system.membus.master +system.physmem.port = system.membus.mem_side_ports # ----------------------- diff --git a/tests/gem5/memory/simple-run.py b/tests/gem5/memory/simple-run.py index 7cf9745ca7..16349536ae 100644 --- a/tests/gem5/memory/simple-run.py +++ b/tests/gem5/memory/simple-run.py @@ -76,14 +76,14 @@ class MyMem(SimpleMemory): system.monitor.stackdist = StackDistProbe(verify = True) # connect the traffic generator to the bus via a communication monitor -system.cpu.port = system.monitor.slave -system.monitor.master = system.membus.slave +system.cpu.port = system.monitor.cpu_side_port +system.monitor.mem_side_port = system.membus.cpu_side_ports # connect the system port even if it is not used in this example -system.system_port = system.membus.slave +system.system_port = system.membus.cpu_side_ports # connect memory to the membus -system.physmem.port = system.membus.master +system.physmem.port = system.membus.mem_side_ports # ----------------------- # run simulation