PCI: j721e: Deassert PERST# after a delay of PCIE_T_PVPERL_MS milliseconds

JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: 22a9120

commit 22a9120
Author: Siddharth Vadapalli <[email protected]>
Date:   Mon Nov 4 13:14:20 2024 +0530

    PCI: j721e: Deassert PERST# after a delay of PCIE_T_PVPERL_MS milliseconds

    According to Section 2.2 of the PCI Express Card Electromechanical
    Specification (Revision 5.1), in order to ensure that the power and the
    reference clock are stable, PERST# has to be deasserted after a delay of
    100 milliseconds (TPVPERL).

    Currently, it is being assumed that the power is already stable, which
    is not necessarily true.

    Hence, change the delay to PCIE_T_PVPERL_MS to guarantee that power and
    reference clock are stable.

    Fixes: f3e2591 ("PCI: j721e: Add TI J721E PCIe driver")
    Fixes: f96b697 ("PCI: j721e: Use T_PERST_CLK_US macro")
    Link: https://lore.kernel.org/r/[email protected]
    Signed-off-by: Siddharth Vadapalli <[email protected]>
    Signed-off-by: Krzysztof Wilczyński <[email protected]>

Signed-off-by: Myron Stowe <[email protected]>

Author: Myron Stowe

drivers/pci/controller/cadence/pci-j721e.c

@@ -572,15 +572,14 @@ static int j721e_pcie_probe(struct platform_device *pdev)
 		pcie->refclk = clk;
 
 		/*
-		 * The "Power Sequencing and Reset Signal Timings" table of the
-		 * PCI Express Card Electromechanical Specification, Revision
-		 * 5.1, Section 2.9.2, Symbol "T_PERST-CLK", indicates PERST#
-		 * should be deasserted after minimum of 100us once REFCLK is
-		 * stable. The REFCLK to the connector in RC mode is selected
-		 * while enabling the PHY. So deassert PERST# after 100 us.
+		 * Section 2.2 of the PCI Express Card Electromechanical
+		 * Specification (Revision 5.1) mandates that the deassertion
+		 * of the PERST# signal should be delayed by 100 ms (TPVPERL).
+		 * This shall ensure that the power and the reference clock
+		 * are stable.
 		 */
 		if (gpiod) {
-			fsleep(PCIE_T_PERST_CLK_US);
+			msleep(PCIE_T_PVPERL_MS);
 			gpiod_set_value_cansleep(gpiod, 1);
 		}
 
@@ -671,15 +670,14 @@ static int j721e_pcie_resume_noirq(struct device *dev)
 			return ret;
 
 		/*
-		 * The "Power Sequencing and Reset Signal Timings" table of the
-		 * PCI Express Card Electromechanical Specification, Revision
-		 * 5.1, Section 2.9.2, Symbol "T_PERST-CLK", indicates PERST#
-		 * should be deasserted after minimum of 100us once REFCLK is
-		 * stable. The REFCLK to the connector in RC mode is selected
-		 * while enabling the PHY. So deassert PERST# after 100 us.
+		 * Section 2.2 of the PCI Express Card Electromechanical
+		 * Specification (Revision 5.1) mandates that the deassertion
+		 * of the PERST# signal should be delayed by 100 ms (TPVPERL).
+		 * This shall ensure that the power and the reference clock
+		 * are stable.
 		 */
 		if (pcie->reset_gpio) {
-			fsleep(PCIE_T_PERST_CLK_US);
+			msleep(PCIE_T_PVPERL_MS);
 			gpiod_set_value_cansleep(pcie->reset_gpio, 1);
 		}