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Auto merge of rust-lang#112374 - chenx97:better-mips64r6, r=jackh726
add mips64r6 and mips32r6 as target_arch values This PR introduces `"mips32r6"` and `"mips64r6"` as valid `target_arch` values, and would be the arch value used by Tier-3 targets `mipsisa32r6-unknown-linux-gnu`, `mipsisa32r6el-unknown-linux-gnu`, `mipsisa64r6-unknown-linux-gnuabi64` and `mipsisa64r6el-unknown-linux-gnuabi64`. This PR was inspired by `rustix` attempting to link traditional mips64el objects with mips64r6el objects when building for mips64r6, even though `rustix` recently removed outline assembly support. This is because currently this target's `target_arch` is `"mips64"` and rustix has its respective assembly implementation as well as a pre-compiled little-endian static library prepared for mips64el, a tier-2 target with the same `target_arch`. After some [discussions on zulip](https://rust-lang.zulipchat.com/#narrow/stream/233931-t-compiler.2Fmajor-changes/topic/Add.20New.20Values.20To.20MIPS_ALLOWED_FEATURES.20compiler-team.23595), I decided to treat mips64r6 as an independent architecture from Rust's POV, since these two architectures are incompatible anyway. This PR is now waiting for `libc` to release a new version with [support](rust-lang/libc#3268) for these `target_arch` values. It is not expected to introduce changes to any other target, especially Tier-1 and Tier-2 targets. This PR has its corresponding [MCP](rust-lang/compiler-team#632) approved.
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compiler/rustc_codegen_cranelift/example/float-minmax-pass.rs

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@@ -22,7 +22,7 @@ fn main() {
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#[cfg(not(any(target_arch = "mips", target_arch = "mips64")))]
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let nan = f32::NAN;
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// MIPS hardware treats f32::NAN as SNAN. Clear the signaling bit.
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// MIPS hardware except MIPS R6 treats f32::NAN as SNAN. Clear the signaling bit.
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// See https://github.com/rust-lang/rust/issues/52746.
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#[cfg(any(target_arch = "mips", target_arch = "mips64"))]
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let nan = f32::from_bits(f32::NAN.to_bits() - 1);

compiler/rustc_codegen_gcc/example/alloc_system.rs

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@@ -10,13 +10,15 @@
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#[cfg(any(target_arch = "x86",
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target_arch = "arm",
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target_arch = "mips",
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target_arch = "mips32r6",
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target_arch = "powerpc",
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target_arch = "powerpc64"))]
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const MIN_ALIGN: usize = 8;
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#[cfg(any(target_arch = "x86_64",
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target_arch = "aarch64",
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target_arch = "loongarch64",
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target_arch = "mips64",
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target_arch = "mips64r6",
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target_arch = "s390x",
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target_arch = "sparc64"))]
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const MIN_ALIGN: usize = 16;

compiler/rustc_codegen_ssa/src/back/metadata.rs

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@@ -193,8 +193,8 @@ pub(crate) fn create_object_file(sess: &Session) -> Option<write::Object<'static
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}
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"x86" => Architecture::I386,
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"s390x" => Architecture::S390x,
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"mips" => Architecture::Mips,
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"mips64" => Architecture::Mips64,
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"mips" | "mips32r6" => Architecture::Mips,
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"mips64" | "mips64r6" => Architecture::Mips64,
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"x86_64" => {
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if sess.target.pointer_width == 32 {
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Architecture::X86_64_X32

compiler/rustc_codegen_ssa/src/target_features.rs

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@@ -321,7 +321,7 @@ pub fn supported_target_features(sess: &Session) -> &'static [(&'static str, Opt
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"aarch64" => AARCH64_ALLOWED_FEATURES,
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"x86" | "x86_64" => X86_ALLOWED_FEATURES,
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"hexagon" => HEXAGON_ALLOWED_FEATURES,
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"mips" | "mips64" => MIPS_ALLOWED_FEATURES,
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"mips" | "mips32r6" | "mips64" | "mips64r6" => MIPS_ALLOWED_FEATURES,
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"powerpc" | "powerpc64" => POWERPC_ALLOWED_FEATURES,
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"riscv32" | "riscv64" => RISCV_ALLOWED_FEATURES,
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"wasm32" | "wasm64" => WASM_ALLOWED_FEATURES,

compiler/rustc_target/src/abi/call/mod.rs

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@@ -693,8 +693,8 @@ impl<'a, Ty> FnAbi<'a, Ty> {
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"avr" => avr::compute_abi_info(self),
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"loongarch64" => loongarch::compute_abi_info(cx, self),
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"m68k" => m68k::compute_abi_info(self),
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"mips" => mips::compute_abi_info(cx, self),
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"mips64" => mips64::compute_abi_info(cx, self),
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"mips" | "mips32r6" => mips::compute_abi_info(cx, self),
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"mips64" | "mips64r6" => mips64::compute_abi_info(cx, self),
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"powerpc" => powerpc::compute_abi_info(self),
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"powerpc64" => powerpc64::compute_abi_info(cx, self),
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"s390x" => s390x::compute_abi_info(cx, self),

compiler/rustc_target/src/asm/mod.rs

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@@ -238,8 +238,8 @@ impl FromStr for InlineAsmArch {
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"powerpc64" => Ok(Self::PowerPC64),
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"hexagon" => Ok(Self::Hexagon),
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"loongarch64" => Ok(Self::LoongArch64),
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"mips" => Ok(Self::Mips),
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"mips64" => Ok(Self::Mips64),
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"mips" | "mips32r6" => Ok(Self::Mips),
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"mips64" | "mips64r6" => Ok(Self::Mips64),
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"s390x" => Ok(Self::S390x),
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"spirv" => Ok(Self::SpirV),
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"wasm32" => Ok(Self::Wasm32),

compiler/rustc_target/src/spec/mipsisa32r6_unknown_linux_gnu.rs

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@@ -6,7 +6,7 @@ pub fn target() -> Target {
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llvm_target: "mipsisa32r6-unknown-linux-gnu".into(),
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pointer_width: 32,
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data_layout: "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64".into(),
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arch: "mips".into(),
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arch: "mips32r6".into(),
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options: TargetOptions {
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endian: Endian::Big,
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cpu: "mips32r6".into(),

compiler/rustc_target/src/spec/mipsisa32r6el_unknown_linux_gnu.rs

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@@ -5,7 +5,7 @@ pub fn target() -> Target {
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llvm_target: "mipsisa32r6el-unknown-linux-gnu".into(),
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pointer_width: 32,
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data_layout: "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64".into(),
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arch: "mips".into(),
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arch: "mips32r6".into(),
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options: TargetOptions {
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cpu: "mips32r6".into(),

compiler/rustc_target/src/spec/mipsisa64r6_unknown_linux_gnuabi64.rs

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@@ -6,7 +6,7 @@ pub fn target() -> Target {
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llvm_target: "mipsisa64r6-unknown-linux-gnuabi64".into(),
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pointer_width: 64,
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data_layout: "E-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128".into(),
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arch: "mips64".into(),
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arch: "mips64r6".into(),
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options: TargetOptions {
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abi: "abi64".into(),
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endian: Endian::Big,

compiler/rustc_target/src/spec/mipsisa64r6el_unknown_linux_gnuabi64.rs

Lines changed: 1 addition & 1 deletion
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@@ -5,7 +5,7 @@ pub fn target() -> Target {
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llvm_target: "mipsisa64r6el-unknown-linux-gnuabi64".into(),
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pointer_width: 64,
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data_layout: "e-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128".into(),
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arch: "mips64".into(),
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arch: "mips64r6".into(),
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options: TargetOptions {
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abi: "abi64".into(),
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// NOTE(mips64r6) matches C toolchain

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