Tolerate overaligned MIR constants for codegen.

Author: cjgillot

compiler/rustc_codegen_ssa/src/mir/operand.rs

@@ -132,7 +132,7 @@ impl<'a, 'tcx, V: CodegenObject> OperandRef<'tcx, V> {
         offset: Size,
     ) -> Self {
         let alloc_align = alloc.inner().align;
-        assert_eq!(alloc_align, layout.align.abi);
+        assert!(alloc_align >= layout.align.abi);
 
         let read_scalar = |start, size, s: abi::Scalar, ty| {
             match alloc.0.read_scalar(

tests/codegen/overaligned-constant.rs

@@ -0,0 +1,31 @@
+// GVN may create indirect constants with higher alignment than their type requires. Verify that we
+// do not ICE during codegen, and that the LLVM constant has the higher alignment.
+//
+// compile-flags: -O -Zmir-enable-passes=+GVN -Cdebuginfo=2
+// compile-flags: -Cno-prepopulate-passes
+// only-64bit
+
+struct S(i32);
+
+struct SmallStruct(f32, Option<S>, &'static [f32]);
+
+fn main() {
+    let mut s = S(1);
+
+    s.0 = 3;
+
+    // SMALL_VAL corresponds to a MIR allocation with alignment 8.
+    const SMALL_VAL: SmallStruct = SmallStruct(4., Some(S(1)), &[]);
+
+    // In pre-codegen MIR:
+    // `a` is a scalar 4.
+    // `b` is an indirect constant at `SMALL_VAL`'s alloc with 0 offset.
+    // `c` is the empty slice.
+    //
+    // As a consequence, during codegen, we create a LLVM allocation for `SMALL_VAL`, with
+    // alignment 8, but only use the `Option<S>` field, at offset 0 with alignment 4.
+    let SmallStruct(a, b, c) = SMALL_VAL;
+}
+
+// CHECK: @0 = private unnamed_addr constant
+// CHECK-SAME: , align 8