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Commit b2d2a3c

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author
robo9k
committed
Fix/remove code that requires feature gates
1 parent 5d5cb53 commit b2d2a3c

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3 files changed

+45
-15
lines changed

3 files changed

+45
-15
lines changed

src/instructions.rs

Lines changed: 42 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,10 @@
11
//! Raw and high-level instruction abstractions
22
3-
use std::num::{FromPrimitive, ToPrimitive};
43

54
/// A register index/name
65
///
76
/// There are 16 data registers, `V0`..`VF`
8-
#[derive(FromPrimitive, Clone, Copy, Debug)]
7+
#[derive(Clone, Copy, Debug)]
98
pub enum Register {
109
V0 = 0x0,
1110
V1 = 0x1,
@@ -25,13 +24,31 @@ pub enum Register {
2524
VF = 0xF,
2625
}
2726

28-
impl ToPrimitive for Register {
29-
fn to_i64(&self) -> Option<i64> {
30-
Some(*self as i64)
31-
}
27+
impl Register {
28+
pub fn new(bits: u8) -> Result<Register, ()> {
29+
use self::Register::*;
30+
31+
match bits {
32+
0x0 => Ok(V0),
33+
0x1 => Ok(V1),
34+
0x2 => Ok(V2),
35+
0x3 => Ok(V3),
36+
0x4 => Ok(V4),
37+
0x5 => Ok(V5),
38+
0x6 => Ok(V6),
39+
0x7 => Ok(V7),
40+
0x8 => Ok(V8),
41+
0x9 => Ok(V9),
42+
0xA => Ok(VA),
43+
0xB => Ok(VB),
44+
0xC => Ok(VC),
45+
0xD => Ok(VD),
46+
0xE => Ok(VE),
47+
0xF => Ok(VF),
3248

33-
fn to_u64(&self) -> Option<u64> {
34-
Some(*self as u64)
49+
// TODO: Return a proper Error
50+
_ => Err(())
51+
}
3552
}
3653
}
3754

@@ -103,12 +120,12 @@ impl RawInstruction {
103120

104121
/// The *`Vx` register-index* part, i.e. `0xE` is `VE`
105122
pub fn x(&self) -> Vx {
106-
FromPrimitive::from_u8(((self.bits & 0x0F00) >> 8) as u8).unwrap()
123+
Register::new(((self.bits & 0x0F00) >> 8) as u8).unwrap()
107124
}
108125

109126
/// The *`Vy` register-index* part, i.e. `0xE` is `VE`
110127
pub fn y(&self) -> Vy {
111-
FromPrimitive::from_u8(((self.bits & 0x00F0) >> 4) as u8).unwrap()
128+
Register::new(((self.bits & 0x00F0) >> 4) as u8).unwrap()
112129
}
113130

114131
/// The *high nibble* part
@@ -297,3 +314,18 @@ impl Instruction {
297314
}
298315
}
299316
}
317+
318+
#[cfg(test)]
319+
mod tests {
320+
use super::*;
321+
322+
#[test]
323+
fn unknown_register() {
324+
assert!(Register::new(0x42).is_err())
325+
}
326+
327+
#[test]
328+
fn known_register() {
329+
assert_eq!(Register::new(0xF).unwrap() as u8, Register::VF as u8)
330+
}
331+
}

src/lib.rs

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -17,11 +17,6 @@
1717
//! `std:error::Error` for any kinds of errors that might occur using
1818
//! the `chip8_vm` crate.
1919
20-
// Silence 'core' feature warnings
21-
// for `error:Error` and such
22-
#![feature(core)]
23-
24-
#![feature(slice_patterns)]
2520

2621
extern crate rand;
2722

src/vm.rs

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -423,6 +423,8 @@ impl Vm {
423423
}
424424
}
425425

426+
// This needs experimental slice patterns and is unused anyways
427+
/*
426428
/// Prints a disassembly of the entire RAM to `stdout`
427429
#[allow(dead_code)]
428430
pub fn print_disassembly(&self) {
@@ -444,6 +446,7 @@ impl Vm {
444446
}
445447
}
446448
}
449+
*/
447450
}
448451

449452
#[cfg(test)]

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