more testing on GD32, SPI not working

Author: dword1511

Makefile

@@ -3,6 +3,7 @@
 # * Override toochain: make CROSS=/path/to/arm-none-eabi
 # * Override UART for downloading: make SERIAL=/dev/ttyS1
 # * Override hardware config: make BOARD=some_board_in_boards_folder
+# * Build for GD32 variants with 12MHz crystal: make EXTRA_CFLAGS=-DGD32F103
 
 ###############################################################################
 
@@ -39,7 +40,7 @@ CFLAGS     += -O3 -Wall -g
 #CFLAGS     += -Os -Wall -g
 #CFLAGS     += -Wextra -fprofile-generate -fprofile-use
 CFLAGS     += -fno-common -ffunction-sections -fdata-sections
-CFLAGS     += $(ARCH_FLAGS) -Ilibopencm3/include/
+CFLAGS     += $(ARCH_FLAGS) -Ilibopencm3/include/ $(EXTRA_CFLAGS)
 
 LIBM        = $(shell $(CC) $(CFLAGS) --print-file-name=libm.a)
 LIBC        = $(shell $(CC) $(CFLAGS) --print-file-name=libc.a)

spi.c

@@ -9,6 +9,7 @@
 #define likely(x)   __builtin_expect((x), 1)
 #define unlikely(x) __builtin_expect((x), 0)
 
+/* DMA channel and requests has fixed mapping, do not change */
 #define SPI_DMA_RX_CH DMA_CHANNEL2
 #define SPI_DMA_TX_CH DMA_CHANNEL3
 
@@ -66,6 +67,7 @@ uint32_t spi_setup(uint32_t speed_hz) {
   gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO_SPI1_MISO);
   gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO_SPI1_NSS); /* SS is manual */
   gpio_set(GPIOA, GPIO_SPI1_MISO);
+  gpio_set(GPIOA, GPIO_SPI1_NSS);
 
   /* Reset SPI, SPI_CR1 register cleared, SPI is disabled */
   spi_reset(SPI1);
@@ -187,6 +189,16 @@ static void spi_copy_from_usb(uint32_t len) {
   }
 }
 
+#ifdef GD32F103
+/* FIXME: Currently SPI does not work on GD32 under any clock... */
+void spi_bulk_read(uint32_t rlen) {
+  spi_copy_to_usb(rlen);
+}
+
+void spi_bulk_write(uint32_t slen) {
+  spi_copy_from_usb(slen);
+}
+#else
 void spi_bulk_read(uint32_t rlen) {
   while (likely(rlen >= USBCDC_PKT_SIZE_DAT)) {
     spi_dma_read(USBCDC_PKT_SIZE_DAT);
@@ -254,3 +266,4 @@ void spi_bulk_write(uint32_t slen) {
   /* Mark USB RX buffer as used. */
   usbcdc_get_remainder(&urbuf);
 }
+#endif /* GD32F103 */

usbcdc.c

@@ -187,6 +187,12 @@ static int cdcacm_control_request(usbd_device *usbd_dev, struct usb_setup_data *
   return 0;
 }
 
+volatile bool usb_ready = false;
+
+static void cdcacm_reset(void) {
+  usb_ready = false;
+}
+
 static void cdcacm_set_config(usbd_device *usbd_dev, uint16_t wValue) {
   usbd_ep_setup(usbd_dev, EP_IN , USB_ENDPOINT_ATTR_BULK, 64, NULL);
   usbd_ep_setup(usbd_dev, EP_OUT, USB_ENDPOINT_ATTR_BULK, 64, NULL);
@@ -197,6 +203,10 @@ static void cdcacm_set_config(usbd_device *usbd_dev, uint16_t wValue) {
         USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE,
         USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT,
         cdcacm_control_request);
+
+  if (wValue > 0) {
+    usb_ready = true;
+  }
 }
 
 static usbd_device *usbd_dev; /* Just a pointer, need not to be volatile. */
@@ -215,6 +225,7 @@ void usbcdc_init(void) {
 
   usbd_dev = usbd_init(&st_usbfs_v1_usb_driver, &dev, &config, usb_strings, 3, usbd_control_buffer, sizeof(usbd_control_buffer));
   usbd_register_set_config_callback(usbd_dev, cdcacm_set_config);
+  usbd_register_reset_callback(usbd_dev, cdcacm_reset);
 
   /* NOTE: Must be called after USB setup since this enables calling usbd_poll(). */
   nvic_enable_irq(NVIC_USB_LP_CAN_RX0_IRQ);

usbcdc.h

@@ -8,6 +8,7 @@
 #define USBCDC_PKT_SIZE_INT 16
 
 extern char usbcdc_rxbuf[USBCDC_PKT_SIZE_DAT]; /* DMA needs access */
+extern volatile bool usb_ready;
 
 void     usbcdc_init(void);
 uint16_t usbcdc_write(void *buf, size_t len);

vserprog.c

@@ -232,7 +232,12 @@ void handle_command(unsigned char command) {
 }
 
 #ifdef GD32F103
-void rcc_clock_setup_in_hse_12mhz_out_120mhz(void) {
+#define  RCC_GCFGR_ADCPS_DIV12  ((uint32_t)0x10004000)
+#define  RCC_GCFGR_ADCPS_DIV16  ((uint32_t)0x1000C000)
+#define  RCC_GCFGR_USBPS_Div2_5 ((uint32_t)0x00800000)
+#define  RCC_GCFGR_USBPS_Div2   ((uint32_t)0x00C00000)
+
+static void rcc_clock_setup_in_hse_12mhz_out_96mhz(void) {
   /* Enable internal high-speed oscillator. */
   rcc_osc_on(RCC_HSI);
   rcc_wait_for_osc_ready(RCC_HSI);
@@ -247,16 +252,68 @@ void rcc_clock_setup_in_hse_12mhz_out_120mhz(void) {
 
   /*
    * Set prescalers for AHB, ADC, ABP1, ABP2.
-   * Do this before touching the PLL (TODO: why?).
+   * Do this before touching the PLL
+   */
+  rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV);   /* Set. 96MHz Max. 108MHz */
+  rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 12MHz Max. 14MHz  */
+  rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2);    /* Set. 48MHz Max. 54MHz  */
+  rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV);   /* Set. 96MHz Max. 108MHz */
+  RCC_CFGR |= RCC_GCFGR_USBPS_Div2;           /* USB Set. 48MHz  Max. 48MHz  */
+
+  /* GD32 has 0-wait-state flash, do not touch anything! */
+
+  /*
+   * Set the PLL multiplication factor to 10.
+   * 12MHz (external) * 8 (multiplier) = 96MHz
+   */
+  rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL8);
+
+  /* Select HSE as PLL source. */
+  rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK);
+
+  /*
+   * External frequency undivided before entering PLL
+   * (only valid/needed for HSE).
+   */
+  rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK);
+
+  /* Enable PLL oscillator and wait for it to stabilize. */
+  rcc_osc_on(RCC_PLL);
+  rcc_wait_for_osc_ready(RCC_PLL);
+
+  /* Select PLL as SYSCLK source. */
+  rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
+
+  /* Set the peripheral clock frequencies used */
+  rcc_ahb_frequency  = 96000000;
+  rcc_apb1_frequency = 48000000;
+  rcc_apb2_frequency = 96000000;
+}
+
+static void rcc_clock_setup_in_hse_12mhz_out_120mhz(void) {
+  /* Enable internal high-speed oscillator. */
+  rcc_osc_on(RCC_HSI);
+  rcc_wait_for_osc_ready(RCC_HSI);
+
+  /* Select HSI as SYSCLK source. */
+  rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK);
+
+  /* Enable external high-speed oscillator 12MHz. */
+  rcc_osc_on(RCC_HSE);
+  rcc_wait_for_osc_ready(RCC_HSE);
+  rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK);
+
+  /*
+   * Set prescalers for AHB, ADC, ABP1, ABP2.
+   * Do this before touching the PLL
    */
   rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV);      /* Set. 120MHz Max. 108MHz */
-  RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_ADCPRE) | ((uint32_t)0x10004000); /* ADC Set. 12MHz  Max. 14MHz  */
+  RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_ADCPRE) | RCC_GCFGR_ADCPS_DIV12; /* ADC Set. 10MHz  Max. 14MHz  */
   rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2);       /* Set. 60MHz  Max. 54MHz  */
   rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV);      /* Set. 120MHz Max. 108MHz */
-  RCC_CFGR |= ((uint32_t)0x00800000);            /* USB Set. 48MHz  Max. 48MHz  */
+  RCC_CFGR |= RCC_GCFGR_USBPS_Div2_5;            /* USB Set. 48MHz  Max. 48MHz  */
 
-  /* GD32 has 0-wait-state flash */
-  flash_set_ws(FLASH_ACR_LATENCY_0WS);
+  /* GD32 has 0-wait-state flash, do not touch anything! */
 
   /*
    * Set the PLL multiplication factor to 10.
@@ -319,15 +376,24 @@ int main(void) {
 
   usbcdc_init();
   spi_setup(SPI_DEFAULT_CLOCK);
-  /* Wait 500ms for USB setup to complete before trying to send anything. */
-  /* FIXME: in ST's USB library there is some way to tell whether USB has finished initialization. */
-  for (i = 0; i < 10000000; i ++) {
-    asm("nop");
-  }
-  LED_IDLE();
 
   /* The loop. */
   while (true) {
+    /* Wait and blink if USB is not ready. */
+    LED_IDLE();
+    while (!usb_ready) {
+      LED_DISABLE();
+      for (i = 0; i < 1000000; i ++) {
+        asm("nop");
+      }
+      LED_ENABLE();
+      for (i = 0; i < 1000000; i ++) {
+        asm("nop");
+      }
+    }
+
+    /* Actual thing */
+    /* TODO: we are blocked here, hence no knowledge about USB bet reset. */
     handle_command(usbcdc_getc());
   }