winch(aarch64): Handle division signedness (#9784)

This commit fixes how signedness division is hanlded in aarch64.
Prior to this commit, sign-extension was emitted unconditionally.

This commit ensures that the correct extension is emitted depending on
the division kind.

Additionally this commit prefers making use of existing assembler
helpers.

Author: saulecabrera

tests/disas/winch/aarch64/i32_divu/const.wat

@@ -23,8 +23,8 @@
 ;;       mov     x16, #0x14
 ;;       mov     w1, w16
 ;;       cbz     x0, #0x54
-;;   34: sxtw    x0, w0
-;;       sxtw    x1, w1
+;;   34: mov     w0, w0
+;;       mov     w1, w1
 ;;       udiv    x1, x1, x0
 ;;       mov     w0, w1
 ;;       add     sp, sp, #0x10

tests/disas/winch/aarch64/i32_divu/one_zero.wat

@@ -23,8 +23,8 @@
 ;;       mov     x16, #1
 ;;       mov     w1, w16
 ;;       cbz     x0, #0x54
-;;   34: sxtw    x0, w0
-;;       sxtw    x1, w1
+;;   34: mov     w0, w0
+;;       mov     w1, w1
 ;;       udiv    x1, x1, x0
 ;;       mov     w0, w1
 ;;       add     sp, sp, #0x10

tests/disas/winch/aarch64/i32_divu/params.wat

@@ -23,8 +23,8 @@
 ;;       ldur    w0, [x28]
 ;;       ldur    w1, [x28, #4]
 ;;       cbz     x0, #0x54
-;;   34: sxtw    x0, w0
-;;       sxtw    x1, w1
+;;   34: mov     w0, w0
+;;       mov     w1, w1
 ;;       udiv    x1, x1, x0
 ;;       mov     w0, w1
 ;;       add     sp, sp, #0x18

tests/disas/winch/aarch64/i32_divu/signed.wat

@@ -23,8 +23,8 @@
 ;;       orr     x16, xzr, #0xffffffff
 ;;       mov     w1, w16
 ;;       cbz     x0, #0x54
-;;   34: sxtw    x0, w0
-;;       sxtw    x1, w1
+;;   34: mov     w0, w0
+;;       mov     w1, w1
 ;;       udiv    x1, x1, x0
 ;;       mov     w0, w1
 ;;       add     sp, sp, #0x10

tests/disas/winch/aarch64/i32_divu/zero_zero.wat

@@ -23,8 +23,8 @@
 ;;       mov     x16, #0
 ;;       mov     w1, w16
 ;;       cbz     x0, #0x54
-;;   34: sxtw    x0, w0
-;;       sxtw    x1, w1
+;;   34: mov     w0, w0
+;;       mov     w1, w1
 ;;       udiv    x1, x1, x0
 ;;       mov     w0, w1
 ;;       add     sp, sp, #0x10

winch/codegen/src/isa/aarch64/asm.rs

@@ -407,23 +407,21 @@ impl Assembler {
         kind: DivKind,
         size: OperandSize,
     ) {
-        // Check for division by 0
-        self.emit(Inst::TrapIf {
-            kind: CondBrKind::Zero(divisor.into()),
-            trap_code: TrapCode::INTEGER_DIVISION_BY_ZERO,
-        });
+        // Check for division by 0.
+        self.trapz(divisor, TrapCode::INTEGER_DIVISION_BY_ZERO);
 
         // check for overflow
         if kind == DivKind::Signed {
-            // we first check whether the divisor is -1
-            self.emit(Inst::AluRRImm12 {
-                alu_op: ALUOp::AddS,
-                size: size.into(),
-                rd: writable!(zero().into()),
-                rn: divisor.into(),
-                imm12: Imm12::maybe_from_u64(1).expect("1 fits in 12 bits"),
-            });
-            // if it is -1, then we check if the dividend is MIN
+            // Check for divisor overflow.
+            self.emit_alu_rri(
+                ALUOp::AddS,
+                Imm12::maybe_from_u64(1).expect("1 to fit in 12 bits"),
+                divisor,
+                writable!(zero()),
+                size,
+            );
+
+            // Check if the dividend is 1.
             self.emit(Inst::CCmpImm {
                 size: size.into(),
                 rn: dividend.into(),
@@ -432,31 +430,22 @@ impl Assembler {
                 cond: Cond::Eq,
             });
 
-            // Finally, trap if the previous operation overflowed
-            self.emit(Inst::TrapIf {
-                kind: CondBrKind::Cond(Cond::Vs),
-                trap_code: TrapCode::INTEGER_OVERFLOW,
-            })
+            // Finally, trap if the previous operation overflowed.
+            self.trapif(Cond::Vs, TrapCode::INTEGER_OVERFLOW);
         }
 
         // `cranelift-codegen` doesn't support emitting u/sdiv for anything but I64,
         // we therefore sign-extend the operand.
         // see: https://github.com/bytecodealliance/wasmtime/issues/9766
         if size == OperandSize::S32 {
-            self.emit(Inst::Extend {
-                rd: writable!(divisor.into()),
-                rn: divisor.into(),
-                signed: true,
-                from_bits: 32,
-                to_bits: 64,
-            });
-            self.emit(Inst::Extend {
-                rd: writable!(dividend.into()),
-                rn: dividend.into(),
-                signed: true,
-                from_bits: 32,
-                to_bits: 64,
-            });
+            let extend_kind = if kind == DivKind::Signed {
+                ExtendKind::I64Extend32S
+            } else {
+                ExtendKind::I64ExtendI32U
+            };
+
+            self.extend(divisor, writable!(divisor), extend_kind);
+            self.extend(dividend, writable!(dividend), extend_kind);
         }
 
         let op = match kind {

winch/codegen/src/masm.rs

@@ -163,6 +163,7 @@ pub(crate) enum ShiftKind {
 /// Kinds of extends in WebAssembly. Each MacroAssembler implementation
 /// is responsible for emitting the correct sequence of instructions when
 /// lowering to machine code.
+#[derive(Copy, Clone)]
 pub(crate) enum ExtendKind {
     /// Sign extends i32 to i64.
     I64ExtendI32S,