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pulley: Finish simd proposal implementation (#9935)
* pulley: Finish `simd` proposal implementation This commit fills out the final and miscellaneous set of opcodes for Pulley to have a complete implementation of the `simd` proposal for WebAssembly. All spec tests are now enabled and the Pulley-specific exceptions for `*.wast` tests are all gone. Closes #9783 * Remove stray build script
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+313
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lines changed

‎cranelift/codegen/src/isa/pulley_shared/lower.isle

+20
Original file line numberDiff line numberDiff line change
@@ -1041,6 +1041,9 @@
10411041
(rule 1 (lower (has_type $F64 (select c a b)))
10421042
(pulley_fselect64 (emit_cond (lower_cond c)) a b))
10431043

1044+
(rule 2 (lower (has_type (ty_vec128 _) (select c a b)))
1045+
(pulley_vselect (emit_cond (lower_cond c)) a b))
1046+
10441047
;; Helper to emit a conditional into a register itself.
10451048
(decl emit_cond (Cond) XReg)
10461049
(rule (emit_cond (Cond.If32 reg)) reg)
@@ -1213,6 +1216,18 @@
12131216
(rule (lower (has_type $I64 (fcvt_to_sint_sat val @ (value_type $F64))))
12141217
(pulley_x64_from_f64_s_sat val))
12151218

1219+
(rule (lower (has_type $I32X4 (fcvt_to_sint_sat val @ (value_type $F32X4))))
1220+
(pulley_vi32x4_from_f32x4_s val))
1221+
1222+
(rule (lower (has_type $I32X4 (fcvt_to_uint_sat val @ (value_type $F32X4))))
1223+
(pulley_vi32x4_from_f32x4_u val))
1224+
1225+
(rule (lower (has_type $I64X2 (fcvt_to_sint_sat val @ (value_type $F64X2))))
1226+
(pulley_vi64x2_from_f64x2_s val))
1227+
1228+
(rule (lower (has_type $I64X2 (fcvt_to_uint_sat val @ (value_type $F64X2))))
1229+
(pulley_vi64x2_from_f64x2_u val))
1230+
12161231
;;;; Rules for `fdemote` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
12171232

12181233
(rule (lower (has_type $F32 (fdemote val @ (value_type $F64))))
@@ -1429,12 +1444,17 @@
14291444

14301445
(rule (lower (snarrow a @ (value_type $I16X8) b)) (pulley_vnarrow16x8_s a b))
14311446
(rule (lower (snarrow a @ (value_type $I32X4) b)) (pulley_vnarrow32x4_s a b))
1447+
(rule (lower (snarrow a @ (value_type $I64X2) b)) (pulley_vnarrow64x2_s a b))
14321448

14331449
;;;; Rules for `unarrow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
14341450

14351451
(rule (lower (unarrow a @ (value_type $I16X8) b)) (pulley_vnarrow16x8_u a b))
14361452
(rule (lower (unarrow a @ (value_type $I32X4) b)) (pulley_vnarrow32x4_u a b))
14371453

1454+
;;;; Rules for `uunarrow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1455+
1456+
(rule (lower (uunarrow a @ (value_type $I64X2) b)) (pulley_vunarrow64x2_u a b))
1457+
14381458
;;;; Rules for `fvpromote_low` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
14391459

14401460
(rule (lower (fvpromote_low a @ (value_type $F32X4))) (pulley_vfpromotelow a))

‎cranelift/filetests/filetests/runtests/simd-arithmetic.clif

+4
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,10 @@ target x86_64 sse42 has_avx
99
set enable_multi_ret_implicit_sret
1010
target riscv64 has_v
1111
target riscv64 has_v has_c has_zcb
12+
target pulley32
13+
target pulley32be
14+
target pulley64
15+
target pulley64be
1216

1317

1418
function %sadd_sat_i8x16(i8x16, i8x16) -> i8x16 {

‎cranelift/filetests/filetests/runtests/simd-avg-round.clif

+4
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,10 @@ target x86_64 skylake
66
set enable_multi_ret_implicit_sret
77
target riscv64 has_v
88
target riscv64 has_v has_c has_zcb
9+
target pulley32
10+
target pulley32be
11+
target pulley64
12+
target pulley64be
913

1014
function %average_rounding_i8x16(i8x16, i8x16) -> i8x16 {
1115
block0(v0: i8x16, v1: i8x16):

‎cranelift/filetests/filetests/runtests/simd-band-splat.clif

+4
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,10 @@ target x86_64 sse42 has_avx
99
set enable_multi_ret_implicit_sret
1010
target riscv64 has_v
1111
target riscv64 has_v has_c has_zcb
12+
target pulley32
13+
target pulley32be
14+
target pulley64
15+
target pulley64be
1216

1317
function %band_splat_const_i8x16(i8x16) -> i8x16 {
1418
block0(v0: i8x16):

‎cranelift/filetests/filetests/runtests/simd-bitcast.clif

+4
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,10 @@ target s390x
77
set enable_multi_ret_implicit_sret
88
target riscv64 has_v
99
target riscv64 has_v has_c has_zcb
10+
target pulley32
11+
target pulley32be
12+
target pulley64
13+
target pulley64be
1014

1115
function %bitcast_if32x4(i32x4) -> f32x4 {
1216
block0(v0: i32x4):

‎cranelift/filetests/filetests/runtests/simd-bitselect-to-vselect.clif

+4
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,10 @@ target x86_64 skylake
77
set enable_multi_ret_implicit_sret
88
target riscv64 has_v
99
target riscv64 has_v has_c has_zcb
10+
target pulley32
11+
target pulley32be
12+
target pulley64
13+
target pulley64be
1014

1115
function %mask_from_icmp(i32x4, i32x4) -> i32x4 {
1216
block0(v0: i32x4, v1: i32x4):

‎cranelift/filetests/filetests/runtests/simd-bitselect.clif

+8
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,10 @@ set enable_multi_ret_implicit_sret
77
target riscv64 has_v
88
target riscv64 has_v has_c has_zcb
99
set enable_multi_ret_implicit_sret=false
10+
target pulley32
11+
target pulley32be
12+
target pulley64
13+
target pulley64be
1014

1115
set opt_level=speed
1216
target aarch64
@@ -16,6 +20,10 @@ target x86_64 has_sse3 has_ssse3 has_sse41 has_avx
1620
set enable_multi_ret_implicit_sret
1721
target riscv64 has_v
1822
target riscv64 has_v has_c has_zcb
23+
target pulley32
24+
target pulley32be
25+
target pulley64
26+
target pulley64be
1927

2028
function %bitselect_i64x2(i64x2, i64x2, i64x2) -> i64x2 {
2129
block0(v0: i64x2, v1: i64x2, v2: i64x2):

‎cranelift/filetests/filetests/runtests/simd-bor-splat.clif

+4
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,10 @@ target x86_64 sse42 has_avx
88
set enable_multi_ret_implicit_sret
99
target riscv64 has_v
1010
target riscv64 has_v has_c has_zcb
11+
target pulley32
12+
target pulley32be
13+
target pulley64
14+
target pulley64be
1115

1216
function %bor_splat_const_i8x16(i8x16) -> i8x16 {
1317
block0(v0: i8x16):

‎cranelift/filetests/filetests/runtests/simd-bxor-splat.clif

+4
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,10 @@ target x86_64 sse42 has_avx
99
set enable_multi_ret_implicit_sret
1010
target riscv64 has_v
1111
target riscv64 has_v has_c has_zcb
12+
target pulley32
13+
target pulley32be
14+
target pulley64
15+
target pulley64be
1216

1317
function %bxor_splat_const_i8x16(i8x16) -> i8x16 {
1418
block0(v0: i8x16):

‎cranelift/filetests/filetests/runtests/simd-ceil.clif

+4
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,10 @@ target s390x
99
set enable_multi_ret_implicit_sret
1010
target riscv64 has_v
1111
target riscv64 has_v has_c has_zcb
12+
target pulley32
13+
target pulley32be
14+
target pulley64
15+
target pulley64be
1216

1317
function %ceil_f32x4(f32x4) -> f32x4 {
1418
block0(v0: f32x4):

‎cranelift/filetests/filetests/runtests/simd-fcvt-to-sint-sat.clif

+4
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,10 @@ target x86_64 sse42 has_avx
99
set enable_multi_ret_implicit_sret
1010
target riscv64 has_v
1111
target riscv64 has_v has_c has_zcb
12+
target pulley32
13+
target pulley32be
14+
target pulley64
15+
target pulley64be
1216

1317
function %fcvt_to_sint_sat(f32x4) -> i32x4 {
1418
block0(v0:f32x4):

‎cranelift/filetests/filetests/runtests/simd-fcvt-to-uint-sat.clif

+4
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,10 @@ target x86_64 sse42 has_avx
99
set enable_multi_ret_implicit_sret
1010
target riscv64 has_v
1111
target riscv64 has_v has_c has_zcb
12+
target pulley32
13+
target pulley32be
14+
target pulley64
15+
target pulley64be
1216

1317
function %fcvt_to_uint_sat(f32x4) -> i32x4 {
1418
block0(v0:f32x4):

‎cranelift/filetests/filetests/runtests/simd-iabs.clif

+4
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,10 @@ target x86_64 sse42 has_avx
1010
set enable_multi_ret_implicit_sret
1111
target riscv64 has_v
1212
target riscv64 has_v has_c has_zcb
13+
target pulley32
14+
target pulley32be
15+
target pulley64
16+
target pulley64be
1317

1418
function %iabs_i8x16(i8x16) -> i8x16 {
1519
block0(v0: i8x16):

‎cranelift/filetests/filetests/runtests/simd-iadd-splat.clif

+4
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,10 @@ target x86_64 sse42 has_avx
88
set enable_multi_ret_implicit_sret
99
target riscv64 has_v
1010
target riscv64 has_v has_c has_zcb
11+
target pulley32
12+
target pulley32be
13+
target pulley64
14+
target pulley64be
1115

1216
function %iadd_splat_const_i8x16(i8x16) -> i8x16 {
1317
block0(v0: i8x16):

‎cranelift/filetests/filetests/runtests/simd-iadd-swiden-high.clif

+4
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,10 @@ target x86_64 sse41 has_avx
88
set enable_multi_ret_implicit_sret
99
target riscv64 has_v
1010
target riscv64 has_v has_c has_zcb
11+
target pulley32
12+
target pulley32be
13+
target pulley64
14+
target pulley64be
1115

1216

1317
function %iadd_swidenhigh_i32x4(i32x4, i32x4) -> i64x2 {

‎cranelift/filetests/filetests/runtests/simd-iadd-swiden-low.clif

+4
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,10 @@ target x86_64 sse41 has_avx
88
set enable_multi_ret_implicit_sret
99
target riscv64 has_v
1010
target riscv64 has_v has_c has_zcb
11+
target pulley32
12+
target pulley32be
13+
target pulley64
14+
target pulley64be
1115

1216

1317
function %iadd_swidenlow_i32x4(i32x4, i32x4) -> i64x2 {

‎cranelift/filetests/filetests/runtests/simd-iadd-swiden-mix.clif

+4
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,10 @@ target x86_64 sse41 has_avx
88
set enable_multi_ret_implicit_sret
99
target riscv64 has_v
1010
target riscv64 has_v has_c has_zcb
11+
target pulley32
12+
target pulley32be
13+
target pulley64
14+
target pulley64be
1115

1216

1317
function %iadd_swiden_high_low_i32x4(i32x4, i32x4) -> i64x2 {

‎cranelift/filetests/filetests/runtests/simd-iadd-uwiden-high.clif

+4
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,10 @@ target x86_64 sse41 has_avx
88
set enable_multi_ret_implicit_sret
99
target riscv64 has_v
1010
target riscv64 has_v has_c has_zcb
11+
target pulley32
12+
target pulley32be
13+
target pulley64
14+
target pulley64be
1115

1216

1317
function %iadd_uwidenhigh_i32x4(i32x4, i32x4) -> i64x2 {

‎cranelift/filetests/filetests/runtests/simd-iadd-uwiden-low.clif

+4
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,10 @@ target x86_64 sse41 has_avx
88
set enable_multi_ret_implicit_sret
99
target riscv64 has_v
1010
target riscv64 has_v has_c has_zcb
11+
target pulley32
12+
target pulley32be
13+
target pulley64
14+
target pulley64be
1115

1216

1317
function %iadd_uwidenlow_i32x4(i32x4, i32x4) -> i64x2 {

‎cranelift/filetests/filetests/runtests/simd-iadd-uwiden-mix.clif

+4
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,10 @@ target x86_64 sse41 has_avx
88
set enable_multi_ret_implicit_sret
99
target riscv64 has_v
1010
target riscv64 has_v has_c has_zcb
11+
target pulley32
12+
target pulley32be
13+
target pulley64
14+
target pulley64be
1115

1216

1317
function %iadd_uwiden_high_low_i32x4(i32x4, i32x4) -> i64x2 {

‎cranelift/filetests/filetests/runtests/simd-ifma.clif

+4
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,10 @@ target x86_64 skylake
66
set enable_multi_ret_implicit_sret
77
target riscv64 has_v
88
target riscv64 has_v has_c has_zcb
9+
target pulley32
10+
target pulley32be
11+
target pulley64
12+
target pulley64be
913

1014
;; These tests test integer fused multiply add/subtract instructions.
1115

‎cranelift/filetests/filetests/runtests/simd-insert-extract-lane.clif

+4
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,10 @@ target x86_64 sse42 has_avx
88
set enable_multi_ret_implicit_sret
99
target riscv64 has_v
1010
target riscv64 has_v has_c has_zcb
11+
target pulley32
12+
target pulley32be
13+
target pulley64
14+
target pulley64be
1115

1216
function %insertlane_preserves_upper_bits(f64) -> i64 fast {
1317
block0(v5: f64):

‎cranelift/filetests/filetests/runtests/simd-ishl.clif

+4
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,10 @@ target x86_64 skylake
77
set enable_multi_ret_implicit_sret
88
target riscv64 has_v
99
target riscv64 has_v has_c has_zcb
10+
target pulley32
11+
target pulley32be
12+
target pulley64
13+
target pulley64be
1014

1115

1216
function %ishl_i8x16(i8x16, i32) -> i8x16 {

‎cranelift/filetests/filetests/runtests/simd-isub-splat.clif

+4
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,10 @@ target x86_64 sse42 has_avx
88
set enable_multi_ret_implicit_sret
99
target riscv64 has_v
1010
target riscv64 has_v has_c has_zcb
11+
target pulley32
12+
target pulley32be
13+
target pulley64
14+
target pulley64be
1115

1216

1317
function %isub_splat_reverse_i8x16(i8x16, i8) -> i8x16 {

‎cranelift/filetests/filetests/runtests/simd-isub-swiden-high.clif

+4
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,10 @@ target x86_64 sse41 has_avx
88
set enable_multi_ret_implicit_sret
99
target riscv64 has_v
1010
target riscv64 has_v has_c has_zcb
11+
target pulley32
12+
target pulley32be
13+
target pulley64
14+
target pulley64be
1115

1216

1317
function %isub_swidenhigh_i32x4(i32x4, i32x4) -> i64x2 {

‎cranelift/filetests/filetests/runtests/simd-isub-swiden-low.clif

+4
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,10 @@ target x86_64 sse41 has_avx
88
set enable_multi_ret_implicit_sret
99
target riscv64 has_v
1010
target riscv64 has_v has_c has_zcb
11+
target pulley32
12+
target pulley32be
13+
target pulley64
14+
target pulley64be
1115

1216

1317
function %isub_swidenlow_i32x4(i32x4, i32x4) -> i64x2 {

‎cranelift/filetests/filetests/runtests/simd-isub-uwiden-high.clif

+4
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,10 @@ target x86_64 sse41 has_avx
88
set enable_multi_ret_implicit_sret
99
target riscv64 has_v
1010
target riscv64 has_v has_c has_zcb
11+
target pulley32
12+
target pulley32be
13+
target pulley64
14+
target pulley64be
1115

1216

1317
function %isub_uwidenhigh_i32x4(i32x4, i32x4) -> i64x2 {

‎cranelift/filetests/filetests/runtests/simd-isub-uwiden-low.clif

+4
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,10 @@ target x86_64 sse41 has_avx
88
set enable_multi_ret_implicit_sret
99
target riscv64 has_v
1010
target riscv64 has_v has_c has_zcb
11+
target pulley32
12+
target pulley32be
13+
target pulley64
14+
target pulley64be
1115

1216

1317
function %isub_uwidenlow_i32x4(i32x4, i32x4) -> i64x2 {

‎cranelift/filetests/filetests/runtests/simd-lane-access.clif

+4
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,10 @@ target x86_64 has_sse3 has_ssse3 has_sse41 has_avx
66
set enable_multi_ret_implicit_sret
77
target riscv64 has_v
88
target riscv64 has_v has_c has_zcb
9+
target pulley32
10+
target pulley32be
11+
target pulley64
12+
target pulley64be
913

1014
;; shuffle
1115

‎cranelift/filetests/filetests/runtests/simd-logical.clif

+4
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,10 @@ target x86_64 has_sse3 has_ssse3 has_sse41 has_avx
66
set enable_multi_ret_implicit_sret
77
target riscv64 has_v
88
target riscv64 has_v has_c has_zcb
9+
target pulley32
10+
target pulley32be
11+
target pulley64
12+
target pulley64be
913

1014
function %bnot() -> i32 {
1115
block0:

‎cranelift/filetests/filetests/runtests/simd-make-vectors.clif

+4
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,10 @@ target x86_64 sse42 has_avx
88
set enable_multi_ret_implicit_sret
99
target riscv64 has_v
1010
target riscv64 has_v has_c has_zcb
11+
target pulley32
12+
target pulley32be
13+
target pulley64
14+
target pulley64be
1115

1216
function %i64x2_make0() -> i64x2 {
1317
block0:

‎cranelift/filetests/filetests/runtests/simd-nearest.clif

+4
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,10 @@ target s390x
99
set enable_multi_ret_implicit_sret
1010
target riscv64 has_v
1111
target riscv64 has_v has_c has_zcb
12+
target pulley32
13+
target pulley32be
14+
target pulley64
15+
target pulley64be
1216

1317
function %nearest_f32x4(f32x4) -> f32x4 {
1418
block0(v0: f32x4):

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