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/* SPDX-License-Identifier: MIT */
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/*
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- * Copyright (c) 2020-2023 , Intel Corporation.
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+ * Copyright (c) 2020-2024 , Intel Corporation.
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*/
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#ifndef VPU_BOOT_API_H
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#define VPU_BOOT_API_H
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/*
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- * =========== FW API version information beginning ================
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* The below values will be used to construct the version info this way:
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* fw_bin_header->api_version[VPU_BOOT_API_VER_ID] = (VPU_BOOT_API_VER_MAJOR << 16) |
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* VPU_BOOT_API_VER_MINOR;
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* Minor version changes when API backward compatibility is preserved.
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* Resets to 0 if Major version is incremented.
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*/
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- #define VPU_BOOT_API_VER_MINOR 24
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+ #define VPU_BOOT_API_VER_MINOR 26
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/*
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* API header changed (field names, documentation, formatting) but API itself has not been changed
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*/
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- #define VPU_BOOT_API_VER_PATCH 0
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+ #define VPU_BOOT_API_VER_PATCH 3
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/*
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* Index in the API version table
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* Must be unique for each API
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*/
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#define VPU_BOOT_API_VER_INDEX 0
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- /* ------------ FW API version information end ---------------------*/
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#pragma pack(push, 4)
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@@ -164,8 +162,6 @@ enum vpu_trace_destination {
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/* VPU 30xx HW component IDs are sequential, so define first and last IDs. */
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#define VPU_TRACE_PROC_BIT_30XX_FIRST VPU_TRACE_PROC_BIT_LRT
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#define VPU_TRACE_PROC_BIT_30XX_LAST VPU_TRACE_PROC_BIT_SHV_15
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- #define VPU_TRACE_PROC_BIT_KMB_FIRST VPU_TRACE_PROC_BIT_30XX_FIRST
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- #define VPU_TRACE_PROC_BIT_KMB_LAST VPU_TRACE_PROC_BIT_30XX_LAST
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struct vpu_boot_l2_cache_config {
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u8 use ;
@@ -199,6 +195,17 @@ struct vpu_warm_boot_section {
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*/
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#define POWER_PROFILE_SURVIVABILITY 0x1
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+ /**
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+ * Enum for dvfs_mode boot param.
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+ */
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+ enum vpu_governor {
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+ VPU_GOV_DEFAULT = 0 , /* Default Governor for the system */
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+ VPU_GOV_MAX_PERFORMANCE = 1 , /* Maximum performance governor */
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+ VPU_GOV_ON_DEMAND = 2 , /* On Demand frequency control governor */
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+ VPU_GOV_POWER_SAVE = 3 , /* Power save governor */
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+ VPU_GOV_ON_DEMAND_PRIORITY_AWARE = 4 /* On Demand priority based governor */
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+ };
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+
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struct vpu_boot_params {
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u32 magic ;
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u32 vpu_id ;
@@ -301,7 +308,14 @@ struct vpu_boot_params {
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u32 temp_sensor_period_ms ;
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/** PLL ratio for efficient clock frequency */
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u32 pn_freq_pll_ratio ;
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- /** DVFS Mode: Default: 0, Max Performance: 1, On Demand: 2, Power Save: 3 */
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+ /**
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+ * DVFS Mode:
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+ * 0 - Default, DVFS mode selected by the firmware
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+ * 1 - Max Performance
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+ * 2 - On Demand
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+ * 3 - Power Save
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+ * 4 - On Demand Priority Aware
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+ */
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u32 dvfs_mode ;
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/**
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* Depending on DVFS Mode:
@@ -332,8 +346,8 @@ struct vpu_boot_params {
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u64 d0i3_entry_vpu_ts ;
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/*
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* The system time of the host operating system in microseconds.
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- * E.g the number of microseconds since 1st of January 1970, or whatever date the
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- * host operating system uses to maintain system time.
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+ * E.g the number of microseconds since 1st of January 1970, or whatever
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+ * date the host operating system uses to maintain system time.
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* This value will be used to track system time on the VPU.
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* The KMD is required to update this value on every VPU reset.
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*/
@@ -382,10 +396,7 @@ struct vpu_boot_params {
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u32 pad6 [734 ];
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};
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- /*
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- * Magic numbers set between host and vpu to detect corruptio of tracing init
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- */
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-
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+ /* Magic numbers set between host and vpu to detect corruption of tracing init */
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#define VPU_TRACING_BUFFER_CANARY (0xCAFECAFE)
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/* Tracing buffer message format definitions */
@@ -405,7 +416,9 @@ struct vpu_tracing_buffer_header {
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u32 host_canary_start ;
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/* offset from start of buffer for trace entries */
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u32 read_index ;
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- u32 pad_to_cache_line_size_0 [14 ];
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+ /* keeps track of wrapping on the reader side */
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+ u32 read_wrap_count ;
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+ u32 pad_to_cache_line_size_0 [13 ];
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/* End of first cache line */
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/**
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