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358 | 358 | #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
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359 | 359 | #define CMD_HDR_TLR_CTRL_OFF 6
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360 | 360 | #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
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| 361 | +#define CMD_HDR_PHY_ID_OFF 8 |
| 362 | +#define CMD_HDR_PHY_ID_MSK (0x1ff << CMD_HDR_PHY_ID_OFF) |
| 363 | +#define CMD_HDR_FORCE_PHY_OFF 17 |
| 364 | +#define CMD_HDR_FORCE_PHY_MSK (0x1U << CMD_HDR_FORCE_PHY_OFF) |
361 | 365 | #define CMD_HDR_PORT_OFF 18
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362 | 366 | #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
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363 | 367 | #define CMD_HDR_PRIORITY_OFF 27
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@@ -1425,15 +1429,21 @@ static void prep_ata_v3_hw(struct hisi_hba *hisi_hba,
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1425 | 1429 | struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
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1426 | 1430 | struct asd_sas_port *sas_port = device->port;
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1427 | 1431 | struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
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| 1432 | + int phy_id; |
1428 | 1433 | u8 *buf_cmd;
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1429 | 1434 | int has_data = 0, hdr_tag = 0;
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1430 | 1435 | u32 dw1 = 0, dw2 = 0;
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1431 | 1436 |
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1432 | 1437 | hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
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1433 |
| - if (parent_dev && dev_is_expander(parent_dev->dev_type)) |
| 1438 | + if (parent_dev && dev_is_expander(parent_dev->dev_type)) { |
1434 | 1439 | hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
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1435 |
| - else |
| 1440 | + } else { |
| 1441 | + phy_id = device->phy->identify.phy_identifier; |
| 1442 | + hdr->dw0 |= cpu_to_le32((1U << phy_id) |
| 1443 | + << CMD_HDR_PHY_ID_OFF); |
| 1444 | + hdr->dw0 |= CMD_HDR_FORCE_PHY_MSK; |
1436 | 1445 | hdr->dw0 |= cpu_to_le32(4U << CMD_HDR_CMD_OFF);
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| 1446 | + } |
1437 | 1447 |
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1438 | 1448 | switch (task->data_dir) {
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1439 | 1449 | case DMA_TO_DEVICE:
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