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3 | 3 | #define CONFIG_UART_INTERRUPT_DRIVEN 1 |
4 | 4 | #define CONFIG_I2C 1 |
5 | 5 | #define CONFIG_SPI 1 |
| 6 | +#define CONFIG_SPI_STM32_INTERRUPT 1 |
6 | 7 | #define CONFIG_NUM_IRQS 150 |
7 | 8 | #define CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC 480000000 |
8 | 9 | #define CONFIG_FLASH_SIZE 1024 |
9 | 10 | #define CONFIG_FLASH_BASE_ADDRESS 0x8000000 |
10 | 11 | #define CONFIG_MP_MAX_NUM_CPUS 1 |
11 | | -#define CONFIG_MAIN_STACK_SIZE 32768 |
| 12 | +#define CONFIG_MAIN_STACK_SIZE 8192 |
12 | 13 | #define CONFIG_IDLE_STACK_SIZE 320 |
13 | 14 | #define CONFIG_ISR_STACK_SIZE 2048 |
14 | 15 | #define CONFIG_CLOCK_CONTROL 1 |
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22 | 23 | #define CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION 1 |
23 | 24 | #define CONFIG_STM32H7_DUAL_CORE 1 |
24 | 25 | #define CONFIG_TICKLESS_KERNEL 1 |
| 26 | +#define CONFIG_ENTROPY_STM32_CLK_CHECK 1 |
25 | 27 | #define CONFIG_FPU 1 |
26 | 28 | #define CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE 1024 |
27 | 29 | #define CONFIG_CORTEX_M_SYSTICK 1 |
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49 | 51 | #define CONFIG_BUILD_OUTPUT_HEX 1 |
50 | 52 | #define CONFIG_UART_USE_RUNTIME_CONFIGURE 1 |
51 | 53 | #define CONFIG_SERIAL_INIT_PRIORITY 50 |
| 54 | +#define CONFIG_ENTROPY_INIT_PRIORITY 50 |
52 | 55 | #define CONFIG_COMMON_LIBC_MALLOC_ARENA_SIZE -1 |
53 | 56 | #define CONFIG_SOC_TOOLCHAIN_NAME "amd_acp_6_0_adsp" |
54 | 57 | #define CONFIG_GEN_SW_ISR_TABLE 1 |
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66 | 69 | #define CONFIG_DT_HAS_ARM_V7M_NVIC_ENABLED 1 |
67 | 70 | #define CONFIG_DT_HAS_FIXED_CLOCK_ENABLED 1 |
68 | 71 | #define CONFIG_DT_HAS_FIXED_PARTITIONS_ENABLED 1 |
| 72 | +#define CONFIG_DT_HAS_GALAXYCORE_GC2145_ENABLED 1 |
69 | 73 | #define CONFIG_DT_HAS_GPIO_KEYS_ENABLED 1 |
70 | 74 | #define CONFIG_DT_HAS_GPIO_LEDS_ENABLED 1 |
71 | 75 | #define CONFIG_DT_HAS_INFINEON_CYW43XXX_BT_HCI_ENABLED 1 |
72 | 76 | #define CONFIG_DT_HAS_MMIO_SRAM_ENABLED 1 |
73 | | -#define CONFIG_DT_HAS_OVTI_OV7670_ENABLED 1 |
74 | 77 | #define CONFIG_DT_HAS_PWM_CLOCK_ENABLED 1 |
75 | 78 | #define CONFIG_DT_HAS_SOC_NV_FLASH_ENABLED 1 |
76 | 79 | #define CONFIG_DT_HAS_ST_MBOX_STM32_HSEM_ENABLED 1 |
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111 | 114 | #define CONFIG_DT_HAS_ZEPHYR_BT_HCI_UART_ENABLED 1 |
112 | 115 | #define CONFIG_DT_HAS_ZEPHYR_CDC_ACM_UART_ENABLED 1 |
113 | 116 | #define CONFIG_DT_HAS_ZEPHYR_MEMORY_REGION_ENABLED 1 |
114 | | -#define CONFIG_TAINT_BLOBS 1 |
115 | 117 | #define CONFIG_ZEPHYR_ARDUINO_API_MODULE 1 |
116 | 118 | #define CONFIG_ZEPHYR_CMSIS_MODULE 1 |
117 | 119 | #define CONFIG_HAS_CMSIS_CORE 1 |
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124 | 126 | #define CONFIG_ZEPHYR_HAL_INTEL_MODULE 1 |
125 | 127 | #define CONFIG_ZEPHYR_HAL_NORDIC_MODULE 1 |
126 | 128 | #define CONFIG_ZEPHYR_HAL_NXP_MODULE 1 |
127 | | -#define CONFIG_ZEPHYR_HAL_NXP_MODULE_BLOBS 1 |
128 | 129 | #define CONFIG_ZEPHYR_HAL_RENESAS_MODULE 1 |
129 | 130 | #define CONFIG_ZEPHYR_HAL_RPI_PICO_MODULE 1 |
130 | 131 | #define CONFIG_ZEPHYR_HAL_SILABS_MODULE 1 |
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138 | 139 | #define CONFIG_ZEPHYR_TINYCRYPT_MODULE 1 |
139 | 140 | #define CONFIG_HAS_STM32CUBE 1 |
140 | 141 | #define CONFIG_USE_STM32_HAL_CORTEX 1 |
| 142 | +#define CONFIG_USE_STM32_HAL_DCMI 1 |
| 143 | +#define CONFIG_USE_STM32_HAL_DMA 1 |
| 144 | +#define CONFIG_USE_STM32_HAL_DMA_EX 1 |
141 | 145 | #define CONFIG_USE_STM32_HAL_MDMA 1 |
142 | 146 | #define CONFIG_USE_STM32_HAL_PCD 1 |
143 | 147 | #define CONFIG_USE_STM32_HAL_PCD_EX 1 |
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146 | 150 | #define CONFIG_USE_STM32_LL_DMA 1 |
147 | 151 | #define CONFIG_USE_STM32_LL_FMC 1 |
148 | 152 | #define CONFIG_USE_STM32_LL_RCC 1 |
| 153 | +#define CONFIG_USE_STM32_LL_RNG 1 |
149 | 154 | #define CONFIG_USE_STM32_LL_SPI 1 |
150 | 155 | #define CONFIG_USE_STM32_LL_TIM 1 |
151 | 156 | #define CONFIG_USE_STM32_LL_USB 1 |
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255 | 260 | #define CONFIG_POLL 1 |
256 | 261 | #define CONFIG_NUM_MBOX_ASYNC_MSGS 10 |
257 | 262 | #define CONFIG_KERNEL_MEM_POOL 1 |
258 | | -#define CONFIG_HEAP_MEM_POOL_SIZE 32768 |
| 263 | +#define CONFIG_HEAP_MEM_POOL_SIZE 2048 |
259 | 264 | #define CONFIG_SWAP_NONATOMIC 1 |
260 | 265 | #define CONFIG_TIMEOUT_64BIT 1 |
261 | 266 | #define CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS 365 |
| 267 | +#define CONFIG_STACK_POINTER_RANDOM 0 |
262 | 268 | #define CONFIG_TOOLCHAIN_SUPPORTS_THREAD_LOCAL_STORAGE 1 |
263 | 269 | #define CONFIG_THREAD_LOCAL_STORAGE 1 |
264 | 270 | #define CONFIG_KERNEL_WHOLE_ARCHIVE 1 |
265 | 271 | #define CONFIG_TOOLCHAIN_SUPPORTS_STATIC_INIT_GNU 1 |
| 272 | +#define CONFIG_STATIC_INIT_GNU 1 |
266 | 273 | #define CONFIG_DEVICE_DT_METADATA 1 |
267 | 274 | #define CONFIG_KERNEL_INIT_PRIORITY_OBJECTS 30 |
268 | 275 | #define CONFIG_KERNEL_INIT_PRIORITY_LIBC 35 |
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298 | 305 | #define CONFIG_DMAMUX_STM32 1 |
299 | 306 | #define CONFIG_DMAMUX_STM32_INIT_PRIORITY 41 |
300 | 307 | #define CONFIG_DMA_ESP32_MAX_DESCRIPTOR_NUM 16 |
| 308 | +#define CONFIG_ENTROPY_GENERATOR 1 |
| 309 | +#define CONFIG_ENTROPY_LOG_LEVEL_DEFAULT 1 |
| 310 | +#define CONFIG_ENTROPY_LOG_LEVEL 3 |
| 311 | +#define CONFIG_ENTROPY_STM32_RNG 1 |
| 312 | +#define CONFIG_ENTROPY_STM32_THR_POOL_SIZE 8 |
| 313 | +#define CONFIG_ENTROPY_STM32_THR_THRESHOLD 4 |
| 314 | +#define CONFIG_ENTROPY_STM32_ISR_POOL_SIZE 16 |
| 315 | +#define CONFIG_ENTROPY_STM32_ISR_THRESHOLD 12 |
| 316 | +#define CONFIG_ENTROPY_HAS_DRIVER 1 |
301 | 317 | #define CONFIG_FLASH_HAS_DRIVER_ENABLED 1 |
302 | 318 | #define CONFIG_FLASH_HAS_EXPLICIT_ERASE 1 |
303 | 319 | #define CONFIG_FLASH_HAS_PAGE_LAYOUT 1 |
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351 | 367 | #define CONFIG_UART_LOG_LEVEL 3 |
352 | 368 | #define CONFIG_UART_LINE_CTRL 1 |
353 | 369 | #define CONFIG_UART_STM32 1 |
| 370 | +#define CONFIG_SPI_ASYNC 1 |
354 | 371 | #define CONFIG_SPI_INIT_PRIORITY 50 |
355 | 372 | #define CONFIG_SPI_COMPLETION_TIMEOUT_TOLERANCE 200 |
356 | 373 | #define CONFIG_SPI_LOG_LEVEL_DEFAULT 1 |
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373 | 390 | #define CONFIG_NRF_USBD_COMMON_LOG_LEVEL 3 |
374 | 391 | #define CONFIG_USBC_LOG_LEVEL_DEFAULT 1 |
375 | 392 | #define CONFIG_USBC_LOG_LEVEL 3 |
376 | | -#define CONFIG_SHELL_STACK_SIZE 2048 |
| 393 | +#define CONFIG_VIDEO 1 |
| 394 | +#define CONFIG_VIDEO_LOG_LEVEL_DBG 1 |
| 395 | +#define CONFIG_VIDEO_LOG_LEVEL 4 |
| 396 | +#define CONFIG_VIDEO_INIT_PRIORITY 60 |
| 397 | +#define CONFIG_VIDEO_BUFFER_POOL_SZ_MAX 160000 |
| 398 | +#define CONFIG_VIDEO_BUFFER_POOL_NUM_MAX 1 |
| 399 | +#define CONFIG_VIDEO_BUFFER_POOL_ALIGN 32 |
| 400 | +#define CONFIG_VIDEO_STM32_DCMI 1 |
| 401 | +#define CONFIG_VIDEO_GC2145 1 |
| 402 | +#define CONFIG_VIDEO_EMUL_IMAGER_FRAMEBUFFER_SIZE 4096 |
| 403 | +#define CONFIG_SHELL_STACK_SIZE 8192 |
377 | 404 | #define CONFIG_FULL_LIBC_SUPPORTED 1 |
378 | 405 | #define CONFIG_MINIMAL_LIBC_SUPPORTED 1 |
379 | 406 | #define CONFIG_NEWLIB_LIBC_SUPPORTED 1 |
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388 | 415 | #define CONFIG_PICOLIBC_IO_FLOAT 1 |
389 | 416 | #define CONFIG_STDOUT_CONSOLE 1 |
390 | 417 | #define CONFIG_NEED_LIBC_MEM_PARTITION 1 |
| 418 | +#define CONFIG_CPP 1 |
| 419 | +#define CONFIG_STD_CPP17 1 |
| 420 | +#define CONFIG_MINIMAL_LIBCPP 1 |
391 | 421 | #define CONFIG_SYS_HEAP_ALLOC_LOOPS 3 |
392 | 422 | #define CONFIG_SYS_HEAP_AUTO 1 |
393 | 423 | #define CONFIG_ZVFS_OPEN_MAX 4 |
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422 | 452 | #define CONFIG_ASSERT_VERBOSE 1 |
423 | 453 | #define CONFIG_LLEXT 1 |
424 | 454 | #define CONFIG_LLEXT_TYPE_ELF_OBJECT 1 |
425 | | -#define CONFIG_LLEXT_HEAP_SIZE 32 |
| 455 | +#define CONFIG_LLEXT_HEAP_SIZE 128 |
426 | 456 | #define CONFIG_LLEXT_SHELL 1 |
427 | 457 | #define CONFIG_LLEXT_SHELL_MAX_SIZE 8192 |
428 | 458 | #define CONFIG_LLEXT_EXPORT_DEVICES 1 |
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445 | 475 | #define CONFIG_LOG_SIMPLE_MSG_OPTIMIZE 1 |
446 | 476 | #define CONFIG_LOG_ALWAYS_RUNTIME 1 |
447 | 477 | #define CONFIG_LOG_OUTPUT 1 |
| 478 | +#define CONFIG_TEST_RANDOM_GENERATOR 1 |
448 | 479 | #define CONFIG_TIMER_RANDOM_INITIAL_STATE 123456789 |
| 480 | +#define CONFIG_ENTROPY_DEVICE_RANDOM_GENERATOR 1 |
| 481 | +#define CONFIG_CSPRNG_ENABLED 1 |
| 482 | +#define CONFIG_HARDWARE_DEVICE_CS_GENERATOR 1 |
449 | 483 | #define CONFIG_SHELL 1 |
450 | 484 | #define CONFIG_SHELL_LOG_LEVEL_DEFAULT 1 |
451 | 485 | #define CONFIG_SHELL_LOG_LEVEL 3 |
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558 | 592 | #define CONFIG_CHECK_INIT_PRIORITIES 1 |
559 | 593 | #define CONFIG_WARN_DEPRECATED 1 |
560 | 594 | #define CONFIG_EXPERIMENTAL 1 |
561 | | -#define CONFIG_TAINT 1 |
562 | 595 | #define CONFIG_ENFORCE_ZEPHYR_STDINT 1 |
563 | 596 | #define CONFIG_LEGACY_GENERATED_INCLUDE_PATH 1 |
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