From 98cb40424ccde5cbe3f95e13038bc63ed3888a5c Mon Sep 17 00:00:00 2001 From: dz333 Date: Thu, 3 Mar 2022 22:45:24 -0500 Subject: [PATCH] delete unnecessary test files --- src/test/tests/histogram/Circuit.bsv | 49 - .../histogram/Circuit_verilog/mkCircuit.v | 2662 -------- .../tests/histogram/Circuit_verilog/mkTB.v | 127 - src/test/tests/histogram/Functions.bsv | 0 src/test/tests/histogram/Hist.bsv | 97 - src/test/tests/histogram/Outer.bsv | 123 - src/test/tests/histogram/f | 1024 --- src/test/tests/histogram/h | 1024 --- src/test/tests/histogram/mkTB.bexe | 5576 ----------------- src/test/tests/histogram/w | 1024 --- src/test/tests/risc-pipe/Circuit.bsv | 56 - .../Circuit_verilog/mkMulti_stg_div.v | 346 - src/test/tests/risc-pipe/Cpu.bsv | 544 -- src/test/tests/risc-pipe/Functions.bsv | 221 - src/test/tests/risc-pipe/Multi_stg_div.bsv | 93 - src/test/tests/risc-pipe/cmem | 256 - src/test/tests/risc-pipe/mm4 | 0 src/test/tests/risc-pipe/rf | 32 - src/test/tests/risc-pipe/td4 | 0 src/test/tests/risc-pipe/ti4 | 15 - src/test/tests/speculation/Circuit.bsv | 48 - src/test/tests/speculation/Functions.bsv | 0 src/test/tests/speculation/Testwrite.bsv | 309 - src/test/tests/speculation/rename | 32 - src/test/tests/speculation/ti | 14 - 25 files changed, 13672 deletions(-) delete mode 100644 src/test/tests/histogram/Circuit.bsv delete mode 100644 src/test/tests/histogram/Circuit_verilog/mkCircuit.v delete mode 100644 src/test/tests/histogram/Circuit_verilog/mkTB.v delete mode 100644 src/test/tests/histogram/Functions.bsv delete mode 100644 src/test/tests/histogram/Hist.bsv delete mode 100644 src/test/tests/histogram/Outer.bsv delete mode 100644 src/test/tests/histogram/f delete mode 100644 src/test/tests/histogram/h delete mode 100644 src/test/tests/histogram/mkTB.bexe delete mode 100644 src/test/tests/histogram/w delete mode 100644 src/test/tests/risc-pipe/Circuit.bsv delete mode 100644 src/test/tests/risc-pipe/Circuit_verilog/mkMulti_stg_div.v delete mode 100644 src/test/tests/risc-pipe/Cpu.bsv delete mode 100644 src/test/tests/risc-pipe/Functions.bsv delete mode 100644 src/test/tests/risc-pipe/Multi_stg_div.bsv delete mode 100644 src/test/tests/risc-pipe/cmem delete mode 100644 src/test/tests/risc-pipe/mm4 delete mode 100644 src/test/tests/risc-pipe/rf delete mode 100644 src/test/tests/risc-pipe/td4 delete mode 100644 src/test/tests/risc-pipe/ti4 delete mode 100644 src/test/tests/speculation/Circuit.bsv delete mode 100644 src/test/tests/speculation/Functions.bsv delete mode 100644 src/test/tests/speculation/Testwrite.bsv delete mode 100644 src/test/tests/speculation/rename delete mode 100644 src/test/tests/speculation/ti diff --git a/src/test/tests/histogram/Circuit.bsv b/src/test/tests/histogram/Circuit.bsv deleted file mode 100644 index 02a47b8e..00000000 --- a/src/test/tests/histogram/Circuit.bsv +++ /dev/null @@ -1,49 +0,0 @@ -import ClientServer :: *; -import Connectable :: *; -import Locks :: *; -import Memories :: *; -import VerilogLibs :: *; -import RegFile :: *; -import BRAMCore :: *; -import Hist :: *; -import Outer :: *; -import Functions :: *; - - - -interface TopMod; - interface Outer _into; -endinterface - -(* synthesize *) -module mkTB ( Empty _unused_ ) provisos( ); - Reg#( Bool ) started <- mkReg ( False ); - Reg#( UInt#(32) ) timer <- mkReg ( 0 ); - TopMod _topMod <- mkCircuit ( ); - Reg#( UInt#(2) ) reg_unused_0 <- mkReg ( 0 ); - rule initTB (( ! started )); - UInt#(2) _unused_0 = ?; - _unused_0 <- _topMod._into.req(10'd0); - reg_unused_0 <= _unused_0; - started <= True; - endrule - rule timerCount ; - timer <= ( timer + 1 ); - endrule - rule stopTB (( ( timer >= 32'd1000000 ) || _topMod._into.checkHandle(reg_unused_0) )); - $finish(); - endrule -endmodule - -(* synthesize *) -module mkCircuit ( TopMod _unused_ ) provisos( ); - RegFile#( UInt#(10), UInt#(16) ) tf <- mkRegFile ( True, "f" ); - AddrLockCombMem#( UInt#(10), UInt#(16), LockId#(4), 4 ) f <- mkFAAddrLockCombMem ( tf ); - RegFile#( UInt#(10), UInt#(32) ) tw <- mkRegFile ( True, "w" ); - AddrLockCombMem#( UInt#(10), UInt#(32), LockId#(4), 4 ) w <- mkFAAddrLockCombMem ( tw ); - RegFile#( UInt#(10), UInt#(32) ) th <- mkRegFile ( True, "h" ); - AddrLockCombMem#( UInt#(10), UInt#(32), LockId#(4), 4 ) h <- mkFAAddrLockCombMem ( th ); - Hist hg <- mkHist ( f, w, h ); - Outer o <- mkOuter ( hg ); - interface Outer _into = o; -endmodule diff --git a/src/test/tests/histogram/Circuit_verilog/mkCircuit.v b/src/test/tests/histogram/Circuit_verilog/mkCircuit.v deleted file mode 100644 index e26d9dac..00000000 --- a/src/test/tests/histogram/Circuit_verilog/mkCircuit.v +++ /dev/null @@ -1,2662 +0,0 @@ -// -// Generated by Bluespec Compiler -// -// -// Ports: -// Name I/O size props -// _into_req O 2 reg -// RDY__into_req O 1 -// RDY__into_resp O 1 const -// _into_checkHandle O 1 -// RDY__into_checkHandle O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// _into_req_counter I 10 -// _into_checkHandle_handle I 2 -// EN__into_resp I 1 -// EN__into_req I 1 -// -// Combinational paths from inputs to outputs: -// _into_checkHandle_handle -> _into_checkHandle -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCircuit(CLK, - RST_N, - - _into_req_counter, - EN__into_req, - _into_req, - RDY__into_req, - - EN__into_resp, - RDY__into_resp, - - _into_checkHandle_handle, - _into_checkHandle, - RDY__into_checkHandle); - input CLK; - input RST_N; - - // actionvalue method _into_req - input [9 : 0] _into_req_counter; - input EN__into_req; - output [1 : 0] _into_req; - output RDY__into_req; - - // action method _into_resp - input EN__into_resp; - output RDY__into_resp; - - // value method _into_checkHandle - input [1 : 0] _into_checkHandle_handle; - output _into_checkHandle; - output RDY__into_checkHandle; - - // signals for module outputs - wire [1 : 0] _into_req; - wire RDY__into_checkHandle, - RDY__into_req, - RDY__into_resp, - _into_checkHandle; - - // inlined wires - wire [13 : 0] hg_fifo__input__TO_Start_rv$port0__write_1, - hg_fifo__input__TO_Start_rv$port1__read, - hg_fifo__input__TO_Start_rv$port2__read; - wire [11 : 0] o_fifo__input__TO_Start_enq_data$wget; - wire h_l_lockVec_0_doRel$whas, - h_l_lockVec_0_nextId_lat_0$whas, - h_l_lockVec_1_doRel$whas, - h_l_lockVec_1_nextId_lat_0$whas, - h_l_lockVec_2_doRel$whas, - h_l_lockVec_2_nextId_lat_0$whas, - h_l_lockVec_3_doRel$whas, - h_l_lockVec_3_nextId_lat_0$whas, - h_l_resVec_0$whas, - h_l_resVec_1$whas, - h_l_resVec_2$whas, - h_l_resVec_3$whas, - hg_fifo__input__TO_Start_rv$EN_port0__write, - hg_fifo__input__TO_Start_rv$EN_port1__write, - o_doRel$whas, - o_fifo__input__TO_Start_enq_data$whas; - - // register f_l_entryVec_0 - reg [10 : 0] f_l_entryVec_0; - wire [10 : 0] f_l_entryVec_0$D_IN; - wire f_l_entryVec_0$EN; - - // register f_l_entryVec_1 - reg [10 : 0] f_l_entryVec_1; - wire [10 : 0] f_l_entryVec_1$D_IN; - wire f_l_entryVec_1$EN; - - // register f_l_entryVec_2 - reg [10 : 0] f_l_entryVec_2; - wire [10 : 0] f_l_entryVec_2$D_IN; - wire f_l_entryVec_2$EN; - - // register f_l_entryVec_3 - reg [10 : 0] f_l_entryVec_3; - wire [10 : 0] f_l_entryVec_3$D_IN; - wire f_l_entryVec_3$EN; - - // register f_l_lockVec_0_empty - reg f_l_lockVec_0_empty; - wire f_l_lockVec_0_empty$D_IN, f_l_lockVec_0_empty$EN; - - // register f_l_lockVec_0_nextId_rl - reg [1 : 0] f_l_lockVec_0_nextId_rl; - wire [1 : 0] f_l_lockVec_0_nextId_rl$D_IN; - wire f_l_lockVec_0_nextId_rl$EN; - - // register f_l_lockVec_0_owner - reg [1 : 0] f_l_lockVec_0_owner; - wire [1 : 0] f_l_lockVec_0_owner$D_IN; - wire f_l_lockVec_0_owner$EN; - - // register f_l_lockVec_1_empty - reg f_l_lockVec_1_empty; - wire f_l_lockVec_1_empty$D_IN, f_l_lockVec_1_empty$EN; - - // register f_l_lockVec_1_nextId_rl - reg [1 : 0] f_l_lockVec_1_nextId_rl; - wire [1 : 0] f_l_lockVec_1_nextId_rl$D_IN; - wire f_l_lockVec_1_nextId_rl$EN; - - // register f_l_lockVec_1_owner - reg [1 : 0] f_l_lockVec_1_owner; - wire [1 : 0] f_l_lockVec_1_owner$D_IN; - wire f_l_lockVec_1_owner$EN; - - // register f_l_lockVec_2_empty - reg f_l_lockVec_2_empty; - wire f_l_lockVec_2_empty$D_IN, f_l_lockVec_2_empty$EN; - - // register f_l_lockVec_2_nextId_rl - reg [1 : 0] f_l_lockVec_2_nextId_rl; - wire [1 : 0] f_l_lockVec_2_nextId_rl$D_IN; - wire f_l_lockVec_2_nextId_rl$EN; - - // register f_l_lockVec_2_owner - reg [1 : 0] f_l_lockVec_2_owner; - wire [1 : 0] f_l_lockVec_2_owner$D_IN; - wire f_l_lockVec_2_owner$EN; - - // register f_l_lockVec_3_empty - reg f_l_lockVec_3_empty; - wire f_l_lockVec_3_empty$D_IN, f_l_lockVec_3_empty$EN; - - // register f_l_lockVec_3_nextId_rl - reg [1 : 0] f_l_lockVec_3_nextId_rl; - wire [1 : 0] f_l_lockVec_3_nextId_rl$D_IN; - wire f_l_lockVec_3_nextId_rl$EN; - - // register f_l_lockVec_3_owner - reg [1 : 0] f_l_lockVec_3_owner; - wire [1 : 0] f_l_lockVec_3_owner$D_IN; - wire f_l_lockVec_3_owner$EN; - - // register h_l_entryVec_0 - reg [10 : 0] h_l_entryVec_0; - wire [10 : 0] h_l_entryVec_0$D_IN; - wire h_l_entryVec_0$EN; - - // register h_l_entryVec_1 - reg [10 : 0] h_l_entryVec_1; - wire [10 : 0] h_l_entryVec_1$D_IN; - wire h_l_entryVec_1$EN; - - // register h_l_entryVec_2 - reg [10 : 0] h_l_entryVec_2; - wire [10 : 0] h_l_entryVec_2$D_IN; - wire h_l_entryVec_2$EN; - - // register h_l_entryVec_3 - reg [10 : 0] h_l_entryVec_3; - wire [10 : 0] h_l_entryVec_3$D_IN; - wire h_l_entryVec_3$EN; - - // register h_l_lockVec_0_empty - reg h_l_lockVec_0_empty; - wire h_l_lockVec_0_empty$D_IN, h_l_lockVec_0_empty$EN; - - // register h_l_lockVec_0_nextId_rl - reg [1 : 0] h_l_lockVec_0_nextId_rl; - wire [1 : 0] h_l_lockVec_0_nextId_rl$D_IN; - wire h_l_lockVec_0_nextId_rl$EN; - - // register h_l_lockVec_0_owner - reg [1 : 0] h_l_lockVec_0_owner; - wire [1 : 0] h_l_lockVec_0_owner$D_IN; - wire h_l_lockVec_0_owner$EN; - - // register h_l_lockVec_1_empty - reg h_l_lockVec_1_empty; - wire h_l_lockVec_1_empty$D_IN, h_l_lockVec_1_empty$EN; - - // register h_l_lockVec_1_nextId_rl - reg [1 : 0] h_l_lockVec_1_nextId_rl; - wire [1 : 0] h_l_lockVec_1_nextId_rl$D_IN; - wire h_l_lockVec_1_nextId_rl$EN; - - // register h_l_lockVec_1_owner - reg [1 : 0] h_l_lockVec_1_owner; - wire [1 : 0] h_l_lockVec_1_owner$D_IN; - wire h_l_lockVec_1_owner$EN; - - // register h_l_lockVec_2_empty - reg h_l_lockVec_2_empty; - wire h_l_lockVec_2_empty$D_IN, h_l_lockVec_2_empty$EN; - - // register h_l_lockVec_2_nextId_rl - reg [1 : 0] h_l_lockVec_2_nextId_rl; - wire [1 : 0] h_l_lockVec_2_nextId_rl$D_IN; - wire h_l_lockVec_2_nextId_rl$EN; - - // register h_l_lockVec_2_owner - reg [1 : 0] h_l_lockVec_2_owner; - wire [1 : 0] h_l_lockVec_2_owner$D_IN; - wire h_l_lockVec_2_owner$EN; - - // register h_l_lockVec_3_empty - reg h_l_lockVec_3_empty; - wire h_l_lockVec_3_empty$D_IN, h_l_lockVec_3_empty$EN; - - // register h_l_lockVec_3_nextId_rl - reg [1 : 0] h_l_lockVec_3_nextId_rl; - wire [1 : 0] h_l_lockVec_3_nextId_rl$D_IN; - wire h_l_lockVec_3_nextId_rl$EN; - - // register h_l_lockVec_3_owner - reg [1 : 0] h_l_lockVec_3_owner; - wire [1 : 0] h_l_lockVec_3_owner$D_IN; - wire h_l_lockVec_3_owner$EN; - - // register hg - reg [2 : 0] hg; - wire [2 : 0] hg$D_IN; - wire hg$EN; - - // register hg_feature_lock_region - reg hg_feature_lock_region; - wire hg_feature_lock_region$D_IN, hg_feature_lock_region$EN; - - // register hg_fifo__input__TO_Start_rv - reg [13 : 0] hg_fifo__input__TO_Start_rv; - wire [13 : 0] hg_fifo__input__TO_Start_rv$D_IN; - wire hg_fifo__input__TO_Start_rv$EN; - - // register hg_h_lock_region - reg hg_h_lock_region; - wire hg_h_lock_region$D_IN, hg_h_lock_region$EN; - - // register hg_outputQueue_nextTag_rl - reg [2 : 0] hg_outputQueue_nextTag_rl; - wire [2 : 0] hg_outputQueue_nextTag_rl$D_IN; - wire hg_outputQueue_nextTag_rl$EN; - - // register hg_outputQueue_val - reg [1 : 0] hg_outputQueue_val; - wire [1 : 0] hg_outputQueue_val$D_IN; - wire hg_outputQueue_val$EN; - - // register hg_weight_lock_region - reg hg_weight_lock_region; - wire hg_weight_lock_region$D_IN, hg_weight_lock_region$EN; - - // register o - reg [1 : 0] o; - wire [1 : 0] o$D_IN; - wire o$EN; - - // register o_busyReg - reg o_busyReg; - wire o_busyReg$D_IN, o_busyReg$EN; - - // register o_empty - reg o_empty; - wire o_empty$D_IN, o_empty$EN; - - // register o_h_lock_region - reg o_h_lock_region; - wire o_h_lock_region$D_IN, o_h_lock_region$EN; - - // register o_nextId_rl - reg [1 : 0] o_nextId_rl; - wire [1 : 0] o_nextId_rl$D_IN; - wire o_nextId_rl$EN; - - // register o_outputQueue_nextTag_rl - reg [1 : 0] o_outputQueue_nextTag_rl; - wire [1 : 0] o_outputQueue_nextTag_rl$D_IN; - wire o_outputQueue_nextTag_rl$EN; - - // register o_outputQueue_val - reg o_outputQueue_val; - wire o_outputQueue_val$D_IN, o_outputQueue_val$EN; - - // register o_owner - reg [1 : 0] o_owner; - wire [1 : 0] o_owner$D_IN; - wire o_owner$EN; - - // register w_l_entryVec_0 - reg [10 : 0] w_l_entryVec_0; - wire [10 : 0] w_l_entryVec_0$D_IN; - wire w_l_entryVec_0$EN; - - // register w_l_entryVec_1 - reg [10 : 0] w_l_entryVec_1; - wire [10 : 0] w_l_entryVec_1$D_IN; - wire w_l_entryVec_1$EN; - - // register w_l_entryVec_2 - reg [10 : 0] w_l_entryVec_2; - wire [10 : 0] w_l_entryVec_2$D_IN; - wire w_l_entryVec_2$EN; - - // register w_l_entryVec_3 - reg [10 : 0] w_l_entryVec_3; - wire [10 : 0] w_l_entryVec_3$D_IN; - wire w_l_entryVec_3$EN; - - // register w_l_lockVec_0_empty - reg w_l_lockVec_0_empty; - wire w_l_lockVec_0_empty$D_IN, w_l_lockVec_0_empty$EN; - - // register w_l_lockVec_0_nextId_rl - reg [1 : 0] w_l_lockVec_0_nextId_rl; - wire [1 : 0] w_l_lockVec_0_nextId_rl$D_IN; - wire w_l_lockVec_0_nextId_rl$EN; - - // register w_l_lockVec_0_owner - reg [1 : 0] w_l_lockVec_0_owner; - wire [1 : 0] w_l_lockVec_0_owner$D_IN; - wire w_l_lockVec_0_owner$EN; - - // register w_l_lockVec_1_empty - reg w_l_lockVec_1_empty; - wire w_l_lockVec_1_empty$D_IN, w_l_lockVec_1_empty$EN; - - // register w_l_lockVec_1_nextId_rl - reg [1 : 0] w_l_lockVec_1_nextId_rl; - wire [1 : 0] w_l_lockVec_1_nextId_rl$D_IN; - wire w_l_lockVec_1_nextId_rl$EN; - - // register w_l_lockVec_1_owner - reg [1 : 0] w_l_lockVec_1_owner; - wire [1 : 0] w_l_lockVec_1_owner$D_IN; - wire w_l_lockVec_1_owner$EN; - - // register w_l_lockVec_2_empty - reg w_l_lockVec_2_empty; - wire w_l_lockVec_2_empty$D_IN, w_l_lockVec_2_empty$EN; - - // register w_l_lockVec_2_nextId_rl - reg [1 : 0] w_l_lockVec_2_nextId_rl; - wire [1 : 0] w_l_lockVec_2_nextId_rl$D_IN; - wire w_l_lockVec_2_nextId_rl$EN; - - // register w_l_lockVec_2_owner - reg [1 : 0] w_l_lockVec_2_owner; - wire [1 : 0] w_l_lockVec_2_owner$D_IN; - wire w_l_lockVec_2_owner$EN; - - // register w_l_lockVec_3_empty - reg w_l_lockVec_3_empty; - wire w_l_lockVec_3_empty$D_IN, w_l_lockVec_3_empty$EN; - - // register w_l_lockVec_3_nextId_rl - reg [1 : 0] w_l_lockVec_3_nextId_rl; - wire [1 : 0] w_l_lockVec_3_nextId_rl$D_IN; - wire w_l_lockVec_3_nextId_rl$EN; - - // register w_l_lockVec_3_owner - reg [1 : 0] w_l_lockVec_3_owner; - wire [1 : 0] w_l_lockVec_3_owner$D_IN; - wire w_l_lockVec_3_owner$EN; - - // ports of submodule f_l_lockVec_0_nextId_dummy2_0 - wire f_l_lockVec_0_nextId_dummy2_0$D_IN, f_l_lockVec_0_nextId_dummy2_0$EN; - - // ports of submodule f_l_lockVec_0_nextId_dummy2_1 - wire f_l_lockVec_0_nextId_dummy2_1$D_IN, - f_l_lockVec_0_nextId_dummy2_1$EN, - f_l_lockVec_0_nextId_dummy2_1$Q_OUT; - - // ports of submodule f_l_lockVec_1_nextId_dummy2_0 - wire f_l_lockVec_1_nextId_dummy2_0$D_IN, f_l_lockVec_1_nextId_dummy2_0$EN; - - // ports of submodule f_l_lockVec_1_nextId_dummy2_1 - wire f_l_lockVec_1_nextId_dummy2_1$D_IN, - f_l_lockVec_1_nextId_dummy2_1$EN, - f_l_lockVec_1_nextId_dummy2_1$Q_OUT; - - // ports of submodule f_l_lockVec_2_nextId_dummy2_0 - wire f_l_lockVec_2_nextId_dummy2_0$D_IN, f_l_lockVec_2_nextId_dummy2_0$EN; - - // ports of submodule f_l_lockVec_2_nextId_dummy2_1 - wire f_l_lockVec_2_nextId_dummy2_1$D_IN, - f_l_lockVec_2_nextId_dummy2_1$EN, - f_l_lockVec_2_nextId_dummy2_1$Q_OUT; - - // ports of submodule f_l_lockVec_3_nextId_dummy2_0 - wire f_l_lockVec_3_nextId_dummy2_0$D_IN, f_l_lockVec_3_nextId_dummy2_0$EN; - - // ports of submodule f_l_lockVec_3_nextId_dummy2_1 - wire f_l_lockVec_3_nextId_dummy2_1$D_IN, - f_l_lockVec_3_nextId_dummy2_1$EN, - f_l_lockVec_3_nextId_dummy2_1$Q_OUT; - - // ports of submodule h_l_lockVec_0_nextId_dummy2_0 - wire h_l_lockVec_0_nextId_dummy2_0$D_IN, - h_l_lockVec_0_nextId_dummy2_0$EN, - h_l_lockVec_0_nextId_dummy2_0$Q_OUT; - - // ports of submodule h_l_lockVec_0_nextId_dummy2_1 - wire h_l_lockVec_0_nextId_dummy2_1$D_IN, - h_l_lockVec_0_nextId_dummy2_1$EN, - h_l_lockVec_0_nextId_dummy2_1$Q_OUT; - - // ports of submodule h_l_lockVec_1_nextId_dummy2_0 - wire h_l_lockVec_1_nextId_dummy2_0$D_IN, - h_l_lockVec_1_nextId_dummy2_0$EN, - h_l_lockVec_1_nextId_dummy2_0$Q_OUT; - - // ports of submodule h_l_lockVec_1_nextId_dummy2_1 - wire h_l_lockVec_1_nextId_dummy2_1$D_IN, - h_l_lockVec_1_nextId_dummy2_1$EN, - h_l_lockVec_1_nextId_dummy2_1$Q_OUT; - - // ports of submodule h_l_lockVec_2_nextId_dummy2_0 - wire h_l_lockVec_2_nextId_dummy2_0$D_IN, - h_l_lockVec_2_nextId_dummy2_0$EN, - h_l_lockVec_2_nextId_dummy2_0$Q_OUT; - - // ports of submodule h_l_lockVec_2_nextId_dummy2_1 - wire h_l_lockVec_2_nextId_dummy2_1$D_IN, - h_l_lockVec_2_nextId_dummy2_1$EN, - h_l_lockVec_2_nextId_dummy2_1$Q_OUT; - - // ports of submodule h_l_lockVec_3_nextId_dummy2_0 - wire h_l_lockVec_3_nextId_dummy2_0$D_IN, - h_l_lockVec_3_nextId_dummy2_0$EN, - h_l_lockVec_3_nextId_dummy2_0$Q_OUT; - - // ports of submodule h_l_lockVec_3_nextId_dummy2_1 - wire h_l_lockVec_3_nextId_dummy2_1$D_IN, - h_l_lockVec_3_nextId_dummy2_1$EN, - h_l_lockVec_3_nextId_dummy2_1$Q_OUT; - - // ports of submodule hg_fifo_Stage__0_TO_Stage__1 - wire [47 : 0] hg_fifo_Stage__0_TO_Stage__1$D_IN, - hg_fifo_Stage__0_TO_Stage__1$D_OUT; - wire hg_fifo_Stage__0_TO_Stage__1$CLR, - hg_fifo_Stage__0_TO_Stage__1$DEQ, - hg_fifo_Stage__0_TO_Stage__1$EMPTY_N, - hg_fifo_Stage__0_TO_Stage__1$ENQ, - hg_fifo_Stage__0_TO_Stage__1$FULL_N; - - // ports of submodule hg_fifo_Stage__1_TO_Stage__2 - wire [2 : 0] hg_fifo_Stage__1_TO_Stage__2$D_IN, - hg_fifo_Stage__1_TO_Stage__2$D_OUT; - wire hg_fifo_Stage__1_TO_Stage__2$CLR, - hg_fifo_Stage__1_TO_Stage__2$DEQ, - hg_fifo_Stage__1_TO_Stage__2$EMPTY_N, - hg_fifo_Stage__1_TO_Stage__2$ENQ, - hg_fifo_Stage__1_TO_Stage__2$FULL_N; - - // ports of submodule hg_fifo_Start_TO_Stage__0 - wire [44 : 0] hg_fifo_Start_TO_Stage__0$D_IN, - hg_fifo_Start_TO_Stage__0$D_OUT; - wire hg_fifo_Start_TO_Stage__0$CLR, - hg_fifo_Start_TO_Stage__0$DEQ, - hg_fifo_Start_TO_Stage__0$EMPTY_N, - hg_fifo_Start_TO_Stage__0$ENQ, - hg_fifo_Start_TO_Stage__0$FULL_N; - - // ports of submodule hg_outputQueue_nextTag_dummy2_0 - wire hg_outputQueue_nextTag_dummy2_0$D_IN, - hg_outputQueue_nextTag_dummy2_0$EN, - hg_outputQueue_nextTag_dummy2_0$Q_OUT; - - // ports of submodule hg_outputQueue_nextTag_dummy2_1 - wire hg_outputQueue_nextTag_dummy2_1$D_IN, - hg_outputQueue_nextTag_dummy2_1$EN, - hg_outputQueue_nextTag_dummy2_1$Q_OUT; - - // ports of submodule o_fifo_Stage__1_TO_Stage__3 - wire [4 : 0] o_fifo_Stage__1_TO_Stage__3$D_IN, - o_fifo_Stage__1_TO_Stage__3$D_OUT; - wire o_fifo_Stage__1_TO_Stage__3$CLR, - o_fifo_Stage__1_TO_Stage__3$DEQ, - o_fifo_Stage__1_TO_Stage__3$EMPTY_N, - o_fifo_Stage__1_TO_Stage__3$ENQ, - o_fifo_Stage__1_TO_Stage__3$FULL_N; - - // ports of submodule o_fifo_Start_TO_Stage__1 - wire [14 : 0] o_fifo_Start_TO_Stage__1$D_IN, o_fifo_Start_TO_Stage__1$D_OUT; - wire o_fifo_Start_TO_Stage__1$CLR, - o_fifo_Start_TO_Stage__1$DEQ, - o_fifo_Start_TO_Stage__1$EMPTY_N, - o_fifo_Start_TO_Stage__1$ENQ, - o_fifo_Start_TO_Stage__1$FULL_N; - - // ports of submodule o_fifo_Start_TO_Stage__3 - wire [2 : 0] o_fifo_Start_TO_Stage__3$D_IN, o_fifo_Start_TO_Stage__3$D_OUT; - wire o_fifo_Start_TO_Stage__3$CLR, - o_fifo_Start_TO_Stage__3$DEQ, - o_fifo_Start_TO_Stage__3$EMPTY_N, - o_fifo_Start_TO_Stage__3$ENQ, - o_fifo_Start_TO_Stage__3$FULL_N; - - // ports of submodule o_fifo_Start_TO_Stage__3_1 - wire [1 : 0] o_fifo_Start_TO_Stage__3_1$D_IN; - wire o_fifo_Start_TO_Stage__3_1$CLR, - o_fifo_Start_TO_Stage__3_1$DEQ, - o_fifo_Start_TO_Stage__3_1$EMPTY_N, - o_fifo_Start_TO_Stage__3_1$ENQ, - o_fifo_Start_TO_Stage__3_1$FULL_N; - - // ports of submodule o_fifo__input__TO_Start_f - wire [11 : 0] o_fifo__input__TO_Start_f$D_IN, - o_fifo__input__TO_Start_f$D_OUT; - wire o_fifo__input__TO_Start_f$CLR, - o_fifo__input__TO_Start_f$DEQ, - o_fifo__input__TO_Start_f$EMPTY_N, - o_fifo__input__TO_Start_f$ENQ, - o_fifo__input__TO_Start_f$FULL_N; - - // ports of submodule o_nextId_dummy2_0 - wire o_nextId_dummy2_0$D_IN, o_nextId_dummy2_0$EN, o_nextId_dummy2_0$Q_OUT; - - // ports of submodule o_nextId_dummy2_1 - wire o_nextId_dummy2_1$D_IN, o_nextId_dummy2_1$EN, o_nextId_dummy2_1$Q_OUT; - - // ports of submodule o_outputQueue_nextTag_dummy2_0 - wire o_outputQueue_nextTag_dummy2_0$D_IN, - o_outputQueue_nextTag_dummy2_0$EN, - o_outputQueue_nextTag_dummy2_0$Q_OUT; - - // ports of submodule o_outputQueue_nextTag_dummy2_1 - wire o_outputQueue_nextTag_dummy2_1$D_IN, - o_outputQueue_nextTag_dummy2_1$EN, - o_outputQueue_nextTag_dummy2_1$Q_OUT; - - // ports of submodule tf_rf - wire [15 : 0] tf_rf$D_IN, tf_rf$D_OUT_1; - wire [9 : 0] tf_rf$ADDR_1, - tf_rf$ADDR_2, - tf_rf$ADDR_3, - tf_rf$ADDR_4, - tf_rf$ADDR_5, - tf_rf$ADDR_IN; - wire tf_rf$WE; - - // ports of submodule th_rf - wire [31 : 0] th_rf$D_IN, th_rf$D_OUT_1; - wire [9 : 0] th_rf$ADDR_1, - th_rf$ADDR_2, - th_rf$ADDR_3, - th_rf$ADDR_4, - th_rf$ADDR_5, - th_rf$ADDR_IN; - wire th_rf$WE; - - // ports of submodule tw_rf - wire [31 : 0] tw_rf$D_IN, tw_rf$D_OUT_1; - wire [9 : 0] tw_rf$ADDR_1, - tw_rf$ADDR_2, - tw_rf$ADDR_3, - tw_rf$ADDR_4, - tw_rf$ADDR_5, - tw_rf$ADDR_IN; - wire tw_rf$WE; - - // ports of submodule w_l_lockVec_0_nextId_dummy2_0 - wire w_l_lockVec_0_nextId_dummy2_0$D_IN, w_l_lockVec_0_nextId_dummy2_0$EN; - - // ports of submodule w_l_lockVec_0_nextId_dummy2_1 - wire w_l_lockVec_0_nextId_dummy2_1$D_IN, - w_l_lockVec_0_nextId_dummy2_1$EN, - w_l_lockVec_0_nextId_dummy2_1$Q_OUT; - - // ports of submodule w_l_lockVec_1_nextId_dummy2_0 - wire w_l_lockVec_1_nextId_dummy2_0$D_IN, w_l_lockVec_1_nextId_dummy2_0$EN; - - // ports of submodule w_l_lockVec_1_nextId_dummy2_1 - wire w_l_lockVec_1_nextId_dummy2_1$D_IN, - w_l_lockVec_1_nextId_dummy2_1$EN, - w_l_lockVec_1_nextId_dummy2_1$Q_OUT; - - // ports of submodule w_l_lockVec_2_nextId_dummy2_0 - wire w_l_lockVec_2_nextId_dummy2_0$D_IN, w_l_lockVec_2_nextId_dummy2_0$EN; - - // ports of submodule w_l_lockVec_2_nextId_dummy2_1 - wire w_l_lockVec_2_nextId_dummy2_1$D_IN, - w_l_lockVec_2_nextId_dummy2_1$EN, - w_l_lockVec_2_nextId_dummy2_1$Q_OUT; - - // ports of submodule w_l_lockVec_3_nextId_dummy2_0 - wire w_l_lockVec_3_nextId_dummy2_0$D_IN, w_l_lockVec_3_nextId_dummy2_0$EN; - - // ports of submodule w_l_lockVec_3_nextId_dummy2_1 - wire w_l_lockVec_3_nextId_dummy2_1$D_IN, - w_l_lockVec_3_nextId_dummy2_1$EN, - w_l_lockVec_3_nextId_dummy2_1$Q_OUT; - - // rule scheduling signals - wire WILL_FIRE_RL_h_l_freelock, - WILL_FIRE_RL_h_l_freelock_1, - WILL_FIRE_RL_h_l_freelock_2, - WILL_FIRE_RL_h_l_freelock_3, - WILL_FIRE_RL_hg_s_Stage__0_execute, - WILL_FIRE_RL_hg_s_Stage__1_execute, - WILL_FIRE_RL_hg_s_Stage__2_execute, - WILL_FIRE_RL_o_s_Stage__3_execute, - WILL_FIRE_RL_o_s_Start_execute; - - // inputs to muxes for submodule ports - wire [11 : 0] MUX_o_fifo__input__TO_Start_enq_data$wset_1__VAL_1, - MUX_o_fifo__input__TO_Start_enq_data$wset_1__VAL_2; - wire [10 : 0] MUX_h_l_entryVec_0$write_1__VAL_2; - wire MUX_hg_outputQueue_val$write_1__SEL_2, - MUX_o_busyReg$write_1__SEL_1, - MUX_o_fifo__input__TO_Start_enq_data$wset_1__SEL_1; - - // remaining internal signals - reg [1 : 0] SEL_ARR_IF_h_l_lockVec_0_nextId_dummy2_0_read__ETC___d540, - SEL_ARR_IF_h_l_lockVec_0_nextId_dummy2_0_read__ETC___d541; - reg SEL_ARR_f_l_lockVec_0_empty_5_f_l_lockVec_1_em_ETC___d383, - SEL_ARR_h_l_lockVec_0_empty_10_h_l_lockVec_1_e_ETC___d478, - SEL_ARR_h_l_lockVec_0_owner_64_EQ_IF_hg_fifo_S_ETC___d590, - SEL_ARR_w_l_lockVec_0_empty_98_w_l_lockVec_1_e_ETC___d422; - wire [31 : 0] th_rf_sub_hg_fifo_Start_TO_Stage__0_first__41__ETC___d537; - wire [2 : 0] IF_hg_outputQueue_nextTag_dummy2_0_read__86_AN_ETC___d688, - IF_hg_outputQueue_nextTag_lat_0_whas__40_THEN__ETC___d343, - b__h24879; - wire [1 : 0] IF_NOT_f_l_entryVec_0_read__6_BIT_10_7_72_OR_N_ETC___d380, - IF_NOT_h_l_entryVec_0_read__11_BIT_10_12_67_OR_ETC___d475, - IF_NOT_h_l_entryVec_0_read__11_BIT_10_12_67_OR_ETC___d587, - IF_NOT_w_l_entryVec_0_read__99_BIT_10_00_11_OR_ETC___d419, - IF_h_l_entryVec_1_read__18_BIT_10_19_AND_h_l_e_ETC___d520, - IF_h_l_entryVec_3_read__32_BIT_10_33_AND_IF_h__ETC___d543, - IF_h_l_lockVec_0_nextId_dummy2_0_read__98_AND__ETC___d500, - IF_h_l_lockVec_0_nextId_dummy2_0_read__98_AND__ETC___d501, - IF_h_l_lockVec_0_nextId_lat_0_whas__28_THEN_h__ETC___d231, - IF_h_l_lockVec_1_nextId_dummy2_0_read__02_AND__ETC___d504, - IF_h_l_lockVec_1_nextId_dummy2_0_read__02_AND__ETC___d505, - IF_h_l_lockVec_1_nextId_lat_0_whas__49_THEN_h__ETC___d252, - IF_h_l_lockVec_2_nextId_dummy2_0_read__06_AND__ETC___d508, - IF_h_l_lockVec_2_nextId_dummy2_0_read__06_AND__ETC___d509, - IF_h_l_lockVec_2_nextId_lat_0_whas__70_THEN_h__ETC___d273, - IF_h_l_lockVec_3_nextId_dummy2_0_read__10_AND__ETC___d512, - IF_h_l_lockVec_3_nextId_dummy2_0_read__10_AND__ETC___d513, - IF_h_l_lockVec_3_nextId_lat_0_whas__91_THEN_h__ETC___d294, - IF_o_nextId_dummy2_0_read__67_AND_o_nextId_dum_ETC___d669, - IF_o_nextId_lat_0_whas__19_THEN_o_nextId_lat_0_ETC___d622, - IF_o_outputQueue_nextTag_dummy2_0_read__25_AND_ETC___d727, - IF_o_outputQueue_nextTag_lat_0_whas__40_THEN_o_ETC___d643, - b__h17187, - b__h18595, - b__h20003, - b__h21411, - b__h31747, - b__h32070, - b__h33309, - x__h25497, - x__h26014, - x__h26655, - x__h27260, - x__h29141; - wire IF_NOT_h_l_entryVec_2_read__25_BIT_10_26_61_OR_ETC___d491, - IF_NOT_h_l_entryVec_2_read__25_BIT_10_26_61_OR_ETC___d493, - IF_NOT_h_l_entryVec_2_read__25_BIT_10_26_61_OR_ETC___d495, - IF_NOT_h_l_entryVec_2_read__25_BIT_10_26_61_OR_ETC___d497, - IF_f_l_entryVec_3_read__08_BIT_10_09_AND_f_l_e_ETC___d428, - IF_h_l_entryVec_0_read__11_BIT_10_12_THEN_h_l__ETC___d455, - IF_h_l_entryVec_0_read__11_BIT_10_12_THEN_h_l__ETC___d559, - IF_h_l_entryVec_1_read__18_BIT_10_19_THEN_h_l__ETC___d451, - IF_h_l_entryVec_1_read__18_BIT_10_19_THEN_h_l__ETC___d557, - IF_h_l_entryVec_2_read__25_BIT_10_26_THEN_h_l__ETC___d447, - IF_h_l_entryVec_2_read__25_BIT_10_26_THEN_h_l__ETC___d555, - IF_h_l_entryVec_3_read__32_BIT_10_33_AND_IF_h__ETC___d483, - IF_h_l_entryVec_3_read__32_BIT_10_33_THEN_h_l__ETC___d443, - NOT_f_l_entryVec_1_read__4_BIT_10_5_69_OR_NOT__ETC___d378, - NOT_f_l_entryVec_2_read__01_BIT_10_02_66_OR_NO_ETC___d376, - NOT_h_l_entryVec_1_read__18_BIT_10_19_64_OR_NO_ETC___d473, - NOT_h_l_entryVec_1_read__18_BIT_10_19_64_OR_NO_ETC___d585, - NOT_h_l_entryVec_2_read__25_BIT_10_26_61_OR_NO_ETC___d471, - NOT_h_l_entryVec_2_read__25_BIT_10_26_61_OR_NO_ETC___d583, - NOT_h_l_entryVec_3_read__32_BIT_10_33_79_OR_NO_ETC___d482, - NOT_h_l_entryVec_3_read__32_BIT_10_33_79_OR_NO_ETC___d526, - NOT_w_l_entryVec_1_read__06_BIT_10_07_08_OR_NO_ETC___d417, - NOT_w_l_entryVec_2_read__13_BIT_10_14_05_OR_NO_ETC___d415, - f_l_entryVec_0_read__6_BITS_9_TO_0_59_EQ_hg_fi_ETC___d360, - f_l_entryVec_1_read__4_BITS_9_TO_0_56_EQ_hg_fi_ETC___d357, - f_l_entryVec_2_read__01_BITS_9_TO_0_53_EQ_hg_f_ETC___d354, - f_l_entryVec_2_read__01_BIT_10_02_AND_f_l_entr_ETC___d363, - h_l_entryVec_2_read__25_BIT_10_26_AND_IF_h_l_e_ETC___d458, - h_l_entryVec_2_read__25_BIT_10_26_AND_IF_h_l_e_ETC___d562, - h_l_entryVec_3_read__32_BIT_10_33_AND_IF_h_l_e_ETC___d563, - o_fifo_Start_TO_Stage__3_first__77_BIT_2_78_OR_ETC___d695, - o_fifo__input__TO_Start_f_first__47_BITS_11_TO_ETC___d649, - o_fifo__input__TO_Start_f_first__47_BITS_11_TO_ETC___d665, - w_l_entryVec_0_read__99_BITS_9_TO_0_98_EQ_hg_f_ETC___d399, - w_l_entryVec_1_read__06_BITS_9_TO_0_95_EQ_hg_f_ETC___d396, - w_l_entryVec_2_read__13_BITS_9_TO_0_92_EQ_hg_f_ETC___d393, - w_l_entryVec_2_read__13_BIT_10_14_AND_w_l_entr_ETC___d402; - - // actionvalue method _into_req - assign _into_req = o ; - assign RDY__into_req = !o_busyReg && o_fifo__input__TO_Start_f$FULL_N ; - - // action method _into_resp - assign RDY__into_resp = 1'd1 ; - - // value method _into_checkHandle - assign _into_checkHandle = - IF_o_outputQueue_nextTag_dummy2_0_read__25_AND_ETC___d727 == - _into_checkHandle_handle && - o_outputQueue_val ; - assign RDY__into_checkHandle = 1'd1 ; - - // submodule f_l_lockVec_0_nextId_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) f_l_lockVec_0_nextId_dummy2_0(.CLK(CLK), - .D_IN(f_l_lockVec_0_nextId_dummy2_0$D_IN), - .EN(f_l_lockVec_0_nextId_dummy2_0$EN), - .Q_OUT()); - - // submodule f_l_lockVec_0_nextId_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) f_l_lockVec_0_nextId_dummy2_1(.CLK(CLK), - .D_IN(f_l_lockVec_0_nextId_dummy2_1$D_IN), - .EN(f_l_lockVec_0_nextId_dummy2_1$EN), - .Q_OUT(f_l_lockVec_0_nextId_dummy2_1$Q_OUT)); - - // submodule f_l_lockVec_1_nextId_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) f_l_lockVec_1_nextId_dummy2_0(.CLK(CLK), - .D_IN(f_l_lockVec_1_nextId_dummy2_0$D_IN), - .EN(f_l_lockVec_1_nextId_dummy2_0$EN), - .Q_OUT()); - - // submodule f_l_lockVec_1_nextId_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) f_l_lockVec_1_nextId_dummy2_1(.CLK(CLK), - .D_IN(f_l_lockVec_1_nextId_dummy2_1$D_IN), - .EN(f_l_lockVec_1_nextId_dummy2_1$EN), - .Q_OUT(f_l_lockVec_1_nextId_dummy2_1$Q_OUT)); - - // submodule f_l_lockVec_2_nextId_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) f_l_lockVec_2_nextId_dummy2_0(.CLK(CLK), - .D_IN(f_l_lockVec_2_nextId_dummy2_0$D_IN), - .EN(f_l_lockVec_2_nextId_dummy2_0$EN), - .Q_OUT()); - - // submodule f_l_lockVec_2_nextId_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) f_l_lockVec_2_nextId_dummy2_1(.CLK(CLK), - .D_IN(f_l_lockVec_2_nextId_dummy2_1$D_IN), - .EN(f_l_lockVec_2_nextId_dummy2_1$EN), - .Q_OUT(f_l_lockVec_2_nextId_dummy2_1$Q_OUT)); - - // submodule f_l_lockVec_3_nextId_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) f_l_lockVec_3_nextId_dummy2_0(.CLK(CLK), - .D_IN(f_l_lockVec_3_nextId_dummy2_0$D_IN), - .EN(f_l_lockVec_3_nextId_dummy2_0$EN), - .Q_OUT()); - - // submodule f_l_lockVec_3_nextId_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) f_l_lockVec_3_nextId_dummy2_1(.CLK(CLK), - .D_IN(f_l_lockVec_3_nextId_dummy2_1$D_IN), - .EN(f_l_lockVec_3_nextId_dummy2_1$EN), - .Q_OUT(f_l_lockVec_3_nextId_dummy2_1$Q_OUT)); - - // submodule h_l_lockVec_0_nextId_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) h_l_lockVec_0_nextId_dummy2_0(.CLK(CLK), - .D_IN(h_l_lockVec_0_nextId_dummy2_0$D_IN), - .EN(h_l_lockVec_0_nextId_dummy2_0$EN), - .Q_OUT(h_l_lockVec_0_nextId_dummy2_0$Q_OUT)); - - // submodule h_l_lockVec_0_nextId_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) h_l_lockVec_0_nextId_dummy2_1(.CLK(CLK), - .D_IN(h_l_lockVec_0_nextId_dummy2_1$D_IN), - .EN(h_l_lockVec_0_nextId_dummy2_1$EN), - .Q_OUT(h_l_lockVec_0_nextId_dummy2_1$Q_OUT)); - - // submodule h_l_lockVec_1_nextId_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) h_l_lockVec_1_nextId_dummy2_0(.CLK(CLK), - .D_IN(h_l_lockVec_1_nextId_dummy2_0$D_IN), - .EN(h_l_lockVec_1_nextId_dummy2_0$EN), - .Q_OUT(h_l_lockVec_1_nextId_dummy2_0$Q_OUT)); - - // submodule h_l_lockVec_1_nextId_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) h_l_lockVec_1_nextId_dummy2_1(.CLK(CLK), - .D_IN(h_l_lockVec_1_nextId_dummy2_1$D_IN), - .EN(h_l_lockVec_1_nextId_dummy2_1$EN), - .Q_OUT(h_l_lockVec_1_nextId_dummy2_1$Q_OUT)); - - // submodule h_l_lockVec_2_nextId_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) h_l_lockVec_2_nextId_dummy2_0(.CLK(CLK), - .D_IN(h_l_lockVec_2_nextId_dummy2_0$D_IN), - .EN(h_l_lockVec_2_nextId_dummy2_0$EN), - .Q_OUT(h_l_lockVec_2_nextId_dummy2_0$Q_OUT)); - - // submodule h_l_lockVec_2_nextId_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) h_l_lockVec_2_nextId_dummy2_1(.CLK(CLK), - .D_IN(h_l_lockVec_2_nextId_dummy2_1$D_IN), - .EN(h_l_lockVec_2_nextId_dummy2_1$EN), - .Q_OUT(h_l_lockVec_2_nextId_dummy2_1$Q_OUT)); - - // submodule h_l_lockVec_3_nextId_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) h_l_lockVec_3_nextId_dummy2_0(.CLK(CLK), - .D_IN(h_l_lockVec_3_nextId_dummy2_0$D_IN), - .EN(h_l_lockVec_3_nextId_dummy2_0$EN), - .Q_OUT(h_l_lockVec_3_nextId_dummy2_0$Q_OUT)); - - // submodule h_l_lockVec_3_nextId_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) h_l_lockVec_3_nextId_dummy2_1(.CLK(CLK), - .D_IN(h_l_lockVec_3_nextId_dummy2_1$D_IN), - .EN(h_l_lockVec_3_nextId_dummy2_1$EN), - .Q_OUT(h_l_lockVec_3_nextId_dummy2_1$Q_OUT)); - - // submodule hg_fifo_Stage__0_TO_Stage__1 - FIFO2 #(.width(32'd48), - .guarded(1'd1)) hg_fifo_Stage__0_TO_Stage__1(.RST(RST_N), - .CLK(CLK), - .D_IN(hg_fifo_Stage__0_TO_Stage__1$D_IN), - .ENQ(hg_fifo_Stage__0_TO_Stage__1$ENQ), - .DEQ(hg_fifo_Stage__0_TO_Stage__1$DEQ), - .CLR(hg_fifo_Stage__0_TO_Stage__1$CLR), - .D_OUT(hg_fifo_Stage__0_TO_Stage__1$D_OUT), - .FULL_N(hg_fifo_Stage__0_TO_Stage__1$FULL_N), - .EMPTY_N(hg_fifo_Stage__0_TO_Stage__1$EMPTY_N)); - - // submodule hg_fifo_Stage__1_TO_Stage__2 - FIFO2 #(.width(32'd3), - .guarded(1'd1)) hg_fifo_Stage__1_TO_Stage__2(.RST(RST_N), - .CLK(CLK), - .D_IN(hg_fifo_Stage__1_TO_Stage__2$D_IN), - .ENQ(hg_fifo_Stage__1_TO_Stage__2$ENQ), - .DEQ(hg_fifo_Stage__1_TO_Stage__2$DEQ), - .CLR(hg_fifo_Stage__1_TO_Stage__2$CLR), - .D_OUT(hg_fifo_Stage__1_TO_Stage__2$D_OUT), - .FULL_N(hg_fifo_Stage__1_TO_Stage__2$FULL_N), - .EMPTY_N(hg_fifo_Stage__1_TO_Stage__2$EMPTY_N)); - - // submodule hg_fifo_Start_TO_Stage__0 - FIFO2 #(.width(32'd45), - .guarded(1'd1)) hg_fifo_Start_TO_Stage__0(.RST(RST_N), - .CLK(CLK), - .D_IN(hg_fifo_Start_TO_Stage__0$D_IN), - .ENQ(hg_fifo_Start_TO_Stage__0$ENQ), - .DEQ(hg_fifo_Start_TO_Stage__0$DEQ), - .CLR(hg_fifo_Start_TO_Stage__0$CLR), - .D_OUT(hg_fifo_Start_TO_Stage__0$D_OUT), - .FULL_N(hg_fifo_Start_TO_Stage__0$FULL_N), - .EMPTY_N(hg_fifo_Start_TO_Stage__0$EMPTY_N)); - - // submodule hg_outputQueue_nextTag_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) hg_outputQueue_nextTag_dummy2_0(.CLK(CLK), - .D_IN(hg_outputQueue_nextTag_dummy2_0$D_IN), - .EN(hg_outputQueue_nextTag_dummy2_0$EN), - .Q_OUT(hg_outputQueue_nextTag_dummy2_0$Q_OUT)); - - // submodule hg_outputQueue_nextTag_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) hg_outputQueue_nextTag_dummy2_1(.CLK(CLK), - .D_IN(hg_outputQueue_nextTag_dummy2_1$D_IN), - .EN(hg_outputQueue_nextTag_dummy2_1$EN), - .Q_OUT(hg_outputQueue_nextTag_dummy2_1$Q_OUT)); - - // submodule o_fifo_Stage__1_TO_Stage__3 - FIFO2 #(.width(32'd5), - .guarded(1'd1)) o_fifo_Stage__1_TO_Stage__3(.RST(RST_N), - .CLK(CLK), - .D_IN(o_fifo_Stage__1_TO_Stage__3$D_IN), - .ENQ(o_fifo_Stage__1_TO_Stage__3$ENQ), - .DEQ(o_fifo_Stage__1_TO_Stage__3$DEQ), - .CLR(o_fifo_Stage__1_TO_Stage__3$CLR), - .D_OUT(o_fifo_Stage__1_TO_Stage__3$D_OUT), - .FULL_N(o_fifo_Stage__1_TO_Stage__3$FULL_N), - .EMPTY_N(o_fifo_Stage__1_TO_Stage__3$EMPTY_N)); - - // submodule o_fifo_Start_TO_Stage__1 - FIFO2 #(.width(32'd15), - .guarded(1'd1)) o_fifo_Start_TO_Stage__1(.RST(RST_N), - .CLK(CLK), - .D_IN(o_fifo_Start_TO_Stage__1$D_IN), - .ENQ(o_fifo_Start_TO_Stage__1$ENQ), - .DEQ(o_fifo_Start_TO_Stage__1$DEQ), - .CLR(o_fifo_Start_TO_Stage__1$CLR), - .D_OUT(o_fifo_Start_TO_Stage__1$D_OUT), - .FULL_N(o_fifo_Start_TO_Stage__1$FULL_N), - .EMPTY_N(o_fifo_Start_TO_Stage__1$EMPTY_N)); - - // submodule o_fifo_Start_TO_Stage__3 - FIFO2 #(.width(32'd3), .guarded(1'd1)) o_fifo_Start_TO_Stage__3(.RST(RST_N), - .CLK(CLK), - .D_IN(o_fifo_Start_TO_Stage__3$D_IN), - .ENQ(o_fifo_Start_TO_Stage__3$ENQ), - .DEQ(o_fifo_Start_TO_Stage__3$DEQ), - .CLR(o_fifo_Start_TO_Stage__3$CLR), - .D_OUT(o_fifo_Start_TO_Stage__3$D_OUT), - .FULL_N(o_fifo_Start_TO_Stage__3$FULL_N), - .EMPTY_N(o_fifo_Start_TO_Stage__3$EMPTY_N)); - - // submodule o_fifo_Start_TO_Stage__3_1 - FIFO2 #(.width(32'd2), - .guarded(1'd1)) o_fifo_Start_TO_Stage__3_1(.RST(RST_N), - .CLK(CLK), - .D_IN(o_fifo_Start_TO_Stage__3_1$D_IN), - .ENQ(o_fifo_Start_TO_Stage__3_1$ENQ), - .DEQ(o_fifo_Start_TO_Stage__3_1$DEQ), - .CLR(o_fifo_Start_TO_Stage__3_1$CLR), - .D_OUT(), - .FULL_N(o_fifo_Start_TO_Stage__3_1$FULL_N), - .EMPTY_N(o_fifo_Start_TO_Stage__3_1$EMPTY_N)); - - // submodule o_fifo__input__TO_Start_f - FIFO2 #(.width(32'd12), - .guarded(1'd1)) o_fifo__input__TO_Start_f(.RST(RST_N), - .CLK(CLK), - .D_IN(o_fifo__input__TO_Start_f$D_IN), - .ENQ(o_fifo__input__TO_Start_f$ENQ), - .DEQ(o_fifo__input__TO_Start_f$DEQ), - .CLR(o_fifo__input__TO_Start_f$CLR), - .D_OUT(o_fifo__input__TO_Start_f$D_OUT), - .FULL_N(o_fifo__input__TO_Start_f$FULL_N), - .EMPTY_N(o_fifo__input__TO_Start_f$EMPTY_N)); - - // submodule o_nextId_dummy2_0 - RevertReg #(.width(32'd1), .init(1'd1)) o_nextId_dummy2_0(.CLK(CLK), - .D_IN(o_nextId_dummy2_0$D_IN), - .EN(o_nextId_dummy2_0$EN), - .Q_OUT(o_nextId_dummy2_0$Q_OUT)); - - // submodule o_nextId_dummy2_1 - RevertReg #(.width(32'd1), .init(1'd1)) o_nextId_dummy2_1(.CLK(CLK), - .D_IN(o_nextId_dummy2_1$D_IN), - .EN(o_nextId_dummy2_1$EN), - .Q_OUT(o_nextId_dummy2_1$Q_OUT)); - - // submodule o_outputQueue_nextTag_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) o_outputQueue_nextTag_dummy2_0(.CLK(CLK), - .D_IN(o_outputQueue_nextTag_dummy2_0$D_IN), - .EN(o_outputQueue_nextTag_dummy2_0$EN), - .Q_OUT(o_outputQueue_nextTag_dummy2_0$Q_OUT)); - - // submodule o_outputQueue_nextTag_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) o_outputQueue_nextTag_dummy2_1(.CLK(CLK), - .D_IN(o_outputQueue_nextTag_dummy2_1$D_IN), - .EN(o_outputQueue_nextTag_dummy2_1$EN), - .Q_OUT(o_outputQueue_nextTag_dummy2_1$Q_OUT)); - - // submodule tf_rf - RegFileLoad #(.file("f"), - .addr_width(32'd10), - .data_width(32'd16), - .lo(10'h0), - .hi(10'd1023), - .binary(1'd0)) tf_rf(.CLK(CLK), - .ADDR_1(tf_rf$ADDR_1), - .ADDR_2(tf_rf$ADDR_2), - .ADDR_3(tf_rf$ADDR_3), - .ADDR_4(tf_rf$ADDR_4), - .ADDR_5(tf_rf$ADDR_5), - .ADDR_IN(tf_rf$ADDR_IN), - .D_IN(tf_rf$D_IN), - .WE(tf_rf$WE), - .D_OUT_1(tf_rf$D_OUT_1), - .D_OUT_2(), - .D_OUT_3(), - .D_OUT_4(), - .D_OUT_5()); - - // submodule th_rf - RegFileLoad #(.file("h"), - .addr_width(32'd10), - .data_width(32'd32), - .lo(10'h0), - .hi(10'd1023), - .binary(1'd0)) th_rf(.CLK(CLK), - .ADDR_1(th_rf$ADDR_1), - .ADDR_2(th_rf$ADDR_2), - .ADDR_3(th_rf$ADDR_3), - .ADDR_4(th_rf$ADDR_4), - .ADDR_5(th_rf$ADDR_5), - .ADDR_IN(th_rf$ADDR_IN), - .D_IN(th_rf$D_IN), - .WE(th_rf$WE), - .D_OUT_1(th_rf$D_OUT_1), - .D_OUT_2(), - .D_OUT_3(), - .D_OUT_4(), - .D_OUT_5()); - - // submodule tw_rf - RegFileLoad #(.file("w"), - .addr_width(32'd10), - .data_width(32'd32), - .lo(10'h0), - .hi(10'd1023), - .binary(1'd0)) tw_rf(.CLK(CLK), - .ADDR_1(tw_rf$ADDR_1), - .ADDR_2(tw_rf$ADDR_2), - .ADDR_3(tw_rf$ADDR_3), - .ADDR_4(tw_rf$ADDR_4), - .ADDR_5(tw_rf$ADDR_5), - .ADDR_IN(tw_rf$ADDR_IN), - .D_IN(tw_rf$D_IN), - .WE(tw_rf$WE), - .D_OUT_1(tw_rf$D_OUT_1), - .D_OUT_2(), - .D_OUT_3(), - .D_OUT_4(), - .D_OUT_5()); - - // submodule w_l_lockVec_0_nextId_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) w_l_lockVec_0_nextId_dummy2_0(.CLK(CLK), - .D_IN(w_l_lockVec_0_nextId_dummy2_0$D_IN), - .EN(w_l_lockVec_0_nextId_dummy2_0$EN), - .Q_OUT()); - - // submodule w_l_lockVec_0_nextId_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) w_l_lockVec_0_nextId_dummy2_1(.CLK(CLK), - .D_IN(w_l_lockVec_0_nextId_dummy2_1$D_IN), - .EN(w_l_lockVec_0_nextId_dummy2_1$EN), - .Q_OUT(w_l_lockVec_0_nextId_dummy2_1$Q_OUT)); - - // submodule w_l_lockVec_1_nextId_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) w_l_lockVec_1_nextId_dummy2_0(.CLK(CLK), - .D_IN(w_l_lockVec_1_nextId_dummy2_0$D_IN), - .EN(w_l_lockVec_1_nextId_dummy2_0$EN), - .Q_OUT()); - - // submodule w_l_lockVec_1_nextId_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) w_l_lockVec_1_nextId_dummy2_1(.CLK(CLK), - .D_IN(w_l_lockVec_1_nextId_dummy2_1$D_IN), - .EN(w_l_lockVec_1_nextId_dummy2_1$EN), - .Q_OUT(w_l_lockVec_1_nextId_dummy2_1$Q_OUT)); - - // submodule w_l_lockVec_2_nextId_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) w_l_lockVec_2_nextId_dummy2_0(.CLK(CLK), - .D_IN(w_l_lockVec_2_nextId_dummy2_0$D_IN), - .EN(w_l_lockVec_2_nextId_dummy2_0$EN), - .Q_OUT()); - - // submodule w_l_lockVec_2_nextId_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) w_l_lockVec_2_nextId_dummy2_1(.CLK(CLK), - .D_IN(w_l_lockVec_2_nextId_dummy2_1$D_IN), - .EN(w_l_lockVec_2_nextId_dummy2_1$EN), - .Q_OUT(w_l_lockVec_2_nextId_dummy2_1$Q_OUT)); - - // submodule w_l_lockVec_3_nextId_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) w_l_lockVec_3_nextId_dummy2_0(.CLK(CLK), - .D_IN(w_l_lockVec_3_nextId_dummy2_0$D_IN), - .EN(w_l_lockVec_3_nextId_dummy2_0$EN), - .Q_OUT()); - - // submodule w_l_lockVec_3_nextId_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) w_l_lockVec_3_nextId_dummy2_1(.CLK(CLK), - .D_IN(w_l_lockVec_3_nextId_dummy2_1$D_IN), - .EN(w_l_lockVec_3_nextId_dummy2_1$EN), - .Q_OUT(w_l_lockVec_3_nextId_dummy2_1$Q_OUT)); - - // rule RL_hg_s_Stage__0_execute - assign WILL_FIRE_RL_hg_s_Stage__0_execute = - hg_fifo_Start_TO_Stage__0$EMPTY_N && - hg_fifo_Stage__0_TO_Stage__1$FULL_N && - IF_h_l_entryVec_3_read__32_BIT_10_33_AND_IF_h__ETC___d483 && - (IF_h_l_entryVec_3_read__32_BIT_10_33_THEN_h_l__ETC___d443 || - IF_h_l_entryVec_2_read__25_BIT_10_26_THEN_h_l__ETC___d447 || - IF_h_l_entryVec_1_read__18_BIT_10_19_THEN_h_l__ETC___d451 || - IF_h_l_entryVec_0_read__11_BIT_10_12_THEN_h_l__ETC___d455 || - NOT_h_l_entryVec_3_read__32_BIT_10_33_79_OR_NO_ETC___d482) ; - - // rule RL_h_l_freelock - assign WILL_FIRE_RL_h_l_freelock = - h_l_lockVec_0_empty && h_l_entryVec_0[10] && !h_l_resVec_0$whas ; - - // rule RL_h_l_freelock_1 - assign WILL_FIRE_RL_h_l_freelock_1 = - h_l_lockVec_1_empty && h_l_entryVec_1[10] && !h_l_resVec_1$whas ; - - // rule RL_h_l_freelock_2 - assign WILL_FIRE_RL_h_l_freelock_2 = - h_l_lockVec_2_empty && h_l_entryVec_2[10] && !h_l_resVec_2$whas ; - - // rule RL_h_l_freelock_3 - assign WILL_FIRE_RL_h_l_freelock_3 = - h_l_lockVec_3_empty && h_l_entryVec_3[10] && !h_l_resVec_3$whas ; - - // rule RL_hg_s_Stage__1_execute - assign WILL_FIRE_RL_hg_s_Stage__1_execute = - hg_fifo_Stage__0_TO_Stage__1$EMPTY_N && - hg_fifo_Stage__1_TO_Stage__2$FULL_N && - (h_l_entryVec_3_read__32_BIT_10_33_AND_IF_h_l_e_ETC___d563 ? - SEL_ARR_h_l_lockVec_0_owner_64_EQ_IF_hg_fifo_S_ETC___d590 : - NOT_h_l_entryVec_3_read__32_BIT_10_33_79_OR_NO_ETC___d482) ; - - // rule RL_o_s_Start_execute - assign WILL_FIRE_RL_o_s_Start_execute = - o_fifo__input__TO_Start_f$EMPTY_N && - o_fifo_Start_TO_Stage__3$FULL_N && - (o_fifo__input__TO_Start_f_first__47_BITS_11_TO_ETC___d649 || - o_fifo_Start_TO_Stage__3_1$FULL_N) && - (!o_fifo__input__TO_Start_f_first__47_BITS_11_TO_ETC___d649 || - o_fifo__input__TO_Start_f$FULL_N) && - (!o_fifo__input__TO_Start_f_first__47_BITS_11_TO_ETC___d649 || - o_fifo_Start_TO_Stage__1$FULL_N) && - o_fifo__input__TO_Start_f_first__47_BITS_11_TO_ETC___d665 ; - - // rule RL_o_s_Stage__3_execute - assign WILL_FIRE_RL_o_s_Stage__3_execute = - o_fifo_Start_TO_Stage__3$EMPTY_N && - (o_fifo_Start_TO_Stage__3$D_OUT[2] || - o_fifo_Stage__1_TO_Stage__3$EMPTY_N) && - (!o_fifo_Start_TO_Stage__3$D_OUT[2] || - o_fifo_Start_TO_Stage__3_1$EMPTY_N) && - o_fifo_Start_TO_Stage__3_first__77_BIT_2_78_OR_ETC___d695 ; - - // rule RL_hg_s_Stage__2_execute - assign WILL_FIRE_RL_hg_s_Stage__2_execute = - hg_fifo_Stage__1_TO_Stage__2$EMPTY_N && - (hg_outputQueue_nextTag_dummy2_1$Q_OUT ? - IF_hg_outputQueue_nextTag_lat_0_whas__40_THEN__ETC___d343 : - 3'd0) == - hg_fifo_Stage__1_TO_Stage__2$D_OUT ; - - // inputs to muxes for submodule ports - assign MUX_hg_outputQueue_val$write_1__SEL_2 = - WILL_FIRE_RL_o_s_Stage__3_execute && - !o_fifo_Start_TO_Stage__3$D_OUT[2] ; - assign MUX_o_busyReg$write_1__SEL_1 = - WILL_FIRE_RL_o_s_Start_execute && - !o_fifo__input__TO_Start_f_first__47_BITS_11_TO_ETC___d649 ; - assign MUX_o_fifo__input__TO_Start_enq_data$wset_1__SEL_1 = - WILL_FIRE_RL_o_s_Start_execute && - o_fifo__input__TO_Start_f_first__47_BITS_11_TO_ETC___d649 ; - assign MUX_h_l_entryVec_0$write_1__VAL_2 = - { 1'd1, hg_fifo_Start_TO_Stage__0$D_OUT[44:35] } ; - assign MUX_o_fifo__input__TO_Start_enq_data$wset_1__VAL_1 = - { o_fifo__input__TO_Start_f$D_OUT[11:2] + 10'd1, - o_fifo__input__TO_Start_f$D_OUT[1:0] } ; - assign MUX_o_fifo__input__TO_Start_enq_data$wset_1__VAL_2 = - { _into_req_counter, o } ; - - // inlined wires - assign h_l_lockVec_0_nextId_lat_0$whas = - WILL_FIRE_RL_hg_s_Stage__0_execute && - (IF_NOT_h_l_entryVec_2_read__25_BIT_10_26_61_OR_ETC___d491 || - x__h27260 == 2'd0 && - NOT_h_l_entryVec_3_read__32_BIT_10_33_79_OR_NO_ETC___d526) ; - assign h_l_lockVec_0_doRel$whas = - WILL_FIRE_RL_hg_s_Stage__1_execute && x__h29141 == 2'd0 && - h_l_entryVec_3_read__32_BIT_10_33_AND_IF_h_l_e_ETC___d563 ; - assign h_l_lockVec_1_nextId_lat_0$whas = - WILL_FIRE_RL_hg_s_Stage__0_execute && - (IF_NOT_h_l_entryVec_2_read__25_BIT_10_26_61_OR_ETC___d493 || - x__h27260 == 2'd1 && - NOT_h_l_entryVec_3_read__32_BIT_10_33_79_OR_NO_ETC___d526) ; - assign h_l_lockVec_1_doRel$whas = - WILL_FIRE_RL_hg_s_Stage__1_execute && x__h29141 == 2'd1 && - h_l_entryVec_3_read__32_BIT_10_33_AND_IF_h_l_e_ETC___d563 ; - assign h_l_lockVec_2_nextId_lat_0$whas = - WILL_FIRE_RL_hg_s_Stage__0_execute && - (IF_NOT_h_l_entryVec_2_read__25_BIT_10_26_61_OR_ETC___d495 || - x__h27260 == 2'd2 && - NOT_h_l_entryVec_3_read__32_BIT_10_33_79_OR_NO_ETC___d526) ; - assign h_l_lockVec_2_doRel$whas = - WILL_FIRE_RL_hg_s_Stage__1_execute && x__h29141 == 2'd2 && - h_l_entryVec_3_read__32_BIT_10_33_AND_IF_h_l_e_ETC___d563 ; - assign h_l_lockVec_3_nextId_lat_0$whas = - WILL_FIRE_RL_hg_s_Stage__0_execute && - (IF_NOT_h_l_entryVec_2_read__25_BIT_10_26_61_OR_ETC___d497 || - x__h27260 == 2'd3 && - NOT_h_l_entryVec_3_read__32_BIT_10_33_79_OR_NO_ETC___d526) ; - assign h_l_lockVec_3_doRel$whas = - WILL_FIRE_RL_hg_s_Stage__1_execute && x__h29141 == 2'd3 && - h_l_entryVec_3_read__32_BIT_10_33_AND_IF_h_l_e_ETC___d563 ; - assign h_l_resVec_0$whas = - WILL_FIRE_RL_hg_s_Stage__0_execute && - IF_NOT_h_l_entryVec_2_read__25_BIT_10_26_61_OR_ETC___d491 ; - assign h_l_resVec_1$whas = - WILL_FIRE_RL_hg_s_Stage__0_execute && - IF_NOT_h_l_entryVec_2_read__25_BIT_10_26_61_OR_ETC___d493 ; - assign h_l_resVec_2$whas = - WILL_FIRE_RL_hg_s_Stage__0_execute && - IF_NOT_h_l_entryVec_2_read__25_BIT_10_26_61_OR_ETC___d495 ; - assign h_l_resVec_3$whas = - WILL_FIRE_RL_hg_s_Stage__0_execute && - IF_NOT_h_l_entryVec_2_read__25_BIT_10_26_61_OR_ETC___d497 ; - assign o_fifo__input__TO_Start_enq_data$wget = - MUX_o_fifo__input__TO_Start_enq_data$wset_1__SEL_1 ? - MUX_o_fifo__input__TO_Start_enq_data$wset_1__VAL_1 : - MUX_o_fifo__input__TO_Start_enq_data$wset_1__VAL_2 ; - assign o_fifo__input__TO_Start_enq_data$whas = - WILL_FIRE_RL_o_s_Start_execute && - o_fifo__input__TO_Start_f_first__47_BITS_11_TO_ETC___d649 || - EN__into_req ; - assign o_doRel$whas = - o_fifo_Start_TO_Stage__1$EMPTY_N && - !hg_fifo__input__TO_Start_rv[13] && - o_fifo_Stage__1_TO_Stage__3$FULL_N && - o_owner == o_fifo_Start_TO_Stage__1$D_OUT[3:2] ; - assign hg_fifo__input__TO_Start_rv$EN_port0__write = - o_fifo_Start_TO_Stage__1$EMPTY_N && - !hg_fifo__input__TO_Start_rv[13] && - o_fifo_Stage__1_TO_Stage__3$FULL_N && - o_owner == o_fifo_Start_TO_Stage__1$D_OUT[3:2] ; - assign hg_fifo__input__TO_Start_rv$port0__write_1 = - { 1'd1, o_fifo_Start_TO_Stage__1$D_OUT[14:5], hg } ; - assign hg_fifo__input__TO_Start_rv$port1__read = - hg_fifo__input__TO_Start_rv$EN_port0__write ? - hg_fifo__input__TO_Start_rv$port0__write_1 : - hg_fifo__input__TO_Start_rv ; - assign hg_fifo__input__TO_Start_rv$EN_port1__write = - hg_fifo__input__TO_Start_rv$port1__read[13] && - hg_fifo_Start_TO_Stage__0$FULL_N && - IF_f_l_entryVec_3_read__08_BIT_10_09_AND_f_l_e_ETC___d428 ; - assign hg_fifo__input__TO_Start_rv$port2__read = - hg_fifo__input__TO_Start_rv$EN_port1__write ? - 14'd2730 : - hg_fifo__input__TO_Start_rv$port1__read ; - - // register f_l_entryVec_0 - assign f_l_entryVec_0$D_IN = 11'd682 ; - assign f_l_entryVec_0$EN = f_l_lockVec_0_empty && f_l_entryVec_0[10] ; - - // register f_l_entryVec_1 - assign f_l_entryVec_1$D_IN = 11'd682 ; - assign f_l_entryVec_1$EN = f_l_lockVec_1_empty && f_l_entryVec_1[10] ; - - // register f_l_entryVec_2 - assign f_l_entryVec_2$D_IN = 11'd682 ; - assign f_l_entryVec_2$EN = f_l_lockVec_2_empty && f_l_entryVec_2[10] ; - - // register f_l_entryVec_3 - assign f_l_entryVec_3$D_IN = 11'd682 ; - assign f_l_entryVec_3$EN = f_l_lockVec_3_empty && f_l_entryVec_3[10] ; - - // register f_l_lockVec_0_empty - assign f_l_lockVec_0_empty$D_IN = - 2'h0 == - (f_l_lockVec_0_nextId_dummy2_1$Q_OUT ? - f_l_lockVec_0_nextId_rl : - 2'd0) ; - assign f_l_lockVec_0_empty$EN = 1'b0 ; - - // register f_l_lockVec_0_nextId_rl - assign f_l_lockVec_0_nextId_rl$D_IN = f_l_lockVec_0_nextId_rl ; - assign f_l_lockVec_0_nextId_rl$EN = 1'd1 ; - - // register f_l_lockVec_0_owner - assign f_l_lockVec_0_owner$D_IN = 2'h0 ; - assign f_l_lockVec_0_owner$EN = 1'b0 ; - - // register f_l_lockVec_1_empty - assign f_l_lockVec_1_empty$D_IN = - 2'h0 == - (f_l_lockVec_1_nextId_dummy2_1$Q_OUT ? - f_l_lockVec_1_nextId_rl : - 2'd0) ; - assign f_l_lockVec_1_empty$EN = 1'b0 ; - - // register f_l_lockVec_1_nextId_rl - assign f_l_lockVec_1_nextId_rl$D_IN = f_l_lockVec_1_nextId_rl ; - assign f_l_lockVec_1_nextId_rl$EN = 1'd1 ; - - // register f_l_lockVec_1_owner - assign f_l_lockVec_1_owner$D_IN = 2'h0 ; - assign f_l_lockVec_1_owner$EN = 1'b0 ; - - // register f_l_lockVec_2_empty - assign f_l_lockVec_2_empty$D_IN = - 2'h0 == - (f_l_lockVec_2_nextId_dummy2_1$Q_OUT ? - f_l_lockVec_2_nextId_rl : - 2'd0) ; - assign f_l_lockVec_2_empty$EN = 1'b0 ; - - // register f_l_lockVec_2_nextId_rl - assign f_l_lockVec_2_nextId_rl$D_IN = f_l_lockVec_2_nextId_rl ; - assign f_l_lockVec_2_nextId_rl$EN = 1'd1 ; - - // register f_l_lockVec_2_owner - assign f_l_lockVec_2_owner$D_IN = 2'h0 ; - assign f_l_lockVec_2_owner$EN = 1'b0 ; - - // register f_l_lockVec_3_empty - assign f_l_lockVec_3_empty$D_IN = - 2'h0 == - (f_l_lockVec_3_nextId_dummy2_1$Q_OUT ? - f_l_lockVec_3_nextId_rl : - 2'd0) ; - assign f_l_lockVec_3_empty$EN = 1'b0 ; - - // register f_l_lockVec_3_nextId_rl - assign f_l_lockVec_3_nextId_rl$D_IN = f_l_lockVec_3_nextId_rl ; - assign f_l_lockVec_3_nextId_rl$EN = 1'd1 ; - - // register f_l_lockVec_3_owner - assign f_l_lockVec_3_owner$D_IN = 2'h0 ; - assign f_l_lockVec_3_owner$EN = 1'b0 ; - - // register h_l_entryVec_0 - assign h_l_entryVec_0$D_IN = - WILL_FIRE_RL_h_l_freelock ? - 11'd682 : - MUX_h_l_entryVec_0$write_1__VAL_2 ; - assign h_l_entryVec_0$EN = - WILL_FIRE_RL_hg_s_Stage__0_execute && x__h27260 == 2'd0 && - NOT_h_l_entryVec_3_read__32_BIT_10_33_79_OR_NO_ETC___d526 || - WILL_FIRE_RL_h_l_freelock ; - - // register h_l_entryVec_1 - assign h_l_entryVec_1$D_IN = - WILL_FIRE_RL_h_l_freelock_1 ? - 11'd682 : - MUX_h_l_entryVec_0$write_1__VAL_2 ; - assign h_l_entryVec_1$EN = - WILL_FIRE_RL_hg_s_Stage__0_execute && x__h27260 == 2'd1 && - NOT_h_l_entryVec_3_read__32_BIT_10_33_79_OR_NO_ETC___d526 || - WILL_FIRE_RL_h_l_freelock_1 ; - - // register h_l_entryVec_2 - assign h_l_entryVec_2$D_IN = - WILL_FIRE_RL_h_l_freelock_2 ? - 11'd682 : - MUX_h_l_entryVec_0$write_1__VAL_2 ; - assign h_l_entryVec_2$EN = - WILL_FIRE_RL_hg_s_Stage__0_execute && x__h27260 == 2'd2 && - NOT_h_l_entryVec_3_read__32_BIT_10_33_79_OR_NO_ETC___d526 || - WILL_FIRE_RL_h_l_freelock_2 ; - - // register h_l_entryVec_3 - assign h_l_entryVec_3$D_IN = - WILL_FIRE_RL_h_l_freelock_3 ? - 11'd682 : - MUX_h_l_entryVec_0$write_1__VAL_2 ; - assign h_l_entryVec_3$EN = - WILL_FIRE_RL_hg_s_Stage__0_execute && x__h27260 == 2'd3 && - NOT_h_l_entryVec_3_read__32_BIT_10_33_79_OR_NO_ETC___d526 || - WILL_FIRE_RL_h_l_freelock_3 ; - - // register h_l_lockVec_0_empty - assign h_l_lockVec_0_empty$D_IN = - (!h_l_lockVec_0_nextId_lat_0$whas || h_l_lockVec_0_doRel$whas) && - b__h17187 == - (h_l_lockVec_0_nextId_dummy2_1$Q_OUT ? - IF_h_l_lockVec_0_nextId_lat_0_whas__28_THEN_h__ETC___d231 : - 2'd0) ; - assign h_l_lockVec_0_empty$EN = - h_l_lockVec_0_nextId_lat_0$whas && !h_l_lockVec_0_doRel$whas || - !h_l_lockVec_0_nextId_lat_0$whas && h_l_lockVec_0_doRel$whas ; - - // register h_l_lockVec_0_nextId_rl - assign h_l_lockVec_0_nextId_rl$D_IN = - IF_h_l_lockVec_0_nextId_lat_0_whas__28_THEN_h__ETC___d231 ; - assign h_l_lockVec_0_nextId_rl$EN = 1'd1 ; - - // register h_l_lockVec_0_owner - assign h_l_lockVec_0_owner$D_IN = b__h17187 ; - assign h_l_lockVec_0_owner$EN = h_l_lockVec_0_doRel$whas ; - - // register h_l_lockVec_1_empty - assign h_l_lockVec_1_empty$D_IN = - (!h_l_lockVec_1_nextId_lat_0$whas || h_l_lockVec_1_doRel$whas) && - b__h18595 == - (h_l_lockVec_1_nextId_dummy2_1$Q_OUT ? - IF_h_l_lockVec_1_nextId_lat_0_whas__49_THEN_h__ETC___d252 : - 2'd0) ; - assign h_l_lockVec_1_empty$EN = - h_l_lockVec_1_nextId_lat_0$whas && !h_l_lockVec_1_doRel$whas || - !h_l_lockVec_1_nextId_lat_0$whas && h_l_lockVec_1_doRel$whas ; - - // register h_l_lockVec_1_nextId_rl - assign h_l_lockVec_1_nextId_rl$D_IN = - IF_h_l_lockVec_1_nextId_lat_0_whas__49_THEN_h__ETC___d252 ; - assign h_l_lockVec_1_nextId_rl$EN = 1'd1 ; - - // register h_l_lockVec_1_owner - assign h_l_lockVec_1_owner$D_IN = b__h18595 ; - assign h_l_lockVec_1_owner$EN = h_l_lockVec_1_doRel$whas ; - - // register h_l_lockVec_2_empty - assign h_l_lockVec_2_empty$D_IN = - (!h_l_lockVec_2_nextId_lat_0$whas || h_l_lockVec_2_doRel$whas) && - b__h20003 == - (h_l_lockVec_2_nextId_dummy2_1$Q_OUT ? - IF_h_l_lockVec_2_nextId_lat_0_whas__70_THEN_h__ETC___d273 : - 2'd0) ; - assign h_l_lockVec_2_empty$EN = - h_l_lockVec_2_nextId_lat_0$whas && !h_l_lockVec_2_doRel$whas || - !h_l_lockVec_2_nextId_lat_0$whas && h_l_lockVec_2_doRel$whas ; - - // register h_l_lockVec_2_nextId_rl - assign h_l_lockVec_2_nextId_rl$D_IN = - IF_h_l_lockVec_2_nextId_lat_0_whas__70_THEN_h__ETC___d273 ; - assign h_l_lockVec_2_nextId_rl$EN = 1'd1 ; - - // register h_l_lockVec_2_owner - assign h_l_lockVec_2_owner$D_IN = b__h20003 ; - assign h_l_lockVec_2_owner$EN = h_l_lockVec_2_doRel$whas ; - - // register h_l_lockVec_3_empty - assign h_l_lockVec_3_empty$D_IN = - (!h_l_lockVec_3_nextId_lat_0$whas || h_l_lockVec_3_doRel$whas) && - b__h21411 == - (h_l_lockVec_3_nextId_dummy2_1$Q_OUT ? - IF_h_l_lockVec_3_nextId_lat_0_whas__91_THEN_h__ETC___d294 : - 2'd0) ; - assign h_l_lockVec_3_empty$EN = - h_l_lockVec_3_nextId_lat_0$whas && !h_l_lockVec_3_doRel$whas || - !h_l_lockVec_3_nextId_lat_0$whas && h_l_lockVec_3_doRel$whas ; - - // register h_l_lockVec_3_nextId_rl - assign h_l_lockVec_3_nextId_rl$D_IN = - IF_h_l_lockVec_3_nextId_lat_0_whas__91_THEN_h__ETC___d294 ; - assign h_l_lockVec_3_nextId_rl$EN = 1'd1 ; - - // register h_l_lockVec_3_owner - assign h_l_lockVec_3_owner$D_IN = b__h21411 ; - assign h_l_lockVec_3_owner$EN = h_l_lockVec_3_doRel$whas ; - - // register hg - assign hg$D_IN = hg + 3'd1 ; - assign hg$EN = o_doRel$whas ; - - // register hg_feature_lock_region - assign hg_feature_lock_region$D_IN = 1'b0 ; - assign hg_feature_lock_region$EN = 1'b0 ; - - // register hg_fifo__input__TO_Start_rv - assign hg_fifo__input__TO_Start_rv$D_IN = - hg_fifo__input__TO_Start_rv$port2__read ; - assign hg_fifo__input__TO_Start_rv$EN = 1'b1 ; - - // register hg_h_lock_region - assign hg_h_lock_region$D_IN = 1'b0 ; - assign hg_h_lock_region$EN = 1'b0 ; - - // register hg_outputQueue_nextTag_rl - assign hg_outputQueue_nextTag_rl$D_IN = - IF_hg_outputQueue_nextTag_lat_0_whas__40_THEN__ETC___d343 ; - assign hg_outputQueue_nextTag_rl$EN = 1'd1 ; - - // register hg_outputQueue_val - assign hg_outputQueue_val$D_IN = - WILL_FIRE_RL_hg_s_Stage__2_execute ? 2'd3 : 2'd0 ; - assign hg_outputQueue_val$EN = - WILL_FIRE_RL_o_s_Stage__3_execute && - !o_fifo_Start_TO_Stage__3$D_OUT[2] || - WILL_FIRE_RL_hg_s_Stage__2_execute ; - - // register hg_weight_lock_region - assign hg_weight_lock_region$D_IN = 1'b0 ; - assign hg_weight_lock_region$EN = 1'b0 ; - - // register o - assign o$D_IN = o + 2'd1 ; - assign o$EN = EN__into_req ; - - // register o_busyReg - assign o_busyReg$D_IN = !MUX_o_busyReg$write_1__SEL_1 ; - assign o_busyReg$EN = - WILL_FIRE_RL_o_s_Start_execute && - !o_fifo__input__TO_Start_f_first__47_BITS_11_TO_ETC___d649 || - EN__into_req ; - - // register o_empty - assign o_empty$D_IN = - (!MUX_o_fifo__input__TO_Start_enq_data$wset_1__SEL_1 || - o_doRel$whas) && - b__h32070 == - (o_nextId_dummy2_1$Q_OUT ? - IF_o_nextId_lat_0_whas__19_THEN_o_nextId_lat_0_ETC___d622 : - 2'd0) ; - assign o_empty$EN = - MUX_o_fifo__input__TO_Start_enq_data$wset_1__SEL_1 && - !o_doRel$whas || - !MUX_o_fifo__input__TO_Start_enq_data$wset_1__SEL_1 && - o_doRel$whas ; - - // register o_h_lock_region - assign o_h_lock_region$D_IN = 1'b0 ; - assign o_h_lock_region$EN = 1'b0 ; - - // register o_nextId_rl - assign o_nextId_rl$D_IN = - IF_o_nextId_lat_0_whas__19_THEN_o_nextId_lat_0_ETC___d622 ; - assign o_nextId_rl$EN = 1'd1 ; - - // register o_outputQueue_nextTag_rl - assign o_outputQueue_nextTag_rl$D_IN = - IF_o_outputQueue_nextTag_lat_0_whas__40_THEN_o_ETC___d643 ; - assign o_outputQueue_nextTag_rl$EN = 1'd1 ; - - // register o_outputQueue_val - assign o_outputQueue_val$D_IN = MUX_o_busyReg$write_1__SEL_1 ; - assign o_outputQueue_val$EN = - WILL_FIRE_RL_o_s_Start_execute && - !o_fifo__input__TO_Start_f_first__47_BITS_11_TO_ETC___d649 || - EN__into_resp ; - - // register o_owner - assign o_owner$D_IN = b__h32070 ; - assign o_owner$EN = o_doRel$whas ; - - // register w_l_entryVec_0 - assign w_l_entryVec_0$D_IN = 11'd682 ; - assign w_l_entryVec_0$EN = w_l_lockVec_0_empty && w_l_entryVec_0[10] ; - - // register w_l_entryVec_1 - assign w_l_entryVec_1$D_IN = 11'd682 ; - assign w_l_entryVec_1$EN = w_l_lockVec_1_empty && w_l_entryVec_1[10] ; - - // register w_l_entryVec_2 - assign w_l_entryVec_2$D_IN = 11'd682 ; - assign w_l_entryVec_2$EN = w_l_lockVec_2_empty && w_l_entryVec_2[10] ; - - // register w_l_entryVec_3 - assign w_l_entryVec_3$D_IN = 11'd682 ; - assign w_l_entryVec_3$EN = w_l_lockVec_3_empty && w_l_entryVec_3[10] ; - - // register w_l_lockVec_0_empty - assign w_l_lockVec_0_empty$D_IN = - 2'h0 == - (w_l_lockVec_0_nextId_dummy2_1$Q_OUT ? - w_l_lockVec_0_nextId_rl : - 2'd0) ; - assign w_l_lockVec_0_empty$EN = 1'b0 ; - - // register w_l_lockVec_0_nextId_rl - assign w_l_lockVec_0_nextId_rl$D_IN = w_l_lockVec_0_nextId_rl ; - assign w_l_lockVec_0_nextId_rl$EN = 1'd1 ; - - // register w_l_lockVec_0_owner - assign w_l_lockVec_0_owner$D_IN = 2'h0 ; - assign w_l_lockVec_0_owner$EN = 1'b0 ; - - // register w_l_lockVec_1_empty - assign w_l_lockVec_1_empty$D_IN = - 2'h0 == - (w_l_lockVec_1_nextId_dummy2_1$Q_OUT ? - w_l_lockVec_1_nextId_rl : - 2'd0) ; - assign w_l_lockVec_1_empty$EN = 1'b0 ; - - // register w_l_lockVec_1_nextId_rl - assign w_l_lockVec_1_nextId_rl$D_IN = w_l_lockVec_1_nextId_rl ; - assign w_l_lockVec_1_nextId_rl$EN = 1'd1 ; - - // register w_l_lockVec_1_owner - assign w_l_lockVec_1_owner$D_IN = 2'h0 ; - assign w_l_lockVec_1_owner$EN = 1'b0 ; - - // register w_l_lockVec_2_empty - assign w_l_lockVec_2_empty$D_IN = - 2'h0 == - (w_l_lockVec_2_nextId_dummy2_1$Q_OUT ? - w_l_lockVec_2_nextId_rl : - 2'd0) ; - assign w_l_lockVec_2_empty$EN = 1'b0 ; - - // register w_l_lockVec_2_nextId_rl - assign w_l_lockVec_2_nextId_rl$D_IN = w_l_lockVec_2_nextId_rl ; - assign w_l_lockVec_2_nextId_rl$EN = 1'd1 ; - - // register w_l_lockVec_2_owner - assign w_l_lockVec_2_owner$D_IN = 2'h0 ; - assign w_l_lockVec_2_owner$EN = 1'b0 ; - - // register w_l_lockVec_3_empty - assign w_l_lockVec_3_empty$D_IN = - 2'h0 == - (w_l_lockVec_3_nextId_dummy2_1$Q_OUT ? - w_l_lockVec_3_nextId_rl : - 2'd0) ; - assign w_l_lockVec_3_empty$EN = 1'b0 ; - - // register w_l_lockVec_3_nextId_rl - assign w_l_lockVec_3_nextId_rl$D_IN = w_l_lockVec_3_nextId_rl ; - assign w_l_lockVec_3_nextId_rl$EN = 1'd1 ; - - // register w_l_lockVec_3_owner - assign w_l_lockVec_3_owner$D_IN = 2'h0 ; - assign w_l_lockVec_3_owner$EN = 1'b0 ; - - // submodule f_l_lockVec_0_nextId_dummy2_0 - assign f_l_lockVec_0_nextId_dummy2_0$D_IN = 1'b0 ; - assign f_l_lockVec_0_nextId_dummy2_0$EN = 1'b0 ; - - // submodule f_l_lockVec_0_nextId_dummy2_1 - assign f_l_lockVec_0_nextId_dummy2_1$D_IN = 1'b0 ; - assign f_l_lockVec_0_nextId_dummy2_1$EN = 1'b0 ; - - // submodule f_l_lockVec_1_nextId_dummy2_0 - assign f_l_lockVec_1_nextId_dummy2_0$D_IN = 1'b0 ; - assign f_l_lockVec_1_nextId_dummy2_0$EN = 1'b0 ; - - // submodule f_l_lockVec_1_nextId_dummy2_1 - assign f_l_lockVec_1_nextId_dummy2_1$D_IN = 1'b0 ; - assign f_l_lockVec_1_nextId_dummy2_1$EN = 1'b0 ; - - // submodule f_l_lockVec_2_nextId_dummy2_0 - assign f_l_lockVec_2_nextId_dummy2_0$D_IN = 1'b0 ; - assign f_l_lockVec_2_nextId_dummy2_0$EN = 1'b0 ; - - // submodule f_l_lockVec_2_nextId_dummy2_1 - assign f_l_lockVec_2_nextId_dummy2_1$D_IN = 1'b0 ; - assign f_l_lockVec_2_nextId_dummy2_1$EN = 1'b0 ; - - // submodule f_l_lockVec_3_nextId_dummy2_0 - assign f_l_lockVec_3_nextId_dummy2_0$D_IN = 1'b0 ; - assign f_l_lockVec_3_nextId_dummy2_0$EN = 1'b0 ; - - // submodule f_l_lockVec_3_nextId_dummy2_1 - assign f_l_lockVec_3_nextId_dummy2_1$D_IN = 1'b0 ; - assign f_l_lockVec_3_nextId_dummy2_1$EN = 1'b0 ; - - // submodule h_l_lockVec_0_nextId_dummy2_0 - assign h_l_lockVec_0_nextId_dummy2_0$D_IN = 1'd1 ; - assign h_l_lockVec_0_nextId_dummy2_0$EN = h_l_lockVec_0_nextId_lat_0$whas ; - - // submodule h_l_lockVec_0_nextId_dummy2_1 - assign h_l_lockVec_0_nextId_dummy2_1$D_IN = 1'b0 ; - assign h_l_lockVec_0_nextId_dummy2_1$EN = 1'b0 ; - - // submodule h_l_lockVec_1_nextId_dummy2_0 - assign h_l_lockVec_1_nextId_dummy2_0$D_IN = 1'd1 ; - assign h_l_lockVec_1_nextId_dummy2_0$EN = h_l_lockVec_1_nextId_lat_0$whas ; - - // submodule h_l_lockVec_1_nextId_dummy2_1 - assign h_l_lockVec_1_nextId_dummy2_1$D_IN = 1'b0 ; - assign h_l_lockVec_1_nextId_dummy2_1$EN = 1'b0 ; - - // submodule h_l_lockVec_2_nextId_dummy2_0 - assign h_l_lockVec_2_nextId_dummy2_0$D_IN = 1'd1 ; - assign h_l_lockVec_2_nextId_dummy2_0$EN = h_l_lockVec_2_nextId_lat_0$whas ; - - // submodule h_l_lockVec_2_nextId_dummy2_1 - assign h_l_lockVec_2_nextId_dummy2_1$D_IN = 1'b0 ; - assign h_l_lockVec_2_nextId_dummy2_1$EN = 1'b0 ; - - // submodule h_l_lockVec_3_nextId_dummy2_0 - assign h_l_lockVec_3_nextId_dummy2_0$D_IN = 1'd1 ; - assign h_l_lockVec_3_nextId_dummy2_0$EN = h_l_lockVec_3_nextId_lat_0$whas ; - - // submodule h_l_lockVec_3_nextId_dummy2_1 - assign h_l_lockVec_3_nextId_dummy2_1$D_IN = 1'b0 ; - assign h_l_lockVec_3_nextId_dummy2_1$EN = 1'b0 ; - - // submodule hg_fifo_Stage__0_TO_Stage__1 - assign hg_fifo_Stage__0_TO_Stage__1$D_IN = - { th_rf_sub_hg_fifo_Start_TO_Stage__0_first__41__ETC___d537, - 1'd1, - IF_h_l_entryVec_3_read__32_BIT_10_33_AND_IF_h__ETC___d543, - hg_fifo_Start_TO_Stage__0$D_OUT[44:35], - hg_fifo_Start_TO_Stage__0$D_OUT[2:0] } ; - assign hg_fifo_Stage__0_TO_Stage__1$ENQ = - WILL_FIRE_RL_hg_s_Stage__0_execute ; - assign hg_fifo_Stage__0_TO_Stage__1$DEQ = - WILL_FIRE_RL_hg_s_Stage__1_execute ; - assign hg_fifo_Stage__0_TO_Stage__1$CLR = 1'b0 ; - - // submodule hg_fifo_Stage__1_TO_Stage__2 - assign hg_fifo_Stage__1_TO_Stage__2$D_IN = - hg_fifo_Stage__0_TO_Stage__1$D_OUT[2:0] ; - assign hg_fifo_Stage__1_TO_Stage__2$ENQ = - WILL_FIRE_RL_hg_s_Stage__1_execute ; - assign hg_fifo_Stage__1_TO_Stage__2$DEQ = - WILL_FIRE_RL_hg_s_Stage__2_execute ; - assign hg_fifo_Stage__1_TO_Stage__2$CLR = 1'b0 ; - - // submodule hg_fifo_Start_TO_Stage__0 - assign hg_fifo_Start_TO_Stage__0$D_IN = - { tf_rf$D_OUT_1[9:0], - tw_rf$D_OUT_1, - hg_fifo__input__TO_Start_rv$port1__read[2:0] } ; - assign hg_fifo_Start_TO_Stage__0$ENQ = - hg_fifo__input__TO_Start_rv$port1__read[13] && - hg_fifo_Start_TO_Stage__0$FULL_N && - IF_f_l_entryVec_3_read__08_BIT_10_09_AND_f_l_e_ETC___d428 ; - assign hg_fifo_Start_TO_Stage__0$DEQ = WILL_FIRE_RL_hg_s_Stage__0_execute ; - assign hg_fifo_Start_TO_Stage__0$CLR = 1'b0 ; - - // submodule hg_outputQueue_nextTag_dummy2_0 - assign hg_outputQueue_nextTag_dummy2_0$D_IN = 1'd1 ; - assign hg_outputQueue_nextTag_dummy2_0$EN = - MUX_hg_outputQueue_val$write_1__SEL_2 ; - - // submodule hg_outputQueue_nextTag_dummy2_1 - assign hg_outputQueue_nextTag_dummy2_1$D_IN = 1'b0 ; - assign hg_outputQueue_nextTag_dummy2_1$EN = 1'b0 ; - - // submodule o_fifo_Stage__1_TO_Stage__3 - assign o_fifo_Stage__1_TO_Stage__3$D_IN = - { hg, o_fifo_Start_TO_Stage__1$D_OUT[1:0] } ; - assign o_fifo_Stage__1_TO_Stage__3$ENQ = o_doRel$whas ; - assign o_fifo_Stage__1_TO_Stage__3$DEQ = - MUX_hg_outputQueue_val$write_1__SEL_2 ; - assign o_fifo_Stage__1_TO_Stage__3$CLR = 1'b0 ; - - // submodule o_fifo_Start_TO_Stage__1 - assign o_fifo_Start_TO_Stage__1$D_IN = - { o_fifo__input__TO_Start_f$D_OUT[11:2], - o_fifo__input__TO_Start_f_first__47_BITS_11_TO_ETC___d649, - IF_o_nextId_dummy2_0_read__67_AND_o_nextId_dum_ETC___d669, - o_fifo__input__TO_Start_f$D_OUT[1:0] } ; - assign o_fifo_Start_TO_Stage__1$ENQ = - MUX_o_fifo__input__TO_Start_enq_data$wset_1__SEL_1 ; - assign o_fifo_Start_TO_Stage__1$DEQ = o_doRel$whas ; - assign o_fifo_Start_TO_Stage__1$CLR = 1'b0 ; - - // submodule o_fifo_Start_TO_Stage__3 - assign o_fifo_Start_TO_Stage__3$D_IN = - { !o_fifo__input__TO_Start_f_first__47_BITS_11_TO_ETC___d649, - o_fifo__input__TO_Start_f$D_OUT[1:0] } ; - assign o_fifo_Start_TO_Stage__3$ENQ = WILL_FIRE_RL_o_s_Start_execute ; - assign o_fifo_Start_TO_Stage__3$DEQ = WILL_FIRE_RL_o_s_Stage__3_execute ; - assign o_fifo_Start_TO_Stage__3$CLR = 1'b0 ; - - // submodule o_fifo_Start_TO_Stage__3_1 - assign o_fifo_Start_TO_Stage__3_1$D_IN = - o_fifo__input__TO_Start_f$D_OUT[1:0] ; - assign o_fifo_Start_TO_Stage__3_1$ENQ = MUX_o_busyReg$write_1__SEL_1 ; - assign o_fifo_Start_TO_Stage__3_1$DEQ = - WILL_FIRE_RL_o_s_Stage__3_execute && - o_fifo_Start_TO_Stage__3$D_OUT[2] ; - assign o_fifo_Start_TO_Stage__3_1$CLR = 1'b0 ; - - // submodule o_fifo__input__TO_Start_f - assign o_fifo__input__TO_Start_f$D_IN = - o_fifo__input__TO_Start_enq_data$wget ; - assign o_fifo__input__TO_Start_f$ENQ = - o_fifo__input__TO_Start_f$FULL_N && - o_fifo__input__TO_Start_enq_data$whas ; - assign o_fifo__input__TO_Start_f$DEQ = WILL_FIRE_RL_o_s_Start_execute ; - assign o_fifo__input__TO_Start_f$CLR = 1'b0 ; - - // submodule o_nextId_dummy2_0 - assign o_nextId_dummy2_0$D_IN = 1'd1 ; - assign o_nextId_dummy2_0$EN = - MUX_o_fifo__input__TO_Start_enq_data$wset_1__SEL_1 ; - - // submodule o_nextId_dummy2_1 - assign o_nextId_dummy2_1$D_IN = 1'b0 ; - assign o_nextId_dummy2_1$EN = 1'b0 ; - - // submodule o_outputQueue_nextTag_dummy2_0 - assign o_outputQueue_nextTag_dummy2_0$D_IN = 1'd1 ; - assign o_outputQueue_nextTag_dummy2_0$EN = EN__into_resp ; - - // submodule o_outputQueue_nextTag_dummy2_1 - assign o_outputQueue_nextTag_dummy2_1$D_IN = 1'b0 ; - assign o_outputQueue_nextTag_dummy2_1$EN = 1'b0 ; - - // submodule tf_rf - assign tf_rf$ADDR_1 = hg_fifo__input__TO_Start_rv$port1__read[12:3] ; - assign tf_rf$ADDR_2 = 10'h0 ; - assign tf_rf$ADDR_3 = 10'h0 ; - assign tf_rf$ADDR_4 = 10'h0 ; - assign tf_rf$ADDR_5 = 10'h0 ; - assign tf_rf$ADDR_IN = 10'h0 ; - assign tf_rf$D_IN = 16'h0 ; - assign tf_rf$WE = 1'b0 ; - - // submodule th_rf - assign th_rf$ADDR_1 = hg_fifo_Start_TO_Stage__0$D_OUT[44:35] ; - assign th_rf$ADDR_2 = 10'h0 ; - assign th_rf$ADDR_3 = 10'h0 ; - assign th_rf$ADDR_4 = 10'h0 ; - assign th_rf$ADDR_5 = 10'h0 ; - assign th_rf$ADDR_IN = hg_fifo_Stage__0_TO_Stage__1$D_OUT[12:3] ; - assign th_rf$D_IN = hg_fifo_Stage__0_TO_Stage__1$D_OUT[47:16] ; - assign th_rf$WE = WILL_FIRE_RL_hg_s_Stage__1_execute ; - - // submodule tw_rf - assign tw_rf$ADDR_1 = hg_fifo__input__TO_Start_rv$port1__read[12:3] ; - assign tw_rf$ADDR_2 = 10'h0 ; - assign tw_rf$ADDR_3 = 10'h0 ; - assign tw_rf$ADDR_4 = 10'h0 ; - assign tw_rf$ADDR_5 = 10'h0 ; - assign tw_rf$ADDR_IN = 10'h0 ; - assign tw_rf$D_IN = 32'h0 ; - assign tw_rf$WE = 1'b0 ; - - // submodule w_l_lockVec_0_nextId_dummy2_0 - assign w_l_lockVec_0_nextId_dummy2_0$D_IN = 1'b0 ; - assign w_l_lockVec_0_nextId_dummy2_0$EN = 1'b0 ; - - // submodule w_l_lockVec_0_nextId_dummy2_1 - assign w_l_lockVec_0_nextId_dummy2_1$D_IN = 1'b0 ; - assign w_l_lockVec_0_nextId_dummy2_1$EN = 1'b0 ; - - // submodule w_l_lockVec_1_nextId_dummy2_0 - assign w_l_lockVec_1_nextId_dummy2_0$D_IN = 1'b0 ; - assign w_l_lockVec_1_nextId_dummy2_0$EN = 1'b0 ; - - // submodule w_l_lockVec_1_nextId_dummy2_1 - assign w_l_lockVec_1_nextId_dummy2_1$D_IN = 1'b0 ; - assign w_l_lockVec_1_nextId_dummy2_1$EN = 1'b0 ; - - // submodule w_l_lockVec_2_nextId_dummy2_0 - assign w_l_lockVec_2_nextId_dummy2_0$D_IN = 1'b0 ; - assign w_l_lockVec_2_nextId_dummy2_0$EN = 1'b0 ; - - // submodule w_l_lockVec_2_nextId_dummy2_1 - assign w_l_lockVec_2_nextId_dummy2_1$D_IN = 1'b0 ; - assign w_l_lockVec_2_nextId_dummy2_1$EN = 1'b0 ; - - // submodule w_l_lockVec_3_nextId_dummy2_0 - assign w_l_lockVec_3_nextId_dummy2_0$D_IN = 1'b0 ; - assign w_l_lockVec_3_nextId_dummy2_0$EN = 1'b0 ; - - // submodule w_l_lockVec_3_nextId_dummy2_1 - assign w_l_lockVec_3_nextId_dummy2_1$D_IN = 1'b0 ; - assign w_l_lockVec_3_nextId_dummy2_1$EN = 1'b0 ; - - // remaining internal signals - assign IF_NOT_f_l_entryVec_0_read__6_BIT_10_7_72_OR_N_ETC___d380 = - ((!f_l_entryVec_0[10] || - !f_l_entryVec_0_read__6_BITS_9_TO_0_59_EQ_hg_fi_ETC___d360) && - f_l_entryVec_1[10] && - f_l_entryVec_1_read__4_BITS_9_TO_0_56_EQ_hg_fi_ETC___d357) ? - 2'd1 : - 2'd0 ; - assign IF_NOT_h_l_entryVec_0_read__11_BIT_10_12_67_OR_ETC___d475 = - ((!h_l_entryVec_0[10] || - !IF_h_l_entryVec_0_read__11_BIT_10_12_THEN_h_l__ETC___d455) && - h_l_entryVec_1[10] && - IF_h_l_entryVec_1_read__18_BIT_10_19_THEN_h_l__ETC___d451) ? - 2'd1 : - 2'd0 ; - assign IF_NOT_h_l_entryVec_0_read__11_BIT_10_12_67_OR_ETC___d587 = - ((!h_l_entryVec_0[10] || - !IF_h_l_entryVec_0_read__11_BIT_10_12_THEN_h_l__ETC___d559) && - h_l_entryVec_1[10] && - IF_h_l_entryVec_1_read__18_BIT_10_19_THEN_h_l__ETC___d557) ? - 2'd1 : - 2'd0 ; - assign IF_NOT_h_l_entryVec_2_read__25_BIT_10_26_61_OR_ETC___d491 = - x__h26655 == 2'd0 && - (h_l_entryVec_3[10] && - IF_h_l_entryVec_3_read__32_BIT_10_33_THEN_h_l__ETC___d443 || - h_l_entryVec_2_read__25_BIT_10_26_AND_IF_h_l_e_ETC___d458) ; - assign IF_NOT_h_l_entryVec_2_read__25_BIT_10_26_61_OR_ETC___d493 = - x__h26655 == 2'd1 && - (h_l_entryVec_3[10] && - IF_h_l_entryVec_3_read__32_BIT_10_33_THEN_h_l__ETC___d443 || - h_l_entryVec_2_read__25_BIT_10_26_AND_IF_h_l_e_ETC___d458) ; - assign IF_NOT_h_l_entryVec_2_read__25_BIT_10_26_61_OR_ETC___d495 = - x__h26655 == 2'd2 && - (h_l_entryVec_3[10] && - IF_h_l_entryVec_3_read__32_BIT_10_33_THEN_h_l__ETC___d443 || - h_l_entryVec_2_read__25_BIT_10_26_AND_IF_h_l_e_ETC___d458) ; - assign IF_NOT_h_l_entryVec_2_read__25_BIT_10_26_61_OR_ETC___d497 = - x__h26655 == 2'd3 && - (h_l_entryVec_3[10] && - IF_h_l_entryVec_3_read__32_BIT_10_33_THEN_h_l__ETC___d443 || - h_l_entryVec_2_read__25_BIT_10_26_AND_IF_h_l_e_ETC___d458) ; - assign IF_NOT_w_l_entryVec_0_read__99_BIT_10_00_11_OR_ETC___d419 = - ((!w_l_entryVec_0[10] || - !w_l_entryVec_0_read__99_BITS_9_TO_0_98_EQ_hg_f_ETC___d399) && - w_l_entryVec_1[10] && - w_l_entryVec_1_read__06_BITS_9_TO_0_95_EQ_hg_f_ETC___d396) ? - 2'd1 : - 2'd0 ; - assign IF_f_l_entryVec_3_read__08_BIT_10_09_AND_f_l_e_ETC___d428 = - ((f_l_entryVec_3[10] && - f_l_entryVec_3[9:0] == - hg_fifo__input__TO_Start_rv$port1__read[12:3] || - f_l_entryVec_2_read__01_BIT_10_02_AND_f_l_entr_ETC___d363) ? - SEL_ARR_f_l_lockVec_0_empty_5_f_l_lockVec_1_em_ETC___d383 : - !f_l_entryVec_3[10] || !f_l_entryVec_2[10] || - !f_l_entryVec_1[10] || - !f_l_entryVec_0[10]) && - ((w_l_entryVec_3[10] && - w_l_entryVec_3[9:0] == - hg_fifo__input__TO_Start_rv$port1__read[12:3] || - w_l_entryVec_2_read__13_BIT_10_14_AND_w_l_entr_ETC___d402) ? - SEL_ARR_w_l_lockVec_0_empty_98_w_l_lockVec_1_e_ETC___d422 : - !w_l_entryVec_3[10] || !w_l_entryVec_2[10] || - !w_l_entryVec_1[10] || - !w_l_entryVec_0[10]) ; - assign IF_h_l_entryVec_0_read__11_BIT_10_12_THEN_h_l__ETC___d455 = - h_l_entryVec_0[9:0] == hg_fifo_Start_TO_Stage__0$D_OUT[44:35] ; - assign IF_h_l_entryVec_0_read__11_BIT_10_12_THEN_h_l__ETC___d559 = - h_l_entryVec_0[9:0] == hg_fifo_Stage__0_TO_Stage__1$D_OUT[12:3] ; - assign IF_h_l_entryVec_1_read__18_BIT_10_19_AND_h_l_e_ETC___d520 = - (h_l_entryVec_1[10] && h_l_entryVec_0[10] && - !h_l_entryVec_2[10]) ? - 2'd2 : - ((h_l_entryVec_0[10] && !h_l_entryVec_1[10]) ? 2'd1 : 2'd0) ; - assign IF_h_l_entryVec_1_read__18_BIT_10_19_THEN_h_l__ETC___d451 = - h_l_entryVec_1[9:0] == hg_fifo_Start_TO_Stage__0$D_OUT[44:35] ; - assign IF_h_l_entryVec_1_read__18_BIT_10_19_THEN_h_l__ETC___d557 = - h_l_entryVec_1[9:0] == hg_fifo_Stage__0_TO_Stage__1$D_OUT[12:3] ; - assign IF_h_l_entryVec_2_read__25_BIT_10_26_THEN_h_l__ETC___d447 = - h_l_entryVec_2[9:0] == hg_fifo_Start_TO_Stage__0$D_OUT[44:35] ; - assign IF_h_l_entryVec_2_read__25_BIT_10_26_THEN_h_l__ETC___d555 = - h_l_entryVec_2[9:0] == hg_fifo_Stage__0_TO_Stage__1$D_OUT[12:3] ; - assign IF_h_l_entryVec_3_read__32_BIT_10_33_AND_IF_h__ETC___d483 = - (h_l_entryVec_3[10] && - IF_h_l_entryVec_3_read__32_BIT_10_33_THEN_h_l__ETC___d443 || - h_l_entryVec_2_read__25_BIT_10_26_AND_IF_h_l_e_ETC___d458) ? - SEL_ARR_h_l_lockVec_0_empty_10_h_l_lockVec_1_e_ETC___d478 : - NOT_h_l_entryVec_3_read__32_BIT_10_33_79_OR_NO_ETC___d482 ; - assign IF_h_l_entryVec_3_read__32_BIT_10_33_AND_IF_h__ETC___d543 = - (h_l_entryVec_3[10] && - IF_h_l_entryVec_3_read__32_BIT_10_33_THEN_h_l__ETC___d443 || - h_l_entryVec_2_read__25_BIT_10_26_AND_IF_h_l_e_ETC___d458) ? - SEL_ARR_IF_h_l_lockVec_0_nextId_dummy2_0_read__ETC___d540 : - (NOT_h_l_entryVec_3_read__32_BIT_10_33_79_OR_NO_ETC___d482 ? - SEL_ARR_IF_h_l_lockVec_0_nextId_dummy2_0_read__ETC___d541 : - 2'd0) ; - assign IF_h_l_entryVec_3_read__32_BIT_10_33_THEN_h_l__ETC___d443 = - h_l_entryVec_3[9:0] == hg_fifo_Start_TO_Stage__0$D_OUT[44:35] ; - assign IF_h_l_lockVec_0_nextId_dummy2_0_read__98_AND__ETC___d500 = - (h_l_lockVec_0_nextId_dummy2_0$Q_OUT && - h_l_lockVec_0_nextId_dummy2_1$Q_OUT) ? - h_l_lockVec_0_nextId_rl : - 2'd0 ; - assign IF_h_l_lockVec_0_nextId_dummy2_0_read__98_AND__ETC___d501 = - IF_h_l_lockVec_0_nextId_dummy2_0_read__98_AND__ETC___d500 + - 2'd1 ; - assign IF_h_l_lockVec_0_nextId_lat_0_whas__28_THEN_h__ETC___d231 = - h_l_lockVec_0_nextId_lat_0$whas ? - IF_h_l_lockVec_0_nextId_dummy2_0_read__98_AND__ETC___d501 : - h_l_lockVec_0_nextId_rl ; - assign IF_h_l_lockVec_1_nextId_dummy2_0_read__02_AND__ETC___d504 = - (h_l_lockVec_1_nextId_dummy2_0$Q_OUT && - h_l_lockVec_1_nextId_dummy2_1$Q_OUT) ? - h_l_lockVec_1_nextId_rl : - 2'd0 ; - assign IF_h_l_lockVec_1_nextId_dummy2_0_read__02_AND__ETC___d505 = - IF_h_l_lockVec_1_nextId_dummy2_0_read__02_AND__ETC___d504 + - 2'd1 ; - assign IF_h_l_lockVec_1_nextId_lat_0_whas__49_THEN_h__ETC___d252 = - h_l_lockVec_1_nextId_lat_0$whas ? - IF_h_l_lockVec_1_nextId_dummy2_0_read__02_AND__ETC___d505 : - h_l_lockVec_1_nextId_rl ; - assign IF_h_l_lockVec_2_nextId_dummy2_0_read__06_AND__ETC___d508 = - (h_l_lockVec_2_nextId_dummy2_0$Q_OUT && - h_l_lockVec_2_nextId_dummy2_1$Q_OUT) ? - h_l_lockVec_2_nextId_rl : - 2'd0 ; - assign IF_h_l_lockVec_2_nextId_dummy2_0_read__06_AND__ETC___d509 = - IF_h_l_lockVec_2_nextId_dummy2_0_read__06_AND__ETC___d508 + - 2'd1 ; - assign IF_h_l_lockVec_2_nextId_lat_0_whas__70_THEN_h__ETC___d273 = - h_l_lockVec_2_nextId_lat_0$whas ? - IF_h_l_lockVec_2_nextId_dummy2_0_read__06_AND__ETC___d509 : - h_l_lockVec_2_nextId_rl ; - assign IF_h_l_lockVec_3_nextId_dummy2_0_read__10_AND__ETC___d512 = - (h_l_lockVec_3_nextId_dummy2_0$Q_OUT && - h_l_lockVec_3_nextId_dummy2_1$Q_OUT) ? - h_l_lockVec_3_nextId_rl : - 2'd0 ; - assign IF_h_l_lockVec_3_nextId_dummy2_0_read__10_AND__ETC___d513 = - IF_h_l_lockVec_3_nextId_dummy2_0_read__10_AND__ETC___d512 + - 2'd1 ; - assign IF_h_l_lockVec_3_nextId_lat_0_whas__91_THEN_h__ETC___d294 = - h_l_lockVec_3_nextId_lat_0$whas ? - IF_h_l_lockVec_3_nextId_dummy2_0_read__10_AND__ETC___d513 : - h_l_lockVec_3_nextId_rl ; - assign IF_hg_outputQueue_nextTag_dummy2_0_read__86_AN_ETC___d688 = - (hg_outputQueue_nextTag_dummy2_0$Q_OUT && - hg_outputQueue_nextTag_dummy2_1$Q_OUT) ? - hg_outputQueue_nextTag_rl : - 3'd0 ; - assign IF_hg_outputQueue_nextTag_lat_0_whas__40_THEN__ETC___d343 = - MUX_hg_outputQueue_val$write_1__SEL_2 ? - b__h24879 : - hg_outputQueue_nextTag_rl ; - assign IF_o_nextId_dummy2_0_read__67_AND_o_nextId_dum_ETC___d669 = - (o_nextId_dummy2_0$Q_OUT && o_nextId_dummy2_1$Q_OUT) ? - o_nextId_rl : - 2'd0 ; - assign IF_o_nextId_lat_0_whas__19_THEN_o_nextId_lat_0_ETC___d622 = - MUX_o_fifo__input__TO_Start_enq_data$wset_1__SEL_1 ? - b__h31747 : - o_nextId_rl ; - assign IF_o_outputQueue_nextTag_dummy2_0_read__25_AND_ETC___d727 = - (o_outputQueue_nextTag_dummy2_0$Q_OUT && - o_outputQueue_nextTag_dummy2_1$Q_OUT) ? - o_outputQueue_nextTag_rl : - 2'd0 ; - assign IF_o_outputQueue_nextTag_lat_0_whas__40_THEN_o_ETC___d643 = - EN__into_resp ? b__h33309 : o_outputQueue_nextTag_rl ; - assign NOT_f_l_entryVec_1_read__4_BIT_10_5_69_OR_NOT__ETC___d378 = - (!f_l_entryVec_1[10] || - !f_l_entryVec_1_read__4_BITS_9_TO_0_56_EQ_hg_fi_ETC___d357) && - (!f_l_entryVec_0[10] || - !f_l_entryVec_0_read__6_BITS_9_TO_0_59_EQ_hg_fi_ETC___d360) && - f_l_entryVec_2[10] && - f_l_entryVec_2_read__01_BITS_9_TO_0_53_EQ_hg_f_ETC___d354 ; - assign NOT_f_l_entryVec_2_read__01_BIT_10_02_66_OR_NO_ETC___d376 = - (!f_l_entryVec_2[10] || - !f_l_entryVec_2_read__01_BITS_9_TO_0_53_EQ_hg_f_ETC___d354) && - (!f_l_entryVec_1[10] || - !f_l_entryVec_1_read__4_BITS_9_TO_0_56_EQ_hg_fi_ETC___d357) && - (!f_l_entryVec_0[10] || - !f_l_entryVec_0_read__6_BITS_9_TO_0_59_EQ_hg_fi_ETC___d360) ; - assign NOT_h_l_entryVec_1_read__18_BIT_10_19_64_OR_NO_ETC___d473 = - (!h_l_entryVec_1[10] || - !IF_h_l_entryVec_1_read__18_BIT_10_19_THEN_h_l__ETC___d451) && - (!h_l_entryVec_0[10] || - !IF_h_l_entryVec_0_read__11_BIT_10_12_THEN_h_l__ETC___d455) && - h_l_entryVec_2[10] && - IF_h_l_entryVec_2_read__25_BIT_10_26_THEN_h_l__ETC___d447 ; - assign NOT_h_l_entryVec_1_read__18_BIT_10_19_64_OR_NO_ETC___d585 = - (!h_l_entryVec_1[10] || - !IF_h_l_entryVec_1_read__18_BIT_10_19_THEN_h_l__ETC___d557) && - (!h_l_entryVec_0[10] || - !IF_h_l_entryVec_0_read__11_BIT_10_12_THEN_h_l__ETC___d559) && - h_l_entryVec_2[10] && - IF_h_l_entryVec_2_read__25_BIT_10_26_THEN_h_l__ETC___d555 ; - assign NOT_h_l_entryVec_2_read__25_BIT_10_26_61_OR_NO_ETC___d471 = - (!h_l_entryVec_2[10] || - !IF_h_l_entryVec_2_read__25_BIT_10_26_THEN_h_l__ETC___d447) && - (!h_l_entryVec_1[10] || - !IF_h_l_entryVec_1_read__18_BIT_10_19_THEN_h_l__ETC___d451) && - (!h_l_entryVec_0[10] || - !IF_h_l_entryVec_0_read__11_BIT_10_12_THEN_h_l__ETC___d455) ; - assign NOT_h_l_entryVec_2_read__25_BIT_10_26_61_OR_NO_ETC___d583 = - (!h_l_entryVec_2[10] || - !IF_h_l_entryVec_2_read__25_BIT_10_26_THEN_h_l__ETC___d555) && - (!h_l_entryVec_1[10] || - !IF_h_l_entryVec_1_read__18_BIT_10_19_THEN_h_l__ETC___d557) && - (!h_l_entryVec_0[10] || - !IF_h_l_entryVec_0_read__11_BIT_10_12_THEN_h_l__ETC___d559) ; - assign NOT_h_l_entryVec_3_read__32_BIT_10_33_79_OR_NO_ETC___d482 = - !h_l_entryVec_3[10] || !h_l_entryVec_2[10] || - !h_l_entryVec_1[10] || - !h_l_entryVec_0[10] ; - assign NOT_h_l_entryVec_3_read__32_BIT_10_33_79_OR_NO_ETC___d526 = - (!h_l_entryVec_3[10] || - !IF_h_l_entryVec_3_read__32_BIT_10_33_THEN_h_l__ETC___d443) && - NOT_h_l_entryVec_2_read__25_BIT_10_26_61_OR_NO_ETC___d471 && - NOT_h_l_entryVec_3_read__32_BIT_10_33_79_OR_NO_ETC___d482 ; - assign NOT_w_l_entryVec_1_read__06_BIT_10_07_08_OR_NO_ETC___d417 = - (!w_l_entryVec_1[10] || - !w_l_entryVec_1_read__06_BITS_9_TO_0_95_EQ_hg_f_ETC___d396) && - (!w_l_entryVec_0[10] || - !w_l_entryVec_0_read__99_BITS_9_TO_0_98_EQ_hg_f_ETC___d399) && - w_l_entryVec_2[10] && - w_l_entryVec_2_read__13_BITS_9_TO_0_92_EQ_hg_f_ETC___d393 ; - assign NOT_w_l_entryVec_2_read__13_BIT_10_14_05_OR_NO_ETC___d415 = - (!w_l_entryVec_2[10] || - !w_l_entryVec_2_read__13_BITS_9_TO_0_92_EQ_hg_f_ETC___d393) && - (!w_l_entryVec_1[10] || - !w_l_entryVec_1_read__06_BITS_9_TO_0_95_EQ_hg_f_ETC___d396) && - (!w_l_entryVec_0[10] || - !w_l_entryVec_0_read__99_BITS_9_TO_0_98_EQ_hg_f_ETC___d399) ; - assign b__h17187 = h_l_lockVec_0_owner + 2'd1 ; - assign b__h18595 = h_l_lockVec_1_owner + 2'd1 ; - assign b__h20003 = h_l_lockVec_2_owner + 2'd1 ; - assign b__h21411 = h_l_lockVec_3_owner + 2'd1 ; - assign b__h24879 = - IF_hg_outputQueue_nextTag_dummy2_0_read__86_AN_ETC___d688 + - 3'd1 ; - assign b__h31747 = - IF_o_nextId_dummy2_0_read__67_AND_o_nextId_dum_ETC___d669 + - 2'd1 ; - assign b__h32070 = o_owner + 2'd1 ; - assign b__h33309 = - IF_o_outputQueue_nextTag_dummy2_0_read__25_AND_ETC___d727 + - 2'd1 ; - assign f_l_entryVec_0_read__6_BITS_9_TO_0_59_EQ_hg_fi_ETC___d360 = - f_l_entryVec_0[9:0] == - hg_fifo__input__TO_Start_rv$port1__read[12:3] ; - assign f_l_entryVec_1_read__4_BITS_9_TO_0_56_EQ_hg_fi_ETC___d357 = - f_l_entryVec_1[9:0] == - hg_fifo__input__TO_Start_rv$port1__read[12:3] ; - assign f_l_entryVec_2_read__01_BITS_9_TO_0_53_EQ_hg_f_ETC___d354 = - f_l_entryVec_2[9:0] == - hg_fifo__input__TO_Start_rv$port1__read[12:3] ; - assign f_l_entryVec_2_read__01_BIT_10_02_AND_f_l_entr_ETC___d363 = - f_l_entryVec_2[10] && - f_l_entryVec_2_read__01_BITS_9_TO_0_53_EQ_hg_f_ETC___d354 || - f_l_entryVec_1[10] && - f_l_entryVec_1_read__4_BITS_9_TO_0_56_EQ_hg_fi_ETC___d357 || - f_l_entryVec_0[10] && - f_l_entryVec_0_read__6_BITS_9_TO_0_59_EQ_hg_fi_ETC___d360 ; - assign h_l_entryVec_2_read__25_BIT_10_26_AND_IF_h_l_e_ETC___d458 = - h_l_entryVec_2[10] && - IF_h_l_entryVec_2_read__25_BIT_10_26_THEN_h_l__ETC___d447 || - h_l_entryVec_1[10] && - IF_h_l_entryVec_1_read__18_BIT_10_19_THEN_h_l__ETC___d451 || - h_l_entryVec_0[10] && - IF_h_l_entryVec_0_read__11_BIT_10_12_THEN_h_l__ETC___d455 ; - assign h_l_entryVec_2_read__25_BIT_10_26_AND_IF_h_l_e_ETC___d562 = - h_l_entryVec_2[10] && - IF_h_l_entryVec_2_read__25_BIT_10_26_THEN_h_l__ETC___d555 || - h_l_entryVec_1[10] && - IF_h_l_entryVec_1_read__18_BIT_10_19_THEN_h_l__ETC___d557 || - h_l_entryVec_0[10] && - IF_h_l_entryVec_0_read__11_BIT_10_12_THEN_h_l__ETC___d559 ; - assign h_l_entryVec_3_read__32_BIT_10_33_AND_IF_h_l_e_ETC___d563 = - h_l_entryVec_3[10] && - h_l_entryVec_3[9:0] == - hg_fifo_Stage__0_TO_Stage__1$D_OUT[12:3] || - h_l_entryVec_2_read__25_BIT_10_26_AND_IF_h_l_e_ETC___d562 ; - assign o_fifo_Start_TO_Stage__3_first__77_BIT_2_78_OR_ETC___d695 = - o_fifo_Start_TO_Stage__3$D_OUT[2] || - IF_hg_outputQueue_nextTag_dummy2_0_read__86_AN_ETC___d688 == - o_fifo_Stage__1_TO_Stage__3$D_OUT[4:2] && - hg_outputQueue_val[1] ; - assign o_fifo__input__TO_Start_f_first__47_BITS_11_TO_ETC___d649 = - o_fifo__input__TO_Start_f$D_OUT[11:2] < 10'd1000 ; - assign o_fifo__input__TO_Start_f_first__47_BITS_11_TO_ETC___d665 = - o_fifo__input__TO_Start_f_first__47_BITS_11_TO_ETC___d649 || - (o_outputQueue_nextTag_dummy2_1$Q_OUT ? - IF_o_outputQueue_nextTag_lat_0_whas__40_THEN_o_ETC___d643 : - 2'd0) == - o_fifo__input__TO_Start_f$D_OUT[1:0] ; - assign th_rf_sub_hg_fifo_Start_TO_Stage__0_first__41__ETC___d537 = - th_rf$D_OUT_1 + hg_fifo_Start_TO_Stage__0$D_OUT[34:3] ; - assign w_l_entryVec_0_read__99_BITS_9_TO_0_98_EQ_hg_f_ETC___d399 = - w_l_entryVec_0[9:0] == - hg_fifo__input__TO_Start_rv$port1__read[12:3] ; - assign w_l_entryVec_1_read__06_BITS_9_TO_0_95_EQ_hg_f_ETC___d396 = - w_l_entryVec_1[9:0] == - hg_fifo__input__TO_Start_rv$port1__read[12:3] ; - assign w_l_entryVec_2_read__13_BITS_9_TO_0_92_EQ_hg_f_ETC___d393 = - w_l_entryVec_2[9:0] == - hg_fifo__input__TO_Start_rv$port1__read[12:3] ; - assign w_l_entryVec_2_read__13_BIT_10_14_AND_w_l_entr_ETC___d402 = - w_l_entryVec_2[10] && - w_l_entryVec_2_read__13_BITS_9_TO_0_92_EQ_hg_f_ETC___d393 || - w_l_entryVec_1[10] && - w_l_entryVec_1_read__06_BITS_9_TO_0_95_EQ_hg_f_ETC___d396 || - w_l_entryVec_0[10] && - w_l_entryVec_0_read__99_BITS_9_TO_0_98_EQ_hg_f_ETC___d399 ; - assign x__h25497 = - (NOT_f_l_entryVec_2_read__01_BIT_10_02_66_OR_NO_ETC___d376 && - f_l_entryVec_3[10] && - f_l_entryVec_3[9:0] == - hg_fifo__input__TO_Start_rv$port1__read[12:3]) ? - 2'd3 : - (NOT_f_l_entryVec_1_read__4_BIT_10_5_69_OR_NOT__ETC___d378 ? - 2'd2 : - IF_NOT_f_l_entryVec_0_read__6_BIT_10_7_72_OR_N_ETC___d380) ; - assign x__h26014 = - (NOT_w_l_entryVec_2_read__13_BIT_10_14_05_OR_NO_ETC___d415 && - w_l_entryVec_3[10] && - w_l_entryVec_3[9:0] == - hg_fifo__input__TO_Start_rv$port1__read[12:3]) ? - 2'd3 : - (NOT_w_l_entryVec_1_read__06_BIT_10_07_08_OR_NO_ETC___d417 ? - 2'd2 : - IF_NOT_w_l_entryVec_0_read__99_BIT_10_00_11_OR_ETC___d419) ; - assign x__h26655 = - (NOT_h_l_entryVec_2_read__25_BIT_10_26_61_OR_NO_ETC___d471 && - h_l_entryVec_3[10] && - IF_h_l_entryVec_3_read__32_BIT_10_33_THEN_h_l__ETC___d443) ? - 2'd3 : - (NOT_h_l_entryVec_1_read__18_BIT_10_19_64_OR_NO_ETC___d473 ? - 2'd2 : - IF_NOT_h_l_entryVec_0_read__11_BIT_10_12_67_OR_ETC___d475) ; - assign x__h27260 = - (h_l_entryVec_2[10] && h_l_entryVec_1[10] && - h_l_entryVec_0[10] && - !h_l_entryVec_3[10]) ? - 2'd3 : - IF_h_l_entryVec_1_read__18_BIT_10_19_AND_h_l_e_ETC___d520 ; - assign x__h29141 = - (NOT_h_l_entryVec_2_read__25_BIT_10_26_61_OR_NO_ETC___d583 && - h_l_entryVec_3[10] && - h_l_entryVec_3[9:0] == - hg_fifo_Stage__0_TO_Stage__1$D_OUT[12:3]) ? - 2'd3 : - (NOT_h_l_entryVec_1_read__18_BIT_10_19_64_OR_NO_ETC___d585 ? - 2'd2 : - IF_NOT_h_l_entryVec_0_read__11_BIT_10_12_67_OR_ETC___d587) ; - always@(x__h26655 or - h_l_lockVec_0_empty or - h_l_lockVec_1_empty or h_l_lockVec_2_empty or h_l_lockVec_3_empty) - begin - case (x__h26655) - 2'd0: - SEL_ARR_h_l_lockVec_0_empty_10_h_l_lockVec_1_e_ETC___d478 = - h_l_lockVec_0_empty; - 2'd1: - SEL_ARR_h_l_lockVec_0_empty_10_h_l_lockVec_1_e_ETC___d478 = - h_l_lockVec_1_empty; - 2'd2: - SEL_ARR_h_l_lockVec_0_empty_10_h_l_lockVec_1_e_ETC___d478 = - h_l_lockVec_2_empty; - 2'd3: - SEL_ARR_h_l_lockVec_0_empty_10_h_l_lockVec_1_e_ETC___d478 = - h_l_lockVec_3_empty; - endcase - end - always@(x__h29141 or - h_l_lockVec_0_owner or - hg_fifo_Stage__0_TO_Stage__1$D_OUT or - h_l_lockVec_1_owner or h_l_lockVec_2_owner or h_l_lockVec_3_owner) - begin - case (x__h29141) - 2'd0: - SEL_ARR_h_l_lockVec_0_owner_64_EQ_IF_hg_fifo_S_ETC___d590 = - h_l_lockVec_0_owner == - hg_fifo_Stage__0_TO_Stage__1$D_OUT[14:13]; - 2'd1: - SEL_ARR_h_l_lockVec_0_owner_64_EQ_IF_hg_fifo_S_ETC___d590 = - h_l_lockVec_1_owner == - hg_fifo_Stage__0_TO_Stage__1$D_OUT[14:13]; - 2'd2: - SEL_ARR_h_l_lockVec_0_owner_64_EQ_IF_hg_fifo_S_ETC___d590 = - h_l_lockVec_2_owner == - hg_fifo_Stage__0_TO_Stage__1$D_OUT[14:13]; - 2'd3: - SEL_ARR_h_l_lockVec_0_owner_64_EQ_IF_hg_fifo_S_ETC___d590 = - h_l_lockVec_3_owner == - hg_fifo_Stage__0_TO_Stage__1$D_OUT[14:13]; - endcase - end - always@(x__h26655 or - IF_h_l_lockVec_0_nextId_dummy2_0_read__98_AND__ETC___d500 or - IF_h_l_lockVec_1_nextId_dummy2_0_read__02_AND__ETC___d504 or - IF_h_l_lockVec_2_nextId_dummy2_0_read__06_AND__ETC___d508 or - IF_h_l_lockVec_3_nextId_dummy2_0_read__10_AND__ETC___d512) - begin - case (x__h26655) - 2'd0: - SEL_ARR_IF_h_l_lockVec_0_nextId_dummy2_0_read__ETC___d540 = - IF_h_l_lockVec_0_nextId_dummy2_0_read__98_AND__ETC___d500; - 2'd1: - SEL_ARR_IF_h_l_lockVec_0_nextId_dummy2_0_read__ETC___d540 = - IF_h_l_lockVec_1_nextId_dummy2_0_read__02_AND__ETC___d504; - 2'd2: - SEL_ARR_IF_h_l_lockVec_0_nextId_dummy2_0_read__ETC___d540 = - IF_h_l_lockVec_2_nextId_dummy2_0_read__06_AND__ETC___d508; - 2'd3: - SEL_ARR_IF_h_l_lockVec_0_nextId_dummy2_0_read__ETC___d540 = - IF_h_l_lockVec_3_nextId_dummy2_0_read__10_AND__ETC___d512; - endcase - end - always@(x__h27260 or - IF_h_l_lockVec_0_nextId_dummy2_0_read__98_AND__ETC___d500 or - IF_h_l_lockVec_1_nextId_dummy2_0_read__02_AND__ETC___d504 or - IF_h_l_lockVec_2_nextId_dummy2_0_read__06_AND__ETC___d508 or - IF_h_l_lockVec_3_nextId_dummy2_0_read__10_AND__ETC___d512) - begin - case (x__h27260) - 2'd0: - SEL_ARR_IF_h_l_lockVec_0_nextId_dummy2_0_read__ETC___d541 = - IF_h_l_lockVec_0_nextId_dummy2_0_read__98_AND__ETC___d500; - 2'd1: - SEL_ARR_IF_h_l_lockVec_0_nextId_dummy2_0_read__ETC___d541 = - IF_h_l_lockVec_1_nextId_dummy2_0_read__02_AND__ETC___d504; - 2'd2: - SEL_ARR_IF_h_l_lockVec_0_nextId_dummy2_0_read__ETC___d541 = - IF_h_l_lockVec_2_nextId_dummy2_0_read__06_AND__ETC___d508; - 2'd3: - SEL_ARR_IF_h_l_lockVec_0_nextId_dummy2_0_read__ETC___d541 = - IF_h_l_lockVec_3_nextId_dummy2_0_read__10_AND__ETC___d512; - endcase - end - always@(x__h25497 or - f_l_lockVec_0_empty or - f_l_lockVec_1_empty or f_l_lockVec_2_empty or f_l_lockVec_3_empty) - begin - case (x__h25497) - 2'd0: - SEL_ARR_f_l_lockVec_0_empty_5_f_l_lockVec_1_em_ETC___d383 = - f_l_lockVec_0_empty; - 2'd1: - SEL_ARR_f_l_lockVec_0_empty_5_f_l_lockVec_1_em_ETC___d383 = - f_l_lockVec_1_empty; - 2'd2: - SEL_ARR_f_l_lockVec_0_empty_5_f_l_lockVec_1_em_ETC___d383 = - f_l_lockVec_2_empty; - 2'd3: - SEL_ARR_f_l_lockVec_0_empty_5_f_l_lockVec_1_em_ETC___d383 = - f_l_lockVec_3_empty; - endcase - end - always@(x__h26014 or - w_l_lockVec_0_empty or - w_l_lockVec_1_empty or w_l_lockVec_2_empty or w_l_lockVec_3_empty) - begin - case (x__h26014) - 2'd0: - SEL_ARR_w_l_lockVec_0_empty_98_w_l_lockVec_1_e_ETC___d422 = - w_l_lockVec_0_empty; - 2'd1: - SEL_ARR_w_l_lockVec_0_empty_98_w_l_lockVec_1_e_ETC___d422 = - w_l_lockVec_1_empty; - 2'd2: - SEL_ARR_w_l_lockVec_0_empty_98_w_l_lockVec_1_e_ETC___d422 = - w_l_lockVec_2_empty; - 2'd3: - SEL_ARR_w_l_lockVec_0_empty_98_w_l_lockVec_1_e_ETC___d422 = - w_l_lockVec_3_empty; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - f_l_entryVec_0 <= `BSV_ASSIGNMENT_DELAY 11'd682; - f_l_entryVec_1 <= `BSV_ASSIGNMENT_DELAY 11'd682; - f_l_entryVec_2 <= `BSV_ASSIGNMENT_DELAY 11'd682; - f_l_entryVec_3 <= `BSV_ASSIGNMENT_DELAY 11'd682; - f_l_lockVec_0_empty <= `BSV_ASSIGNMENT_DELAY 1'd1; - f_l_lockVec_0_nextId_rl <= `BSV_ASSIGNMENT_DELAY 2'd0; - f_l_lockVec_0_owner <= `BSV_ASSIGNMENT_DELAY 2'd0; - f_l_lockVec_1_empty <= `BSV_ASSIGNMENT_DELAY 1'd1; - f_l_lockVec_1_nextId_rl <= `BSV_ASSIGNMENT_DELAY 2'd0; - f_l_lockVec_1_owner <= `BSV_ASSIGNMENT_DELAY 2'd0; - f_l_lockVec_2_empty <= `BSV_ASSIGNMENT_DELAY 1'd1; - f_l_lockVec_2_nextId_rl <= `BSV_ASSIGNMENT_DELAY 2'd0; - f_l_lockVec_2_owner <= `BSV_ASSIGNMENT_DELAY 2'd0; - f_l_lockVec_3_empty <= `BSV_ASSIGNMENT_DELAY 1'd1; - f_l_lockVec_3_nextId_rl <= `BSV_ASSIGNMENT_DELAY 2'd0; - f_l_lockVec_3_owner <= `BSV_ASSIGNMENT_DELAY 2'd0; - h_l_entryVec_0 <= `BSV_ASSIGNMENT_DELAY 11'd682; - h_l_entryVec_1 <= `BSV_ASSIGNMENT_DELAY 11'd682; - h_l_entryVec_2 <= `BSV_ASSIGNMENT_DELAY 11'd682; - h_l_entryVec_3 <= `BSV_ASSIGNMENT_DELAY 11'd682; - h_l_lockVec_0_empty <= `BSV_ASSIGNMENT_DELAY 1'd1; - h_l_lockVec_0_nextId_rl <= `BSV_ASSIGNMENT_DELAY 2'd0; - h_l_lockVec_0_owner <= `BSV_ASSIGNMENT_DELAY 2'd0; - h_l_lockVec_1_empty <= `BSV_ASSIGNMENT_DELAY 1'd1; - h_l_lockVec_1_nextId_rl <= `BSV_ASSIGNMENT_DELAY 2'd0; - h_l_lockVec_1_owner <= `BSV_ASSIGNMENT_DELAY 2'd0; - h_l_lockVec_2_empty <= `BSV_ASSIGNMENT_DELAY 1'd1; - h_l_lockVec_2_nextId_rl <= `BSV_ASSIGNMENT_DELAY 2'd0; - h_l_lockVec_2_owner <= `BSV_ASSIGNMENT_DELAY 2'd0; - h_l_lockVec_3_empty <= `BSV_ASSIGNMENT_DELAY 1'd1; - h_l_lockVec_3_nextId_rl <= `BSV_ASSIGNMENT_DELAY 2'd0; - h_l_lockVec_3_owner <= `BSV_ASSIGNMENT_DELAY 2'd0; - hg <= `BSV_ASSIGNMENT_DELAY 3'd0; - hg_feature_lock_region <= `BSV_ASSIGNMENT_DELAY 1'd1; - hg_fifo__input__TO_Start_rv <= `BSV_ASSIGNMENT_DELAY 14'd2730; - hg_h_lock_region <= `BSV_ASSIGNMENT_DELAY 1'd1; - hg_outputQueue_nextTag_rl <= `BSV_ASSIGNMENT_DELAY 3'd0; - hg_outputQueue_val <= `BSV_ASSIGNMENT_DELAY 2'd0; - hg_weight_lock_region <= `BSV_ASSIGNMENT_DELAY 1'd1; - o <= `BSV_ASSIGNMENT_DELAY 2'd0; - o_busyReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - o_empty <= `BSV_ASSIGNMENT_DELAY 1'd1; - o_h_lock_region <= `BSV_ASSIGNMENT_DELAY 1'd1; - o_nextId_rl <= `BSV_ASSIGNMENT_DELAY 2'd0; - o_outputQueue_nextTag_rl <= `BSV_ASSIGNMENT_DELAY 2'd0; - o_outputQueue_val <= `BSV_ASSIGNMENT_DELAY 1'd0; - o_owner <= `BSV_ASSIGNMENT_DELAY 2'd0; - w_l_entryVec_0 <= `BSV_ASSIGNMENT_DELAY 11'd682; - w_l_entryVec_1 <= `BSV_ASSIGNMENT_DELAY 11'd682; - w_l_entryVec_2 <= `BSV_ASSIGNMENT_DELAY 11'd682; - w_l_entryVec_3 <= `BSV_ASSIGNMENT_DELAY 11'd682; - w_l_lockVec_0_empty <= `BSV_ASSIGNMENT_DELAY 1'd1; - w_l_lockVec_0_nextId_rl <= `BSV_ASSIGNMENT_DELAY 2'd0; - w_l_lockVec_0_owner <= `BSV_ASSIGNMENT_DELAY 2'd0; - w_l_lockVec_1_empty <= `BSV_ASSIGNMENT_DELAY 1'd1; - w_l_lockVec_1_nextId_rl <= `BSV_ASSIGNMENT_DELAY 2'd0; - w_l_lockVec_1_owner <= `BSV_ASSIGNMENT_DELAY 2'd0; - w_l_lockVec_2_empty <= `BSV_ASSIGNMENT_DELAY 1'd1; - w_l_lockVec_2_nextId_rl <= `BSV_ASSIGNMENT_DELAY 2'd0; - w_l_lockVec_2_owner <= `BSV_ASSIGNMENT_DELAY 2'd0; - w_l_lockVec_3_empty <= `BSV_ASSIGNMENT_DELAY 1'd1; - w_l_lockVec_3_nextId_rl <= `BSV_ASSIGNMENT_DELAY 2'd0; - w_l_lockVec_3_owner <= `BSV_ASSIGNMENT_DELAY 2'd0; - end - else - begin - if (f_l_entryVec_0$EN) - f_l_entryVec_0 <= `BSV_ASSIGNMENT_DELAY f_l_entryVec_0$D_IN; - if (f_l_entryVec_1$EN) - f_l_entryVec_1 <= `BSV_ASSIGNMENT_DELAY f_l_entryVec_1$D_IN; - if (f_l_entryVec_2$EN) - f_l_entryVec_2 <= `BSV_ASSIGNMENT_DELAY f_l_entryVec_2$D_IN; - if (f_l_entryVec_3$EN) - f_l_entryVec_3 <= `BSV_ASSIGNMENT_DELAY f_l_entryVec_3$D_IN; - if (f_l_lockVec_0_empty$EN) - f_l_lockVec_0_empty <= `BSV_ASSIGNMENT_DELAY - f_l_lockVec_0_empty$D_IN; - if (f_l_lockVec_0_nextId_rl$EN) - f_l_lockVec_0_nextId_rl <= `BSV_ASSIGNMENT_DELAY - f_l_lockVec_0_nextId_rl$D_IN; - if (f_l_lockVec_0_owner$EN) - f_l_lockVec_0_owner <= `BSV_ASSIGNMENT_DELAY - f_l_lockVec_0_owner$D_IN; - if (f_l_lockVec_1_empty$EN) - f_l_lockVec_1_empty <= `BSV_ASSIGNMENT_DELAY - f_l_lockVec_1_empty$D_IN; - if (f_l_lockVec_1_nextId_rl$EN) - f_l_lockVec_1_nextId_rl <= `BSV_ASSIGNMENT_DELAY - f_l_lockVec_1_nextId_rl$D_IN; - if (f_l_lockVec_1_owner$EN) - f_l_lockVec_1_owner <= `BSV_ASSIGNMENT_DELAY - f_l_lockVec_1_owner$D_IN; - if (f_l_lockVec_2_empty$EN) - f_l_lockVec_2_empty <= `BSV_ASSIGNMENT_DELAY - f_l_lockVec_2_empty$D_IN; - if (f_l_lockVec_2_nextId_rl$EN) - f_l_lockVec_2_nextId_rl <= `BSV_ASSIGNMENT_DELAY - f_l_lockVec_2_nextId_rl$D_IN; - if (f_l_lockVec_2_owner$EN) - f_l_lockVec_2_owner <= `BSV_ASSIGNMENT_DELAY - f_l_lockVec_2_owner$D_IN; - if (f_l_lockVec_3_empty$EN) - f_l_lockVec_3_empty <= `BSV_ASSIGNMENT_DELAY - f_l_lockVec_3_empty$D_IN; - if (f_l_lockVec_3_nextId_rl$EN) - f_l_lockVec_3_nextId_rl <= `BSV_ASSIGNMENT_DELAY - f_l_lockVec_3_nextId_rl$D_IN; - if (f_l_lockVec_3_owner$EN) - f_l_lockVec_3_owner <= `BSV_ASSIGNMENT_DELAY - f_l_lockVec_3_owner$D_IN; - if (h_l_entryVec_0$EN) - h_l_entryVec_0 <= `BSV_ASSIGNMENT_DELAY h_l_entryVec_0$D_IN; - if (h_l_entryVec_1$EN) - h_l_entryVec_1 <= `BSV_ASSIGNMENT_DELAY h_l_entryVec_1$D_IN; - if (h_l_entryVec_2$EN) - h_l_entryVec_2 <= `BSV_ASSIGNMENT_DELAY h_l_entryVec_2$D_IN; - if (h_l_entryVec_3$EN) - h_l_entryVec_3 <= `BSV_ASSIGNMENT_DELAY h_l_entryVec_3$D_IN; - if (h_l_lockVec_0_empty$EN) - h_l_lockVec_0_empty <= `BSV_ASSIGNMENT_DELAY - h_l_lockVec_0_empty$D_IN; - if (h_l_lockVec_0_nextId_rl$EN) - h_l_lockVec_0_nextId_rl <= `BSV_ASSIGNMENT_DELAY - h_l_lockVec_0_nextId_rl$D_IN; - if (h_l_lockVec_0_owner$EN) - h_l_lockVec_0_owner <= `BSV_ASSIGNMENT_DELAY - h_l_lockVec_0_owner$D_IN; - if (h_l_lockVec_1_empty$EN) - h_l_lockVec_1_empty <= `BSV_ASSIGNMENT_DELAY - h_l_lockVec_1_empty$D_IN; - if (h_l_lockVec_1_nextId_rl$EN) - h_l_lockVec_1_nextId_rl <= `BSV_ASSIGNMENT_DELAY - h_l_lockVec_1_nextId_rl$D_IN; - if (h_l_lockVec_1_owner$EN) - h_l_lockVec_1_owner <= `BSV_ASSIGNMENT_DELAY - h_l_lockVec_1_owner$D_IN; - if (h_l_lockVec_2_empty$EN) - h_l_lockVec_2_empty <= `BSV_ASSIGNMENT_DELAY - h_l_lockVec_2_empty$D_IN; - if (h_l_lockVec_2_nextId_rl$EN) - h_l_lockVec_2_nextId_rl <= `BSV_ASSIGNMENT_DELAY - h_l_lockVec_2_nextId_rl$D_IN; - if (h_l_lockVec_2_owner$EN) - h_l_lockVec_2_owner <= `BSV_ASSIGNMENT_DELAY - h_l_lockVec_2_owner$D_IN; - if (h_l_lockVec_3_empty$EN) - h_l_lockVec_3_empty <= `BSV_ASSIGNMENT_DELAY - h_l_lockVec_3_empty$D_IN; - if (h_l_lockVec_3_nextId_rl$EN) - h_l_lockVec_3_nextId_rl <= `BSV_ASSIGNMENT_DELAY - h_l_lockVec_3_nextId_rl$D_IN; - if (h_l_lockVec_3_owner$EN) - h_l_lockVec_3_owner <= `BSV_ASSIGNMENT_DELAY - h_l_lockVec_3_owner$D_IN; - if (hg$EN) hg <= `BSV_ASSIGNMENT_DELAY hg$D_IN; - if (hg_feature_lock_region$EN) - hg_feature_lock_region <= `BSV_ASSIGNMENT_DELAY - hg_feature_lock_region$D_IN; - if (hg_fifo__input__TO_Start_rv$EN) - hg_fifo__input__TO_Start_rv <= `BSV_ASSIGNMENT_DELAY - hg_fifo__input__TO_Start_rv$D_IN; - if (hg_h_lock_region$EN) - hg_h_lock_region <= `BSV_ASSIGNMENT_DELAY hg_h_lock_region$D_IN; - if (hg_outputQueue_nextTag_rl$EN) - hg_outputQueue_nextTag_rl <= `BSV_ASSIGNMENT_DELAY - hg_outputQueue_nextTag_rl$D_IN; - if (hg_outputQueue_val$EN) - hg_outputQueue_val <= `BSV_ASSIGNMENT_DELAY hg_outputQueue_val$D_IN; - if (hg_weight_lock_region$EN) - hg_weight_lock_region <= `BSV_ASSIGNMENT_DELAY - hg_weight_lock_region$D_IN; - if (o$EN) o <= `BSV_ASSIGNMENT_DELAY o$D_IN; - if (o_busyReg$EN) o_busyReg <= `BSV_ASSIGNMENT_DELAY o_busyReg$D_IN; - if (o_empty$EN) o_empty <= `BSV_ASSIGNMENT_DELAY o_empty$D_IN; - if (o_h_lock_region$EN) - o_h_lock_region <= `BSV_ASSIGNMENT_DELAY o_h_lock_region$D_IN; - if (o_nextId_rl$EN) - o_nextId_rl <= `BSV_ASSIGNMENT_DELAY o_nextId_rl$D_IN; - if (o_outputQueue_nextTag_rl$EN) - o_outputQueue_nextTag_rl <= `BSV_ASSIGNMENT_DELAY - o_outputQueue_nextTag_rl$D_IN; - if (o_outputQueue_val$EN) - o_outputQueue_val <= `BSV_ASSIGNMENT_DELAY o_outputQueue_val$D_IN; - if (o_owner$EN) o_owner <= `BSV_ASSIGNMENT_DELAY o_owner$D_IN; - if (w_l_entryVec_0$EN) - w_l_entryVec_0 <= `BSV_ASSIGNMENT_DELAY w_l_entryVec_0$D_IN; - if (w_l_entryVec_1$EN) - w_l_entryVec_1 <= `BSV_ASSIGNMENT_DELAY w_l_entryVec_1$D_IN; - if (w_l_entryVec_2$EN) - w_l_entryVec_2 <= `BSV_ASSIGNMENT_DELAY w_l_entryVec_2$D_IN; - if (w_l_entryVec_3$EN) - w_l_entryVec_3 <= `BSV_ASSIGNMENT_DELAY w_l_entryVec_3$D_IN; - if (w_l_lockVec_0_empty$EN) - w_l_lockVec_0_empty <= `BSV_ASSIGNMENT_DELAY - w_l_lockVec_0_empty$D_IN; - if (w_l_lockVec_0_nextId_rl$EN) - w_l_lockVec_0_nextId_rl <= `BSV_ASSIGNMENT_DELAY - w_l_lockVec_0_nextId_rl$D_IN; - if (w_l_lockVec_0_owner$EN) - w_l_lockVec_0_owner <= `BSV_ASSIGNMENT_DELAY - w_l_lockVec_0_owner$D_IN; - if (w_l_lockVec_1_empty$EN) - w_l_lockVec_1_empty <= `BSV_ASSIGNMENT_DELAY - w_l_lockVec_1_empty$D_IN; - if (w_l_lockVec_1_nextId_rl$EN) - w_l_lockVec_1_nextId_rl <= `BSV_ASSIGNMENT_DELAY - w_l_lockVec_1_nextId_rl$D_IN; - if (w_l_lockVec_1_owner$EN) - w_l_lockVec_1_owner <= `BSV_ASSIGNMENT_DELAY - w_l_lockVec_1_owner$D_IN; - if (w_l_lockVec_2_empty$EN) - w_l_lockVec_2_empty <= `BSV_ASSIGNMENT_DELAY - w_l_lockVec_2_empty$D_IN; - if (w_l_lockVec_2_nextId_rl$EN) - w_l_lockVec_2_nextId_rl <= `BSV_ASSIGNMENT_DELAY - w_l_lockVec_2_nextId_rl$D_IN; - if (w_l_lockVec_2_owner$EN) - w_l_lockVec_2_owner <= `BSV_ASSIGNMENT_DELAY - w_l_lockVec_2_owner$D_IN; - if (w_l_lockVec_3_empty$EN) - w_l_lockVec_3_empty <= `BSV_ASSIGNMENT_DELAY - w_l_lockVec_3_empty$D_IN; - if (w_l_lockVec_3_nextId_rl$EN) - w_l_lockVec_3_nextId_rl <= `BSV_ASSIGNMENT_DELAY - w_l_lockVec_3_nextId_rl$D_IN; - if (w_l_lockVec_3_owner$EN) - w_l_lockVec_3_owner <= `BSV_ASSIGNMENT_DELAY - w_l_lockVec_3_owner$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - f_l_entryVec_0 = 11'h2AA; - f_l_entryVec_1 = 11'h2AA; - f_l_entryVec_2 = 11'h2AA; - f_l_entryVec_3 = 11'h2AA; - f_l_lockVec_0_empty = 1'h0; - f_l_lockVec_0_nextId_rl = 2'h2; - f_l_lockVec_0_owner = 2'h2; - f_l_lockVec_1_empty = 1'h0; - f_l_lockVec_1_nextId_rl = 2'h2; - f_l_lockVec_1_owner = 2'h2; - f_l_lockVec_2_empty = 1'h0; - f_l_lockVec_2_nextId_rl = 2'h2; - f_l_lockVec_2_owner = 2'h2; - f_l_lockVec_3_empty = 1'h0; - f_l_lockVec_3_nextId_rl = 2'h2; - f_l_lockVec_3_owner = 2'h2; - h_l_entryVec_0 = 11'h2AA; - h_l_entryVec_1 = 11'h2AA; - h_l_entryVec_2 = 11'h2AA; - h_l_entryVec_3 = 11'h2AA; - h_l_lockVec_0_empty = 1'h0; - h_l_lockVec_0_nextId_rl = 2'h2; - h_l_lockVec_0_owner = 2'h2; - h_l_lockVec_1_empty = 1'h0; - h_l_lockVec_1_nextId_rl = 2'h2; - h_l_lockVec_1_owner = 2'h2; - h_l_lockVec_2_empty = 1'h0; - h_l_lockVec_2_nextId_rl = 2'h2; - h_l_lockVec_2_owner = 2'h2; - h_l_lockVec_3_empty = 1'h0; - h_l_lockVec_3_nextId_rl = 2'h2; - h_l_lockVec_3_owner = 2'h2; - hg = 3'h2; - hg_feature_lock_region = 1'h0; - hg_fifo__input__TO_Start_rv = 14'h2AAA; - hg_h_lock_region = 1'h0; - hg_outputQueue_nextTag_rl = 3'h2; - hg_outputQueue_val = 2'h2; - hg_weight_lock_region = 1'h0; - o = 2'h2; - o_busyReg = 1'h0; - o_empty = 1'h0; - o_h_lock_region = 1'h0; - o_nextId_rl = 2'h2; - o_outputQueue_nextTag_rl = 2'h2; - o_outputQueue_val = 1'h0; - o_owner = 2'h2; - w_l_entryVec_0 = 11'h2AA; - w_l_entryVec_1 = 11'h2AA; - w_l_entryVec_2 = 11'h2AA; - w_l_entryVec_3 = 11'h2AA; - w_l_lockVec_0_empty = 1'h0; - w_l_lockVec_0_nextId_rl = 2'h2; - w_l_lockVec_0_owner = 2'h2; - w_l_lockVec_1_empty = 1'h0; - w_l_lockVec_1_nextId_rl = 2'h2; - w_l_lockVec_1_owner = 2'h2; - w_l_lockVec_2_empty = 1'h0; - w_l_lockVec_2_nextId_rl = 2'h2; - w_l_lockVec_2_owner = 2'h2; - w_l_lockVec_3_empty = 1'h0; - w_l_lockVec_3_nextId_rl = 2'h2; - w_l_lockVec_3_owner = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_hg_s_Stage__0_execute) - $display($unsigned(th_rf_sub_hg_fifo_Start_TO_Stage__0_first__41__ETC___d537)); - end - // synopsys translate_on -endmodule // mkCircuit - diff --git a/src/test/tests/histogram/Circuit_verilog/mkTB.v b/src/test/tests/histogram/Circuit_verilog/mkTB.v deleted file mode 100644 index 0951214c..00000000 --- a/src/test/tests/histogram/Circuit_verilog/mkTB.v +++ /dev/null @@ -1,127 +0,0 @@ -// -// Generated by Bluespec Compiler -// -// -// Ports: -// Name I/O size props -// CLK I 1 clock -// RST_N I 1 reset -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkTB(CLK, - RST_N); - input CLK; - input RST_N; - - // register reg_unused_0 - reg [1 : 0] reg_unused_0; - wire [1 : 0] reg_unused_0$D_IN; - wire reg_unused_0$EN; - - // register started - reg started; - wire started$D_IN, started$EN; - - // register timer - reg [31 : 0] timer; - wire [31 : 0] timer$D_IN; - wire timer$EN; - - // ports of submodule _unnamed_ - wire [9 : 0] _unnamed_$_into_req_counter; - wire [1 : 0] _unnamed_$_into_checkHandle_handle, _unnamed_$_into_req; - wire _unnamed_$EN__into_req, - _unnamed_$EN__into_resp, - _unnamed_$RDY__into_req, - _unnamed_$_into_checkHandle; - - // submodule _unnamed_ - mkCircuit _unnamed_(.CLK(CLK), - .RST_N(RST_N), - ._into_checkHandle_handle(_unnamed_$_into_checkHandle_handle), - ._into_req_counter(_unnamed_$_into_req_counter), - .EN__into_req(_unnamed_$EN__into_req), - .EN__into_resp(_unnamed_$EN__into_resp), - ._into_req(_unnamed_$_into_req), - .RDY__into_req(_unnamed_$RDY__into_req), - .RDY__into_resp(), - ._into_checkHandle(_unnamed_$_into_checkHandle), - .RDY__into_checkHandle()); - - // register reg_unused_0 - assign reg_unused_0$D_IN = _unnamed_$_into_req ; - assign reg_unused_0$EN = _unnamed_$RDY__into_req && !started ; - - // register started - assign started$D_IN = 1'd1 ; - assign started$EN = _unnamed_$RDY__into_req && !started ; - - // register timer - assign timer$D_IN = timer + 32'd1 ; - assign timer$EN = 1'd1 ; - - // submodule _unnamed_ - assign _unnamed_$_into_checkHandle_handle = reg_unused_0 ; - assign _unnamed_$_into_req_counter = 10'd0 ; - assign _unnamed_$EN__into_req = _unnamed_$RDY__into_req && !started ; - assign _unnamed_$EN__into_resp = 1'b0 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - reg_unused_0 <= `BSV_ASSIGNMENT_DELAY 2'd0; - started <= `BSV_ASSIGNMENT_DELAY 1'd0; - timer <= `BSV_ASSIGNMENT_DELAY 32'd0; - end - else - begin - if (reg_unused_0$EN) - reg_unused_0 <= `BSV_ASSIGNMENT_DELAY reg_unused_0$D_IN; - if (started$EN) started <= `BSV_ASSIGNMENT_DELAY started$D_IN; - if (timer$EN) timer <= `BSV_ASSIGNMENT_DELAY timer$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - reg_unused_0 = 2'h2; - started = 1'h0; - timer = 32'hAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (timer >= 32'd1000000 || _unnamed_$_into_checkHandle) $finish(32'd1); - end - // synopsys translate_on -endmodule // mkTB - diff --git a/src/test/tests/histogram/Functions.bsv b/src/test/tests/histogram/Functions.bsv deleted file mode 100644 index e69de29b..00000000 diff --git a/src/test/tests/histogram/Hist.bsv b/src/test/tests/histogram/Hist.bsv deleted file mode 100644 index a1af321f..00000000 --- a/src/test/tests/histogram/Hist.bsv +++ /dev/null @@ -1,97 +0,0 @@ -import FIFOF :: *; -import SpecialFIFOs :: *; -import SpecialQueues :: *; -import Locks :: *; -import Memories :: *; -import VerilogLibs :: *; -import Speculation :: *; -import RegFile :: *; -import Functions :: *; - -export Hist (..); -export mkHist ; - -typedef struct { UInt#(10) counter; UInt#(3) _threadID ; } E__input__TO_Start deriving( Bits,Eq ); -typedef struct { UInt#(10) m1; UInt#(32) wt; UInt#(3) _threadID ; } E_Start_TO_Stage__0 deriving( Bits,Eq ); -typedef struct { UInt#(32) nm; Maybe#( _lidTyp_h ) _lock_id_h_mcp_rs; UInt#(10) mcp; UInt#(3) _threadID ; } E_Stage__0_TO_Stage__1#( type _lidTyp_h ) deriving( Bits,Eq ); -typedef struct { UInt#(3) _threadID ; } E_Stage__1_TO_Stage__2 deriving( Bits,Eq ); - -interface Hist; - method ActionValue#(UInt#(3)) req ( UInt#(10) counter ) ; - method Action resp ( ) ; - method Bool checkHandle ( UInt#(3) handle ) ; - method Bool peek ( ) ; -endinterface - - -module mkHist ( AddrLockCombMem#( UInt#(10), UInt#(16), _lidTyp_feature, _szParam_0_feature ) feature, AddrLockCombMem#( UInt#(10), UInt#(32), _lidTyp_weight, _szParam_0_weight ) weight, AddrLockCombMem#( UInt#(10), UInt#(32), _lidTyp_h, _szParam_0_h ) h, Hist _unused_ ) provisos( Bits#(_lidTyp_h,_sz_lidTyp_h),Bits#(_lidTyp_weight,_sz_lidTyp_weight),Bits#(_lidTyp_feature,_sz_lidTyp_feature) ); - FIFOF#( E__input__TO_Start ) fifo__input__TO_Start <- mkBypassFIFOF ( ); - FIFOF#( E_Start_TO_Stage__0 ) fifo_Start_TO_Stage__0 <- mkFIFOF ( ); - FIFOF#( E_Stage__0_TO_Stage__1#(_lidTyp_h) ) fifo_Stage__0_TO_Stage__1 <- mkFIFOF ( ); - FIFOF#( E_Stage__1_TO_Stage__2 ) fifo_Stage__1_TO_Stage__2 <- mkFIFOF ( ); - Reg#( Bool ) feature_lock_region <- mkReg ( True ); - Reg#( Bool ) weight_lock_region <- mkReg ( True ); - Reg#( Bool ) h_lock_region <- mkReg ( True ); - OutputQ#( UInt#(3), Bool ) outputQueue <- mkOutputFIFOF ( 0 ); - Reg#( UInt#(3) ) _threadID <- mkReg ( 0 ); - UInt#(10) _Start_counter = fifo__input__TO_Start.first.counter; - UInt#(3) _Start__threadID = fifo__input__TO_Start.first._threadID; - UInt#(16) _Start_m = ?; - UInt#(10) _Start_m1 = ?; - UInt#(32) _Start_wt = ?; - _Start_m = feature.atom_r(_Start_counter); - _Start_m1 = unpack( pack( _Start_m ) [ 9 : 0 ] ); - _Start_wt = weight.atom_r(_Start_counter); - UInt#(10) _Stage__0_m1 = fifo_Start_TO_Stage__0.first.m1; - UInt#(32) _Stage__0_wt = fifo_Start_TO_Stage__0.first.wt; - UInt#(3) _Stage__0__threadID = fifo_Start_TO_Stage__0.first._threadID; - UInt#(10) _Stage__0_mcp = ?; - UInt#(32) _Stage__0_nm = ?; - _Stage__0_mcp = _Stage__0_m1; - _Stage__0_nm = ( h.atom_r(_Stage__0_m1) + _Stage__0_wt ); - UInt#(32) _Stage__1_nm = fifo_Stage__0_TO_Stage__1.first.nm; - Maybe#( _lidTyp_h ) _Stage__1__lock_id_h_mcp_rs = fifo_Stage__0_TO_Stage__1.first._lock_id_h_mcp_rs; - UInt#(10) _Stage__1_mcp = fifo_Stage__0_TO_Stage__1.first.mcp; - UInt#(3) _Stage__1__threadID = fifo_Stage__0_TO_Stage__1.first._threadID; - Maybe#( _lidTyp_h ) _Stage__1__lock_id_h_mcp_aq = ?; - Maybe#( _lidTyp_h ) _Stage__1__lock_id_h_mcp_op = ?; - _Stage__1__lock_id_h_mcp_aq = _Stage__1__lock_id_h_mcp_rs; - _Stage__1__lock_id_h_mcp_op = _Stage__1__lock_id_h_mcp_aq; - UInt#(3) _Stage__2__threadID = fifo_Stage__1_TO_Stage__2.first._threadID; - rule s_Start_execute (feature.canAtom_r1(_Start_counter) && weight.canAtom_r1(_Start_counter)); - fifo__input__TO_Start.deq; - fifo_Start_TO_Stage__0.enq(E_Start_TO_Stage__0 { m1 : _Start_m1,wt : _Start_wt,_threadID : _Start__threadID }); - endrule - rule s_Stage__0_execute (h.canAtom_r1(_Stage__0_m1) && h.lock.canRes1(_Stage__0_mcp)); - Maybe#( _lidTyp_h ) _Stage__0__lock_id_h_mcp_rs = tagged Invalid; - let __tmp_0 <- h.lock.res1(_Stage__0_mcp); - _Stage__0__lock_id_h_mcp_rs = tagged Valid __tmp_0; - $display( _Stage__0_nm ); - fifo_Start_TO_Stage__0.deq; - fifo_Stage__0_TO_Stage__1.enq(E_Stage__0_TO_Stage__1 { nm : _Stage__0_nm,_lock_id_h_mcp_rs : _Stage__0__lock_id_h_mcp_rs,mcp : _Stage__0_mcp,_threadID : _Stage__0__threadID }); - endrule - rule s_Stage__1_execute (h.lock.owns1(fromMaybe( ? , _Stage__1__lock_id_h_mcp_rs ), _Stage__1_mcp)); - h.lock.rel1(fromMaybe( ? , _Stage__1__lock_id_h_mcp_op ), _Stage__1_mcp); - h.write(_Stage__1_mcp, _Stage__1_nm); - fifo_Stage__0_TO_Stage__1.deq; - fifo_Stage__1_TO_Stage__2.enq(E_Stage__1_TO_Stage__2 { _threadID : _Stage__1__threadID }); - endrule - rule s_Stage__2_execute (outputQueue.canWrite(_Stage__2__threadID)); - outputQueue.enq(True); - fifo_Stage__1_TO_Stage__2.deq; - endrule - method ActionValue#(UInt#(3)) req ( UInt#(10) counter ) ; - fifo__input__TO_Start.enq(E__input__TO_Start { counter : counter,_threadID : _threadID }); - _threadID <= ( _threadID + 1 ); - return _threadID; - endmethod - method Action resp ( ) ; - outputQueue.deq; - endmethod - method Bool peek ( ) ; - return outputQueue.first; - endmethod - method Bool checkHandle ( UInt#(3) handle ) ; - return outputQueue.canRead(handle); - endmethod -endmodule diff --git a/src/test/tests/histogram/Outer.bsv b/src/test/tests/histogram/Outer.bsv deleted file mode 100644 index 04b1b0d1..00000000 --- a/src/test/tests/histogram/Outer.bsv +++ /dev/null @@ -1,123 +0,0 @@ -import FIFOF :: *; -import SpecialFIFOs :: *; -import SpecialQueues :: *; -import Locks :: *; -import Memories :: *; -import VerilogLibs :: *; -import Speculation :: *; -import RegFile :: *; -import Functions :: *; -import Hist :: *; - -export Outer (..); -export mkOuter ; - -typedef struct { UInt#(10) counter; UInt#(2) _threadID ; } E__input__TO_Start deriving( Bits,Eq ); -typedef struct { UInt#(3) _request_1; UInt#(2) _threadID ; } E_Stage__1_TO_Stage__3 deriving( Bits,Eq ); -typedef struct { UInt#(1) __condStage__4; UInt#(2) _threadID ; } E_Start_TO_Stage__3 deriving( Bits,Eq ); -typedef struct { UInt#(2) _threadID ; } E_Start_TO_Stage__3_1 deriving( Bits,Eq ); -typedef struct { UInt#(10) counter; Maybe#( LockId#(4) ) _lock_id_h_rs; UInt#(2) _threadID ; } E_Start_TO_Stage__1 deriving( Bits,Eq ); - -interface Outer; - method ActionValue#(UInt#(2)) req ( UInt#(10) counter ) ; - method Action resp ( ) ; - method Bool checkHandle ( UInt#(2) handle ) ; -endinterface - - -module mkOuter ( Hist h, Outer _unused_ ) provisos( ); - FIFOF#( E__input__TO_Start ) fifo__input__TO_Start <- mkNBFIFOF ( ); - FIFOF#( E_Start_TO_Stage__3_1 ) fifo_Start_TO_Stage__3_1 <- mkFIFOF ( ); - FIFOF#( E_Start_TO_Stage__1 ) fifo_Start_TO_Stage__1 <- mkFIFOF ( ); - FIFOF#( E_Start_TO_Stage__3 ) fifo_Start_TO_Stage__3 <- mkFIFOF ( ); - FIFOF#( E_Stage__1_TO_Stage__3 ) fifo_Stage__1_TO_Stage__3 <- mkFIFOF ( ); - Reg#( Bool ) h_lock_region <- mkReg ( True ); - CheckpointQueueLock#( LockId#(4), LockId#(4) ) _lock_h <- mkCheckpointQueueLock ( ); - Reg#( Bool ) busyReg <- mkReg ( False ); - OutputQ#( UInt#(2), void ) outputQueue <- mkOutputFIFOF ( 0 ); - Reg#( UInt#(2) ) _threadID <- mkReg ( 0 ); - UInt#(10) _Start_counter = fifo__input__TO_Start.first.counter; - UInt#(2) _Start__threadID = fifo__input__TO_Start.first._threadID; - Bool _Start_done = ?; - UInt#(1) _Start___condStage__4 = ?; - UInt#(10) _Start_carg_332 = ?; - _Start_done = ( _Start_counter >= 10'd1000 ); - _Start___condStage__4 = ( ( ! _Start_done ) ? 1'd0 : 1'd1 ); - if ( ( _Start___condStage__4 == 1'd0 )) - begin - _Start_carg_332 = ( _Start_counter + 10'd1 ); - end - UInt#(1) _Stage__3___condStage__4 = fifo_Start_TO_Stage__3.first.__condStage__4; - UInt#(2) _Stage__3__threadID = fifo_Start_TO_Stage__3.first._threadID; - UInt#(3) _Stage__3__request_1 = ( ( _Stage__3___condStage__4 == 1'd1 ) ? ? : ( ( _Stage__3___condStage__4 == 1'd0 ) ? fifo_Stage__1_TO_Stage__3.first._request_1 : ? ) ); - Bool _Stage__3_x = ?; - if ( ( _Stage__3___condStage__4 == 1'd0 )) - begin - _Stage__3_x = h.peek; - end - UInt#(10) _Stage__1_counter = fifo_Start_TO_Stage__1.first.counter; - Maybe#( LockId#(4) ) _Stage__1__lock_id_h_rs = fifo_Start_TO_Stage__1.first._lock_id_h_rs; - UInt#(2) _Stage__1__threadID = fifo_Start_TO_Stage__1.first._threadID; - Maybe#( LockId#(4) ) _Stage__1__lock_id_h_aq = ?; - UInt#(10) _Stage__1_carg_333 = ?; - _Stage__1__lock_id_h_aq = _Stage__1__lock_id_h_rs; - _Stage__1_carg_333 = _Stage__1_counter; - rule s_Start_execute (( ( ! ( _Start___condStage__4 == 1'd1 ) ) || outputQueue.canWrite(_Start__threadID) )); - Maybe#( LockId#(4) ) _Start__lock_id_h_rs = tagged Invalid; - if ( ( _Start___condStage__4 == 1'd0 )) - begin - let __tmp_0 <- _lock_h.res1; - _Start__lock_id_h_rs = tagged Valid __tmp_0; - fifo__input__TO_Start.enq(E__input__TO_Start { counter : _Start_carg_332,_threadID : _Start__threadID }); - end - if ( ( _Start___condStage__4 == 1'd1 )) - begin - busyReg <= False; - outputQueue.enq(?); - end - fifo__input__TO_Start.deq; - fifo_Start_TO_Stage__3.enq(E_Start_TO_Stage__3 { __condStage__4 : _Start___condStage__4,_threadID : _Start__threadID }); - if ( ( _Start___condStage__4 == 1'd0 )) - begin - fifo_Start_TO_Stage__1.enq(E_Start_TO_Stage__1 { counter : _Start_counter,_lock_id_h_rs : _Start__lock_id_h_rs,_threadID : _Start__threadID }); - end - if ( ( _Start___condStage__4 == 1'd1 )) - begin - fifo_Start_TO_Stage__3_1.enq(E_Start_TO_Stage__3_1 { _threadID : _Start__threadID }); - end - endrule - rule s_Stage__3_execute (( ( ! ( _Stage__3___condStage__4 == 1'd0 ) ) || h.checkHandle(_Stage__3__request_1) )); - if ( ( _Stage__3___condStage__4 == 1'd0 )) - begin - h.resp; - end - if ( ( _Stage__3___condStage__4 == 1'd0 )) - begin - fifo_Stage__1_TO_Stage__3.deq; - end - fifo_Start_TO_Stage__3.deq; - if ( ( _Stage__3___condStage__4 == 1'd1 )) - begin - fifo_Start_TO_Stage__3_1.deq; - end - endrule - rule s_Stage__1_execute (_lock_h.owns1(fromMaybe( ? , _Stage__1__lock_id_h_rs ))); - UInt#(3) _Stage__1__request_1 = ?; - _lock_h.rel1(fromMaybe( ? , _Stage__1__lock_id_h_aq )); - _Stage__1__request_1 <- h.req(_Stage__1_carg_333); - fifo_Stage__1_TO_Stage__3.enq(E_Stage__1_TO_Stage__3 { _request_1 : _Stage__1__request_1,_threadID : _Stage__1__threadID }); - fifo_Start_TO_Stage__1.deq; - endrule - method ActionValue#(UInt#(2)) req ( UInt#(10) counter ) if( ( ! busyReg ) ); - fifo__input__TO_Start.enq(E__input__TO_Start { counter : counter,_threadID : _threadID }); - busyReg <= True; - _threadID <= ( _threadID + 1 ); - return _threadID; - endmethod - method Action resp ( ) ; - outputQueue.deq; - endmethod - method Bool checkHandle ( UInt#(2) handle ) ; - return outputQueue.canRead(handle); - endmethod -endmodule diff --git a/src/test/tests/histogram/f b/src/test/tests/histogram/f deleted file mode 100644 index 2f16247c..00000000 --- a/src/test/tests/histogram/f +++ /dev/null @@ -1,1024 +0,0 @@ -1b9 -1ba -275 -21b -2e4 -3fc -3c6 -197 -1a4 -129 -206 -2b4 -2e -3ea -198 -22e -38 -d2 -129 -200 -1d7 -2b4 -339 -9f -231 -31a -91 -204 -36c -2f1 -2b8 -29f -1cd -17d -3c8 -27d -5c -1dd -342 -18e -6a -178 -289 -105 -1a6 -f7 -1d6 -94 -7e -2ac -319 -2a8 -87 -e3 -22e -bc -2d9 -279 -33d -3b5 -26e -3df -59 -9d -25f -126 -351 -135 -e8 -1e9 -3d -26c -3ab -18e -3ae -61 -2f2 -3b2 -1d6 -cd -1a4 -266 -3c8 -35b -2d6 -3b0 -2cb -28 -167 -356 -4f -390 -194 -1c6 -f8 -4 -2f0 -81 -20a -15d -208 -271 -7c -1a6 -5d -7a -24b -1e2 -2dd -1e2 -18 -325 -b -330 -3af -383 -2ed -205 -301 -29 -172 -2c -1fd -30a -3d3 -4a -92 -3ad -238 -31c -33d -338 -233 -cd -a -70 -9 -3d0 -188 -24b -29c -96 -f6 -30 -58 -19c -167 -123 -100 -3b3 -3f2 -2a -1b5 -290 -364 -19a -356 -23b -31b -4d -21d -3ff -10e -1f6 -235 -af -1c9 -fe -373 -6e -19b -1c3 -36 -a1 -3a -28c -26c -28e -144 -af -254 -230 -139 -28 -108 -178 -3aa -2c9 -c3 -1b6 -211 -3b3 -37 -63 -1b0 -224 -5a -2ca -3f2 -2a7 -5b -2cd -1c0 -c0 -134 -2d8 -133 -17 -1f7 -23f -2a9 -288 -317 -199 -122 -30e -35f -9 -142 -271 -3e0 -103 -18b -67 -f5 -37a -34f -2bb -374 -af -28d -2ee -4e -ca -35d -9 -3ac -21b -334 -7d -2a6 -13e -10b -22 -10f -3f7 -3e1 -2eb -ee -2e7 -378 -10e -380 -241 -2ae -3ae -343 -127 -b0 -2d1 -3b4 -3f8 -1d6 -16f -28a -300 -65 -1ea -39b -118 -8a -32c -1d4 -16f -2ab -2c4 -118 -c9 -3ad -114 -157 -210 -1e -246 -2d0 -3cc -1a2 -3ef -2db -1cc -82 -1f4 -351 -2b3 -2a1 -b1 -2fb -39d -2e0 -281 -297 -1dc -1eb -2b2 -3e2 -11c -303 -1fb -17d -2cf -3e0 -25 -ea -130 -37e -384 -1e8 -36c -f9 -183 -313 -112 -16b -127 -10c -311 -2a5 -1d6 -46 -bb -3b6 -134 -3d1 -11f -4f -373 -314 -1f9 -2e9 -39f -321 -21f -fb -1e8 -201 -82 -71 -c8 -3c1 -247 -80 -3de -53 -1b8 -bd -27e -280 -58 -2c7 -139 -2ec -45 -2a3 -14b -273 -35c -347 -3d4 -209 -23c -5f -38b -37a -75 -3ab -31e -6b -31 -2b9 -188 -376 -39a -194 -12b -20e -68 -1e7 -167 -4b -31a -151 -1e7 -381 -358 -163 -3a9 -45 -1a7 -1c1 -3b8 -3c8 -1af -23 -ef -164 -1d1 -ba -330 -eb -3e -180 -3c7 -2d8 -2f -2dd -23b -35d -388 -9a -18e -20a -2b5 -220 -200 -1f5 -32c -16 -3b5 -2b3 -4a -345 -171 -35e -c8 -2e6 -34e -2c8 -353 -3fa -1bf -2cc -2e8 -16 -345 -59 -a0 -185 -e8 -24 -21d -39f -26a -26 -20b -2c6 -1fd -3f0 -17c -d1 -155 -20 -125 -3a2 -207 -10e -3c6 -42 -11a -112 -25d -1a -1d -18a -39f -2df -2d6 -24e -56 -1e0 -2cf -d3 -3a2 -25f -16f -17a -18c -9f -d7 -48 -27c -65 -220 -38c -3d3 -311 -2ec -31e -3d2 -15c -1f4 -281 -1f3 -17e -a6 -8d -6d -273 -1db -17d -34e -189 -277 -2b0 -2f1 -32a -df -2ca -77 -2dc -314 -185 -249 -261 -3a6 -94 -192 -ca -314 -2b -26 -13e -295 -247 -6d -1fb -1fe -2f9 -3f6 -2f7 -3e6 -104 -a8 -f3 -d4 -2c5 -224 -21 -145 -20b -36d -280 -2b9 -177 -3df -23a -e1 -1c1 -2ed -213 -16b -11c -133 -e5 -59 -180 -35e -394 -36 -193 -1e9 -1a5 -7a -196 -3f3 -26d -13a -151 -184 -e3 -38f -389 -238 -251 -21b -3ec -39a -3b6 -cd -32b -130 -3bc -2b4 -a6 -3cf -102 -269 -2f9 -3c6 -25 -1d0 -b6 -4 -28b -f1 -207 -33d -9a -1a4 -3d9 -379 -2e8 -1ce -2d4 -2e4 -bc -39a -26b -330 -7f -1e -371 -19c -e -cc -25f -263 -36c -28f -3cf -89 -3fe -2ab -63 -191 -7e -288 -32f -3ec -25f -170 -3c8 -376 -28c -9c -18a -14 -1b6 -40 -30b -13a -f6 -20 -10c -5c -33a -14c -36c -225 -24f -3ae -2e2 -12a -17e -2cf -5e -36f -13c -291 -123 -57 -245 -6f -3a4 -1f8 -2d7 -323 -1f3 -9f -27e -33b -62 -239 -22a -b4 -1e5 -142 -2c -194 -2bd -24e -304 -3d9 -117 -2c1 -393 -324 -261 -29c -3cf -2c0 -3ba -27 -348 -65 -d6 -379 -1f1 -3c6 -371 -26b -16b -49 -7d -121 -313 -379 -351 -4b -3de -23c -2e4 -355 -2a6 -12 -71 -145 -13d -206 -69 -340 -310 -3a8 -70 -175 -127 -2e6 -9 -77 -4f -377 -2c0 -297 -399 -2f8 -f2 -16b -2fa -214 -58 -3e0 -119 -3e0 -378 -32 -253 -3ae -6 -30d -3f8 -1bd -10a -241 -272 -351 -397 -b3 -21b -19d -218 -70 -91 -1a6 -10 -db -294 -dd -20c -a8 -310 -19a -50 -2df -2ab -359 -14 -3a4 -128 -157 -2b5 -98 -321 -2e1 -3e8 -358 -2f4 -1fd -2dd -155 -b -2f1 -396 -1ea -214 -2dc -f2 -3b -3fa -9a -2fd -197 -143 -126 -3cd -66 -214 -356 -2df -376 -1f0 -3b9 -2c4 -29e -251 -98 -34 -1ab -24c -304 -325 -141 -32f -10f -e5 -181 -3e -3f4 -13 -2ed -107 -3db -133 -2c5 -241 -18b -1e7 -367 -a2 -158 -b8 -3cf -27f -3d2 -46 -5e -a5 -bf -346 -eb -245 -3e0 -3bb -100 -29 -15d -e2 -1f5 -72 -3ff -d4 -397 -21 -228 -b5 -2a7 -af -2c -3d2 -3f7 -107 -17 -e6 -82 -2ce -2dd -5b -34 -2fc -1f3 -149 -f5 -250 -357 -cf -2b4 -392 -24d -29 -338 -c7 -2c4 -ac -1bb -24a -2a8 -39b -343 -396 -2fc -ca -6c -35a -142 -265 -262 -1bf -1f1 -33c -75 -332 -180 -1fc -1f9 -14f -2c9 -350 -1d4 -f9 -190 -2e7 -28a -164 -1ed -6b -37e -294 -2ba -296 -355 -203 -39e -55 -34 -19a -af -c5 -29a -19e -133 -326 -288 -240 -336 -384 -322 -189 -3a4 -16 -1a7 -35c -b9 -344 -194 -29b -2cc -341 -29b -180 -380 -91 -2fd -1dc -3a8 -d3 -27a -294 -2e3 -29f -20e -24f -b9 -210 -24a -35c -11b -156 -1c6 -db -2f9 -5e -8a -10b -235 -262 -283 -1b5 -2d3 -1a8 -2b2 -254 -45 -362 -1e9 -3e6 -e -6c -286 -14b -106 -396 -2b5 -335 -10a -3c -3b4 -205 -109 -130 -316 -31a -13b -1a1 -1f5 -109 -b6 diff --git a/src/test/tests/histogram/h b/src/test/tests/histogram/h deleted file mode 100644 index 69e7556d..00000000 --- a/src/test/tests/histogram/h +++ /dev/null @@ -1,1024 +0,0 @@ -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 diff --git a/src/test/tests/histogram/mkTB.bexe b/src/test/tests/histogram/mkTB.bexe deleted file mode 100644 index 1a8941db..00000000 --- a/src/test/tests/histogram/mkTB.bexe +++ /dev/null @@ -1,5576 +0,0 @@ -#! /usr/bin/vvp -:ivl_version "0.9.7 " "(v0_9_7)"; -:vpi_time_precision + 0; -:vpi_module "system"; -:vpi_module "v2005_math"; -:vpi_module "va_math"; -S_0x23eaf70 .scope module, "main" "main" 2 27; - .timescale 0 0; -v0x24d7940_0 .var "CLK", 0 0; -v0x24d7b30_0 .var "RST", 0 0; -v0x24d7bb0_0 .var "cycle", 31 0; -v0x24d7c50_0 .var "do_cycles", 0 0; -v0x24d7d00_0 .var "do_fsdb", 0 0; -v0x24d7da0_0 .var "do_fst", 0 0; -v0x24d7e40_0 .var "do_vcd", 0 0; -v0x24d7ee0_0 .var "filename", 2048 1; -S_0x239a640 .scope module, "top" "mkTB" 2 38, 3 27, S_0x23eaf70; - .timescale 0 0; -L_0x250fb60 .functor BUFZ 2, L_0x24cda00, C4<00>, C4<00>, C4<00>; -L_0x250fc60 .functor AND 1, L_0x24d80c0, L_0x250fbc0, C4<1>, C4<1>; -L_0x250fe00 .functor AND 1, L_0x24d80c0, L_0x250fd10, C4<1>, C4<1>; -L_0x25101b0 .functor AND 1, L_0x24d80c0, L_0x2510110, C4<1>, C4<1>; -v0x24d4b60_0 .net "CLK", 0 0, v0x24d7940_0; 1 drivers -v0x24d4be0_0 .net "RST_N", 0 0, v0x24d7b30_0; 1 drivers -v0x24d4c60_0 .net *"_s12", 31 0, C4<00000000000000000000000000000001>; 1 drivers -v0x24d4ce0_0 .net *"_s23", 0 0, L_0x2510110; 1 drivers -v0x24d4d90_0 .net *"_s3", 0 0, L_0x250fbc0; 1 drivers -v0x24d4e30_0 .net *"_s9", 0 0, L_0x250fd10; 1 drivers -v0x24d4ed0_0 .net "_unnamed_$EN__into_req", 0 0, L_0x25101b0; 1 drivers -v0x24d4f50_0 .net "_unnamed_$EN__into_resp", 0 0, C4<0>; 1 drivers -v0x24d5000_0 .net "_unnamed_$RDY__into_req", 0 0, L_0x24d80c0; 1 drivers -v0x24d50b0_0 .net "_unnamed_$_into_checkHandle", 0 0, L_0x24d8300; 1 drivers -v0x24d5160_0 .net "_unnamed_$_into_checkHandle_handle", 1 0, v0x24d74f0_0; 1 drivers -v0x24d7320_0 .net "_unnamed_$_into_req", 1 0, L_0x24cda00; 1 drivers -v0x24d7440_0 .net "_unnamed_$_into_req_counter", 9 0, C4<0000000000>; 1 drivers -v0x24d74f0_0 .var "reg_unused_0", 1 0; -v0x24d75f0_0 .net "reg_unused_0$D_IN", 1 0, L_0x250fb60; 1 drivers -v0x24d7670_0 .net "reg_unused_0$EN", 0 0, L_0x250fc60; 1 drivers -v0x24d7570_0 .var "started", 0 0; -v0x24d7780_0 .net "started$D_IN", 0 0, C4<1>; 1 drivers -v0x24d76f0_0 .net "started$EN", 0 0, L_0x250fe00; 1 drivers -v0x24d78a0_0 .var "timer", 31 0; -v0x24d7800_0 .net "timer$D_IN", 31 0, L_0x250ff30; 1 drivers -v0x24d79d0_0 .net "timer$EN", 0 0, C4<1>; 1 drivers -L_0x250fbc0 .reduce/nor v0x24d7570_0; -L_0x250fd10 .reduce/nor v0x24d7570_0; -L_0x250ff30 .arith/sum 32, v0x24d78a0_0, C4<00000000000000000000000000000001>; -L_0x2510110 .reduce/nor v0x24d7570_0; -S_0x23c0270 .scope module, "_unnamed_" "mkCircuit" 3 55, 4 37, S_0x239a640; - .timescale 0 0; -L_0x24cda00 .functor BUFZ 2, v0x24cdf20_0, C4<00>, C4<00>, C4<00>; -L_0x24d80c0 .functor AND 1, L_0x24d7ff0, L_0x24e04b0, C4<1>, C4<1>; -L_0x24d8300 .functor AND 1, L_0x24d8210, v0x24d0b40_0, C4<1>, C4<1>; -L_0x24e3420 .functor AND 1, L_0x24daf70, L_0x24d87f0, C4<1>, C4<1>; -L_0x24e3480 .functor AND 1, L_0x24e3420, L_0x24fee90, C4<1>, C4<1>; -L_0x24e3530 .functor OR 1, L_0x2500a60, L_0x24fe780, C4<0>, C4<0>; -L_0x24e35d0 .functor OR 1, L_0x24e3530, L_0x24fe230, C4<0>, C4<0>; -L_0x24e3680 .functor OR 1, L_0x24e35d0, L_0x24fdd30, C4<0>, C4<0>; -L_0x24e3780 .functor OR 1, L_0x24e3680, L_0x2506700, C4<0>, C4<0>; -L_0x24e3830 .functor AND 1, L_0x24e3480, L_0x24e3780, C4<1>, C4<1>; -L_0x24e3a30 .functor AND 1, v0x24c9540_0, L_0x24e3990, C4<1>, C4<1>; -L_0x24e3b30 .functor AND 1, L_0x24e3a30, L_0x24e3a90, C4<1>, C4<1>; -L_0x24e3930 .functor AND 1, v0x24c9f80_0, L_0x24e3c30, C4<1>, C4<1>; -L_0x24e3dc0 .functor AND 1, L_0x24e3930, L_0x24e3d20, C4<1>, C4<1>; -L_0x24e3fe0 .functor AND 1, v0x24caa10_0, L_0x24e3f40, C4<1>, C4<1>; -L_0x24e4180 .functor AND 1, L_0x24e3fe0, L_0x24e4090, C4<1>, C4<1>; -L_0x24e43b0 .functor AND 1, v0x24cb430_0, L_0x24e4310, C4<1>, C4<1>; -L_0x24e4560 .functor AND 1, L_0x24e43b0, L_0x24e4460, C4<1>, C4<1>; -L_0x24e4280 .functor AND 1, L_0x24d8e30, L_0x24d9e10, C4<1>, C4<1>; -L_0x24e47a0 .functor AND 1, L_0x24e4280, L_0x24e46b0, C4<1>, C4<1>; -L_0x24e4610 .functor AND 1, L_0x24e0510, L_0x24de340, C4<1>, C4<1>; -L_0x24e4950 .functor OR 1, L_0x250b500, L_0x24df440, C4<0>, C4<0>; -L_0x24e48a0 .functor AND 1, L_0x24e4610, L_0x24e4950, C4<1>, C4<1>; -L_0x24e4500 .functor OR 1, L_0x24e4ac0, L_0x24e04b0, C4<0>, C4<0>; -L_0x24e49b0 .functor AND 1, L_0x24e48a0, L_0x24e4500, C4<1>, C4<1>; -L_0x24e4e00 .functor OR 1, L_0x24e4d60, L_0x24dd240, C4<0>, C4<0>; -L_0x24e4c90 .functor AND 1, L_0x24e49b0, L_0x24e4e00, C4<1>, C4<1>; -L_0x24e4fe0 .functor AND 1, L_0x24e4c90, L_0x250b640, C4<1>, C4<1>; -L_0x24e5180 .functor OR 1, L_0x24e4eb0, L_0x24dc1e0, C4<0>, C4<0>; -L_0x24e5230 .functor AND 1, L_0x24de3a0, L_0x24e5180, C4<1>, C4<1>; -L_0x24e55a0 .functor OR 1, L_0x24e5470, L_0x24df4a0, C4<0>, C4<0>; -L_0x24e5600 .functor AND 1, L_0x24e5230, L_0x24e55a0, C4<1>, C4<1>; -L_0x24e52e0 .functor AND 1, L_0x24e5600, L_0x24e53e0, C4<1>, C4<1>; -L_0x24e58b0 .functor AND 1, L_0x24d9e70, L_0x24e5810, C4<1>, C4<1>; -L_0x24e5510 .functor AND 1, L_0x24e52e0, L_0x24e5ad0, C4<1>, C4<1>; -L_0x24e5a30 .functor AND 1, L_0x24e4fe0, L_0x24e5c10, C4<1>, C4<1>; -L_0x24e5910 .functor AND 1, L_0x24e4fe0, L_0x250b500, C4<1>, C4<1>; -L_0x24e6530 .functor AND 1, L_0x24e66b0, L_0x2506c80, C4<1>, C4<1>; -L_0x24e5e40 .functor OR 1, L_0x24f9fc0, L_0x24e6530, C4<0>, C4<0>; -L_0x24e5ef0 .functor AND 1, L_0x24e3830, L_0x24e5e40, C4<1>, C4<1>; -L_0x24e6bc0 .functor AND 1, L_0x24e47a0, L_0x24e6150, C4<1>, C4<1>; -L_0x24e6c70 .functor AND 1, L_0x24e6bc0, L_0x250a5e0, C4<1>, C4<1>; -L_0x24e67a0 .functor AND 1, L_0x24e6ab0, L_0x2506c80, C4<1>, C4<1>; -L_0x24e7070 .functor OR 1, L_0x24f91f0, L_0x24e67a0, C4<0>, C4<0>; -L_0x24e6d70 .functor AND 1, L_0x24e3830, L_0x24e7070, C4<1>, C4<1>; -L_0x24e7330 .functor AND 1, L_0x24e47a0, L_0x24e6e20, C4<1>, C4<1>; -L_0x24e7120 .functor AND 1, L_0x24e7330, L_0x250a5e0, C4<1>, C4<1>; -L_0x24e6f20 .functor AND 1, L_0x24e7560, L_0x2506c80, C4<1>, C4<1>; -L_0x24e73e0 .functor OR 1, L_0x24fab50, L_0x24e6f20, C4<0>, C4<0>; -L_0x24e7440 .functor AND 1, L_0x24e3830, L_0x24e73e0, C4<1>, C4<1>; -L_0x24e7a40 .functor AND 1, L_0x24e47a0, L_0x24e6890, C4<1>, C4<1>; -L_0x24e7b30 .functor AND 1, L_0x24e7a40, L_0x250a5e0, C4<1>, C4<1>; -L_0x24e7600 .functor AND 1, L_0x24e7750, L_0x2506c80, C4<1>, C4<1>; -L_0x24e7ef0 .functor OR 1, L_0x24faed0, L_0x24e7600, C4<0>, C4<0>; -L_0x24e7c20 .functor AND 1, L_0x24e3830, L_0x24e7ef0, C4<1>, C4<1>; -L_0x24e7980 .functor AND 1, L_0x24e47a0, L_0x24e7d10, C4<1>, C4<1>; -L_0x24e7f50 .functor AND 1, L_0x24e7980, L_0x250a5e0, C4<1>, C4<1>; -L_0x24e8000 .functor AND 1, L_0x24e3830, L_0x24f9fc0, C4<1>, C4<1>; -L_0x24e8450 .functor AND 1, L_0x24e3830, L_0x24f91f0, C4<1>, C4<1>; -L_0x24e8550 .functor AND 1, L_0x24e3830, L_0x24fab50, C4<1>, C4<1>; -L_0x24e74f0 .functor AND 1, L_0x24e3830, L_0x24faed0, C4<1>, C4<1>; -L_0x24e7e00 .functor AND 1, L_0x24e4fe0, L_0x250b500, C4<1>, C4<1>; -L_0x24e8710 .functor OR 1, L_0x24e7e00, L_0x25101b0, C4<0>, C4<0>; -L_0x24e8900 .functor AND 1, L_0x24dd2a0, L_0x24e8860, C4<1>, C4<1>; -L_0x24e89b0 .functor AND 1, L_0x24e8900, L_0x24d8d90, C4<1>, C4<1>; -L_0x24e8c80 .functor AND 1, L_0x24e89b0, L_0x24e8b00, C4<1>, C4<1>; -L_0x24e8f60 .functor AND 1, L_0x24dd2a0, L_0x24e8e70, C4<1>, C4<1>; -L_0x24e9050 .functor AND 1, L_0x24e8f60, L_0x24d8d90, C4<1>, C4<1>; -L_0x24e92d0 .functor AND 1, L_0x24e9050, L_0x24e9230, C4<1>, C4<1>; -L_0x24e9a10 .functor AND 1, L_0x24e9b90, L_0x24daf10, C4<1>, C4<1>; -L_0x24e9ac0 .functor AND 1, L_0x24e9a10, L_0x24fc2c0, C4<1>, C4<1>; -L_0x24e9c80 .functor AND 1, v0x24c6940_0, L_0x24ea050, C4<1>, C4<1>; -L_0x24e9f50 .functor AND 1, v0x24c71a0_0, L_0x24e9eb0, C4<1>, C4<1>; -L_0x24e9610 .functor AND 1, v0x24c9060_0, L_0x24e9570, C4<1>, C4<1>; -L_0x24ea360 .functor AND 1, v0x24c8200_0, L_0x24ea2c0, C4<1>, C4<1>; -L_0x24ea5f0 .functor BUFZ 2, v0x24c6e60_0, C4<00>, C4<00>, C4<00>; -L_0x24ea590 .functor BUFZ 2, v0x24c76f0_0, C4<00>, C4<00>, C4<00>; -L_0x24ea960 .functor BUFZ 2, v0x24c7ee0_0, C4<00>, C4<00>, C4<00>; -L_0x24eb580 .functor BUFZ 2, v0x24c8750_0, C4<00>, C4<00>, C4<00>; -L_0x24eb7a0 .functor AND 1, L_0x24e3830, L_0x24eb6b0, C4<1>, C4<1>; -L_0x24eb1f0 .functor AND 1, L_0x24eb7a0, L_0x2506c80, C4<1>, C4<1>; -L_0x24eaa90 .functor OR 1, L_0x24eb1f0, L_0x24e3b30, C4<0>, C4<0>; -L_0x24ebc20 .functor AND 1, L_0x24e3830, L_0x24ebb30, C4<1>, C4<1>; -L_0x24eacc0 .functor AND 1, L_0x24ebc20, L_0x2506c80, C4<1>, C4<1>; -L_0x24ebcd0 .functor OR 1, L_0x24eacc0, L_0x24e3dc0, C4<0>, C4<0>; -L_0x24ec0a0 .functor AND 1, L_0x24e3830, L_0x24ebfb0, C4<1>, C4<1>; -L_0x24eb8e0 .functor AND 1, L_0x24ec0a0, L_0x2506c80, C4<1>, C4<1>; -L_0x24eb990 .functor OR 1, L_0x24eb8e0, L_0x24e4180, C4<0>, C4<0>; -L_0x24ecbc0 .functor AND 1, L_0x24e3830, L_0x24ec720, C4<1>, C4<1>; -L_0x24ecc70 .functor AND 1, L_0x24ecbc0, L_0x2506c80, C4<1>, C4<1>; -L_0x24e7660 .functor OR 1, L_0x24ecc70, L_0x24e4560, C4<0>, C4<0>; -L_0x24ec9c0 .functor OR 1, L_0x24ec8d0, L_0x24e6c70, C4<0>, C4<0>; -L_0x24ec1e0 .functor AND 1, L_0x24ec9c0, L_0x24ecac0, C4<1>, C4<1>; -L_0x24ed060 .functor AND 1, L_0x24e5ef0, L_0x24ec2e0, C4<1>, C4<1>; -L_0x24ed240 .functor AND 1, L_0x24ed110, L_0x24e6c70, C4<1>, C4<1>; -L_0x24ed2d0 .functor OR 1, L_0x24ed060, L_0x24ed240, C4<0>, C4<0>; -L_0x24ed330 .functor BUFZ 2, L_0x2500f60, C4<00>, C4<00>, C4<00>; -L_0x24ec4b0 .functor BUFZ 2, L_0x2509120, C4<00>, C4<00>, C4<00>; -L_0x24ec590 .functor BUFZ 1, L_0x24e6c70, C4<0>, C4<0>, C4<0>; -L_0x24ece30 .functor OR 1, L_0x24ec5f0, L_0x24e7120, C4<0>, C4<0>; -L_0x24ed000 .functor AND 1, L_0x24ece30, L_0x24ecf30, C4<1>, C4<1>; -L_0x24ed830 .functor AND 1, L_0x24e6d70, L_0x24ed790, C4<1>, C4<1>; -L_0x24ec6c0 .functor AND 1, L_0x24edc20, L_0x24e7120, C4<1>, C4<1>; -L_0x24ede60 .functor OR 1, L_0x24ed830, L_0x24ec6c0, C4<0>, C4<0>; -L_0x24d73a0 .functor BUFZ 2, L_0x24ffdc0, C4<00>, C4<00>, C4<00>; -L_0x24edb60 .functor BUFZ 2, L_0x25091c0, C4<00>, C4<00>, C4<00>; -L_0x24ed3c0 .functor BUFZ 1, L_0x24e7120, C4<0>, C4<0>, C4<0>; -L_0x24ed510 .functor OR 1, L_0x24ed420, L_0x24e7b30, C4<0>, C4<0>; -L_0x24edfb0 .functor AND 1, L_0x24ed510, L_0x24edf10, C4<1>, C4<1>; -L_0x24ee3f0 .functor AND 1, L_0x24e7440, L_0x24ee0e0, C4<1>, C4<1>; -L_0x24ee5d0 .functor AND 1, L_0x24ee4a0, L_0x24e7b30, C4<1>, C4<1>; -L_0x24ee6c0 .functor OR 1, L_0x24ee3f0, L_0x24ee5d0, C4<0>, C4<0>; -L_0x24ee720 .functor BUFZ 2, L_0x25005a0, C4<00>, C4<00>, C4<00>; -L_0x24ee7b0 .functor BUFZ 2, L_0x2509b90, C4<00>, C4<00>, C4<00>; -L_0x24ee890 .functor BUFZ 1, L_0x24e7b30, C4<0>, C4<0>, C4<0>; -L_0x24eea10 .functor OR 1, L_0x24ee8f0, L_0x24e7f50, C4<0>, C4<0>; -L_0x24ee2a0 .functor AND 1, L_0x24eea10, L_0x24ee1d0, C4<1>, C4<1>; -L_0x24eee60 .functor AND 1, L_0x24e7c20, L_0x24eeb30, C4<1>, C4<1>; -L_0x24ef040 .functor AND 1, L_0x24eef10, L_0x24e7f50, C4<1>, C4<1>; -L_0x24ef0d0 .functor OR 1, L_0x24eee60, L_0x24ef040, C4<0>, C4<0>; -L_0x24ef130 .functor BUFZ 2, L_0x2501e50, C4<00>, C4<00>, C4<00>; -L_0x24ef420 .functor BUFZ 2, L_0x2509c80, C4<00>, C4<00>, C4<00>; -L_0x24ed8e0 .functor BUFZ 1, L_0x24e7f50, C4<0>, C4<0>, C4<0>; -L_0x24eebd0 .functor BUFZ 1, L_0x24e8c80, C4<0>, C4<0>, C4<0>; -L_0x24ef8d0 .functor BUFZ 14, L_0x24e8110, C4<00000000000000>, C4<00000000000000>, C4<00000000000000>; -L_0x24eed00 .functor BUFZ 3, L_0x24ff2c0, C4<000>, C4<000>, C4<000>; -L_0x24ef6e0 .functor AND 1, L_0x24e52e0, L_0x24ef5f0, C4<1>, C4<1>; -L_0x24ef790 .functor OR 1, L_0x24ef6e0, L_0x24e58b0, C4<0>, C4<0>; -L_0x24efed0 .functor BUFZ 1, L_0x25101b0, C4<0>, C4<0>, C4<0>; -L_0x24efb60 .functor AND 1, L_0x24e4fe0, L_0x24efac0, C4<1>, C4<1>; -L_0x24efe10 .functor OR 1, L_0x24efb60, L_0x25101b0, C4<0>, C4<0>; -L_0x24f04a0 .functor OR 1, L_0x24f0400, L_0x24e8c80, C4<0>, C4<0>; -L_0x24efc60 .functor AND 1, L_0x24f04a0, L_0x24f0530, C4<1>, C4<1>; -L_0x24f00f0 .functor AND 1, L_0x24e5910, L_0x24effc0, C4<1>, C4<1>; -L_0x24f0d60 .functor AND 1, L_0x24f01e0, L_0x24e8c80, C4<1>, C4<1>; -L_0x24f0df0 .functor OR 1, L_0x24f00f0, L_0x24f0d60, C4<0>, C4<0>; -L_0x24f0f30 .functor BUFZ 2, L_0x24ff670, C4<00>, C4<00>, C4<00>; -L_0x24f1020 .functor BUFZ 2, L_0x250e2d0, C4<00>, C4<00>, C4<00>; -L_0x24f1420 .functor BUFZ 1, L_0x24e5a30, C4<0>, C4<0>, C4<0>; -L_0x24e5cb0 .functor AND 1, L_0x24e4fe0, L_0x24f14b0, C4<1>, C4<1>; -L_0x24f16e0 .functor OR 1, L_0x24e5cb0, C4<0>, C4<0>, C4<0>; -L_0x24f17e0 .functor BUFZ 2, L_0x25086b0, C4<00>, C4<00>, C4<00>; -L_0x24f0700 .functor BUFZ 1, L_0x24e8c80, C4<0>, C4<0>, C4<0>; -L_0x24f0860 .functor AND 1, v0x24d28e0_0, L_0x24f0760, C4<1>, C4<1>; -L_0x24f1cf0 .functor AND 1, v0x24d30d0_0, L_0x24f1bf0, C4<1>, C4<1>; -L_0x24f0c00 .functor AND 1, v0x24d3900_0, L_0x24f0b00, C4<1>, C4<1>; -L_0x24f1e50 .functor AND 1, v0x24d40f0_0, L_0x24f1d50, C4<1>, C4<1>; -L_0x24f19c0 .functor BUFZ 2, v0x24d2dd0_0, C4<00>, C4<00>, C4<00>; -L_0x24f12d0 .functor BUFZ 2, v0x24d3600_0, C4<00>, C4<00>, C4<00>; -L_0x24f2b30 .functor BUFZ 2, v0x24d3df0_0, C4<00>, C4<00>, C4<00>; -L_0x24f2df0 .functor BUFZ 2, v0x24d45e0_0, C4<00>, C4<00>, C4<00>; -L_0x24f3980 .functor BUFZ 1, L_0x24e5ef0, C4<0>, C4<0>, C4<0>; -L_0x24f3c50 .functor BUFZ 1, L_0x24e6d70, C4<0>, C4<0>, C4<0>; -L_0x24f3eb0 .functor BUFZ 1, L_0x24e7440, C4<0>, C4<0>, C4<0>; -L_0x24f3310 .functor BUFZ 1, L_0x24e7c20, C4<0>, C4<0>, C4<0>; -L_0x24f4880 .functor BUFZ 1, L_0x24e3830, C4<0>, C4<0>, C4<0>; -L_0x24f48e0 .functor BUFZ 1, L_0x24e47a0, C4<0>, C4<0>, C4<0>; -L_0x24f3180 .functor BUFZ 1, L_0x24e47a0, C4<0>, C4<0>, C4<0>; -L_0x24f44b0 .functor BUFZ 1, L_0x24e58b0, C4<0>, C4<0>, C4<0>; -L_0x24f4720 .functor AND 1, L_0x24f4680, L_0x24daf10, C4<1>, C4<1>; -L_0x24f5030 .functor AND 1, L_0x24f4720, L_0x24fc2c0, C4<1>, C4<1>; -L_0x24f50e0 .functor BUFZ 1, L_0x24e3830, C4<0>, C4<0>, C4<0>; -L_0x24f4a60 .functor BUFZ 1, L_0x24e5510, C4<0>, C4<0>, C4<0>; -L_0x24f5690 .functor BUFZ 1, L_0x24e8c80, C4<0>, C4<0>, C4<0>; -L_0x24f56f0 .functor BUFZ 1, L_0x24e5510, C4<0>, C4<0>, C4<0>; -L_0x24f5400 .functor BUFZ 1, L_0x24e5910, C4<0>, C4<0>, C4<0>; -L_0x24f5460 .functor BUFZ 1, L_0x24e8c80, C4<0>, C4<0>, C4<0>; -L_0x24f60b0 .functor BUFZ 1, L_0x24e4fe0, C4<0>, C4<0>, C4<0>; -L_0x24f6110 .functor BUFZ 1, L_0x24e52e0, C4<0>, C4<0>, C4<0>; -L_0x24f4450 .functor BUFZ 1, L_0x24e5a30, C4<0>, C4<0>, C4<0>; -L_0x24f5880 .functor AND 1, L_0x24e52e0, L_0x24f57e0, C4<1>, C4<1>; -L_0x24f5970 .functor BUFZ 12, L_0x24e8310, C4<000000000000>, C4<000000000000>, C4<000000000000>; -L_0x24f5a70 .functor AND 1, L_0x24e04b0, L_0x24e8710, C4<1>, C4<1>; -L_0x24f5b20 .functor BUFZ 1, L_0x24e4fe0, C4<0>, C4<0>, C4<0>; -L_0x24f6910 .functor BUFZ 1, L_0x24e5910, C4<0>, C4<0>, C4<0>; -L_0x24f6b70 .functor BUFZ 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x24f6ed0 .functor BUFZ 1, L_0x24e47a0, C4<0>, C4<0>, C4<0>; -L_0x24f8810 .functor OR 1, L_0x24f8320, L_0x24f7e40, C4<0>, C4<0>; -L_0x24f7c90 .functor AND 1, L_0x24f8810, L_0x24f7f80, C4<1>, C4<1>; -L_0x24f7d90 .functor AND 1, L_0x24f7c90, L_0x2502480, C4<1>, C4<1>; -L_0x24f8550 .functor OR 1, L_0x24f8d70, L_0x24f8e60, C4<0>, C4<0>; -L_0x24f86f0 .functor AND 1, L_0x24f8550, L_0x24f8600, C4<1>, C4<1>; -L_0x24f7880 .functor AND 1, L_0x24f86f0, L_0x24fe230, C4<1>, C4<1>; -L_0x24f89f0 .functor OR 1, L_0x24f7b60, L_0x24f8950, C4<0>, C4<0>; -L_0x24f8b90 .functor AND 1, L_0x24f89f0, L_0x24f8af0, C4<1>, C4<1>; -L_0x24f8c90 .functor AND 1, L_0x24f8b90, L_0x24fe4b0, C4<1>, C4<1>; -L_0x24f9e60 .functor AND 1, L_0x24f9d70, L_0x2500a60, C4<1>, C4<1>; -L_0x24f9f60 .functor OR 1, L_0x24f9e60, L_0x25097f0, C4<0>, C4<0>; -L_0x24f9fc0 .functor AND 1, L_0x24f9c80, L_0x24f9f60, C4<1>, C4<1>; -L_0x24f9040 .functor AND 1, L_0x24f8fa0, L_0x2500a60, C4<1>, C4<1>; -L_0x24f90f0 .functor OR 1, L_0x24f9040, L_0x25097f0, C4<0>, C4<0>; -L_0x24f91f0 .functor AND 1, L_0x24fa790, L_0x24f90f0, C4<1>, C4<1>; -L_0x24faa00 .functor AND 1, L_0x24fa8d0, L_0x2500a60, C4<1>, C4<1>; -L_0x24faaf0 .functor OR 1, L_0x24faa00, L_0x25097f0, C4<0>, C4<0>; -L_0x24fab50 .functor AND 1, L_0x24f9330, L_0x24faaf0, C4<1>, C4<1>; -L_0x24facf0 .functor AND 1, L_0x24f9990, L_0x2500a60, C4<1>, C4<1>; -L_0x24fa730 .functor OR 1, L_0x24facf0, L_0x25097f0, C4<0>, C4<0>; -L_0x24faed0 .functor AND 1, L_0x24fac50, L_0x24fa730, C4<1>, C4<1>; -L_0x24fa6a0 .functor OR 1, L_0x24fa5b0, L_0x24fb6b0, C4<0>, C4<0>; -L_0x24fb7f0 .functor AND 1, L_0x24fa6a0, L_0x24f94f0, C4<1>, C4<1>; -L_0x24f9680 .functor AND 1, L_0x24fb7f0, L_0x250acf0, C4<1>, C4<1>; -L_0x24fb540 .functor AND 1, L_0x24f97d0, L_0x24fa2b0, C4<1>, C4<1>; -L_0x24fa440 .functor OR 1, L_0x24fb540, L_0x2508e60, C4<0>, C4<0>; -L_0x24fc9a0 .functor OR 1, L_0x24fb010, L_0x24fb0b0, C4<0>, C4<0>; -L_0x24fb3d0 .functor OR 1, L_0x24fc9a0, L_0x24fb2e0, C4<0>, C4<0>; -L_0x24fba80 .functor OR 1, L_0x24fb3d0, L_0x24fb990, C4<0>, C4<0>; -L_0x24fc730 .functor AND 1, L_0x24fc3c0, L_0x24fc5f0, C4<1>, C4<1>; -L_0x24fbcc0 .functor OR 1, L_0x24fc730, L_0x250bf80, C4<0>, C4<0>; -L_0x24acc30 .functor OR 1, L_0x24fd0b0, L_0x24fd240, C4<0>, C4<0>; -L_0x24fd560 .functor OR 1, L_0x24acc30, L_0x24fd470, C4<0>, C4<0>; -L_0x24fc080 .functor OR 1, L_0x24fd560, L_0x24fbf90, C4<0>, C4<0>; -L_0x24fc2c0 .functor AND 1, L_0x24fbb80, L_0x24fc180, C4<1>, C4<1>; -L_0x24fd6f0 .functor AND 1, L_0x24fe0f0, L_0x24fd650, C4<1>, C4<1>; -L_0x24fd980 .functor AND 1, L_0x24fd6f0, L_0x24fd890, C4<1>, C4<1>; -L_0x24b3420 .functor AND 1, L_0x24fda80, L_0x24fe830, C4<1>, C4<1>; -L_0x24fcec0 .functor AND 1, L_0x24fce20, L_0x2500a60, C4<1>, C4<1>; -L_0x24f6da0 .functor OR 1, L_0x24fcec0, L_0x25097f0, C4<0>, C4<0>; -L_0x24ff020 .functor AND 1, L_0x24fef80, L_0x2500a60, C4<1>, C4<1>; -L_0x24ff0d0 .functor OR 1, L_0x24ff020, L_0x25097f0, C4<0>, C4<0>; -L_0x2500c10 .functor AND 1, C4<1>, C4<1>, C4<1>, C4<1>; -L_0x24ffac0 .functor AND 1, C4<1>, C4<1>, C4<1>, C4<1>; -L_0x24fff50 .functor AND 1, C4<1>, C4<1>, C4<1>, C4<1>; -L_0x2500730 .functor AND 1, C4<1>, C4<1>, C4<1>, C4<1>; -L_0x2501fe0 .functor AND 1, C4<1>, C4<1>, C4<1>, C4<1>; -L_0x24ff440 .functor AND 1, C4<1>, C4<1>, C4<1>, C4<1>; -L_0x24f0150 .functor AND 1, C4<1>, C4<1>, C4<1>, C4<1>; -L_0x2503270 .functor OR 1, L_0x25030e0, L_0x2503180, C4<0>, C4<0>; -L_0x2501b90 .functor OR 1, L_0x2501a00, L_0x2501aa0, C4<0>, C4<0>; -L_0x2501c90 .functor AND 1, L_0x2503270, L_0x2501b90, C4<1>, C4<1>; -L_0x25010b0 .functor AND 1, L_0x2501c90, L_0x2501010, C4<1>, C4<1>; -L_0x25011b0 .functor AND 1, L_0x25010b0, L_0x25089f0, C4<1>, C4<1>; -L_0x2501520 .functor OR 1, L_0x2501390, L_0x2501430, C4<0>, C4<0>; -L_0x25016c0 .functor OR 1, L_0x25027a0, L_0x2502890, C4<0>, C4<0>; -L_0x25029d0 .functor AND 1, L_0x2501520, L_0x25016c0, C4<1>, C4<1>; -L_0x2502d00 .functor OR 1, L_0x2502b70, L_0x2502c60, C4<0>, C4<0>; -L_0x2502e00 .functor AND 1, L_0x25029d0, L_0x2502d00, C4<1>, C4<1>; -L_0x2503d90 .functor OR 1, L_0x2503c00, L_0x2503cf0, C4<0>, C4<0>; -L_0x2504980 .functor OR 1, L_0x2503ff0, L_0x25040e0, C4<0>, C4<0>; -L_0x25032e0 .functor AND 1, L_0x2503d90, L_0x2504980, C4<1>, C4<1>; -L_0x2503480 .functor AND 1, L_0x25032e0, L_0x25033e0, C4<1>, C4<1>; -L_0x2503580 .functor AND 1, L_0x2503480, L_0x24fe780, C4<1>, C4<1>; -L_0x2503860 .functor OR 1, L_0x25036d0, L_0x25037c0, C4<0>, C4<0>; -L_0x2504b70 .functor OR 1, L_0x2504a30, L_0x2504ad0, C4<0>, C4<0>; -L_0x2504c20 .functor AND 1, L_0x2503860, L_0x2504b70, C4<1>, C4<1>; -L_0x2504dc0 .functor AND 1, L_0x2504c20, L_0x2504d20, C4<1>, C4<1>; -L_0x2504ec0 .functor AND 1, L_0x2504dc0, L_0x24fcd30, C4<1>, C4<1>; -L_0x2504450 .functor OR 1, L_0x2504230, L_0x2504320, C4<0>, C4<0>; -L_0x2504730 .functor OR 1, L_0x25045a0, L_0x2504690, C4<0>, C4<0>; -L_0x2504830 .functor AND 1, L_0x2504450, L_0x2504730, C4<1>, C4<1>; -L_0x25059c0 .functor OR 1, L_0x2505830, L_0x2505920, C4<0>, C4<0>; -L_0x2505ac0 .functor AND 1, L_0x2504830, L_0x25059c0, C4<1>, C4<1>; -L_0x2505f00 .functor OR 1, L_0x2505d70, L_0x2505e60, C4<0>, C4<0>; -L_0x25051f0 .functor OR 1, L_0x2505060, L_0x2505150, C4<0>, C4<0>; -L_0x25052a0 .functor AND 1, L_0x2505f00, L_0x25051f0, C4<1>, C4<1>; -L_0x2505660 .functor OR 1, L_0x2505440, L_0x2505530, C4<0>, C4<0>; -L_0x24b7a00 .functor AND 1, L_0x25052a0, L_0x2505660, C4<1>, C4<1>; -L_0x25061e0 .functor OR 1, L_0x2507100, L_0x25060f0, C4<0>, C4<0>; -L_0x2506470 .functor OR 1, L_0x25061e0, L_0x2506380, C4<0>, C4<0>; -L_0x2506700 .functor OR 1, L_0x2506470, L_0x2506610, C4<0>, C4<0>; -L_0x2506a80 .functor OR 1, L_0x25068f0, L_0x25069e0, C4<0>, C4<0>; -L_0x2506b80 .functor AND 1, L_0x2506a80, L_0x2505ac0, C4<1>, C4<1>; -L_0x2506c80 .functor AND 1, L_0x2506b80, L_0x2506700, C4<1>, C4<1>; -L_0x2506ff0 .functor OR 1, L_0x2506e60, L_0x2506f00, C4<0>, C4<0>; -L_0x2507d40 .functor OR 1, L_0x2507bb0, L_0x2507c50, C4<0>, C4<0>; -L_0x2507e40 .functor AND 1, L_0x2506ff0, L_0x2507d40, C4<1>, C4<1>; -L_0x2507fe0 .functor AND 1, L_0x2507e40, L_0x2507f40, C4<1>, C4<1>; -L_0x25071a0 .functor AND 1, L_0x2507fe0, L_0x250b9c0, C4<1>, C4<1>; -L_0x2507510 .functor OR 1, L_0x2507380, L_0x2507420, C4<0>, C4<0>; -L_0x2507840 .functor OR 1, L_0x25076b0, L_0x25077a0, C4<0>, C4<0>; -L_0x2507940 .functor AND 1, L_0x2507510, L_0x2507840, C4<1>, C4<1>; -L_0x2508180 .functor OR 1, L_0x2509310, L_0x25080e0, C4<0>, C4<0>; -L_0x2508280 .functor AND 1, L_0x2507940, L_0x2508180, C4<1>, C4<1>; -L_0x2502740 .functor AND 1, L_0x2508b30, L_0x25089f0, C4<1>, C4<1>; -L_0x2508d50 .functor AND 1, L_0x2508cb0, L_0x2502480, C4<1>, C4<1>; -L_0x2508380 .functor OR 1, L_0x2502740, L_0x2508d50, C4<0>, C4<0>; -L_0x2508db0 .functor AND 1, L_0x250b6f0, L_0x25021c0, C4<1>, C4<1>; -L_0x2508e60 .functor OR 1, L_0x2508380, L_0x2508db0, C4<0>, C4<0>; -L_0x2509050 .functor AND 1, L_0x2508fb0, L_0x24fe780, C4<1>, C4<1>; -L_0x25094f0 .functor AND 1, L_0x2509450, L_0x24fe230, C4<1>, C4<1>; -L_0x25095a0 .functor OR 1, L_0x2509050, L_0x25094f0, C4<0>, C4<0>; -L_0x2509740 .functor AND 1, L_0x25096a0, L_0x24fdd30, C4<1>, C4<1>; -L_0x25097f0 .functor OR 1, L_0x25095a0, L_0x2509740, C4<0>, C4<0>; -L_0x2509990 .functor AND 1, L_0x25098f0, L_0x24fcd30, C4<1>, C4<1>; -L_0x2509e10 .functor AND 1, L_0x2509ad0, L_0x24fe4b0, C4<1>, C4<1>; -L_0x2509e70 .functor OR 1, L_0x2509990, L_0x2509e10, C4<0>, C4<0>; -L_0x250a010 .functor AND 1, L_0x2509f70, L_0x24fdf60, C4<1>, C4<1>; -L_0x250a0c0 .functor OR 1, L_0x2509e70, L_0x250a010, C4<0>, C4<0>; -L_0x250a4e0 .functor AND 1, L_0x250a1c0, L_0x250a3a0, C4<1>, C4<1>; -L_0x250a5e0 .functor OR 1, L_0x250a4e0, L_0x250a0c0, C4<0>, C4<0>; -L_0x250b230 .functor AND 1, L_0x250b0a0, L_0x250b190, C4<1>, C4<1>; -L_0x24e53e0 .functor OR 1, L_0x250ae50, L_0x250b230, C4<0>, C4<0>; -L_0x250b640 .functor OR 1, L_0x250b500, L_0x250c8d0, C4<0>, C4<0>; -L_0x250bba0 .functor AND 1, L_0x250bb00, L_0x250b9c0, C4<1>, C4<1>; -L_0x250bd80 .functor AND 1, L_0x250bce0, L_0x250acf0, C4<1>, C4<1>; -L_0x250ad90 .functor OR 1, L_0x250bba0, L_0x250bd80, C4<0>, C4<0>; -L_0x250bed0 .functor AND 1, L_0x250be30, L_0x250aa30, C4<1>, C4<1>; -L_0x250bf80 .functor OR 1, L_0x250ad90, L_0x250bed0, C4<0>, C4<0>; -L_0x250d4a0 .functor AND 1, L_0x2502e00, L_0x250d400, C4<1>, C4<1>; -L_0x250da30 .functor AND 1, L_0x250d4a0, L_0x250d8f0, C4<1>, C4<1>; -L_0x250c250 .functor AND 1, L_0x2508280, L_0x250c1b0, C4<1>, C4<1>; -L_0x250c5d0 .functor AND 1, L_0x250c250, L_0x250c490, C4<1>, C4<1>; -L_0x250ef00 .functor AND 1, L_0x2505ac0, L_0x250ee60, C4<1>, C4<1>; -L_0x250efb0 .functor AND 1, L_0x250ef00, L_0x2500a60, C4<1>, C4<1>; -L_0x250cc40 .functor AND 1, L_0x250cb00, L_0x250cba0, C4<1>, C4<1>; -L_0x250cde0 .functor AND 1, L_0x250cc40, L_0x250cd40, C4<1>, C4<1>; -L_0x250d070 .functor AND 1, L_0x250cde0, L_0x250cf80, C4<1>, C4<1>; -L_0x2510680 .functor AND 1, L_0x24b7a00, L_0x25105e0, C4<1>, C4<1>; -L_0x250de80 .functor AND 1, L_0x2510680, L_0x250dd40, C4<1>, C4<1>; -L_0x2510330 .functor BUFZ 3, L_0x24ff2c0, C4<000>, C4<000>, C4<000>; -L_0x2510390 .functor BUFZ 2, v0x24c6e60_0, C4<00>, C4<00>, C4<00>; -L_0x250f360 .functor BUFZ 2, v0x24c76f0_0, C4<00>, C4<00>, C4<00>; -L_0x250f460 .functor BUFZ 2, v0x24c7ee0_0, C4<00>, C4<00>, C4<00>; -L_0x250f560 .functor BUFZ 2, v0x24c8750_0, C4<00>, C4<00>, C4<00>; -L_0x250f660 .functor BUFZ 2, L_0x2500f60, C4<00>, C4<00>, C4<00>; -L_0x250f710 .functor BUFZ 2, L_0x24ffdc0, C4<00>, C4<00>, C4<00>; -L_0x250f7c0 .functor BUFZ 2, L_0x25005a0, C4<00>, C4<00>, C4<00>; -L_0x250f870 .functor BUFZ 2, L_0x2501e50, C4<00>, C4<00>, C4<00>; -L_0x250f920 .functor BUFZ 2, L_0x24ff670, C4<00>, C4<00>, C4<00>; -L_0x250f9d0 .functor BUFZ 2, v0x24d2dd0_0, C4<00>, C4<00>, C4<00>; -L_0x250dfd0 .functor BUFZ 2, v0x24d3600_0, C4<00>, C4<00>, C4<00>; -L_0x250e0d0 .functor BUFZ 2, v0x24d3df0_0, C4<00>, C4<00>, C4<00>; -L_0x250e1d0 .functor BUFZ 2, v0x24d45e0_0, C4<00>, C4<00>, C4<00>; -L_0x250e2d0 .functor BUFZ 2, v0x24d09c0_0, C4<00>, C4<00>, C4<00>; -L_0x250e3d0 .functor BUFZ 2, L_0x250e2d0, C4<00>, C4<00>, C4<00>; -v0x24ac5b0_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x24ac630_0 .alias "EN__into_req", 0 0, v0x24d4ed0_0; -v0x24ac6b0_0 .alias "EN__into_resp", 0 0, v0x24d4f50_0; -v0x24ac750_0 .net "IF_NOT_f_l_entryVec_0_read__6_BIT_10_7_72_OR_N_ETC___d380", 1 0, L_0x24f80b0; 1 drivers -v0x24ac800_0 .net "IF_NOT_h_l_entryVec_0_read__11_BIT_10_12_67_OR_ETC___d475", 1 0, L_0x24f7980; 1 drivers -v0x24ac8a0_0 .net "IF_NOT_h_l_entryVec_0_read__11_BIT_10_12_67_OR_ETC___d587", 1 0, L_0x24f9ab0; 1 drivers -v0x24ac980_0 .net "IF_NOT_h_l_entryVec_2_read__25_BIT_10_26_61_OR_ETC___d491", 0 0, L_0x24f9fc0; 1 drivers -v0x24aca20_0 .net "IF_NOT_h_l_entryVec_2_read__25_BIT_10_26_61_OR_ETC___d493", 0 0, L_0x24f91f0; 1 drivers -v0x24acb10_0 .net "IF_NOT_h_l_entryVec_2_read__25_BIT_10_26_61_OR_ETC___d495", 0 0, L_0x24fab50; 1 drivers -v0x24acbb0_0 .net "IF_NOT_h_l_entryVec_2_read__25_BIT_10_26_61_OR_ETC___d497", 0 0, L_0x24faed0; 1 drivers -v0x24accb0_0 .net "IF_NOT_w_l_entryVec_0_read__99_BIT_10_00_11_OR_ETC___d419", 1 0, L_0x24f9730; 1 drivers -v0x24acd50_0 .net "IF_f_l_entryVec_3_read__08_BIT_10_09_AND_f_l_e_ETC___d428", 0 0, L_0x24fc2c0; 1 drivers -v0x24ace60_0 .net "IF_h_l_entryVec_0_read__11_BIT_10_12_THEN_h_l__ETC___d455", 0 0, L_0x24fdd30; 1 drivers -v0x24acf00_0 .net "IF_h_l_entryVec_0_read__11_BIT_10_12_THEN_h_l__ETC___d559", 0 0, L_0x24fdf60; 1 drivers -v0x24ad020_0 .net "IF_h_l_entryVec_1_read__18_BIT_10_19_AND_h_l_e_ETC___d520", 1 0, L_0x24fea60; 1 drivers -v0x24ad0c0_0 .net "IF_h_l_entryVec_1_read__18_BIT_10_19_THEN_h_l__ETC___d451", 0 0, L_0x24fe230; 1 drivers -v0x24acf80_0 .net "IF_h_l_entryVec_1_read__18_BIT_10_19_THEN_h_l__ETC___d557", 0 0, L_0x24fe4b0; 1 drivers -v0x24ad210_0 .net "IF_h_l_entryVec_2_read__25_BIT_10_26_THEN_h_l__ETC___d447", 0 0, L_0x24fe780; 1 drivers -v0x24ad330_0 .net "IF_h_l_entryVec_2_read__25_BIT_10_26_THEN_h_l__ETC___d555", 0 0, L_0x24fcd30; 1 drivers -v0x24ad3b0_0 .net "IF_h_l_entryVec_3_read__32_BIT_10_33_AND_IF_h__ETC___d483", 0 0, L_0x24fee90; 1 drivers -v0x24ad290_0 .net "IF_h_l_entryVec_3_read__32_BIT_10_33_AND_IF_h__ETC___d543", 1 0, L_0x24ff980; 1 drivers -v0x24ad4e0_0 .net "IF_h_l_entryVec_3_read__32_BIT_10_33_THEN_h_l__ETC___d443", 0 0, L_0x2500a60; 1 drivers -v0x24ad430_0 .net "IF_h_l_lockVec_0_nextId_dummy2_0_read__98_AND__ETC___d500", 1 0, L_0x2500c70; 1 drivers -v0x24ad620_0 .net "IF_h_l_lockVec_0_nextId_dummy2_0_read__98_AND__ETC___d501", 1 0, L_0x2500db0; 1 drivers -v0x24ad580_0 .net "IF_h_l_lockVec_0_nextId_lat_0_whas__28_THEN_h__ETC___d231", 1 0, L_0x2500f60; 1 drivers -v0x24ad770_0 .net "IF_h_l_lockVec_1_nextId_dummy2_0_read__02_AND__ETC___d504", 1 0, L_0x24ffb20; 1 drivers -v0x24ad6c0_0 .net "IF_h_l_lockVec_1_nextId_dummy2_0_read__02_AND__ETC___d505", 1 0, L_0x24ffc60; 1 drivers -v0x24ad8d0_0 .net "IF_h_l_lockVec_1_nextId_lat_0_whas__49_THEN_h__ETC___d252", 1 0, L_0x24ffdc0; 1 drivers -v0x24ad810_0 .net "IF_h_l_lockVec_2_nextId_dummy2_0_read__06_AND__ETC___d508", 1 0, L_0x24fffb0; 1 drivers -v0x24ada40_0 .net "IF_h_l_lockVec_2_nextId_dummy2_0_read__06_AND__ETC___d509", 1 0, L_0x25003f0; 1 drivers -v0x24ad950_0 .net "IF_h_l_lockVec_2_nextId_lat_0_whas__70_THEN_h__ETC___d273", 1 0, L_0x25005a0; 1 drivers -v0x24adbc0_0 .net "IF_h_l_lockVec_3_nextId_dummy2_0_read__10_AND__ETC___d512", 1 0, L_0x25007d0; 1 drivers -v0x24adac0_0 .net "IF_h_l_lockVec_3_nextId_dummy2_0_read__10_AND__ETC___d513", 1 0, L_0x2500950; 1 drivers -v0x24add50_0 .net "IF_h_l_lockVec_3_nextId_lat_0_whas__91_THEN_h__ETC___d294", 1 0, L_0x2501e50; 1 drivers -v0x24adc40_0 .net "IF_hg_outputQueue_nextTag_dummy2_0_read__86_AN_ETC___d688", 2 0, L_0x24ff180; 1 drivers -v0x24adef0_0 .net "IF_hg_outputQueue_nextTag_lat_0_whas__40_THEN__ETC___d343", 2 0, L_0x24ff2c0; 1 drivers -v0x24addd0_0 .net "IF_o_nextId_dummy2_0_read__67_AND_o_nextId_dum_ETC___d669", 1 0, L_0x24ff4e0; 1 drivers -v0x24ade70_0 .net "IF_o_nextId_lat_0_whas__19_THEN_o_nextId_lat_0_ETC___d622", 1 0, L_0x24ff670; 1 drivers -v0x24ae0b0_0 .net "IF_o_outputQueue_nextTag_dummy2_0_read__25_AND_ETC___d727", 1 0, L_0x24ff7a0; 1 drivers -v0x24ae130_0 .net "IF_o_outputQueue_nextTag_lat_0_whas__40_THEN_o_ETC___d643", 1 0, L_0x250e2d0; 1 drivers -v0x24adf70_0 .net "MUX_h_l_entryVec_0$write_1__VAL_2", 10 0, L_0x24e5f70; 1 drivers -v0x24ae010_0 .net "MUX_hg_outputQueue_val$write_1__SEL_2", 0 0, L_0x24e5510; 1 drivers -v0x24ae310_0 .net "MUX_o_busyReg$write_1__SEL_1", 0 0, L_0x24e5a30; 1 drivers -v0x24ae390_0 .net "MUX_o_fifo__input__TO_Start_enq_data$wset_1__SEL_1", 0 0, L_0x24e5910; 1 drivers -v0x24ae1b0_0 .net "MUX_o_fifo__input__TO_Start_enq_data$wset_1__VAL_1", 11 0, L_0x24e6440; 1 drivers -v0x24ae250_0 .net "MUX_o_fifo__input__TO_Start_enq_data$wset_1__VAL_2", 11 0, L_0x24e62e0; 1 drivers -v0x24ae590_0 .net "NOT_f_l_entryVec_1_read__4_BIT_10_5_69_OR_NOT__ETC___d378", 0 0, L_0x25011b0; 1 drivers -v0x24ae610_0 .net "NOT_f_l_entryVec_2_read__01_BIT_10_02_66_OR_NO_ETC___d376", 0 0, L_0x2502e00; 1 drivers -v0x24ae430_0 .net "NOT_h_l_entryVec_1_read__18_BIT_10_19_64_OR_NO_ETC___d473", 0 0, L_0x2503580; 1 drivers -v0x24ae4d0_0 .net "NOT_h_l_entryVec_1_read__18_BIT_10_19_64_OR_NO_ETC___d585", 0 0, L_0x2504ec0; 1 drivers -v0x24ae830_0 .net "NOT_h_l_entryVec_2_read__25_BIT_10_26_61_OR_NO_ETC___d471", 0 0, L_0x2505ac0; 1 drivers -v0x24ae8b0_0 .net "NOT_h_l_entryVec_2_read__25_BIT_10_26_61_OR_NO_ETC___d583", 0 0, L_0x24b7a00; 1 drivers -v0x24ae6b0_0 .net "NOT_h_l_entryVec_3_read__32_BIT_10_33_79_OR_NO_ETC___d482", 0 0, L_0x2506700; 1 drivers -v0x24ae750_0 .net "NOT_h_l_entryVec_3_read__32_BIT_10_33_79_OR_NO_ETC___d526", 0 0, L_0x2506c80; 1 drivers -v0x24aeaf0_0 .net "NOT_w_l_entryVec_1_read__06_BIT_10_07_08_OR_NO_ETC___d417", 0 0, L_0x25071a0; 1 drivers -v0x24aeb70_0 .net "NOT_w_l_entryVec_2_read__13_BIT_10_14_05_OR_NO_ETC___d415", 0 0, L_0x2508280; 1 drivers -v0x24ae930_0 .net "RDY__into_checkHandle", 0 0, C4<1>; 1 drivers -v0x24ae9d0_0 .alias "RDY__into_req", 0 0, v0x24d5000_0; -v0x24aea70_0 .net "RDY__into_resp", 0 0, C4<1>; 1 drivers -v0x24aedf0_0 .alias "RST_N", 0 0, v0x24d4be0_0; -v0x23b1d10_0 .var "SEL_ARR_IF_h_l_lockVec_0_nextId_dummy2_0_read__ETC___d540", 1 0; -v0x24aed20_0 .var "SEL_ARR_IF_h_l_lockVec_0_nextId_dummy2_0_read__ETC___d541", 1 0; -v0x24af070_0 .var "SEL_ARR_f_l_lockVec_0_empty_5_f_l_lockVec_1_em_ETC___d383", 0 0; -v0x24af110_0 .var "SEL_ARR_h_l_lockVec_0_empty_10_h_l_lockVec_1_e_ETC___d478", 0 0; -v0x24aee90_0 .var "SEL_ARR_h_l_lockVec_0_owner_64_EQ_IF_hg_fifo_S_ETC___d590", 0 0; -v0x24aef30_0 .var "SEL_ARR_w_l_lockVec_0_empty_98_w_l_lockVec_1_e_ETC___d422", 0 0; -v0x24aefd0_0 .net "WILL_FIRE_RL_h_l_freelock", 0 0, L_0x24e3b30; 1 drivers -v0x24af3b0_0 .net "WILL_FIRE_RL_h_l_freelock_1", 0 0, L_0x24e3dc0; 1 drivers -v0x24af1b0_0 .net "WILL_FIRE_RL_h_l_freelock_2", 0 0, L_0x24e4180; 1 drivers -v0x24af250_0 .net "WILL_FIRE_RL_h_l_freelock_3", 0 0, L_0x24e4560; 1 drivers -v0x24af2f0_0 .net "WILL_FIRE_RL_hg_s_Stage__0_execute", 0 0, L_0x24e3830; 1 drivers -v0x24af670_0 .net "WILL_FIRE_RL_hg_s_Stage__1_execute", 0 0, L_0x24e47a0; 1 drivers -v0x24af430_0 .net "WILL_FIRE_RL_hg_s_Stage__2_execute", 0 0, L_0x24e58b0; 1 drivers -v0x24af4d0_0 .net "WILL_FIRE_RL_o_s_Stage__3_execute", 0 0, L_0x24e52e0; 1 drivers -v0x24af570_0 .net "WILL_FIRE_RL_o_s_Start_execute", 0 0, L_0x24e4fe0; 1 drivers -v0x24af950_0 .alias "_into_checkHandle", 0 0, v0x24d50b0_0; -v0x24af6f0_0 .alias "_into_checkHandle_handle", 1 0, v0x24d5160_0; -v0x24af790_0 .alias "_into_req", 1 0, v0x24d7320_0; -v0x24af830_0 .alias "_into_req_counter", 9 0, v0x24d7440_0; -v0x24af8d0_0 .net *"_s1001", 0 0, L_0x24f8320; 1 drivers -v0x24afc60_0 .net *"_s1003", 0 0, L_0x24f7e40; 1 drivers -v0x24afce0_0 .net *"_s1004", 0 0, L_0x24f8810; 1 drivers -v0x24af9f0_0 .net *"_s1007", 0 0, L_0x24f7f80; 1 drivers -v0x24afa90_0 .net *"_s1008", 0 0, L_0x24f7c90; 1 drivers -v0x24afb30_0 .net *"_s1010", 0 0, L_0x24f7d90; 1 drivers -v0x24afbd0_0 .net *"_s1012", 1 0, C4<01>; 1 drivers -v0x24b0040_0 .net *"_s1014", 1 0, C4<00>; 1 drivers -v0x24b00e0_0 .net *"_s1019", 0 0, L_0x24f8460; 1 drivers -v0x24afd80_0 .net *"_s1021", 0 0, L_0x24f8d70; 1 drivers -v0x24afe20_0 .net *"_s1023", 0 0, L_0x24f8e60; 1 drivers -v0x24afec0_0 .net *"_s1024", 0 0, L_0x24f8550; 1 drivers -v0x24aff60_0 .net *"_s1027", 0 0, L_0x24f8600; 1 drivers -v0x24b0450_0 .net *"_s1028", 0 0, L_0x24f86f0; 1 drivers -v0x24b04d0_0 .net *"_s1030", 0 0, L_0x24f7880; 1 drivers -v0x24b0180_0 .net *"_s1032", 1 0, C4<01>; 1 drivers -v0x24b0220_0 .net *"_s1034", 1 0, C4<00>; 1 drivers -v0x24b02c0_0 .net *"_s1039", 0 0, L_0x24f7ac0; 1 drivers -v0x24b0360_0 .net *"_s104", 2 0, L_0x2510330; 1 drivers -v0x24b0870_0 .net *"_s1041", 0 0, L_0x24f7b60; 1 drivers -v0x24b08f0_0 .net *"_s1043", 0 0, L_0x24f8950; 1 drivers -v0x24b0550_0 .net *"_s1044", 0 0, L_0x24f89f0; 1 drivers -v0x24b05f0_0 .net *"_s1047", 0 0, L_0x24f8af0; 1 drivers -v0x24b0690_0 .net *"_s1048", 0 0, L_0x24f8b90; 1 drivers -v0x24b0730_0 .net *"_s1050", 0 0, L_0x24f8c90; 1 drivers -v0x24b07d0_0 .net *"_s1052", 1 0, C4<01>; 1 drivers -v0x24b0cc0_0 .net *"_s1054", 1 0, C4<00>; 1 drivers -v0x24b0990_0 .net *"_s1058", 1 0, C4<00>; 1 drivers -v0x24b0a30_0 .net *"_s106", 0 0, L_0x24e5810; 1 drivers -v0x24b0ad0_0 .net *"_s1060", 0 0, L_0x24f9c80; 1 drivers -v0x24b0b70_0 .net *"_s1063", 0 0, L_0x24f9d70; 1 drivers -v0x24b0c10_0 .net *"_s1064", 0 0, L_0x24f9e60; 1 drivers -v0x24b10c0_0 .net *"_s1066", 0 0, L_0x24f9f60; 1 drivers -v0x24b0d60_0 .net *"_s1070", 1 0, C4<01>; 1 drivers -v0x24b0e00_0 .net *"_s1072", 0 0, L_0x24fa790; 1 drivers -v0x24b0ea0_0 .net *"_s1075", 0 0, L_0x24f8fa0; 1 drivers -v0x24b0f40_0 .net *"_s1076", 0 0, L_0x24f9040; 1 drivers -v0x24b0fe0_0 .net *"_s1078", 0 0, L_0x24f90f0; 1 drivers -v0x24b14f0_0 .net *"_s1082", 1 0, C4<10>; 1 drivers -v0x24b1140_0 .net *"_s1084", 0 0, L_0x24f9330; 1 drivers -v0x24b11c0_0 .net *"_s1087", 0 0, L_0x24fa8d0; 1 drivers -v0x24b1260_0 .net *"_s1088", 0 0, L_0x24faa00; 1 drivers -v0x24b1300_0 .net *"_s1090", 0 0, L_0x24faaf0; 1 drivers -v0x24b13a0_0 .net *"_s1094", 1 0, C4<11>; 1 drivers -v0x24b1440_0 .net *"_s1096", 0 0, L_0x24fac50; 1 drivers -v0x24b1960_0 .net *"_s1099", 0 0, L_0x24f9990; 1 drivers -v0x24b1a00_0 .net *"_s1100", 0 0, L_0x24facf0; 1 drivers -v0x24b1570_0 .net *"_s1102", 0 0, L_0x24fa730; 1 drivers -v0x24b1610_0 .net *"_s1107", 0 0, L_0x24fb5c0; 1 drivers -v0x24b16b0_0 .net *"_s1109", 0 0, L_0x24fa5b0; 1 drivers -v0x24b1750_0 .net *"_s111", 0 0, L_0x24e5700; 1 drivers -v0x24b17f0_0 .net *"_s1111", 0 0, L_0x24fb6b0; 1 drivers -v0x24b1890_0 .net *"_s1112", 0 0, L_0x24fa6a0; 1 drivers -v0x24b1eb0_0 .net *"_s1115", 0 0, L_0x24f94f0; 1 drivers -v0x24b1f30_0 .net *"_s1116", 0 0, L_0x24fb7f0; 1 drivers -v0x24b1a80_0 .net *"_s1118", 0 0, L_0x24f9680; 1 drivers -v0x24b1b00_0 .net *"_s1120", 1 0, C4<01>; 1 drivers -v0x24b1ba0_0 .net *"_s1122", 1 0, C4<00>; 1 drivers -v0x24b1c40_0 .net *"_s1127", 0 0, L_0x24f97d0; 1 drivers -v0x24b1ce0_0 .net *"_s1129", 9 0, L_0x24f98c0; 1 drivers -v0x24b1d80_0 .net *"_s113", 0 0, L_0x24e5ad0; 1 drivers -v0x24b1e20_0 .net *"_s1131", 9 0, L_0x24fa100; 1 drivers -v0x24b2420_0 .net *"_s1132", 0 0, L_0x24fa2b0; 1 drivers -v0x24b1fb0_0 .net *"_s1134", 0 0, L_0x24fb540; 1 drivers -v0x24b2050_0 .net *"_s1136", 0 0, L_0x24fa440; 1 drivers -v0x24b20f0_0 .net *"_s1139", 0 0, L_0x24fa4f0; 1 drivers -v0x24b2190_0 .net *"_s1141", 0 0, L_0x24fb010; 1 drivers -v0x24b2230_0 .net *"_s1143", 0 0, L_0x24fc8b0; 1 drivers -v0x24b22d0_0 .net *"_s1145", 0 0, L_0x24fb0b0; 1 drivers -v0x24b2370_0 .net *"_s1146", 0 0, L_0x24fc9a0; 1 drivers -v0x24b2950_0 .net *"_s1149", 0 0, L_0x24fb240; 1 drivers -v0x24b24a0_0 .net *"_s1151", 0 0, L_0x24fb2e0; 1 drivers -v0x24b2540_0 .net *"_s1152", 0 0, L_0x24fb3d0; 1 drivers -v0x24b25e0_0 .net *"_s1155", 0 0, L_0x24fb8f0; 1 drivers -v0x24b2680_0 .net *"_s1157", 0 0, L_0x24fb990; 1 drivers -v0x24b2720_0 .net *"_s1158", 0 0, L_0x24fba80; 1 drivers -v0x24b27c0_0 .net *"_s1160", 0 0, L_0x24fbb80; 1 drivers -v0x24b2860_0 .net *"_s1163", 0 0, L_0x24fc3c0; 1 drivers -v0x24b2ec0_0 .net *"_s1165", 9 0, L_0x24fc4b0; 1 drivers -v0x24b29d0_0 .net *"_s1167", 9 0, L_0x24fc550; 1 drivers -v0x24b2a50_0 .net *"_s1168", 0 0, L_0x24fc5f0; 1 drivers -v0x24b2af0_0 .net *"_s117", 0 0, L_0x24e5c10; 1 drivers -v0x24b2b90_0 .net *"_s1170", 0 0, L_0x24fc730; 1 drivers -v0x24b2c30_0 .net *"_s1172", 0 0, L_0x24fbcc0; 1 drivers -v0x24b2cd0_0 .net *"_s1175", 0 0, L_0x24fbd20; 1 drivers -v0x24b2d70_0 .net *"_s1177", 0 0, L_0x24fd0b0; 1 drivers -v0x24b2e10_0 .net *"_s1179", 0 0, L_0x24fd150; 1 drivers -v0x24b3480_0 .net *"_s1181", 0 0, L_0x24fd240; 1 drivers -v0x24b3500_0 .net *"_s1182", 0 0, L_0x24acc30; 1 drivers -v0x24b2f40_0 .net *"_s1185", 0 0, L_0x24fd3d0; 1 drivers -v0x24b2fe0_0 .net *"_s1187", 0 0, L_0x24fd470; 1 drivers -v0x24b3080_0 .net *"_s1188", 0 0, L_0x24fd560; 1 drivers -v0x24b3120_0 .net *"_s1191", 0 0, L_0x24fbef0; 1 drivers -v0x24b31c0_0 .net *"_s1193", 0 0, L_0x24fbf90; 1 drivers -v0x24b3260_0 .net *"_s1194", 0 0, L_0x24fc080; 1 drivers -v0x24b3300_0 .net *"_s1196", 0 0, L_0x24fc180; 1 drivers -v0x24b33a0_0 .net *"_s1201", 9 0, L_0x24fdb60; 1 drivers -v0x24b3b10_0 .net *"_s1203", 9 0, L_0x24fdc90; 1 drivers -v0x24b3b90_0 .net *"_s1207", 9 0, L_0x24fde20; 1 drivers -v0x24b3580_0 .net *"_s1209", 9 0, L_0x24fdec0; 1 drivers -v0x24b3620_0 .net *"_s1213", 0 0, L_0x24fe0f0; 1 drivers -v0x24b36c0_0 .net *"_s1215", 0 0, L_0x24fd650; 1 drivers -v0x24b3760_0 .net *"_s1216", 0 0, L_0x24fd6f0; 1 drivers -v0x24b3800_0 .net *"_s1219", 0 0, L_0x24fd7a0; 1 drivers -v0x24b38a0_0 .net *"_s122", 0 0, C4<1>; 1 drivers -v0x24b3940_0 .net *"_s1221", 0 0, L_0x24fd890; 1 drivers -v0x24b39e0_0 .net *"_s1222", 0 0, L_0x24fd980; 1 drivers -v0x24b3a80_0 .net *"_s1224", 1 0, C4<10>; 1 drivers -v0x24b41f0_0 .net *"_s1227", 0 0, L_0x24fda80; 1 drivers -v0x24b3c10_0 .net *"_s1229", 0 0, L_0x24fe190; 1 drivers -v0x24b3cb0_0 .net *"_s1231", 0 0, L_0x24fe830; 1 drivers -v0x24b3d50_0 .net *"_s1232", 0 0, L_0x24b3420; 1 drivers -v0x24b3df0_0 .net *"_s1234", 1 0, C4<01>; 1 drivers -v0x24b3e90_0 .net *"_s1236", 1 0, C4<00>; 1 drivers -v0x24b3f30_0 .net *"_s1238", 1 0, L_0x24fe970; 1 drivers -v0x24b3fd0_0 .net *"_s1243", 9 0, L_0x24febf0; 1 drivers -v0x24b4070_0 .net *"_s1245", 9 0, L_0x24fec90; 1 drivers -v0x24b4110_0 .net *"_s1249", 9 0, L_0x24fe370; 1 drivers -v0x24b48a0_0 .net *"_s125", 9 0, L_0x24e5970; 1 drivers -v0x24b4270_0 .net *"_s1251", 9 0, L_0x24fe410; 1 drivers -v0x24b4310_0 .net *"_s1255", 9 0, L_0x24fe640; 1 drivers -v0x24b43b0_0 .net *"_s1257", 9 0, L_0x24fe6e0; 1 drivers -v0x24b4450_0 .net *"_s1261", 9 0, L_0x24fca50; 1 drivers -v0x24b44f0_0 .net *"_s1263", 9 0, L_0x24fcb80; 1 drivers -v0x24b4590_0 .net *"_s1267", 0 0, L_0x24fce20; 1 drivers -v0x24b4630_0 .net *"_s1268", 0 0, L_0x24fcec0; 1 drivers -v0x24b46d0_0 .net *"_s1270", 0 0, L_0x24f6da0; 1 drivers -v0x24b4770_0 .net *"_s1275", 0 0, L_0x24fef80; 1 drivers -v0x24b4810_0 .net *"_s1276", 0 0, L_0x24ff020; 1 drivers -v0x24b4fb0_0 .net *"_s1278", 0 0, L_0x24ff0d0; 1 drivers -v0x24b5030_0 .net *"_s1280", 1 0, C4<00>; 1 drivers -v0x24b4940_0 .net *"_s1282", 1 0, L_0x24ff850; 1 drivers -v0x24b49e0_0 .net *"_s1287", 9 0, L_0x2500160; 1 drivers -v0x24b4a80_0 .net *"_s1289", 9 0, L_0x2500310; 1 drivers -v0x24b4b20_0 .net *"_s129", 9 0, L_0x24e5d40; 1 drivers -v0x24b4bc0_0 .net *"_s1292", 0 0, L_0x2500c10; 1 drivers -v0x24b4c60_0 .net *"_s1294", 1 0, C4<00>; 1 drivers -v0x24b4d00_0 .net *"_s1298", 1 0, C4<01>; 1 drivers -v0x24b4da0_0 .net *"_s130", 9 0, C4<0000000001>; 1 drivers -v0x24b4e40_0 .net *"_s1304", 0 0, L_0x24ffac0; 1 drivers -v0x24b4ee0_0 .net *"_s1306", 1 0, C4<00>; 1 drivers -v0x24b57a0_0 .net *"_s1310", 1 0, C4<01>; 1 drivers -v0x24b5820_0 .net *"_s1316", 0 0, L_0x24fff50; 1 drivers -v0x24b50d0_0 .net *"_s1318", 1 0, C4<00>; 1 drivers -v0x24b5170_0 .net *"_s132", 9 0, L_0x24e3310; 1 drivers -v0x24b5210_0 .net *"_s1322", 1 0, C4<01>; 1 drivers -v0x24b52b0_0 .net *"_s1328", 0 0, L_0x2500730; 1 drivers -v0x24b5350_0 .net *"_s1330", 1 0, C4<00>; 1 drivers -v0x24b53f0_0 .net *"_s1334", 1 0, C4<01>; 1 drivers -v0x24b5490_0 .net *"_s1340", 0 0, L_0x2501fe0; 1 drivers -v0x24b5530_0 .net *"_s1342", 2 0, C4<000>; 1 drivers -v0x24b55d0_0 .net *"_s1348", 0 0, L_0x24ff440; 1 drivers -v0x24b5670_0 .net *"_s135", 1 0, L_0x24e60b0; 1 drivers -v0x24b5710_0 .net *"_s1350", 1 0, C4<00>; 1 drivers -v0x24b6010_0 .net *"_s1356", 0 0, L_0x24f0150; 1 drivers -v0x24b58c0_0 .net *"_s1358", 1 0, C4<00>; 1 drivers -v0x24b5960_0 .net *"_s1365", 0 0, L_0x2502fb0; 1 drivers -v0x24b5a00_0 .net *"_s1367", 0 0, L_0x25030e0; 1 drivers -v0x24b5aa0_0 .net *"_s1369", 0 0, L_0x2503180; 1 drivers -v0x24b5b40_0 .net *"_s1370", 0 0, L_0x2503270; 1 drivers -v0x24b5be0_0 .net *"_s1373", 0 0, L_0x25018d0; 1 drivers -v0x24b5c80_0 .net *"_s1375", 0 0, L_0x2501a00; 1 drivers -v0x24b5d20_0 .net *"_s1377", 0 0, L_0x2501aa0; 1 drivers -v0x24b5dc0_0 .net *"_s1378", 0 0, L_0x2501b90; 1 drivers -v0x24b5e60_0 .net *"_s1380", 0 0, L_0x2501c90; 1 drivers -v0x24b5f00_0 .net *"_s1383", 0 0, L_0x2501010; 1 drivers -v0x24b6840_0 .net *"_s1384", 0 0, L_0x25010b0; 1 drivers -v0x24b6090_0 .net *"_s1389", 0 0, L_0x2501260; 1 drivers -v0x24b6130_0 .net *"_s1391", 0 0, L_0x2501390; 1 drivers -v0x24b61d0_0 .net *"_s1393", 0 0, L_0x2501430; 1 drivers -v0x24b6270_0 .net *"_s1394", 0 0, L_0x2501520; 1 drivers -v0x24b6310_0 .net *"_s1397", 0 0, L_0x2501620; 1 drivers -v0x24b63b0_0 .net *"_s1399", 0 0, L_0x25027a0; 1 drivers -v0x24b6450_0 .net *"_s14", 0 0, L_0x24e3420; 1 drivers -v0x24b64f0_0 .net *"_s140", 1 0, C4<00>; 1 drivers -v0x24b6590_0 .net *"_s1401", 0 0, L_0x2502890; 1 drivers -v0x24b6630_0 .net *"_s1402", 0 0, L_0x25016c0; 1 drivers -v0x24b66d0_0 .net *"_s1404", 0 0, L_0x25029d0; 1 drivers -v0x24b6770_0 .net *"_s1407", 0 0, L_0x2502ad0; 1 drivers -v0x24b70e0_0 .net *"_s1409", 0 0, L_0x2502b70; 1 drivers -v0x24b7160_0 .net *"_s1411", 0 0, L_0x2502c60; 1 drivers -v0x24b68c0_0 .net *"_s1412", 0 0, L_0x2502d00; 1 drivers -v0x24b6960_0 .net *"_s1417", 0 0, L_0x2503a50; 1 drivers -v0x24b6a00_0 .net *"_s1419", 0 0, L_0x2503c00; 1 drivers -v0x24b6aa0_0 .net *"_s142", 0 0, L_0x24e66b0; 1 drivers -v0x24b6b40_0 .net *"_s1421", 0 0, L_0x2503cf0; 1 drivers -v0x24b6be0_0 .net *"_s1422", 0 0, L_0x2503d90; 1 drivers -v0x24b6c80_0 .net *"_s1425", 0 0, L_0x2503e40; 1 drivers -v0x24b6d20_0 .net *"_s1427", 0 0, L_0x2503ff0; 1 drivers -v0x24b6dc0_0 .net *"_s1429", 0 0, L_0x25040e0; 1 drivers -v0x24b6e60_0 .net *"_s1430", 0 0, L_0x2504980; 1 drivers -v0x24b6f00_0 .net *"_s1432", 0 0, L_0x25032e0; 1 drivers -v0x24b6fa0_0 .net *"_s1435", 0 0, L_0x25033e0; 1 drivers -v0x24b7040_0 .net *"_s1436", 0 0, L_0x2503480; 1 drivers -v0x24b7a70_0 .net *"_s144", 0 0, L_0x24e6530; 1 drivers -v0x24b7200_0 .net *"_s1441", 0 0, L_0x2503630; 1 drivers -v0x24b72a0_0 .net *"_s1443", 0 0, L_0x25036d0; 1 drivers -v0x24b7340_0 .net *"_s1445", 0 0, L_0x25037c0; 1 drivers -v0x24b73e0_0 .net *"_s1446", 0 0, L_0x2503860; 1 drivers -v0x24b7480_0 .net *"_s1449", 0 0, L_0x2503960; 1 drivers -v0x24b7520_0 .net *"_s1451", 0 0, L_0x2504a30; 1 drivers -v0x24b75c0_0 .net *"_s1453", 0 0, L_0x2504ad0; 1 drivers -v0x24b7660_0 .net *"_s1454", 0 0, L_0x2504b70; 1 drivers -v0x24b7700_0 .net *"_s1456", 0 0, L_0x2504c20; 1 drivers -v0x24b77a0_0 .net *"_s1459", 0 0, L_0x2504d20; 1 drivers -v0x24b7840_0 .net *"_s146", 0 0, L_0x24e5e40; 1 drivers -v0x24b78e0_0 .net *"_s1460", 0 0, L_0x2504dc0; 1 drivers -v0x24b7980_0 .net *"_s1465", 0 0, L_0x2504190; 1 drivers -v0x24b83f0_0 .net *"_s1467", 0 0, L_0x2504230; 1 drivers -v0x24b7af0_0 .net *"_s1469", 0 0, L_0x2504320; 1 drivers -v0x24b7b90_0 .net *"_s1470", 0 0, L_0x2504450; 1 drivers -v0x24b7c30_0 .net *"_s1473", 0 0, L_0x2504500; 1 drivers -v0x24b7cd0_0 .net *"_s1475", 0 0, L_0x25045a0; 1 drivers -v0x24b7d70_0 .net *"_s1477", 0 0, L_0x2504690; 1 drivers -v0x24b7e10_0 .net *"_s1478", 0 0, L_0x2504730; 1 drivers -v0x24b7eb0_0 .net *"_s1480", 0 0, L_0x2504830; 1 drivers -v0x24b7f50_0 .net *"_s1483", 0 0, L_0x2505790; 1 drivers -v0x24b7ff0_0 .net *"_s1485", 0 0, L_0x2505830; 1 drivers -v0x24b8090_0 .net *"_s1487", 0 0, L_0x2505920; 1 drivers -v0x24b8130_0 .net *"_s1488", 0 0, L_0x25059c0; 1 drivers -v0x24b81d0_0 .net *"_s1493", 0 0, L_0x2505bc0; 1 drivers -v0x24b8270_0 .net *"_s1495", 0 0, L_0x2505d70; 1 drivers -v0x24b8310_0 .net *"_s1497", 0 0, L_0x2505e60; 1 drivers -v0x24b8df0_0 .net *"_s1498", 0 0, L_0x2505f00; 1 drivers -v0x24b8e70_0 .net *"_s150", 1 0, C4<00>; 1 drivers -v0x24b8470_0 .net *"_s1501", 0 0, L_0x2504fc0; 1 drivers -v0x24b84f0_0 .net *"_s1503", 0 0, L_0x2505060; 1 drivers -v0x24b8590_0 .net *"_s1505", 0 0, L_0x2505150; 1 drivers -v0x24b8630_0 .net *"_s1506", 0 0, L_0x25051f0; 1 drivers -v0x24b86d0_0 .net *"_s1508", 0 0, L_0x25052a0; 1 drivers -v0x24b8770_0 .net *"_s1511", 0 0, L_0x25053a0; 1 drivers -v0x24b8810_0 .net *"_s1513", 0 0, L_0x2505440; 1 drivers -v0x24b88b0_0 .net *"_s1515", 0 0, L_0x2505530; 1 drivers -v0x24b8950_0 .net *"_s1516", 0 0, L_0x2505660; 1 drivers -v0x24b89f0_0 .net *"_s152", 0 0, L_0x24e6150; 1 drivers -v0x24b8a90_0 .net *"_s1521", 0 0, L_0x2507060; 1 drivers -v0x24b8b30_0 .net *"_s1523", 0 0, L_0x2507100; 1 drivers -v0x24b8bd0_0 .net *"_s1525", 0 0, L_0x2506050; 1 drivers -v0x24b8c70_0 .net *"_s1527", 0 0, L_0x25060f0; 1 drivers -v0x24b8d10_0 .net *"_s1528", 0 0, L_0x25061e0; 1 drivers -v0x24b98f0_0 .net *"_s1531", 0 0, L_0x25062e0; 1 drivers -v0x24b8ef0_0 .net *"_s1533", 0 0, L_0x2506380; 1 drivers -v0x24b8f70_0 .net *"_s1534", 0 0, L_0x2506470; 1 drivers -v0x24b9010_0 .net *"_s1537", 0 0, L_0x2506570; 1 drivers -v0x24b90b0_0 .net *"_s1539", 0 0, L_0x2506610; 1 drivers -v0x24b9150_0 .net *"_s154", 0 0, L_0x24e6bc0; 1 drivers -v0x24b91f0_0 .net *"_s1543", 0 0, L_0x2506850; 1 drivers -v0x24b9290_0 .net *"_s1545", 0 0, L_0x25068f0; 1 drivers -v0x24b9330_0 .net *"_s1547", 0 0, L_0x25069e0; 1 drivers -v0x24b93d0_0 .net *"_s1548", 0 0, L_0x2506a80; 1 drivers -v0x24b9470_0 .net *"_s1550", 0 0, L_0x2506b80; 1 drivers -v0x24b9510_0 .net *"_s1555", 0 0, L_0x2506d30; 1 drivers -v0x24b95b0_0 .net *"_s1557", 0 0, L_0x2506e60; 1 drivers -v0x24b9650_0 .net *"_s1559", 0 0, L_0x2506f00; 1 drivers -v0x24b96f0_0 .net *"_s1560", 0 0, L_0x2506ff0; 1 drivers -v0x24b9790_0 .net *"_s1563", 0 0, L_0x2507a80; 1 drivers -v0x24b9830_0 .net *"_s1565", 0 0, L_0x2507bb0; 1 drivers -v0x24ba400_0 .net *"_s1567", 0 0, L_0x2507c50; 1 drivers -v0x24ba480_0 .net *"_s1568", 0 0, L_0x2507d40; 1 drivers -v0x24b9990_0 .net *"_s1570", 0 0, L_0x2507e40; 1 drivers -v0x24b9a30_0 .net *"_s1573", 0 0, L_0x2507f40; 1 drivers -v0x24b9ad0_0 .net *"_s1574", 0 0, L_0x2507fe0; 1 drivers -v0x24b9b70_0 .net *"_s1579", 0 0, L_0x2507250; 1 drivers -v0x24b9c10_0 .net *"_s158", 1 0, C4<01>; 1 drivers -v0x24b9cb0_0 .net *"_s1581", 0 0, L_0x2507380; 1 drivers -v0x24b9d50_0 .net *"_s1583", 0 0, L_0x2507420; 1 drivers -v0x24b9df0_0 .net *"_s1584", 0 0, L_0x2507510; 1 drivers -v0x24b9e90_0 .net *"_s1587", 0 0, L_0x2507610; 1 drivers -v0x24b9f30_0 .net *"_s1589", 0 0, L_0x25076b0; 1 drivers -v0x24b9fd0_0 .net *"_s1591", 0 0, L_0x25077a0; 1 drivers -v0x24ba070_0 .net *"_s1592", 0 0, L_0x2507840; 1 drivers -v0x24ba110_0 .net *"_s1594", 0 0, L_0x2507940; 1 drivers -v0x24ba1b0_0 .net *"_s1597", 0 0, L_0x2509270; 1 drivers -v0x24ba250_0 .net *"_s1599", 0 0, L_0x2509310; 1 drivers -v0x24ba2f0_0 .net *"_s16", 0 0, L_0x24e3480; 1 drivers -v0x24bb020_0 .net *"_s160", 0 0, L_0x24e6ab0; 1 drivers -v0x24bb0a0_0 .net *"_s1601", 0 0, L_0x25080e0; 1 drivers -v0x24ba500_0 .net *"_s1602", 0 0, L_0x2508180; 1 drivers -v0x24ba5a0_0 .net *"_s1606", 1 0, C4<01>; 1 drivers -v0x24ba640_0 .net *"_s1610", 1 0, C4<01>; 1 drivers -v0x24ba6e0_0 .net *"_s1614", 1 0, C4<01>; 1 drivers -v0x24ba780_0 .net *"_s1618", 1 0, C4<01>; 1 drivers -v0x24ba820_0 .net *"_s162", 0 0, L_0x24e67a0; 1 drivers -v0x24ba8c0_0 .net *"_s1622", 2 0, C4<001>; 1 drivers -v0x24ba960_0 .net *"_s1626", 1 0, C4<01>; 1 drivers -v0x24baa00_0 .net *"_s1630", 1 0, C4<01>; 1 drivers -v0x24baaa0_0 .net *"_s1634", 1 0, C4<01>; 1 drivers -v0x24bab40_0 .net *"_s1639", 9 0, L_0x2502080; 1 drivers -v0x24babe0_0 .net *"_s164", 0 0, L_0x24e7070; 1 drivers -v0x24bac80_0 .net *"_s1641", 9 0, L_0x2502120; 1 drivers -v0x24bad20_0 .net *"_s1645", 9 0, L_0x2502340; 1 drivers -v0x24badc0_0 .net *"_s1647", 9 0, L_0x25023e0; 1 drivers -v0x24bae60_0 .net *"_s1651", 9 0, L_0x2502600; 1 drivers -v0x24baf00_0 .net *"_s1653", 9 0, L_0x25026a0; 1 drivers -v0x24bafa0_0 .net *"_s1657", 0 0, L_0x2508b30; 1 drivers -v0x24bbce0_0 .net *"_s1658", 0 0, L_0x2502740; 1 drivers -v0x24bbd80_0 .net *"_s1661", 0 0, L_0x2508cb0; 1 drivers -v0x24bb140_0 .net *"_s1662", 0 0, L_0x2508d50; 1 drivers -v0x24bb1e0_0 .net *"_s1664", 0 0, L_0x2508380; 1 drivers -v0x24bb280_0 .net *"_s1667", 0 0, L_0x250b6f0; 1 drivers -v0x24bb320_0 .net *"_s1668", 0 0, L_0x2508db0; 1 drivers -v0x24bb3c0_0 .net *"_s1673", 0 0, L_0x2508fb0; 1 drivers -v0x24bb460_0 .net *"_s1674", 0 0, L_0x2509050; 1 drivers -v0x24bb500_0 .net *"_s1677", 0 0, L_0x2509450; 1 drivers -v0x24bb5a0_0 .net *"_s1678", 0 0, L_0x25094f0; 1 drivers -v0x24bb640_0 .net *"_s168", 1 0, C4<01>; 1 drivers -v0x24bb6e0_0 .net *"_s1680", 0 0, L_0x25095a0; 1 drivers -v0x24bb780_0 .net *"_s1683", 0 0, L_0x25096a0; 1 drivers -v0x24bb820_0 .net *"_s1684", 0 0, L_0x2509740; 1 drivers -v0x24bb8c0_0 .net *"_s1689", 0 0, L_0x25098f0; 1 drivers -v0x24bb960_0 .net *"_s1690", 0 0, L_0x2509990; 1 drivers -v0x24bba00_0 .net *"_s1693", 0 0, L_0x2509ad0; 1 drivers -v0x24bbaa0_0 .net *"_s1694", 0 0, L_0x2509e10; 1 drivers -v0x24bbb40_0 .net *"_s1696", 0 0, L_0x2509e70; 1 drivers -v0x24bbbe0_0 .net *"_s1699", 0 0, L_0x2509f70; 1 drivers -v0x24bca60_0 .net *"_s170", 0 0, L_0x24e6e20; 1 drivers -v0x24bcae0_0 .net *"_s1700", 0 0, L_0x250a010; 1 drivers -v0x24bbe00_0 .net *"_s1705", 0 0, L_0x250a1c0; 1 drivers -v0x24bbe80_0 .net *"_s1707", 9 0, L_0x250a260; 1 drivers -v0x24bbf20_0 .net *"_s1709", 9 0, L_0x250a300; 1 drivers -v0x24bbfc0_0 .net *"_s1710", 0 0, L_0x250a3a0; 1 drivers -v0x24bc060_0 .net *"_s1712", 0 0, L_0x250a4e0; 1 drivers -v0x24bc100_0 .net *"_s1717", 0 0, L_0x250ae50; 1 drivers -v0x24bc1a0_0 .net *"_s1719", 2 0, L_0x250b000; 1 drivers -v0x24bc240_0 .net *"_s172", 0 0, L_0x24e7330; 1 drivers -v0x24bc2e0_0 .net *"_s1720", 0 0, L_0x250b0a0; 1 drivers -v0x24bc380_0 .net *"_s1723", 0 0, L_0x250b190; 1 drivers -v0x24bc420_0 .net *"_s1724", 0 0, L_0x250b230; 1 drivers -v0x24bc4c0_0 .net *"_s1729", 9 0, L_0x250b420; 1 drivers -v0x24bc560_0 .net *"_s1730", 9 0, C4<1111101000>; 1 drivers -v0x24bc600_0 .net *"_s1736", 1 0, L_0x250e3d0; 1 drivers -v0x24bc6a0_0 .net *"_s1739", 1 0, L_0x250c830; 1 drivers -v0x24bc740_0 .net *"_s1740", 0 0, L_0x250c8d0; 1 drivers -v0x24bc7e0_0 .net *"_s1745", 31 0, L_0x250a6a0; 1 drivers -v0x24bc880_0 .net *"_s1749", 9 0, L_0x250a8f0; 1 drivers -v0x24bc920_0 .net *"_s1751", 9 0, L_0x250a990; 1 drivers -v0x24bc9c0_0 .net *"_s1755", 9 0, L_0x250abb0; 1 drivers -v0x24bd870_0 .net *"_s1757", 9 0, L_0x250ac50; 1 drivers -v0x24bd910_0 .net *"_s176", 1 0, C4<10>; 1 drivers -v0x24bcb80_0 .net *"_s1761", 9 0, L_0x250b880; 1 drivers -v0x24bcc20_0 .net *"_s1763", 9 0, L_0x250b920; 1 drivers -v0x24bccc0_0 .net *"_s1767", 0 0, L_0x250bb00; 1 drivers -v0x24bcd60_0 .net *"_s1768", 0 0, L_0x250bba0; 1 drivers -v0x24bce00_0 .net *"_s1771", 0 0, L_0x250bce0; 1 drivers -v0x24bcea0_0 .net *"_s1772", 0 0, L_0x250bd80; 1 drivers -v0x24bcf40_0 .net *"_s1774", 0 0, L_0x250ad90; 1 drivers -v0x24bcfe0_0 .net *"_s1777", 0 0, L_0x250be30; 1 drivers -v0x24bd080_0 .net *"_s1778", 0 0, L_0x250bed0; 1 drivers -v0x24bd120_0 .net *"_s178", 0 0, L_0x24e7560; 1 drivers -v0x24bd1c0_0 .net *"_s1783", 0 0, L_0x250d400; 1 drivers -v0x24bd260_0 .net *"_s1784", 0 0, L_0x250d4a0; 1 drivers -v0x24bd300_0 .net *"_s1787", 9 0, L_0x250d5a0; 1 drivers -v0x24bd3a0_0 .net *"_s1789", 9 0, L_0x250d640; 1 drivers -v0x24bd440_0 .net *"_s1790", 0 0, L_0x250d8f0; 1 drivers -v0x24bd4e0_0 .net *"_s1792", 0 0, L_0x250da30; 1 drivers -v0x24bd580_0 .net *"_s1794", 1 0, C4<11>; 1 drivers -v0x24bd620_0 .net *"_s1796", 1 0, C4<10>; 1 drivers -v0x24bd6c0_0 .net *"_s1798", 1 0, L_0x24fa1e0; 1 drivers -v0x24bd760_0 .net *"_s18", 0 0, L_0x24e3530; 1 drivers -v0x24be750_0 .net *"_s180", 0 0, L_0x24e6f20; 1 drivers -v0x24be7d0_0 .net *"_s1803", 0 0, L_0x250c1b0; 1 drivers -v0x24bd990_0 .net *"_s1804", 0 0, L_0x250c250; 1 drivers -v0x24bda30_0 .net *"_s1807", 9 0, L_0x250c350; 1 drivers -v0x24bdad0_0 .net *"_s1809", 9 0, L_0x250c3f0; 1 drivers -v0x24bdb70_0 .net *"_s1810", 0 0, L_0x250c490; 1 drivers -v0x24bdc10_0 .net *"_s1812", 0 0, L_0x250c5d0; 1 drivers -v0x24bdcb0_0 .net *"_s1814", 1 0, C4<11>; 1 drivers -v0x24bdd50_0 .net *"_s1816", 1 0, C4<10>; 1 drivers -v0x24bddf0_0 .net *"_s1818", 1 0, L_0x250c710; 1 drivers -v0x24bde90_0 .net *"_s182", 0 0, L_0x24e73e0; 1 drivers -v0x24bdf30_0 .net *"_s1823", 0 0, L_0x250ee60; 1 drivers -v0x24bdfd0_0 .net *"_s1824", 0 0, L_0x250ef00; 1 drivers -v0x24be070_0 .net *"_s1826", 0 0, L_0x250efb0; 1 drivers -v0x24be110_0 .net *"_s1828", 1 0, C4<11>; 1 drivers -v0x24be1b0_0 .net *"_s1830", 1 0, C4<10>; 1 drivers -v0x24be250_0 .net *"_s1832", 1 0, L_0x250f0e0; 1 drivers -v0x24be2f0_0 .net *"_s1837", 0 0, L_0x250cb00; 1 drivers -v0x24be390_0 .net *"_s1839", 0 0, L_0x250cba0; 1 drivers -v0x24be430_0 .net *"_s1840", 0 0, L_0x250cc40; 1 drivers -v0x24be4d0_0 .net *"_s1843", 0 0, L_0x250cd40; 1 drivers -v0x24be570_0 .net *"_s1844", 0 0, L_0x250cde0; 1 drivers -v0x24be610_0 .net *"_s1847", 0 0, L_0x250cee0; 1 drivers -v0x24be6b0_0 .net *"_s1849", 0 0, L_0x250cf80; 1 drivers -v0x24bf6d0_0 .net *"_s1850", 0 0, L_0x250d070; 1 drivers -v0x24bf750_0 .net *"_s1852", 1 0, C4<11>; 1 drivers -v0x24be870_0 .net *"_s1857", 0 0, L_0x25105e0; 1 drivers -v0x24be910_0 .net *"_s1858", 0 0, L_0x2510680; 1 drivers -v0x24be9b0_0 .net *"_s186", 1 0, C4<10>; 1 drivers -v0x24bea50_0 .net *"_s1861", 9 0, L_0x2510780; 1 drivers -v0x24beaf0_0 .net *"_s1863", 9 0, L_0x2500200; 1 drivers -v0x24beb90_0 .net *"_s1864", 0 0, L_0x250dd40; 1 drivers -v0x24bec30_0 .net *"_s1866", 0 0, L_0x250de80; 1 drivers -v0x24becd0_0 .net *"_s1868", 1 0, C4<11>; 1 drivers -v0x24bed70_0 .net *"_s1870", 1 0, C4<10>; 1 drivers -v0x24bee10_0 .net *"_s1872", 1 0, L_0x250e970; 1 drivers -v0x24beeb0_0 .net *"_s188", 0 0, L_0x24e6890; 1 drivers -v0x24bef50_0 .net *"_s190", 0 0, L_0x24e7a40; 1 drivers -v0x24beff0_0 .net *"_s194", 1 0, C4<11>; 1 drivers -v0x24bf090_0 .net *"_s196", 0 0, L_0x24e7750; 1 drivers -v0x24bf130_0 .net *"_s198", 0 0, L_0x24e7600; 1 drivers -v0x24bf1d0_0 .net *"_s20", 0 0, L_0x24e35d0; 1 drivers -v0x24bf270_0 .net *"_s200", 0 0, L_0x24e7ef0; 1 drivers -v0x24bf310_0 .net *"_s204", 1 0, C4<11>; 1 drivers -v0x24bf3b0_0 .net *"_s206", 0 0, L_0x24e7d10; 1 drivers -v0x24bf450_0 .net *"_s208", 0 0, L_0x24e7980; 1 drivers -v0x24bf4f0_0 .net *"_s22", 0 0, L_0x24e3680; 1 drivers -v0x24bf590_0 .net *"_s222", 0 0, L_0x24e7e00; 1 drivers -v0x24bf630_0 .net *"_s227", 0 0, L_0x24e87c0; 1 drivers -v0x24c0710_0 .net *"_s229", 0 0, L_0x24e8860; 1 drivers -v0x24bf7f0_0 .net *"_s230", 0 0, L_0x24e8900; 1 drivers -v0x24bf890_0 .net *"_s232", 0 0, L_0x24e89b0; 1 drivers -v0x24bf930_0 .net *"_s235", 1 0, L_0x24e8a60; 1 drivers -v0x24bf9d0_0 .net *"_s236", 0 0, L_0x24e8b00; 1 drivers -v0x24bfa70_0 .net *"_s24", 0 0, L_0x24e3780; 1 drivers -v0x24bfb10_0 .net *"_s241", 0 0, L_0x24e8d80; 1 drivers -v0x24bfbb0_0 .net *"_s243", 0 0, L_0x24e8e70; 1 drivers -v0x24bfc50_0 .net *"_s244", 0 0, L_0x24e8f60; 1 drivers -v0x24bfcf0_0 .net *"_s246", 0 0, L_0x24e9050; 1 drivers -v0x24bfd90_0 .net *"_s249", 1 0, L_0x24e9100; 1 drivers -v0x24bfe30_0 .net *"_s250", 0 0, L_0x24e9230; 1 drivers -v0x24bfed0_0 .net *"_s254", 0 0, C4<1>; 1 drivers -v0x24bff70_0 .net *"_s257", 9 0, L_0x24e93d0; 1 drivers -v0x24c0010_0 .net *"_s263", 0 0, L_0x24e9b90; 1 drivers -v0x24c00b0_0 .net *"_s264", 0 0, L_0x24e9a10; 1 drivers -v0x24c0150_0 .net *"_s268", 13 0, C4<00101010101010>; 1 drivers -v0x24c01f0_0 .net *"_s275", 0 0, L_0x24ea050; 1 drivers -v0x24c0290_0 .net *"_s281", 0 0, L_0x24e9eb0; 1 drivers -v0x24c0330_0 .net *"_s287", 0 0, L_0x24e9570; 1 drivers -v0x24c03d0_0 .net *"_s29", 0 0, L_0x24e3990; 1 drivers -v0x24c0470_0 .net *"_s293", 0 0, L_0x24ea2c0; 1 drivers -v0x24c0510_0 .net *"_s296", 1 0, C4<00>; 1 drivers -v0x24c05b0_0 .net *"_s3", 0 0, L_0x24d7ff0; 1 drivers -v0x24c0650_0 .net *"_s30", 0 0, L_0x24e3a30; 1 drivers -v0x24c17a0_0 .net *"_s300", 1 0, L_0x2510390; 1 drivers -v0x24c1820_0 .net *"_s314", 1 0, C4<00>; 1 drivers -v0x24c07b0_0 .net *"_s318", 1 0, L_0x250f360; 1 drivers -v0x24c0850_0 .net *"_s33", 0 0, L_0x24e3a90; 1 drivers -v0x24c08f0_0 .net *"_s332", 1 0, C4<00>; 1 drivers -v0x24c0990_0 .net *"_s336", 1 0, L_0x250f460; 1 drivers -v0x24c0a30_0 .net *"_s350", 1 0, C4<00>; 1 drivers -v0x24c0ad0_0 .net *"_s354", 1 0, L_0x250f560; 1 drivers -v0x24c0b70_0 .net *"_s368", 10 0, C4<01010101010>; 1 drivers -v0x24c0c10_0 .net *"_s37", 0 0, L_0x24e3c30; 1 drivers -v0x24c0cb0_0 .net *"_s372", 1 0, C4<00>; 1 drivers -v0x24c0d50_0 .net *"_s374", 0 0, L_0x24eb6b0; 1 drivers -v0x24c0df0_0 .net *"_s376", 0 0, L_0x24eb7a0; 1 drivers -v0x24c0e90_0 .net *"_s378", 0 0, L_0x24eb1f0; 1 drivers -v0x24c0f30_0 .net *"_s38", 0 0, L_0x24e3930; 1 drivers -v0x24c0fd0_0 .net *"_s382", 10 0, C4<01010101010>; 1 drivers -v0x24c1070_0 .net *"_s386", 1 0, C4<01>; 1 drivers -v0x24c1110_0 .net *"_s388", 0 0, L_0x24ebb30; 1 drivers -v0x24c11b0_0 .net *"_s390", 0 0, L_0x24ebc20; 1 drivers -v0x24c1250_0 .net *"_s392", 0 0, L_0x24eacc0; 1 drivers -v0x24c12f0_0 .net *"_s396", 10 0, C4<01010101010>; 1 drivers -v0x24c1390_0 .net *"_s400", 1 0, C4<10>; 1 drivers -v0x24c1430_0 .net *"_s402", 0 0, L_0x24ebfb0; 1 drivers -v0x24c14d0_0 .net *"_s404", 0 0, L_0x24ec0a0; 1 drivers -v0x24c1570_0 .net *"_s406", 0 0, L_0x24eb8e0; 1 drivers -v0x24c1610_0 .net *"_s41", 0 0, L_0x24e3d20; 1 drivers -v0x24c16b0_0 .net *"_s410", 10 0, C4<01010101010>; 1 drivers -v0x24c2980_0 .net *"_s414", 1 0, C4<11>; 1 drivers -v0x24c18a0_0 .net *"_s416", 0 0, L_0x24ec720; 1 drivers -v0x24c1940_0 .net *"_s418", 0 0, L_0x24ecbc0; 1 drivers -v0x24c19e0_0 .net *"_s420", 0 0, L_0x24ecc70; 1 drivers -v0x24c1a80_0 .net *"_s425", 0 0, L_0x24ec8d0; 1 drivers -v0x24c1b20_0 .net *"_s426", 0 0, L_0x24ec9c0; 1 drivers -v0x24c1bc0_0 .net *"_s430", 1 0, L_0x250f660; 1 drivers -v0x24c1c60_0 .net *"_s432", 0 0, L_0x24ecac0; 1 drivers -v0x24c1d00_0 .net *"_s437", 0 0, L_0x24ec2e0; 1 drivers -v0x24c1da0_0 .net *"_s438", 0 0, L_0x24ed060; 1 drivers -v0x24c1e40_0 .net *"_s441", 0 0, L_0x24ed110; 1 drivers -v0x24c1ee0_0 .net *"_s442", 0 0, L_0x24ed240; 1 drivers -v0x24c1f80_0 .net *"_s45", 0 0, L_0x24e3f40; 1 drivers -v0x24c2020_0 .net *"_s455", 0 0, L_0x24ec5f0; 1 drivers -v0x24c20c0_0 .net *"_s456", 0 0, L_0x24ece30; 1 drivers -v0x24c2160_0 .net *"_s46", 0 0, L_0x24e3fe0; 1 drivers -v0x24c2200_0 .net *"_s460", 1 0, L_0x250f710; 1 drivers -v0x24c22a0_0 .net *"_s462", 0 0, L_0x24ecf30; 1 drivers -v0x24c2340_0 .net *"_s467", 0 0, L_0x24ed790; 1 drivers -v0x24c23e0_0 .net *"_s468", 0 0, L_0x24ed830; 1 drivers -v0x24c2480_0 .net *"_s471", 0 0, L_0x24edc20; 1 drivers -v0x24c2520_0 .net *"_s472", 0 0, L_0x24ec6c0; 1 drivers -v0x24c25c0_0 .net *"_s485", 0 0, L_0x24ed420; 1 drivers -v0x24c2660_0 .net *"_s486", 0 0, L_0x24ed510; 1 drivers -v0x24c2700_0 .net *"_s49", 0 0, L_0x24e4090; 1 drivers -v0x24c27a0_0 .net *"_s490", 1 0, L_0x250f7c0; 1 drivers -v0x24c2840_0 .net *"_s492", 0 0, L_0x24edf10; 1 drivers -v0x24c28e0_0 .net *"_s497", 0 0, L_0x24ee0e0; 1 drivers -v0x24c3bc0_0 .net *"_s498", 0 0, L_0x24ee3f0; 1 drivers -v0x24c2a00_0 .net *"_s501", 0 0, L_0x24ee4a0; 1 drivers -v0x24c2aa0_0 .net *"_s502", 0 0, L_0x24ee5d0; 1 drivers -v0x24c2b40_0 .net *"_s515", 0 0, L_0x24ee8f0; 1 drivers -v0x24c2be0_0 .net *"_s516", 0 0, L_0x24eea10; 1 drivers -v0x24c2c80_0 .net *"_s520", 1 0, L_0x250f870; 1 drivers -v0x24c2d20_0 .net *"_s522", 0 0, L_0x24ee1d0; 1 drivers -v0x24c2dc0_0 .net *"_s527", 0 0, L_0x24eeb30; 1 drivers -v0x24c2e60_0 .net *"_s528", 0 0, L_0x24eee60; 1 drivers -v0x24c2f00_0 .net *"_s53", 0 0, L_0x24e4310; 1 drivers -v0x24c2fa0_0 .net *"_s531", 0 0, L_0x24eef10; 1 drivers -v0x24c3040_0 .net *"_s532", 0 0, L_0x24ef040; 1 drivers -v0x24c30e0_0 .net *"_s54", 0 0, L_0x24e43b0; 1 drivers -v0x24c3180_0 .net *"_s544", 2 0, C4<001>; 1 drivers -v0x24c3220_0 .net *"_s566", 1 0, C4<11>; 1 drivers -v0x24c32c0_0 .net *"_s568", 1 0, C4<00>; 1 drivers -v0x24c3360_0 .net *"_s57", 0 0, L_0x24e4460; 1 drivers -v0x24c3400_0 .net *"_s573", 0 0, L_0x24ef350; 1 drivers -v0x24c34a0_0 .net *"_s575", 0 0, L_0x24ef5f0; 1 drivers -v0x24c3540_0 .net *"_s576", 0 0, L_0x24ef6e0; 1 drivers -v0x24c35e0_0 .net *"_s584", 1 0, C4<01>; 1 drivers -v0x24c3680_0 .net *"_s593", 0 0, L_0x24efac0; 1 drivers -v0x24c3720_0 .net *"_s594", 0 0, L_0x24efb60; 1 drivers -v0x24c37c0_0 .net *"_s599", 0 0, L_0x24f0400; 1 drivers -v0x24c3860_0 .net *"_s60", 0 0, L_0x24e4280; 1 drivers -v0x24c3900_0 .net *"_s600", 0 0, L_0x24f04a0; 1 drivers -v0x24c39a0_0 .net *"_s604", 1 0, L_0x250f920; 1 drivers -v0x24c3a40_0 .net *"_s606", 0 0, L_0x24f0530; 1 drivers -v0x24c3ae0_0 .net *"_s611", 0 0, L_0x24effc0; 1 drivers -v0x24c4ef0_0 .net *"_s612", 0 0, L_0x24f00f0; 1 drivers -v0x24c4f70_0 .net *"_s615", 0 0, L_0x24f01e0; 1 drivers -v0x24c3c40_0 .net *"_s616", 0 0, L_0x24f0d60; 1 drivers -v0x24c3ce0_0 .net *"_s62", 0 0, L_0x24e46b0; 1 drivers -v0x24c3d80_0 .net *"_s635", 0 0, L_0x24f14b0; 1 drivers -v0x24c3e20_0 .net *"_s636", 0 0, L_0x24e5cb0; 1 drivers -v0x24c3ec0_0 .net *"_s647", 0 0, L_0x24f0760; 1 drivers -v0x24c3f60_0 .net *"_s653", 0 0, L_0x24f1bf0; 1 drivers -v0x24c4000_0 .net *"_s659", 0 0, L_0x24f0b00; 1 drivers -v0x24c40a0_0 .net *"_s66", 0 0, L_0x24e4610; 1 drivers -v0x24c4140_0 .net *"_s665", 0 0, L_0x24f1d50; 1 drivers -v0x24c41e0_0 .net *"_s668", 1 0, C4<00>; 1 drivers -v0x24c4280_0 .net *"_s672", 1 0, L_0x250f9d0; 1 drivers -v0x24c4320_0 .net *"_s68", 0 0, L_0x24e4950; 1 drivers -v0x24c43c0_0 .net *"_s686", 1 0, C4<00>; 1 drivers -v0x24c4460_0 .net *"_s690", 1 0, L_0x250dfd0; 1 drivers -v0x24c4500_0 .net *"_s70", 0 0, L_0x24e48a0; 1 drivers -v0x24c45a0_0 .net *"_s704", 1 0, C4<00>; 1 drivers -v0x24c4640_0 .net *"_s708", 1 0, L_0x250e0d0; 1 drivers -v0x24c46e0_0 .net *"_s722", 1 0, C4<00>; 1 drivers -v0x24c4780_0 .net *"_s726", 1 0, L_0x250e1d0; 1 drivers -v0x24c4820_0 .net *"_s73", 0 0, L_0x24e4ac0; 1 drivers -v0x24c48c0_0 .net *"_s74", 0 0, L_0x24e4500; 1 drivers -v0x24c4960_0 .net *"_s76", 0 0, L_0x24e49b0; 1 drivers -v0x24c4a00_0 .net *"_s79", 0 0, L_0x24e4d60; 1 drivers -v0x24c4aa0_0 .net *"_s8", 0 0, L_0x24d8210; 1 drivers -v0x24c4b40_0 .net *"_s80", 0 0, L_0x24e4e00; 1 drivers -v0x24c4be0_0 .net *"_s804", 0 0, C4<1>; 1 drivers -v0x24c4c80_0 .net *"_s807", 9 0, L_0x24f3520; 1 drivers -v0x24c4d20_0 .net *"_s809", 2 0, L_0x24f47e0; 1 drivers -v0x24c4dc0_0 .net *"_s82", 0 0, L_0x24e4c90; 1 drivers -v0x24c4e60_0 .net *"_s827", 9 0, L_0x24f45e0; 1 drivers -v0x24c63c0_0 .net *"_s829", 2 0, L_0x24f4d30; 1 drivers -v0x24c6460_0 .net *"_s833", 0 0, L_0x24f4680; 1 drivers -v0x24c5010_0 .net *"_s834", 0 0, L_0x24f4720; 1 drivers -v0x24c50b0_0 .net *"_s851", 1 0, L_0x24f4c80; 1 drivers -v0x24c5150_0 .net *"_s861", 9 0, L_0x24f3ff0; 1 drivers -v0x24c51f0_0 .net *"_s863", 1 0, L_0x24f51d0; 1 drivers -v0x24c5290_0 .net *"_s87", 0 0, L_0x24e4eb0; 1 drivers -v0x24c5330_0 .net *"_s873", 0 0, L_0x24f5de0; 1 drivers -v0x24c53d0_0 .net *"_s875", 1 0, L_0x24f5e80; 1 drivers -v0x24c5470_0 .net *"_s88", 0 0, L_0x24e5180; 1 drivers -v0x24c5510_0 .net *"_s889", 0 0, L_0x24f57e0; 1 drivers -v0x24c55b0_0 .net *"_s90", 0 0, L_0x24e5230; 1 drivers -v0x24c5650_0 .net *"_s93", 0 0, L_0x24e5090; 1 drivers -v0x24c56f0_0 .net *"_s95", 0 0, L_0x24e5470; 1 drivers -v0x24c5790_0 .net *"_s96", 0 0, L_0x24e55a0; 1 drivers -v0x24c5830_0 .net *"_s98", 0 0, L_0x24e5600; 1 drivers -v0x24c58d0_0 .net *"_s999", 0 0, L_0x24f8230; 1 drivers -v0x24c5970_0 .net "b__h17187", 1 0, L_0x2509120; 1 drivers -v0x24c5a10_0 .net "b__h18595", 1 0, L_0x25091c0; 1 drivers -v0x24c5ab0_0 .net "b__h20003", 1 0, L_0x2509b90; 1 drivers -v0x24c5b50_0 .net "b__h21411", 1 0, L_0x2509c80; 1 drivers -v0x24c5bf0_0 .net "b__h24879", 2 0, L_0x2509d70; 1 drivers -v0x24c5c90_0 .net "b__h31747", 1 0, L_0x2508530; 1 drivers -v0x24c5d30_0 .net "b__h32070", 1 0, L_0x25086b0; 1 drivers -v0x24c5dd0_0 .net "b__h33309", 1 0, L_0x25087e0; 1 drivers -v0x24c5e70_0 .var "f_l_entryVec_0", 10 0; -v0x24c5f10_0 .net "f_l_entryVec_0$D_IN", 10 0, C4<01010101010>; 1 drivers -v0x24c5fb0_0 .net "f_l_entryVec_0$EN", 0 0, L_0x24e9c80; 1 drivers -v0x24c6050_0 .net "f_l_entryVec_0_read__6_BITS_9_TO_0_59_EQ_hg_fi_ETC___d360", 0 0, L_0x25021c0; 1 drivers -v0x24c60f0_0 .var "f_l_entryVec_1", 10 0; -v0x24c6190_0 .net "f_l_entryVec_1$D_IN", 10 0, C4<01010101010>; 1 drivers -v0x24c6230_0 .net "f_l_entryVec_1$EN", 0 0, L_0x24e9f50; 1 drivers -v0x24c62d0_0 .net "f_l_entryVec_1_read__4_BITS_9_TO_0_56_EQ_hg_fi_ETC___d357", 0 0, L_0x2502480; 1 drivers -v0x24c7990_0 .var "f_l_entryVec_2", 10 0; -v0x24c64e0_0 .net "f_l_entryVec_2$D_IN", 10 0, C4<01010101010>; 1 drivers -v0x24c6580_0 .net "f_l_entryVec_2$EN", 0 0, L_0x24e9610; 1 drivers -v0x24c6620_0 .net "f_l_entryVec_2_read__01_BITS_9_TO_0_53_EQ_hg_f_ETC___d354", 0 0, L_0x25089f0; 1 drivers -v0x24c66c0_0 .net "f_l_entryVec_2_read__01_BIT_10_02_AND_f_l_entr_ETC___d363", 0 0, L_0x2508e60; 1 drivers -v0x24c6760_0 .var "f_l_entryVec_3", 10 0; -v0x24c6800_0 .net "f_l_entryVec_3$D_IN", 10 0, C4<01010101010>; 1 drivers -v0x24c68a0_0 .net "f_l_entryVec_3$EN", 0 0, L_0x24ea360; 1 drivers -v0x24c6940_0 .var "f_l_lockVec_0_empty", 0 0; -v0x24c69e0_0 .net "f_l_lockVec_0_empty$D_IN", 0 0, L_0x24e9d30; 1 drivers -v0x24c6a80_0 .net "f_l_lockVec_0_empty$EN", 0 0, C4<0>; 1 drivers -v0x24c6b20_0 .net "f_l_lockVec_0_nextId_dummy2_0$D_IN", 0 0, C4<0>; 1 drivers -v0x24c6bd0_0 .net "f_l_lockVec_0_nextId_dummy2_0$EN", 0 0, C4<0>; 1 drivers -v0x24c6c80_0 .net "f_l_lockVec_0_nextId_dummy2_1$D_IN", 0 0, C4<0>; 1 drivers -v0x24c6d00_0 .net "f_l_lockVec_0_nextId_dummy2_1$EN", 0 0, C4<0>; 1 drivers -v0x24c6db0_0 .net "f_l_lockVec_0_nextId_dummy2_1$Q_OUT", 0 0, C4<1>; 1 drivers -v0x24c6e60_0 .var "f_l_lockVec_0_nextId_rl", 1 0; -v0x24c6ee0_0 .net "f_l_lockVec_0_nextId_rl$D_IN", 1 0, L_0x24ea5f0; 1 drivers -v0x24c6f60_0 .net "f_l_lockVec_0_nextId_rl$EN", 0 0, C4<1>; 1 drivers -v0x24c6fe0_0 .var "f_l_lockVec_0_owner", 1 0; -v0x24c7060_0 .net "f_l_lockVec_0_owner$D_IN", 1 0, C4<00>; 1 drivers -v0x24c7100_0 .net "f_l_lockVec_0_owner$EN", 0 0, C4<0>; 1 drivers -v0x24c71a0_0 .var "f_l_lockVec_1_empty", 0 0; -v0x24c7240_0 .net "f_l_lockVec_1_empty$D_IN", 0 0, L_0x24ea450; 1 drivers -v0x24c72e0_0 .net "f_l_lockVec_1_empty$EN", 0 0, C4<0>; 1 drivers -v0x24c7380_0 .net "f_l_lockVec_1_nextId_dummy2_0$D_IN", 0 0, C4<0>; 1 drivers -v0x24c7430_0 .net "f_l_lockVec_1_nextId_dummy2_0$EN", 0 0, C4<0>; 1 drivers -v0x24c74e0_0 .net "f_l_lockVec_1_nextId_dummy2_1$D_IN", 0 0, C4<0>; 1 drivers -v0x24c7590_0 .net "f_l_lockVec_1_nextId_dummy2_1$EN", 0 0, C4<0>; 1 drivers -v0x24c7640_0 .net "f_l_lockVec_1_nextId_dummy2_1$Q_OUT", 0 0, C4<1>; 1 drivers -v0x24c76f0_0 .var "f_l_lockVec_1_nextId_rl", 1 0; -v0x24c7770_0 .net "f_l_lockVec_1_nextId_rl$D_IN", 1 0, L_0x24ea590; 1 drivers -v0x24c77f0_0 .net "f_l_lockVec_1_nextId_rl$EN", 0 0, C4<1>; 1 drivers -v0x24c7870_0 .var "f_l_lockVec_1_owner", 1 0; -v0x24c78f0_0 .net "f_l_lockVec_1_owner$D_IN", 1 0, C4<00>; 1 drivers -v0x24c8fe0_0 .net "f_l_lockVec_1_owner$EN", 0 0, C4<0>; 1 drivers -v0x24c9060_0 .var "f_l_lockVec_2_empty", 0 0; -v0x24c7a30_0 .net "f_l_lockVec_2_empty$D_IN", 0 0, L_0x24eaf70; 1 drivers -v0x24c7ad0_0 .net "f_l_lockVec_2_empty$EN", 0 0, C4<0>; 1 drivers -v0x24c7b70_0 .net "f_l_lockVec_2_nextId_dummy2_0$D_IN", 0 0, C4<0>; 1 drivers -v0x24c7c20_0 .net "f_l_lockVec_2_nextId_dummy2_0$EN", 0 0, C4<0>; 1 drivers -v0x24c7cd0_0 .net "f_l_lockVec_2_nextId_dummy2_1$D_IN", 0 0, C4<0>; 1 drivers -v0x24c7d80_0 .net "f_l_lockVec_2_nextId_dummy2_1$EN", 0 0, C4<0>; 1 drivers -v0x24c7e30_0 .net "f_l_lockVec_2_nextId_dummy2_1$Q_OUT", 0 0, C4<1>; 1 drivers -v0x24c7ee0_0 .var "f_l_lockVec_2_nextId_rl", 1 0; -v0x24c7f60_0 .net "f_l_lockVec_2_nextId_rl$D_IN", 1 0, L_0x24ea960; 1 drivers -v0x24c7fe0_0 .net "f_l_lockVec_2_nextId_rl$EN", 0 0, C4<1>; 1 drivers -v0x24c8060_0 .var "f_l_lockVec_2_owner", 1 0; -v0x24c80e0_0 .net "f_l_lockVec_2_owner$D_IN", 1 0, C4<00>; 1 drivers -v0x24c8160_0 .net "f_l_lockVec_2_owner$EN", 0 0, C4<0>; 1 drivers -v0x24c8200_0 .var "f_l_lockVec_3_empty", 0 0; -v0x24c82a0_0 .net "f_l_lockVec_3_empty$D_IN", 0 0, L_0x24eb470; 1 drivers -v0x24c8340_0 .net "f_l_lockVec_3_empty$EN", 0 0, C4<0>; 1 drivers -v0x24c83e0_0 .net "f_l_lockVec_3_nextId_dummy2_0$D_IN", 0 0, C4<0>; 1 drivers -v0x24c8490_0 .net "f_l_lockVec_3_nextId_dummy2_0$EN", 0 0, C4<0>; 1 drivers -v0x24c8540_0 .net "f_l_lockVec_3_nextId_dummy2_1$D_IN", 0 0, C4<0>; 1 drivers -v0x24c85f0_0 .net "f_l_lockVec_3_nextId_dummy2_1$EN", 0 0, C4<0>; 1 drivers -v0x24c86a0_0 .net "f_l_lockVec_3_nextId_dummy2_1$Q_OUT", 0 0, C4<1>; 1 drivers -v0x24c8750_0 .var "f_l_lockVec_3_nextId_rl", 1 0; -v0x24c87d0_0 .net "f_l_lockVec_3_nextId_rl$D_IN", 1 0, L_0x24eb580; 1 drivers -v0x24c8850_0 .net "f_l_lockVec_3_nextId_rl$EN", 0 0, C4<1>; 1 drivers -v0x24c88d0_0 .var "f_l_lockVec_3_owner", 1 0; -v0x24c8950_0 .net "f_l_lockVec_3_owner$D_IN", 1 0, C4<00>; 1 drivers -v0x24c89d0_0 .net "f_l_lockVec_3_owner$EN", 0 0, C4<0>; 1 drivers -v0x24c8a70_0 .var "h_l_entryVec_0", 10 0; -v0x24c8b10_0 .net "h_l_entryVec_0$D_IN", 10 0, L_0x24eb3b0; 1 drivers -v0x24c8bb0_0 .net "h_l_entryVec_0$EN", 0 0, L_0x24eaa90; 1 drivers -v0x24c8c50_0 .var "h_l_entryVec_1", 10 0; -v0x24c8cf0_0 .net "h_l_entryVec_1$D_IN", 10 0, L_0x24eab40; 1 drivers -v0x24c8d90_0 .net "h_l_entryVec_1$EN", 0 0, L_0x24ebcd0; 1 drivers -v0x24c8e30_0 .var "h_l_entryVec_2", 10 0; -v0x24c8ed0_0 .net "h_l_entryVec_2$D_IN", 10 0, L_0x24ebdc0; 1 drivers -v0x24ca7d0_0 .net "h_l_entryVec_2$EN", 0 0, L_0x24eb990; 1 drivers -v0x24c90e0_0 .net "h_l_entryVec_2_read__25_BIT_10_26_AND_IF_h_l_e_ETC___d458", 0 0, L_0x25097f0; 1 drivers -v0x24c9180_0 .net "h_l_entryVec_2_read__25_BIT_10_26_AND_IF_h_l_e_ETC___d562", 0 0, L_0x250a0c0; 1 drivers -v0x24c9220_0 .var "h_l_entryVec_3", 10 0; -v0x24c92c0_0 .net "h_l_entryVec_3$D_IN", 10 0, L_0x24eba40; 1 drivers -v0x24c9360_0 .net "h_l_entryVec_3$EN", 0 0, L_0x24e7660; 1 drivers -v0x24c9400_0 .net "h_l_entryVec_3_read__32_BIT_10_33_AND_IF_h_l_e_ETC___d563", 0 0, L_0x250a5e0; 1 drivers -v0x24c94a0_0 .net "h_l_lockVec_0_doRel$whas", 0 0, L_0x24e6c70; 1 drivers -v0x24c9540_0 .var "h_l_lockVec_0_empty", 0 0; -v0x24c95e0_0 .net "h_l_lockVec_0_empty$D_IN", 0 0, L_0x24ec1e0; 1 drivers -v0x24c9680_0 .net "h_l_lockVec_0_empty$EN", 0 0, L_0x24ed2d0; 1 drivers -v0x24c9720_0 .net "h_l_lockVec_0_nextId_dummy2_0$D_IN", 0 0, C4<1>; 1 drivers -v0x24c97d0_0 .net "h_l_lockVec_0_nextId_dummy2_0$EN", 0 0, L_0x24f3980; 1 drivers -v0x24c9880_0 .net "h_l_lockVec_0_nextId_dummy2_0$Q_OUT", 0 0, C4<1>; 1 drivers -v0x24c9930_0 .net "h_l_lockVec_0_nextId_dummy2_1$D_IN", 0 0, C4<0>; 1 drivers -v0x24c99e0_0 .net "h_l_lockVec_0_nextId_dummy2_1$EN", 0 0, C4<0>; 1 drivers -v0x24c9a90_0 .net "h_l_lockVec_0_nextId_dummy2_1$Q_OUT", 0 0, C4<1>; 1 drivers -v0x24c9b40_0 .net "h_l_lockVec_0_nextId_lat_0$whas", 0 0, L_0x24e5ef0; 1 drivers -v0x24c9bc0_0 .var "h_l_lockVec_0_nextId_rl", 1 0; -v0x24c9c40_0 .net "h_l_lockVec_0_nextId_rl$D_IN", 1 0, L_0x24ed330; 1 drivers -v0x24c9cc0_0 .net "h_l_lockVec_0_nextId_rl$EN", 0 0, C4<1>; 1 drivers -v0x24c9d40_0 .var "h_l_lockVec_0_owner", 1 0; -v0x24c9dc0_0 .net "h_l_lockVec_0_owner$D_IN", 1 0, L_0x24ec4b0; 1 drivers -v0x24c9e40_0 .net "h_l_lockVec_0_owner$EN", 0 0, L_0x24ec590; 1 drivers -v0x24c9ee0_0 .net "h_l_lockVec_1_doRel$whas", 0 0, L_0x24e7120; 1 drivers -v0x24c9f80_0 .var "h_l_lockVec_1_empty", 0 0; -v0x24ca020_0 .net "h_l_lockVec_1_empty$D_IN", 0 0, L_0x24ed000; 1 drivers -v0x24ca0c0_0 .net "h_l_lockVec_1_empty$EN", 0 0, L_0x24ede60; 1 drivers -v0x24ca160_0 .net "h_l_lockVec_1_nextId_dummy2_0$D_IN", 0 0, C4<1>; 1 drivers -v0x24ca210_0 .net "h_l_lockVec_1_nextId_dummy2_0$EN", 0 0, L_0x24f3c50; 1 drivers -v0x24ca2c0_0 .net "h_l_lockVec_1_nextId_dummy2_0$Q_OUT", 0 0, C4<1>; 1 drivers -v0x24ca370_0 .net "h_l_lockVec_1_nextId_dummy2_1$D_IN", 0 0, C4<0>; 1 drivers -v0x24ca420_0 .net "h_l_lockVec_1_nextId_dummy2_1$EN", 0 0, C4<0>; 1 drivers -v0x24ca4d0_0 .net "h_l_lockVec_1_nextId_dummy2_1$Q_OUT", 0 0, C4<1>; 1 drivers -v0x24ca580_0 .net "h_l_lockVec_1_nextId_lat_0$whas", 0 0, L_0x24e6d70; 1 drivers -v0x24ca600_0 .var "h_l_lockVec_1_nextId_rl", 1 0; -v0x24ca680_0 .net "h_l_lockVec_1_nextId_rl$D_IN", 1 0, L_0x24d73a0; 1 drivers -v0x24ca700_0 .net "h_l_lockVec_1_nextId_rl$EN", 0 0, C4<1>; 1 drivers -v0x24cc070_0 .var "h_l_lockVec_1_owner", 1 0; -v0x24ca850_0 .net "h_l_lockVec_1_owner$D_IN", 1 0, L_0x24edb60; 1 drivers -v0x24ca8d0_0 .net "h_l_lockVec_1_owner$EN", 0 0, L_0x24ed3c0; 1 drivers -v0x24ca970_0 .net "h_l_lockVec_2_doRel$whas", 0 0, L_0x24e7b30; 1 drivers -v0x24caa10_0 .var "h_l_lockVec_2_empty", 0 0; -v0x24caab0_0 .net "h_l_lockVec_2_empty$D_IN", 0 0, L_0x24edfb0; 1 drivers -v0x24cab50_0 .net "h_l_lockVec_2_empty$EN", 0 0, L_0x24ee6c0; 1 drivers -v0x24cabf0_0 .net "h_l_lockVec_2_nextId_dummy2_0$D_IN", 0 0, C4<1>; 1 drivers -v0x24caca0_0 .net "h_l_lockVec_2_nextId_dummy2_0$EN", 0 0, L_0x24f3eb0; 1 drivers -v0x24cad50_0 .net "h_l_lockVec_2_nextId_dummy2_0$Q_OUT", 0 0, C4<1>; 1 drivers -v0x24cadd0_0 .net "h_l_lockVec_2_nextId_dummy2_1$D_IN", 0 0, C4<0>; 1 drivers -v0x24cae80_0 .net "h_l_lockVec_2_nextId_dummy2_1$EN", 0 0, C4<0>; 1 drivers -v0x24caf00_0 .net "h_l_lockVec_2_nextId_dummy2_1$Q_OUT", 0 0, C4<1>; 1 drivers -v0x24cafb0_0 .net "h_l_lockVec_2_nextId_lat_0$whas", 0 0, L_0x24e7440; 1 drivers -v0x24cb030_0 .var "h_l_lockVec_2_nextId_rl", 1 0; -v0x24cb0b0_0 .net "h_l_lockVec_2_nextId_rl$D_IN", 1 0, L_0x24ee720; 1 drivers -v0x24cb130_0 .net "h_l_lockVec_2_nextId_rl$EN", 0 0, C4<1>; 1 drivers -v0x24cb1b0_0 .var "h_l_lockVec_2_owner", 1 0; -v0x24cb250_0 .net "h_l_lockVec_2_owner$D_IN", 1 0, L_0x24ee7b0; 1 drivers -v0x24cb2f0_0 .net "h_l_lockVec_2_owner$EN", 0 0, L_0x24ee890; 1 drivers -v0x24cb390_0 .net "h_l_lockVec_3_doRel$whas", 0 0, L_0x24e7f50; 1 drivers -v0x24cb430_0 .var "h_l_lockVec_3_empty", 0 0; -v0x24cb4d0_0 .net "h_l_lockVec_3_empty$D_IN", 0 0, L_0x24ee2a0; 1 drivers -v0x24cb570_0 .net "h_l_lockVec_3_empty$EN", 0 0, L_0x24ef0d0; 1 drivers -v0x24cb610_0 .net "h_l_lockVec_3_nextId_dummy2_0$D_IN", 0 0, C4<1>; 1 drivers -v0x24cb6c0_0 .net "h_l_lockVec_3_nextId_dummy2_0$EN", 0 0, L_0x24f3310; 1 drivers -v0x24cb740_0 .net "h_l_lockVec_3_nextId_dummy2_0$Q_OUT", 0 0, C4<1>; 1 drivers -v0x24cb7f0_0 .net "h_l_lockVec_3_nextId_dummy2_1$D_IN", 0 0, C4<0>; 1 drivers -v0x24cb8a0_0 .net "h_l_lockVec_3_nextId_dummy2_1$EN", 0 0, C4<0>; 1 drivers -v0x24cb950_0 .net "h_l_lockVec_3_nextId_dummy2_1$Q_OUT", 0 0, C4<1>; 1 drivers -v0x24cba00_0 .net "h_l_lockVec_3_nextId_lat_0$whas", 0 0, L_0x24e7c20; 1 drivers -v0x24cba80_0 .var "h_l_lockVec_3_nextId_rl", 1 0; -v0x24cbb00_0 .net "h_l_lockVec_3_nextId_rl$D_IN", 1 0, L_0x24ef130; 1 drivers -v0x24cbb80_0 .net "h_l_lockVec_3_nextId_rl$EN", 0 0, C4<1>; 1 drivers -v0x24cbc00_0 .var "h_l_lockVec_3_owner", 1 0; -v0x24cbc80_0 .net "h_l_lockVec_3_owner$D_IN", 1 0, L_0x24ef420; 1 drivers -v0x24cbd20_0 .net "h_l_lockVec_3_owner$EN", 0 0, L_0x24ed8e0; 1 drivers -v0x24cbdc0_0 .net "h_l_resVec_0$whas", 0 0, L_0x24e8000; 1 drivers -v0x24cbe60_0 .net "h_l_resVec_1$whas", 0 0, L_0x24e8450; 1 drivers -v0x24cbf00_0 .net "h_l_resVec_2$whas", 0 0, L_0x24e8550; 1 drivers -v0x24cbfa0_0 .net "h_l_resVec_3$whas", 0 0, L_0x24e74f0; 1 drivers -v0x24cda60_0 .var "hg", 2 0; -v0x24cdae0_0 .net "hg$D_IN", 2 0, L_0x24ed970; 1 drivers -v0x24cc0f0_0 .net "hg$EN", 0 0, L_0x24eebd0; 1 drivers -v0x24cc190_0 .var "hg_feature_lock_region", 0 0; -v0x24cc230_0 .net "hg_feature_lock_region$D_IN", 0 0, C4<0>; 1 drivers -v0x24cc2d0_0 .net "hg_feature_lock_region$EN", 0 0, C4<0>; 1 drivers -v0x24cc370_0 .net "hg_fifo_Stage__0_TO_Stage__1$CLR", 0 0, C4<0>; 1 drivers -v0x24cc3f0_0 .net "hg_fifo_Stage__0_TO_Stage__1$DEQ", 0 0, L_0x24f48e0; 1 drivers -v0x24cc470_0 .net "hg_fifo_Stage__0_TO_Stage__1$D_IN", 47 0, L_0x24f2ec0; 1 drivers -v0x24cc520_0 .net "hg_fifo_Stage__0_TO_Stage__1$D_OUT", 47 0, v0x2457dc0_0; 1 drivers -v0x24cc5d0_0 .net "hg_fifo_Stage__0_TO_Stage__1$EMPTY_N", 0 0, L_0x24d8e30; 1 drivers -v0x24cc680_0 .net "hg_fifo_Stage__0_TO_Stage__1$ENQ", 0 0, L_0x24f4880; 1 drivers -v0x24cc730_0 .net "hg_fifo_Stage__0_TO_Stage__1$FULL_N", 0 0, L_0x24d87f0; 1 drivers -v0x24cc7e0_0 .net "hg_fifo_Stage__1_TO_Stage__2$CLR", 0 0, C4<0>; 1 drivers -v0x24cc860_0 .net "hg_fifo_Stage__1_TO_Stage__2$DEQ", 0 0, L_0x24f44b0; 1 drivers -v0x24cc8e0_0 .net "hg_fifo_Stage__1_TO_Stage__2$D_IN", 2 0, L_0x24f3090; 1 drivers -v0x24cc990_0 .net "hg_fifo_Stage__1_TO_Stage__2$D_OUT", 2 0, v0x2385210_0; 1 drivers -v0x24cca40_0 .net "hg_fifo_Stage__1_TO_Stage__2$EMPTY_N", 0 0, L_0x24d9e70; 1 drivers -v0x24ccaf0_0 .net "hg_fifo_Stage__1_TO_Stage__2$ENQ", 0 0, L_0x24f3180; 1 drivers -v0x24ccb70_0 .net "hg_fifo_Stage__1_TO_Stage__2$FULL_N", 0 0, L_0x24d9e10; 1 drivers -v0x24ccc20_0 .net "hg_fifo_Start_TO_Stage__0$CLR", 0 0, C4<0>; 1 drivers -v0x24ccca0_0 .net "hg_fifo_Start_TO_Stage__0$DEQ", 0 0, L_0x24f50e0; 1 drivers -v0x24ccd20_0 .net "hg_fifo_Start_TO_Stage__0$D_IN", 44 0, L_0x24f4e60; 1 drivers -v0x24ccdd0_0 .net "hg_fifo_Start_TO_Stage__0$D_OUT", 44 0, v0x242c4b0_0; 1 drivers -v0x24cce80_0 .net "hg_fifo_Start_TO_Stage__0$EMPTY_N", 0 0, L_0x24daf70; 1 drivers -v0x24ccf30_0 .net "hg_fifo_Start_TO_Stage__0$ENQ", 0 0, L_0x24f5030; 1 drivers -v0x24ccfe0_0 .net "hg_fifo_Start_TO_Stage__0$FULL_N", 0 0, L_0x24daf10; 1 drivers -v0x24cd090_0 .var "hg_fifo__input__TO_Start_rv", 13 0; -v0x24cd110_0 .net "hg_fifo__input__TO_Start_rv$D_IN", 13 0, L_0x24ef8d0; 1 drivers -v0x24cd190_0 .net "hg_fifo__input__TO_Start_rv$EN", 0 0, C4<1>; 1 drivers -v0x24cd210_0 .net "hg_fifo__input__TO_Start_rv$EN_port0__write", 0 0, L_0x24e92d0; 1 drivers -v0x24cd290_0 .net "hg_fifo__input__TO_Start_rv$EN_port1__write", 0 0, L_0x24e9ac0; 1 drivers -v0x24cd310_0 .net "hg_fifo__input__TO_Start_rv$port0__write_1", 13 0, L_0x24e98d0; 1 drivers -v0x24cd390_0 .net "hg_fifo__input__TO_Start_rv$port1__read", 13 0, L_0x24e9760; 1 drivers -v0x24cd410_0 .net "hg_fifo__input__TO_Start_rv$port2__read", 13 0, L_0x24e8110; 1 drivers -v0x24cd490_0 .var "hg_h_lock_region", 0 0; -v0x24cd510_0 .net "hg_h_lock_region$D_IN", 0 0, C4<0>; 1 drivers -v0x24cd590_0 .net "hg_h_lock_region$EN", 0 0, C4<0>; 1 drivers -v0x24cd610_0 .net "hg_outputQueue_nextTag_dummy2_0$D_IN", 0 0, C4<1>; 1 drivers -v0x24cd6c0_0 .net "hg_outputQueue_nextTag_dummy2_0$EN", 0 0, L_0x24f4a60; 1 drivers -v0x24cd770_0 .net "hg_outputQueue_nextTag_dummy2_0$Q_OUT", 0 0, C4<1>; 1 drivers -v0x24cd7f0_0 .net "hg_outputQueue_nextTag_dummy2_1$D_IN", 0 0, C4<0>; 1 drivers -v0x24cd8a0_0 .net "hg_outputQueue_nextTag_dummy2_1$EN", 0 0, C4<0>; 1 drivers -v0x24cd950_0 .net "hg_outputQueue_nextTag_dummy2_1$Q_OUT", 0 0, C4<1>; 1 drivers -v0x24cf630_0 .var "hg_outputQueue_nextTag_rl", 2 0; -v0x24cf6b0_0 .net "hg_outputQueue_nextTag_rl$D_IN", 2 0, L_0x24eed00; 1 drivers -v0x24cdb60_0 .net "hg_outputQueue_nextTag_rl$EN", 0 0, C4<1>; 1 drivers -v0x24cdbe0_0 .var "hg_outputQueue_val", 1 0; -v0x24cdc60_0 .net "hg_outputQueue_val$D_IN", 1 0, L_0x24ef190; 1 drivers -v0x24cdce0_0 .net "hg_outputQueue_val$EN", 0 0, L_0x24ef790; 1 drivers -v0x24cdd60_0 .var "hg_weight_lock_region", 0 0; -v0x24cdde0_0 .net "hg_weight_lock_region$D_IN", 0 0, C4<0>; 1 drivers -v0x24cde80_0 .net "hg_weight_lock_region$EN", 0 0, C4<0>; 1 drivers -v0x24cdf20_0 .var "o", 1 0; -v0x24cdfc0_0 .net "o$D_IN", 1 0, L_0x24efd10; 1 drivers -v0x24ce060_0 .net "o$EN", 0 0, L_0x24efed0; 1 drivers -v0x24ce100_0 .var "o_busyReg", 0 0; -v0x24ce1a0_0 .net "o_busyReg$D_IN", 0 0, L_0x24efa20; 1 drivers -v0x24ce240_0 .net "o_busyReg$EN", 0 0, L_0x24efe10; 1 drivers -v0x24ce2e0_0 .net "o_doRel$whas", 0 0, L_0x24e8c80; 1 drivers -v0x24ce380_0 .var "o_empty", 0 0; -v0x24ce420_0 .net "o_empty$D_IN", 0 0, L_0x24efc60; 1 drivers -v0x24ce4c0_0 .net "o_empty$EN", 0 0, L_0x24f0df0; 1 drivers -v0x24ce560_0 .net "o_fifo_Stage__1_TO_Stage__3$CLR", 0 0, C4<0>; 1 drivers -v0x24ce610_0 .net "o_fifo_Stage__1_TO_Stage__3$DEQ", 0 0, L_0x24f56f0; 1 drivers -v0x24ce690_0 .net "o_fifo_Stage__1_TO_Stage__3$D_IN", 4 0, L_0x24f5550; 1 drivers -v0x24ce740_0 .net "o_fifo_Stage__1_TO_Stage__3$D_OUT", 4 0, v0x23c8070_0; 1 drivers -v0x24ce7f0_0 .net "o_fifo_Stage__1_TO_Stage__3$EMPTY_N", 0 0, L_0x24dc1e0; 1 drivers -v0x24ce8a0_0 .net "o_fifo_Stage__1_TO_Stage__3$ENQ", 0 0, L_0x24f5690; 1 drivers -v0x24ce950_0 .net "o_fifo_Stage__1_TO_Stage__3$FULL_N", 0 0, L_0x24d8d90; 1 drivers -v0x24cea00_0 .net "o_fifo_Start_TO_Stage__1$CLR", 0 0, C4<0>; 1 drivers -v0x24ceab0_0 .net "o_fifo_Start_TO_Stage__1$DEQ", 0 0, L_0x24f5460; 1 drivers -v0x24ceb60_0 .net "o_fifo_Start_TO_Stage__1$D_IN", 14 0, L_0x24f5270; 1 drivers -v0x24cec10_0 .net "o_fifo_Start_TO_Stage__1$D_OUT", 14 0, v0x23a2e70_0; 1 drivers -v0x24cecc0_0 .net "o_fifo_Start_TO_Stage__1$EMPTY_N", 0 0, L_0x24dd2a0; 1 drivers -v0x24ced70_0 .net "o_fifo_Start_TO_Stage__1$ENQ", 0 0, L_0x24f5400; 1 drivers -v0x24cee20_0 .net "o_fifo_Start_TO_Stage__1$FULL_N", 0 0, L_0x24dd240; 1 drivers -v0x24ceed0_0 .net "o_fifo_Start_TO_Stage__3$CLR", 0 0, C4<0>; 1 drivers -v0x24cef80_0 .net "o_fifo_Start_TO_Stage__3$DEQ", 0 0, L_0x24f6110; 1 drivers -v0x24cf000_0 .net "o_fifo_Start_TO_Stage__3$D_IN", 2 0, L_0x24f5f20; 1 drivers -v0x24cf0b0_0 .net "o_fifo_Start_TO_Stage__3$D_OUT", 2 0, v0x2387990_0; 1 drivers -v0x24cf160_0 .net "o_fifo_Start_TO_Stage__3$EMPTY_N", 0 0, L_0x24de3a0; 1 drivers -v0x24cf210_0 .net "o_fifo_Start_TO_Stage__3$ENQ", 0 0, L_0x24f60b0; 1 drivers -v0x24cf2c0_0 .net "o_fifo_Start_TO_Stage__3$FULL_N", 0 0, L_0x24de340; 1 drivers -v0x24cf370_0 .net "o_fifo_Start_TO_Stage__3_1$CLR", 0 0, C4<0>; 1 drivers -v0x24cf420_0 .net "o_fifo_Start_TO_Stage__3_1$DEQ", 0 0, L_0x24f5880; 1 drivers -v0x24cf4d0_0 .net "o_fifo_Start_TO_Stage__3_1$D_IN", 1 0, L_0x24f61b0; 1 drivers -v0x24cf580_0 .net "o_fifo_Start_TO_Stage__3_1$EMPTY_N", 0 0, L_0x24df4a0; 1 drivers -v0x24d1360_0 .net "o_fifo_Start_TO_Stage__3_1$ENQ", 0 0, L_0x24f4450; 1 drivers -v0x24d13e0_0 .net "o_fifo_Start_TO_Stage__3_1$FULL_N", 0 0, L_0x24df440; 1 drivers -v0x24cf730_0 .net "o_fifo_Start_TO_Stage__3_first__77_BIT_2_78_OR_ETC___d695", 0 0, L_0x24e53e0; 1 drivers -v0x24cf7b0_0 .net "o_fifo__input__TO_Start_enq_data$wget", 11 0, L_0x24e8310; 1 drivers -v0x24cf830_0 .net "o_fifo__input__TO_Start_enq_data$whas", 0 0, L_0x24e8710; 1 drivers -v0x24cf8b0_0 .net "o_fifo__input__TO_Start_f$CLR", 0 0, C4<0>; 1 drivers -v0x24cf960_0 .net "o_fifo__input__TO_Start_f$DEQ", 0 0, L_0x24f5b20; 1 drivers -v0x24cfa10_0 .net "o_fifo__input__TO_Start_f$D_IN", 11 0, L_0x24f5970; 1 drivers -v0x24cfac0_0 .net "o_fifo__input__TO_Start_f$D_OUT", 11 0, v0x247f0f0_0; 1 drivers -v0x24cfb70_0 .net "o_fifo__input__TO_Start_f$EMPTY_N", 0 0, L_0x24e0510; 1 drivers -v0x24cfc20_0 .net "o_fifo__input__TO_Start_f$ENQ", 0 0, L_0x24f5a70; 1 drivers -v0x24cfcd0_0 .net "o_fifo__input__TO_Start_f$FULL_N", 0 0, L_0x24e04b0; 1 drivers -v0x24cfd80_0 .net "o_fifo__input__TO_Start_f_first__47_BITS_11_TO_ETC___d649", 0 0, L_0x250b500; 1 drivers -v0x24cfe00_0 .net "o_fifo__input__TO_Start_f_first__47_BITS_11_TO_ETC___d665", 0 0, L_0x250b640; 1 drivers -v0x24cfe80_0 .var "o_h_lock_region", 0 0; -v0x24cff00_0 .net "o_h_lock_region$D_IN", 0 0, C4<0>; 1 drivers -v0x24cff80_0 .net "o_h_lock_region$EN", 0 0, C4<0>; 1 drivers -v0x24d0000_0 .net "o_nextId_dummy2_0$D_IN", 0 0, C4<1>; 1 drivers -v0x24d00b0_0 .net "o_nextId_dummy2_0$EN", 0 0, L_0x24f6910; 1 drivers -v0x24d0160_0 .net "o_nextId_dummy2_0$Q_OUT", 0 0, C4<1>; 1 drivers -v0x24d0210_0 .net "o_nextId_dummy2_1$D_IN", 0 0, C4<0>; 1 drivers -v0x24d02c0_0 .net "o_nextId_dummy2_1$EN", 0 0, C4<0>; 1 drivers -v0x24d0370_0 .net "o_nextId_dummy2_1$Q_OUT", 0 0, C4<1>; 1 drivers -v0x24d0420_0 .var "o_nextId_rl", 1 0; -v0x24d04a0_0 .net "o_nextId_rl$D_IN", 1 0, L_0x24f0f30; 1 drivers -v0x24d0520_0 .net "o_nextId_rl$EN", 0 0, C4<1>; 1 drivers -v0x24d05a0_0 .net "o_outputQueue_nextTag_dummy2_0$D_IN", 0 0, C4<1>; 1 drivers -v0x24d0650_0 .net "o_outputQueue_nextTag_dummy2_0$EN", 0 0, L_0x24f6b70; 1 drivers -v0x24d0700_0 .net "o_outputQueue_nextTag_dummy2_0$Q_OUT", 0 0, C4<1>; 1 drivers -v0x24d07b0_0 .net "o_outputQueue_nextTag_dummy2_1$D_IN", 0 0, C4<0>; 1 drivers -v0x24d0860_0 .net "o_outputQueue_nextTag_dummy2_1$EN", 0 0, C4<0>; 1 drivers -v0x24d0910_0 .net "o_outputQueue_nextTag_dummy2_1$Q_OUT", 0 0, C4<1>; 1 drivers -v0x24d09c0_0 .var "o_outputQueue_nextTag_rl", 1 0; -v0x24d0a40_0 .net "o_outputQueue_nextTag_rl$D_IN", 1 0, L_0x24f1020; 1 drivers -v0x24d0ac0_0 .net "o_outputQueue_nextTag_rl$EN", 0 0, C4<1>; 1 drivers -v0x24d0b40_0 .var "o_outputQueue_val", 0 0; -v0x24d0bc0_0 .net "o_outputQueue_val$D_IN", 0 0, L_0x24f1420; 1 drivers -v0x24d0c40_0 .net "o_outputQueue_val$EN", 0 0, L_0x24f16e0; 1 drivers -v0x24d0cc0_0 .var "o_owner", 1 0; -v0x24d0d40_0 .net "o_owner$D_IN", 1 0, L_0x24f17e0; 1 drivers -v0x24d0dc0_0 .net "o_owner$EN", 0 0, L_0x24f0700; 1 drivers -v0x24d0e40_0 .net "tf_rf$ADDR_1", 9 0, L_0x24f6440; 1 drivers -v0x24d0ef0_0 .net "tf_rf$ADDR_2", 9 0, C4<0000000000>; 1 drivers -v0x24d0fa0_0 .net "tf_rf$ADDR_3", 9 0, C4<0000000000>; 1 drivers -v0x24d1050_0 .net "tf_rf$ADDR_4", 9 0, C4<0000000000>; 1 drivers -v0x24d10d0_0 .net "tf_rf$ADDR_5", 9 0, C4<0000000000>; 1 drivers -v0x24d1180_0 .net "tf_rf$ADDR_IN", 9 0, C4<0000000000>; 1 drivers -v0x24d1230_0 .net "tf_rf$D_IN", 15 0, C4<0000000000000000>; 1 drivers -v0x24d12e0_0 .net "tf_rf$D_OUT_1", 15 0, L_0x24e1860; 1 drivers -v0x24d3210_0 .net "tf_rf$WE", 0 0, C4<0>; 1 drivers -v0x24d1460_0 .net "th_rf$ADDR_1", 9 0, L_0x24f4340; 1 drivers -v0x24d1510_0 .net "th_rf$ADDR_2", 9 0, C4<0000000000>; 1 drivers -v0x24d15c0_0 .net "th_rf$ADDR_3", 9 0, C4<0000000000>; 1 drivers -v0x24d1670_0 .net "th_rf$ADDR_4", 9 0, C4<0000000000>; 1 drivers -v0x24d16f0_0 .net "th_rf$ADDR_5", 9 0, C4<0000000000>; 1 drivers -v0x24d17a0_0 .net "th_rf$ADDR_IN", 9 0, L_0x24f6cb0; 1 drivers -v0x24d1850_0 .net "th_rf$D_IN", 31 0, L_0x24f6e30; 1 drivers -v0x24d1900_0 .net "th_rf$D_OUT_1", 31 0, L_0x24e20d0; 1 drivers -v0x24d19b0_0 .net "th_rf$WE", 0 0, L_0x24f6ed0; 1 drivers -v0x24d1a60_0 .net "th_rf_sub_hg_fifo_Start_TO_Stage__0_first__41__ETC___d537", 31 0, L_0x250a740; 1 drivers -v0x24d1ae0_0 .net "tw_rf$ADDR_1", 9 0, L_0x24f7090; 1 drivers -v0x24d1b90_0 .net "tw_rf$ADDR_2", 9 0, C4<0000000000>; 1 drivers -v0x24d1c40_0 .net "tw_rf$ADDR_3", 9 0, C4<0000000000>; 1 drivers -v0x24d1cf0_0 .net "tw_rf$ADDR_4", 9 0, C4<0000000000>; 1 drivers -v0x24d1d70_0 .net "tw_rf$ADDR_5", 9 0, C4<0000000000>; 1 drivers -v0x24d1e20_0 .net "tw_rf$ADDR_IN", 9 0, C4<0000000000>; 1 drivers -v0x24d1ed0_0 .net "tw_rf$D_IN", 31 0, C4<00000000000000000000000000000000>; 1 drivers -v0x24d1f80_0 .net "tw_rf$D_OUT_1", 31 0, L_0x24e2940; 1 drivers -v0x24d2030_0 .net "tw_rf$WE", 0 0, C4<0>; 1 drivers -v0x24d20e0_0 .var "w_l_entryVec_0", 10 0; -v0x24d2160_0 .net "w_l_entryVec_0$D_IN", 10 0, C4<01010101010>; 1 drivers -v0x24d21e0_0 .net "w_l_entryVec_0$EN", 0 0, L_0x24f0860; 1 drivers -v0x24d2260_0 .net "w_l_entryVec_0_read__99_BITS_9_TO_0_98_EQ_hg_f_ETC___d399", 0 0, L_0x250aa30; 1 drivers -v0x24d22e0_0 .var "w_l_entryVec_1", 10 0; -v0x24d2360_0 .net "w_l_entryVec_1$D_IN", 10 0, C4<01010101010>; 1 drivers -v0x24d23e0_0 .net "w_l_entryVec_1$EN", 0 0, L_0x24f1cf0; 1 drivers -v0x24d2460_0 .net "w_l_entryVec_1_read__06_BITS_9_TO_0_95_EQ_hg_f_ETC___d396", 0 0, L_0x250acf0; 1 drivers -v0x24d24e0_0 .var "w_l_entryVec_2", 10 0; -v0x24d2560_0 .net "w_l_entryVec_2$D_IN", 10 0, C4<01010101010>; 1 drivers -v0x24d25e0_0 .net "w_l_entryVec_2$EN", 0 0, L_0x24f0c00; 1 drivers -v0x24d2660_0 .net "w_l_entryVec_2_read__13_BITS_9_TO_0_92_EQ_hg_f_ETC___d393", 0 0, L_0x250b9c0; 1 drivers -v0x24d26e0_0 .net "w_l_entryVec_2_read__13_BIT_10_14_AND_w_l_entr_ETC___d402", 0 0, L_0x250bf80; 1 drivers -v0x24d2760_0 .var "w_l_entryVec_3", 10 0; -v0x24d27e0_0 .net "w_l_entryVec_3$D_IN", 10 0, C4<01010101010>; 1 drivers -v0x24d2860_0 .net "w_l_entryVec_3$EN", 0 0, L_0x24f1e50; 1 drivers -v0x24d28e0_0 .var "w_l_lockVec_0_empty", 0 0; -v0x24d2960_0 .net "w_l_lockVec_0_empty$D_IN", 0 0, L_0x24f1fa0; 1 drivers -v0x24d29e0_0 .net "w_l_lockVec_0_empty$EN", 0 0, C4<0>; 1 drivers -v0x24d2a60_0 .net "w_l_lockVec_0_nextId_dummy2_0$D_IN", 0 0, C4<0>; 1 drivers -v0x24d2b10_0 .net "w_l_lockVec_0_nextId_dummy2_0$EN", 0 0, C4<0>; 1 drivers -v0x24d2bc0_0 .net "w_l_lockVec_0_nextId_dummy2_1$D_IN", 0 0, C4<0>; 1 drivers -v0x24d2c70_0 .net "w_l_lockVec_0_nextId_dummy2_1$EN", 0 0, C4<0>; 1 drivers -v0x24d2d20_0 .net "w_l_lockVec_0_nextId_dummy2_1$Q_OUT", 0 0, C4<1>; 1 drivers -v0x24d2dd0_0 .var "w_l_lockVec_0_nextId_rl", 1 0; -v0x24d2e50_0 .net "w_l_lockVec_0_nextId_rl$D_IN", 1 0, L_0x24f19c0; 1 drivers -v0x24d2ed0_0 .net "w_l_lockVec_0_nextId_rl$EN", 0 0, C4<1>; 1 drivers -v0x24d2f50_0 .var "w_l_lockVec_0_owner", 1 0; -v0x24d2fd0_0 .net "w_l_lockVec_0_owner$D_IN", 1 0, C4<00>; 1 drivers -v0x24d3050_0 .net "w_l_lockVec_0_owner$EN", 0 0, C4<0>; 1 drivers -v0x24d30d0_0 .var "w_l_lockVec_1_empty", 0 0; -v0x24d3150_0 .net "w_l_lockVec_1_empty$D_IN", 0 0, L_0x24f1140; 1 drivers -v0x24d51e0_0 .net "w_l_lockVec_1_empty$EN", 0 0, C4<0>; 1 drivers -v0x24d3290_0 .net "w_l_lockVec_1_nextId_dummy2_0$D_IN", 0 0, C4<0>; 1 drivers -v0x24d3340_0 .net "w_l_lockVec_1_nextId_dummy2_0$EN", 0 0, C4<0>; 1 drivers -v0x24d33f0_0 .net "w_l_lockVec_1_nextId_dummy2_1$D_IN", 0 0, C4<0>; 1 drivers -v0x24d34a0_0 .net "w_l_lockVec_1_nextId_dummy2_1$EN", 0 0, C4<0>; 1 drivers -v0x24d3550_0 .net "w_l_lockVec_1_nextId_dummy2_1$Q_OUT", 0 0, C4<1>; 1 drivers -v0x24d3600_0 .var "w_l_lockVec_1_nextId_rl", 1 0; -v0x24d3680_0 .net "w_l_lockVec_1_nextId_rl$D_IN", 1 0, L_0x24f12d0; 1 drivers -v0x24d3700_0 .net "w_l_lockVec_1_nextId_rl$EN", 0 0, C4<1>; 1 drivers -v0x24d3780_0 .var "w_l_lockVec_1_owner", 1 0; -v0x24d3800_0 .net "w_l_lockVec_1_owner$D_IN", 1 0, C4<00>; 1 drivers -v0x24d3880_0 .net "w_l_lockVec_1_owner$EN", 0 0, C4<0>; 1 drivers -v0x24d3900_0 .var "w_l_lockVec_2_empty", 0 0; -v0x24d3980_0 .net "w_l_lockVec_2_empty$D_IN", 0 0, L_0x24f2610; 1 drivers -v0x24d3a00_0 .net "w_l_lockVec_2_empty$EN", 0 0, C4<0>; 1 drivers -v0x24d3a80_0 .net "w_l_lockVec_2_nextId_dummy2_0$D_IN", 0 0, C4<0>; 1 drivers -v0x24d3b30_0 .net "w_l_lockVec_2_nextId_dummy2_0$EN", 0 0, C4<0>; 1 drivers -v0x24d3be0_0 .net "w_l_lockVec_2_nextId_dummy2_1$D_IN", 0 0, C4<0>; 1 drivers -v0x24d3c90_0 .net "w_l_lockVec_2_nextId_dummy2_1$EN", 0 0, C4<0>; 1 drivers -v0x24d3d40_0 .net "w_l_lockVec_2_nextId_dummy2_1$Q_OUT", 0 0, C4<1>; 1 drivers -v0x24d3df0_0 .var "w_l_lockVec_2_nextId_rl", 1 0; -v0x24d3e70_0 .net "w_l_lockVec_2_nextId_rl$D_IN", 1 0, L_0x24f2b30; 1 drivers -v0x24d3ef0_0 .net "w_l_lockVec_2_nextId_rl$EN", 0 0, C4<1>; 1 drivers -v0x24d3f70_0 .var "w_l_lockVec_2_owner", 1 0; -v0x24d3ff0_0 .net "w_l_lockVec_2_owner$D_IN", 1 0, C4<00>; 1 drivers -v0x24d4070_0 .net "w_l_lockVec_2_owner$EN", 0 0, C4<0>; 1 drivers -v0x24d40f0_0 .var "w_l_lockVec_3_empty", 0 0; -v0x24d4170_0 .net "w_l_lockVec_3_empty$D_IN", 0 0, L_0x24f2c90; 1 drivers -v0x24d41f0_0 .net "w_l_lockVec_3_empty$EN", 0 0, C4<0>; 1 drivers -v0x24d4270_0 .net "w_l_lockVec_3_nextId_dummy2_0$D_IN", 0 0, C4<0>; 1 drivers -v0x24d4320_0 .net "w_l_lockVec_3_nextId_dummy2_0$EN", 0 0, C4<0>; 1 drivers -v0x24d43d0_0 .net "w_l_lockVec_3_nextId_dummy2_1$D_IN", 0 0, C4<0>; 1 drivers -v0x24d4480_0 .net "w_l_lockVec_3_nextId_dummy2_1$EN", 0 0, C4<0>; 1 drivers -v0x24d4530_0 .net "w_l_lockVec_3_nextId_dummy2_1$Q_OUT", 0 0, C4<1>; 1 drivers -v0x24d45e0_0 .var "w_l_lockVec_3_nextId_rl", 1 0; -v0x24d4660_0 .net "w_l_lockVec_3_nextId_rl$D_IN", 1 0, L_0x24f2df0; 1 drivers -v0x24d46e0_0 .net "w_l_lockVec_3_nextId_rl$EN", 0 0, C4<1>; 1 drivers -v0x24d4760_0 .var "w_l_lockVec_3_owner", 1 0; -v0x24d47e0_0 .net "w_l_lockVec_3_owner$D_IN", 1 0, C4<00>; 1 drivers -v0x24d4860_0 .net "w_l_lockVec_3_owner$EN", 0 0, C4<0>; 1 drivers -v0x24d48e0_0 .net "x__h25497", 1 0, L_0x250d2d0; 1 drivers -v0x24d4960_0 .net "x__h26014", 1 0, L_0x250ecd0; 1 drivers -v0x24d49e0_0 .net "x__h26655", 1 0, L_0x250f270; 1 drivers -v0x24d4a60_0 .net "x__h27260", 1 0, L_0x2510450; 1 drivers -v0x24d4ae0_0 .net "x__h29141", 1 0, L_0x250eb00; 1 drivers -E_0x24a1a60 .event negedge, v0x22b62d0_0; -E_0x238a5c0/0 .event edge, v0x24d40f0_0, v0x24d3900_0, v0x24d30d0_0, v0x24d28e0_0; -E_0x238a5c0/1 .event edge, v0x24d4960_0; -E_0x238a5c0 .event/or E_0x238a5c0/0, E_0x238a5c0/1; -E_0x2391990/0 .event edge, v0x24c8200_0, v0x24c9060_0, v0x24c71a0_0, v0x24c6940_0; -E_0x2391990/1 .event edge, v0x24d48e0_0; -E_0x2391990 .event/or E_0x2391990/0, E_0x2391990/1; -E_0x2398f30/0 .event edge, v0x24adbc0_0, v0x24ad810_0, v0x24ad770_0, v0x24ad430_0; -E_0x2398f30/1 .event edge, v0x24d4a60_0; -E_0x2398f30 .event/or E_0x2398f30/0, E_0x2398f30/1; -E_0x23a8450/0 .event edge, v0x24adbc0_0, v0x24ad810_0, v0x24ad770_0, v0x24ad430_0; -E_0x23a8450/1 .event edge, v0x24d49e0_0; -E_0x23a8450 .event/or E_0x23a8450/0, E_0x23a8450/1; -E_0x23afc50/0 .event edge, v0x24cbc00_0, v0x24cb1b0_0, v0x24cc070_0, v0x23d0da0_0; -E_0x23afc50/1 .event edge, v0x24c9d40_0, v0x24d4ae0_0; -E_0x23afc50 .event/or E_0x23afc50/0, E_0x23afc50/1; -E_0x23a0c80/0 .event edge, v0x24cb430_0, v0x24caa10_0, v0x24c9f80_0, v0x24c9540_0; -E_0x23a0c80/1 .event edge, v0x24d49e0_0; -E_0x23a0c80 .event/or E_0x23a0c80/0, E_0x23a0c80/1; -L_0x24d7ff0 .reduce/nor v0x24ce100_0; -L_0x24d8210 .cmp/eq 2, L_0x24ff7a0, v0x24d74f0_0; -L_0x24e3990 .part v0x24c8a70_0, 10, 1; -L_0x24e3a90 .reduce/nor L_0x24e8000; -L_0x24e3c30 .part v0x24c8c50_0, 10, 1; -L_0x24e3d20 .reduce/nor L_0x24e8450; -L_0x24e3f40 .part v0x24c8e30_0, 10, 1; -L_0x24e4090 .reduce/nor L_0x24e8550; -L_0x24e4310 .part v0x24c9220_0, 10, 1; -L_0x24e4460 .reduce/nor L_0x24e74f0; -L_0x24e46b0 .functor MUXZ 1, L_0x2506700, v0x24aee90_0, L_0x250a5e0, C4<>; -L_0x24e4ac0 .reduce/nor L_0x250b500; -L_0x24e4d60 .reduce/nor L_0x250b500; -L_0x24e4eb0 .part v0x2387990_0, 2, 1; -L_0x24e5090 .part v0x2387990_0, 2, 1; -L_0x24e5470 .reduce/nor L_0x24e5090; -L_0x24e5810 .cmp/eq 3, L_0x2510330, v0x2385210_0; -L_0x24e5700 .part v0x2387990_0, 2, 1; -L_0x24e5ad0 .reduce/nor L_0x24e5700; -L_0x24e5c10 .reduce/nor L_0x250b500; -L_0x24e5970 .part v0x242c4b0_0, 35, 10; -L_0x24e5f70 .concat [ 10 1 0 0], L_0x24e5970, C4<1>; -L_0x24e5d40 .part v0x247f0f0_0, 2, 10; -L_0x24e3310 .arith/sum 10, L_0x24e5d40, C4<0000000001>; -L_0x24e60b0 .part v0x247f0f0_0, 0, 2; -L_0x24e6440 .concat [ 2 10 0 0], L_0x24e60b0, L_0x24e3310; -L_0x24e62e0 .concat [ 2 10 0 0], v0x24cdf20_0, C4<0000000000>; -L_0x24e66b0 .cmp/eq 2, L_0x2510450, C4<00>; -L_0x24e6150 .cmp/eq 2, L_0x250eb00, C4<00>; -L_0x24e6ab0 .cmp/eq 2, L_0x2510450, C4<01>; -L_0x24e6e20 .cmp/eq 2, L_0x250eb00, C4<01>; -L_0x24e7560 .cmp/eq 2, L_0x2510450, C4<10>; -L_0x24e6890 .cmp/eq 2, L_0x250eb00, C4<10>; -L_0x24e7750 .cmp/eq 2, L_0x2510450, C4<11>; -L_0x24e7d10 .cmp/eq 2, L_0x250eb00, C4<11>; -L_0x24e8310 .functor MUXZ 12, L_0x24e62e0, L_0x24e6440, L_0x24e5910, C4<>; -L_0x24e87c0 .part v0x24cd090_0, 13, 1; -L_0x24e8860 .reduce/nor L_0x24e87c0; -L_0x24e8a60 .part v0x23a2e70_0, 2, 2; -L_0x24e8b00 .cmp/eq 2, v0x24d0cc0_0, L_0x24e8a60; -L_0x24e8d80 .part v0x24cd090_0, 13, 1; -L_0x24e8e70 .reduce/nor L_0x24e8d80; -L_0x24e9100 .part v0x23a2e70_0, 2, 2; -L_0x24e9230 .cmp/eq 2, v0x24d0cc0_0, L_0x24e9100; -L_0x24e93d0 .part v0x23a2e70_0, 5, 10; -L_0x24e98d0 .concat [ 3 10 1 0], v0x24cda60_0, L_0x24e93d0, C4<1>; -L_0x24e9760 .functor MUXZ 14, v0x24cd090_0, L_0x24e98d0, L_0x24e92d0, C4<>; -L_0x24e9b90 .part L_0x24e9760, 13, 1; -L_0x24e8110 .functor MUXZ 14, L_0x24e9760, C4<00101010101010>, L_0x24e9ac0, C4<>; -L_0x24ea050 .part v0x24c5e70_0, 10, 1; -L_0x24e9eb0 .part v0x24c60f0_0, 10, 1; -L_0x24e9570 .part v0x24c7990_0, 10, 1; -L_0x24ea2c0 .part v0x24c6760_0, 10, 1; -L_0x24e9d30 .cmp/eq 2, C4<00>, L_0x2510390; -L_0x24ea450 .cmp/eq 2, C4<00>, L_0x250f360; -L_0x24eaf70 .cmp/eq 2, C4<00>, L_0x250f460; -L_0x24eb470 .cmp/eq 2, C4<00>, L_0x250f560; -L_0x24eb3b0 .functor MUXZ 11, L_0x24e5f70, C4<01010101010>, L_0x24e3b30, C4<>; -L_0x24eb6b0 .cmp/eq 2, L_0x2510450, C4<00>; -L_0x24eab40 .functor MUXZ 11, L_0x24e5f70, C4<01010101010>, L_0x24e3dc0, C4<>; -L_0x24ebb30 .cmp/eq 2, L_0x2510450, C4<01>; -L_0x24ebdc0 .functor MUXZ 11, L_0x24e5f70, C4<01010101010>, L_0x24e4180, C4<>; -L_0x24ebfb0 .cmp/eq 2, L_0x2510450, C4<10>; -L_0x24eba40 .functor MUXZ 11, L_0x24e5f70, C4<01010101010>, L_0x24e4560, C4<>; -L_0x24ec720 .cmp/eq 2, L_0x2510450, C4<11>; -L_0x24ec8d0 .reduce/nor L_0x24e5ef0; -L_0x24ecac0 .cmp/eq 2, L_0x2509120, L_0x250f660; -L_0x24ec2e0 .reduce/nor L_0x24e6c70; -L_0x24ed110 .reduce/nor L_0x24e5ef0; -L_0x24ec5f0 .reduce/nor L_0x24e6d70; -L_0x24ecf30 .cmp/eq 2, L_0x25091c0, L_0x250f710; -L_0x24ed790 .reduce/nor L_0x24e7120; -L_0x24edc20 .reduce/nor L_0x24e6d70; -L_0x24ed420 .reduce/nor L_0x24e7440; -L_0x24edf10 .cmp/eq 2, L_0x2509b90, L_0x250f7c0; -L_0x24ee0e0 .reduce/nor L_0x24e7b30; -L_0x24ee4a0 .reduce/nor L_0x24e7440; -L_0x24ee8f0 .reduce/nor L_0x24e7c20; -L_0x24ee1d0 .cmp/eq 2, L_0x2509c80, L_0x250f870; -L_0x24eeb30 .reduce/nor L_0x24e7f50; -L_0x24eef10 .reduce/nor L_0x24e7c20; -L_0x24ed970 .arith/sum 3, v0x24cda60_0, C4<001>; -L_0x24ef190 .functor MUXZ 2, C4<00>, C4<11>, L_0x24e58b0, C4<>; -L_0x24ef350 .part v0x2387990_0, 2, 1; -L_0x24ef5f0 .reduce/nor L_0x24ef350; -L_0x24efd10 .arith/sum 2, v0x24cdf20_0, C4<01>; -L_0x24efa20 .reduce/nor L_0x24e5a30; -L_0x24efac0 .reduce/nor L_0x250b500; -L_0x24f0400 .reduce/nor L_0x24e5910; -L_0x24f0530 .cmp/eq 2, L_0x25086b0, L_0x250f920; -L_0x24effc0 .reduce/nor L_0x24e8c80; -L_0x24f01e0 .reduce/nor L_0x24e5910; -L_0x24f14b0 .reduce/nor L_0x250b500; -L_0x24f0760 .part v0x24d20e0_0, 10, 1; -L_0x24f1bf0 .part v0x24d22e0_0, 10, 1; -L_0x24f0b00 .part v0x24d24e0_0, 10, 1; -L_0x24f1d50 .part v0x24d2760_0, 10, 1; -L_0x24f1fa0 .cmp/eq 2, C4<00>, L_0x250f9d0; -L_0x24f1140 .cmp/eq 2, C4<00>, L_0x250dfd0; -L_0x24f2610 .cmp/eq 2, C4<00>, L_0x250e0d0; -L_0x24f2c90 .cmp/eq 2, C4<00>, L_0x250e1d0; -L_0x24f3520 .part v0x242c4b0_0, 35, 10; -L_0x24f47e0 .part v0x242c4b0_0, 0, 3; -LS_0x24f2ec0_0_0 .concat [ 3 10 2 1], L_0x24f47e0, L_0x24f3520, L_0x24ff980, C4<1>; -LS_0x24f2ec0_0_4 .concat [ 32 0 0 0], L_0x250a740; -L_0x24f2ec0 .concat [ 16 32 0 0], LS_0x24f2ec0_0_0, LS_0x24f2ec0_0_4; -L_0x24f3090 .part v0x2457dc0_0, 0, 3; -L_0x24f45e0 .part L_0x24e1860, 0, 10; -L_0x24f4d30 .part L_0x24e9760, 0, 3; -L_0x24f4e60 .concat [ 3 32 10 0], L_0x24f4d30, L_0x24e2940, L_0x24f45e0; -L_0x24f4680 .part L_0x24e9760, 13, 1; -L_0x24f4c80 .part v0x23a2e70_0, 0, 2; -L_0x24f5550 .concat [ 2 3 0 0], L_0x24f4c80, v0x24cda60_0; -L_0x24f3ff0 .part v0x247f0f0_0, 2, 10; -L_0x24f51d0 .part v0x247f0f0_0, 0, 2; -L_0x24f5270 .concat [ 2 2 1 10], L_0x24f51d0, L_0x24ff4e0, L_0x250b500, L_0x24f3ff0; -L_0x24f5de0 .reduce/nor L_0x250b500; -L_0x24f5e80 .part v0x247f0f0_0, 0, 2; -L_0x24f5f20 .concat [ 2 1 0 0], L_0x24f5e80, L_0x24f5de0; -L_0x24f61b0 .part v0x247f0f0_0, 0, 2; -L_0x24f57e0 .part v0x2387990_0, 2, 1; -L_0x24f6440 .part L_0x24e9760, 3, 10; -L_0x24f4340 .part v0x242c4b0_0, 35, 10; -L_0x24f6cb0 .part v0x2457dc0_0, 3, 10; -L_0x24f6e30 .part v0x2457dc0_0, 16, 32; -L_0x24f7090 .part L_0x24e9760, 3, 10; -L_0x24f8230 .part v0x24c5e70_0, 10, 1; -L_0x24f8320 .reduce/nor L_0x24f8230; -L_0x24f7e40 .reduce/nor L_0x25021c0; -L_0x24f7f80 .part v0x24c60f0_0, 10, 1; -L_0x24f80b0 .functor MUXZ 2, C4<00>, C4<01>, L_0x24f7d90, C4<>; -L_0x24f8460 .part v0x24c8a70_0, 10, 1; -L_0x24f8d70 .reduce/nor L_0x24f8460; -L_0x24f8e60 .reduce/nor L_0x24fdd30; -L_0x24f8600 .part v0x24c8c50_0, 10, 1; -L_0x24f7980 .functor MUXZ 2, C4<00>, C4<01>, L_0x24f7880, C4<>; -L_0x24f7ac0 .part v0x24c8a70_0, 10, 1; -L_0x24f7b60 .reduce/nor L_0x24f7ac0; -L_0x24f8950 .reduce/nor L_0x24fdf60; -L_0x24f8af0 .part v0x24c8c50_0, 10, 1; -L_0x24f9ab0 .functor MUXZ 2, C4<00>, C4<01>, L_0x24f8c90, C4<>; -L_0x24f9c80 .cmp/eq 2, L_0x250f270, C4<00>; -L_0x24f9d70 .part v0x24c9220_0, 10, 1; -L_0x24fa790 .cmp/eq 2, L_0x250f270, C4<01>; -L_0x24f8fa0 .part v0x24c9220_0, 10, 1; -L_0x24f9330 .cmp/eq 2, L_0x250f270, C4<10>; -L_0x24fa8d0 .part v0x24c9220_0, 10, 1; -L_0x24fac50 .cmp/eq 2, L_0x250f270, C4<11>; -L_0x24f9990 .part v0x24c9220_0, 10, 1; -L_0x24fb5c0 .part v0x24d20e0_0, 10, 1; -L_0x24fa5b0 .reduce/nor L_0x24fb5c0; -L_0x24fb6b0 .reduce/nor L_0x250aa30; -L_0x24f94f0 .part v0x24d22e0_0, 10, 1; -L_0x24f9730 .functor MUXZ 2, C4<00>, C4<01>, L_0x24f9680, C4<>; -L_0x24f97d0 .part v0x24c6760_0, 10, 1; -L_0x24f98c0 .part v0x24c6760_0, 0, 10; -L_0x24fa100 .part L_0x24e9760, 3, 10; -L_0x24fa2b0 .cmp/eq 10, L_0x24f98c0, L_0x24fa100; -L_0x24fa4f0 .part v0x24c6760_0, 10, 1; -L_0x24fb010 .reduce/nor L_0x24fa4f0; -L_0x24fc8b0 .part v0x24c7990_0, 10, 1; -L_0x24fb0b0 .reduce/nor L_0x24fc8b0; -L_0x24fb240 .part v0x24c60f0_0, 10, 1; -L_0x24fb2e0 .reduce/nor L_0x24fb240; -L_0x24fb8f0 .part v0x24c5e70_0, 10, 1; -L_0x24fb990 .reduce/nor L_0x24fb8f0; -L_0x24fbb80 .functor MUXZ 1, L_0x24fba80, v0x24af070_0, L_0x24fa440, C4<>; -L_0x24fc3c0 .part v0x24d2760_0, 10, 1; -L_0x24fc4b0 .part v0x24d2760_0, 0, 10; -L_0x24fc550 .part L_0x24e9760, 3, 10; -L_0x24fc5f0 .cmp/eq 10, L_0x24fc4b0, L_0x24fc550; -L_0x24fbd20 .part v0x24d2760_0, 10, 1; -L_0x24fd0b0 .reduce/nor L_0x24fbd20; -L_0x24fd150 .part v0x24d24e0_0, 10, 1; -L_0x24fd240 .reduce/nor L_0x24fd150; -L_0x24fd3d0 .part v0x24d22e0_0, 10, 1; -L_0x24fd470 .reduce/nor L_0x24fd3d0; -L_0x24fbef0 .part v0x24d20e0_0, 10, 1; -L_0x24fbf90 .reduce/nor L_0x24fbef0; -L_0x24fc180 .functor MUXZ 1, L_0x24fc080, v0x24aef30_0, L_0x24fbcc0, C4<>; -L_0x24fdb60 .part v0x24c8a70_0, 0, 10; -L_0x24fdc90 .part v0x242c4b0_0, 35, 10; -L_0x24fdd30 .cmp/eq 10, L_0x24fdb60, L_0x24fdc90; -L_0x24fde20 .part v0x24c8a70_0, 0, 10; -L_0x24fdec0 .part v0x2457dc0_0, 3, 10; -L_0x24fdf60 .cmp/eq 10, L_0x24fde20, L_0x24fdec0; -L_0x24fe0f0 .part v0x24c8c50_0, 10, 1; -L_0x24fd650 .part v0x24c8a70_0, 10, 1; -L_0x24fd7a0 .part v0x24c8e30_0, 10, 1; -L_0x24fd890 .reduce/nor L_0x24fd7a0; -L_0x24fda80 .part v0x24c8a70_0, 10, 1; -L_0x24fe190 .part v0x24c8c50_0, 10, 1; -L_0x24fe830 .reduce/nor L_0x24fe190; -L_0x24fe970 .functor MUXZ 2, C4<00>, C4<01>, L_0x24b3420, C4<>; -L_0x24fea60 .functor MUXZ 2, L_0x24fe970, C4<10>, L_0x24fd980, C4<>; -L_0x24febf0 .part v0x24c8c50_0, 0, 10; -L_0x24fec90 .part v0x242c4b0_0, 35, 10; -L_0x24fe230 .cmp/eq 10, L_0x24febf0, L_0x24fec90; -L_0x24fe370 .part v0x24c8c50_0, 0, 10; -L_0x24fe410 .part v0x2457dc0_0, 3, 10; -L_0x24fe4b0 .cmp/eq 10, L_0x24fe370, L_0x24fe410; -L_0x24fe640 .part v0x24c8e30_0, 0, 10; -L_0x24fe6e0 .part v0x242c4b0_0, 35, 10; -L_0x24fe780 .cmp/eq 10, L_0x24fe640, L_0x24fe6e0; -L_0x24fca50 .part v0x24c8e30_0, 0, 10; -L_0x24fcb80 .part v0x2457dc0_0, 3, 10; -L_0x24fcd30 .cmp/eq 10, L_0x24fca50, L_0x24fcb80; -L_0x24fce20 .part v0x24c9220_0, 10, 1; -L_0x24fee90 .functor MUXZ 1, L_0x2506700, v0x24af110_0, L_0x24f6da0, C4<>; -L_0x24fef80 .part v0x24c9220_0, 10, 1; -L_0x24ff850 .functor MUXZ 2, C4<00>, v0x24aed20_0, L_0x2506700, C4<>; -L_0x24ff980 .functor MUXZ 2, L_0x24ff850, v0x23b1d10_0, L_0x24ff0d0, C4<>; -L_0x2500160 .part v0x24c9220_0, 0, 10; -L_0x2500310 .part v0x242c4b0_0, 35, 10; -L_0x2500a60 .cmp/eq 10, L_0x2500160, L_0x2500310; -L_0x2500c70 .functor MUXZ 2, C4<00>, v0x24c9bc0_0, L_0x2500c10, C4<>; -L_0x2500db0 .arith/sum 2, L_0x2500c70, C4<01>; -L_0x2500f60 .functor MUXZ 2, v0x24c9bc0_0, L_0x2500db0, L_0x24e5ef0, C4<>; -L_0x24ffb20 .functor MUXZ 2, C4<00>, v0x24ca600_0, L_0x24ffac0, C4<>; -L_0x24ffc60 .arith/sum 2, L_0x24ffb20, C4<01>; -L_0x24ffdc0 .functor MUXZ 2, v0x24ca600_0, L_0x24ffc60, L_0x24e6d70, C4<>; -L_0x24fffb0 .functor MUXZ 2, C4<00>, v0x24cb030_0, L_0x24fff50, C4<>; -L_0x25003f0 .arith/sum 2, L_0x24fffb0, C4<01>; -L_0x25005a0 .functor MUXZ 2, v0x24cb030_0, L_0x25003f0, L_0x24e7440, C4<>; -L_0x25007d0 .functor MUXZ 2, C4<00>, v0x24cba80_0, L_0x2500730, C4<>; -L_0x2500950 .arith/sum 2, L_0x25007d0, C4<01>; -L_0x2501e50 .functor MUXZ 2, v0x24cba80_0, L_0x2500950, L_0x24e7c20, C4<>; -L_0x24ff180 .functor MUXZ 3, C4<000>, v0x24cf630_0, L_0x2501fe0, C4<>; -L_0x24ff2c0 .functor MUXZ 3, v0x24cf630_0, L_0x2509d70, L_0x24e5510, C4<>; -L_0x24ff4e0 .functor MUXZ 2, C4<00>, v0x24d0420_0, L_0x24ff440, C4<>; -L_0x24ff670 .functor MUXZ 2, v0x24d0420_0, L_0x2508530, L_0x24e5910, C4<>; -L_0x24ff7a0 .functor MUXZ 2, C4<00>, v0x24d09c0_0, L_0x24f0150, C4<>; -L_0x2502fb0 .part v0x24c60f0_0, 10, 1; -L_0x25030e0 .reduce/nor L_0x2502fb0; -L_0x2503180 .reduce/nor L_0x2502480; -L_0x25018d0 .part v0x24c5e70_0, 10, 1; -L_0x2501a00 .reduce/nor L_0x25018d0; -L_0x2501aa0 .reduce/nor L_0x25021c0; -L_0x2501010 .part v0x24c7990_0, 10, 1; -L_0x2501260 .part v0x24c7990_0, 10, 1; -L_0x2501390 .reduce/nor L_0x2501260; -L_0x2501430 .reduce/nor L_0x25089f0; -L_0x2501620 .part v0x24c60f0_0, 10, 1; -L_0x25027a0 .reduce/nor L_0x2501620; -L_0x2502890 .reduce/nor L_0x2502480; -L_0x2502ad0 .part v0x24c5e70_0, 10, 1; -L_0x2502b70 .reduce/nor L_0x2502ad0; -L_0x2502c60 .reduce/nor L_0x25021c0; -L_0x2503a50 .part v0x24c8c50_0, 10, 1; -L_0x2503c00 .reduce/nor L_0x2503a50; -L_0x2503cf0 .reduce/nor L_0x24fe230; -L_0x2503e40 .part v0x24c8a70_0, 10, 1; -L_0x2503ff0 .reduce/nor L_0x2503e40; -L_0x25040e0 .reduce/nor L_0x24fdd30; -L_0x25033e0 .part v0x24c8e30_0, 10, 1; -L_0x2503630 .part v0x24c8c50_0, 10, 1; -L_0x25036d0 .reduce/nor L_0x2503630; -L_0x25037c0 .reduce/nor L_0x24fe4b0; -L_0x2503960 .part v0x24c8a70_0, 10, 1; -L_0x2504a30 .reduce/nor L_0x2503960; -L_0x2504ad0 .reduce/nor L_0x24fdf60; -L_0x2504d20 .part v0x24c8e30_0, 10, 1; -L_0x2504190 .part v0x24c8e30_0, 10, 1; -L_0x2504230 .reduce/nor L_0x2504190; -L_0x2504320 .reduce/nor L_0x24fe780; -L_0x2504500 .part v0x24c8c50_0, 10, 1; -L_0x25045a0 .reduce/nor L_0x2504500; -L_0x2504690 .reduce/nor L_0x24fe230; -L_0x2505790 .part v0x24c8a70_0, 10, 1; -L_0x2505830 .reduce/nor L_0x2505790; -L_0x2505920 .reduce/nor L_0x24fdd30; -L_0x2505bc0 .part v0x24c8e30_0, 10, 1; -L_0x2505d70 .reduce/nor L_0x2505bc0; -L_0x2505e60 .reduce/nor L_0x24fcd30; -L_0x2504fc0 .part v0x24c8c50_0, 10, 1; -L_0x2505060 .reduce/nor L_0x2504fc0; -L_0x2505150 .reduce/nor L_0x24fe4b0; -L_0x25053a0 .part v0x24c8a70_0, 10, 1; -L_0x2505440 .reduce/nor L_0x25053a0; -L_0x2505530 .reduce/nor L_0x24fdf60; -L_0x2507060 .part v0x24c9220_0, 10, 1; -L_0x2507100 .reduce/nor L_0x2507060; -L_0x2506050 .part v0x24c8e30_0, 10, 1; -L_0x25060f0 .reduce/nor L_0x2506050; -L_0x25062e0 .part v0x24c8c50_0, 10, 1; -L_0x2506380 .reduce/nor L_0x25062e0; -L_0x2506570 .part v0x24c8a70_0, 10, 1; -L_0x2506610 .reduce/nor L_0x2506570; -L_0x2506850 .part v0x24c9220_0, 10, 1; -L_0x25068f0 .reduce/nor L_0x2506850; -L_0x25069e0 .reduce/nor L_0x2500a60; -L_0x2506d30 .part v0x24d22e0_0, 10, 1; -L_0x2506e60 .reduce/nor L_0x2506d30; -L_0x2506f00 .reduce/nor L_0x250acf0; -L_0x2507a80 .part v0x24d20e0_0, 10, 1; -L_0x2507bb0 .reduce/nor L_0x2507a80; -L_0x2507c50 .reduce/nor L_0x250aa30; -L_0x2507f40 .part v0x24d24e0_0, 10, 1; -L_0x2507250 .part v0x24d24e0_0, 10, 1; -L_0x2507380 .reduce/nor L_0x2507250; -L_0x2507420 .reduce/nor L_0x250b9c0; -L_0x2507610 .part v0x24d22e0_0, 10, 1; -L_0x25076b0 .reduce/nor L_0x2507610; -L_0x25077a0 .reduce/nor L_0x250acf0; -L_0x2509270 .part v0x24d20e0_0, 10, 1; -L_0x2509310 .reduce/nor L_0x2509270; -L_0x25080e0 .reduce/nor L_0x250aa30; -L_0x2509120 .arith/sum 2, v0x24c9d40_0, C4<01>; -L_0x25091c0 .arith/sum 2, v0x24cc070_0, C4<01>; -L_0x2509b90 .arith/sum 2, v0x24cb1b0_0, C4<01>; -L_0x2509c80 .arith/sum 2, v0x24cbc00_0, C4<01>; -L_0x2509d70 .arith/sum 3, L_0x24ff180, C4<001>; -L_0x2508530 .arith/sum 2, L_0x24ff4e0, C4<01>; -L_0x25086b0 .arith/sum 2, v0x24d0cc0_0, C4<01>; -L_0x25087e0 .arith/sum 2, L_0x24ff7a0, C4<01>; -L_0x2502080 .part v0x24c5e70_0, 0, 10; -L_0x2502120 .part L_0x24e9760, 3, 10; -L_0x25021c0 .cmp/eq 10, L_0x2502080, L_0x2502120; -L_0x2502340 .part v0x24c60f0_0, 0, 10; -L_0x25023e0 .part L_0x24e9760, 3, 10; -L_0x2502480 .cmp/eq 10, L_0x2502340, L_0x25023e0; -L_0x2502600 .part v0x24c7990_0, 0, 10; -L_0x25026a0 .part L_0x24e9760, 3, 10; -L_0x25089f0 .cmp/eq 10, L_0x2502600, L_0x25026a0; -L_0x2508b30 .part v0x24c7990_0, 10, 1; -L_0x2508cb0 .part v0x24c60f0_0, 10, 1; -L_0x250b6f0 .part v0x24c5e70_0, 10, 1; -L_0x2508fb0 .part v0x24c8e30_0, 10, 1; -L_0x2509450 .part v0x24c8c50_0, 10, 1; -L_0x25096a0 .part v0x24c8a70_0, 10, 1; -L_0x25098f0 .part v0x24c8e30_0, 10, 1; -L_0x2509ad0 .part v0x24c8c50_0, 10, 1; -L_0x2509f70 .part v0x24c8a70_0, 10, 1; -L_0x250a1c0 .part v0x24c9220_0, 10, 1; -L_0x250a260 .part v0x24c9220_0, 0, 10; -L_0x250a300 .part v0x2457dc0_0, 3, 10; -L_0x250a3a0 .cmp/eq 10, L_0x250a260, L_0x250a300; -L_0x250ae50 .part v0x2387990_0, 2, 1; -L_0x250b000 .part v0x23c8070_0, 2, 3; -L_0x250b0a0 .cmp/eq 3, L_0x24ff180, L_0x250b000; -L_0x250b190 .part v0x24cdbe0_0, 1, 1; -L_0x250b420 .part v0x247f0f0_0, 2, 10; -L_0x250b500 .cmp/gt 10, C4<1111101000>, L_0x250b420; -L_0x250c830 .part v0x247f0f0_0, 0, 2; -L_0x250c8d0 .cmp/eq 2, L_0x250e3d0, L_0x250c830; -L_0x250a6a0 .part v0x242c4b0_0, 3, 32; -L_0x250a740 .arith/sum 32, L_0x24e20d0, L_0x250a6a0; -L_0x250a8f0 .part v0x24d20e0_0, 0, 10; -L_0x250a990 .part L_0x24e9760, 3, 10; -L_0x250aa30 .cmp/eq 10, L_0x250a8f0, L_0x250a990; -L_0x250abb0 .part v0x24d22e0_0, 0, 10; -L_0x250ac50 .part L_0x24e9760, 3, 10; -L_0x250acf0 .cmp/eq 10, L_0x250abb0, L_0x250ac50; -L_0x250b880 .part v0x24d24e0_0, 0, 10; -L_0x250b920 .part L_0x24e9760, 3, 10; -L_0x250b9c0 .cmp/eq 10, L_0x250b880, L_0x250b920; -L_0x250bb00 .part v0x24d24e0_0, 10, 1; -L_0x250bce0 .part v0x24d22e0_0, 10, 1; -L_0x250be30 .part v0x24d20e0_0, 10, 1; -L_0x250d400 .part v0x24c6760_0, 10, 1; -L_0x250d5a0 .part v0x24c6760_0, 0, 10; -L_0x250d640 .part L_0x24e9760, 3, 10; -L_0x250d8f0 .cmp/eq 10, L_0x250d5a0, L_0x250d640; -L_0x24fa1e0 .functor MUXZ 2, L_0x24f80b0, C4<10>, L_0x25011b0, C4<>; -L_0x250d2d0 .functor MUXZ 2, L_0x24fa1e0, C4<11>, L_0x250da30, C4<>; -L_0x250c1b0 .part v0x24d2760_0, 10, 1; -L_0x250c350 .part v0x24d2760_0, 0, 10; -L_0x250c3f0 .part L_0x24e9760, 3, 10; -L_0x250c490 .cmp/eq 10, L_0x250c350, L_0x250c3f0; -L_0x250c710 .functor MUXZ 2, L_0x24f9730, C4<10>, L_0x25071a0, C4<>; -L_0x250ecd0 .functor MUXZ 2, L_0x250c710, C4<11>, L_0x250c5d0, C4<>; -L_0x250ee60 .part v0x24c9220_0, 10, 1; -L_0x250f0e0 .functor MUXZ 2, L_0x24f7980, C4<10>, L_0x2503580, C4<>; -L_0x250f270 .functor MUXZ 2, L_0x250f0e0, C4<11>, L_0x250efb0, C4<>; -L_0x250cb00 .part v0x24c8e30_0, 10, 1; -L_0x250cba0 .part v0x24c8c50_0, 10, 1; -L_0x250cd40 .part v0x24c8a70_0, 10, 1; -L_0x250cee0 .part v0x24c9220_0, 10, 1; -L_0x250cf80 .reduce/nor L_0x250cee0; -L_0x2510450 .functor MUXZ 2, L_0x24fea60, C4<11>, L_0x250d070, C4<>; -L_0x25105e0 .part v0x24c9220_0, 10, 1; -L_0x2510780 .part v0x24c9220_0, 0, 10; -L_0x2500200 .part v0x2457dc0_0, 3, 10; -L_0x250dd40 .cmp/eq 10, L_0x2510780, L_0x2500200; -L_0x250e970 .functor MUXZ 2, L_0x24f9ab0, C4<10>, L_0x2504ec0, C4<>; -L_0x250eb00 .functor MUXZ 2, L_0x250e970, C4<11>, L_0x250de80, C4<>; -S_0x24aa100 .scope module, "f_l_lockVec_0_nextId_dummy2_0" "RevertReg" 4 741, 5 7, S_0x23c0270; - .timescale 0 0; -P_0x24aa1f8 .param/l "init" 5 10, C4<1>; -P_0x24aa220 .param/l "width" 5 9, C4<00000000000000000000000000000001>; -v0x24aa310_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x24ac430_0 .alias "D_IN", 0 0, v0x24c6b20_0; -v0x24ac4b0_0 .alias "EN", 0 0, v0x24c6bd0_0; -v0x24ac530_0 .net "Q_OUT", 0 0, C4<1>; 1 drivers -S_0x24a9c40 .scope module, "f_l_lockVec_0_nextId_dummy2_1" "RevertReg" 4 748, 5 7, S_0x23c0270; - .timescale 0 0; -P_0x24a9d38 .param/l "init" 5 10, C4<1>; -P_0x24a9d60 .param/l "width" 5 9, C4<00000000000000000000000000000001>; -v0x24a9e50_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x24a9f10_0 .alias "D_IN", 0 0, v0x24c6c80_0; -v0x24a9fb0_0 .alias "EN", 0 0, v0x24c6d00_0; -v0x24aa050_0 .alias "Q_OUT", 0 0, v0x24c6db0_0; -S_0x24a9780 .scope module, "f_l_lockVec_1_nextId_dummy2_0" "RevertReg" 4 755, 5 7, S_0x23c0270; - .timescale 0 0; -P_0x24a9878 .param/l "init" 5 10, C4<1>; -P_0x24a98a0 .param/l "width" 5 9, C4<00000000000000000000000000000001>; -v0x24a9990_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x24a9a50_0 .alias "D_IN", 0 0, v0x24c7380_0; -v0x24a9af0_0 .alias "EN", 0 0, v0x24c7430_0; -v0x24a9b90_0 .net "Q_OUT", 0 0, C4<1>; 1 drivers -S_0x24a92c0 .scope module, "f_l_lockVec_1_nextId_dummy2_1" "RevertReg" 4 762, 5 7, S_0x23c0270; - .timescale 0 0; -P_0x24a93b8 .param/l "init" 5 10, C4<1>; -P_0x24a93e0 .param/l "width" 5 9, C4<00000000000000000000000000000001>; -v0x24a94d0_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x24a9590_0 .alias "D_IN", 0 0, v0x24c74e0_0; -v0x24a9630_0 .alias "EN", 0 0, v0x24c7590_0; -v0x24a96d0_0 .alias "Q_OUT", 0 0, v0x24c7640_0; -S_0x24a8e00 .scope module, "f_l_lockVec_2_nextId_dummy2_0" "RevertReg" 4 769, 5 7, S_0x23c0270; - .timescale 0 0; -P_0x24a8ef8 .param/l "init" 5 10, C4<1>; -P_0x24a8f20 .param/l "width" 5 9, C4<00000000000000000000000000000001>; -v0x24a9010_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x24a90d0_0 .alias "D_IN", 0 0, v0x24c7b70_0; -v0x24a9170_0 .alias "EN", 0 0, v0x24c7c20_0; -v0x24a9210_0 .net "Q_OUT", 0 0, C4<1>; 1 drivers -S_0x24a8940 .scope module, "f_l_lockVec_2_nextId_dummy2_1" "RevertReg" 4 776, 5 7, S_0x23c0270; - .timescale 0 0; -P_0x24a8a38 .param/l "init" 5 10, C4<1>; -P_0x24a8a60 .param/l "width" 5 9, C4<00000000000000000000000000000001>; -v0x24a8b50_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x24a8c10_0 .alias "D_IN", 0 0, v0x24c7cd0_0; -v0x24a8cb0_0 .alias "EN", 0 0, v0x24c7d80_0; -v0x24a8d50_0 .alias "Q_OUT", 0 0, v0x24c7e30_0; -S_0x24a60a0 .scope module, "f_l_lockVec_3_nextId_dummy2_0" "RevertReg" 4 783, 5 7, S_0x23c0270; - .timescale 0 0; -P_0x24a6198 .param/l "init" 5 10, C4<1>; -P_0x24a61c0 .param/l "width" 5 9, C4<00000000000000000000000000000001>; -v0x24a6270_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x24a6330_0 .alias "D_IN", 0 0, v0x24c83e0_0; -v0x24a8820_0 .alias "EN", 0 0, v0x24c8490_0; -v0x24a88c0_0 .net "Q_OUT", 0 0, C4<1>; 1 drivers -S_0x241da10 .scope module, "f_l_lockVec_3_nextId_dummy2_1" "RevertReg" 4 790, 5 7, S_0x23c0270; - .timescale 0 0; -P_0x23eeb38 .param/l "init" 5 10, C4<1>; -P_0x23eeb60 .param/l "width" 5 9, C4<00000000000000000000000000000001>; -v0x2291c10_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x2291cd0_0 .alias "D_IN", 0 0, v0x24c8540_0; -v0x2291d70_0 .alias "EN", 0 0, v0x24c85f0_0; -v0x2291e10_0 .alias "Q_OUT", 0 0, v0x24c86a0_0; -S_0x22547d0 .scope module, "h_l_lockVec_0_nextId_dummy2_0" "RevertReg" 4 797, 5 7, S_0x23c0270; - .timescale 0 0; -P_0x24189f8 .param/l "init" 5 10, C4<1>; -P_0x2418a20 .param/l "width" 5 9, C4<00000000000000000000000000000001>; -v0x2253770_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x2253810_0 .alias "D_IN", 0 0, v0x24c9720_0; -v0x22538b0_0 .alias "EN", 0 0, v0x24c97d0_0; -v0x241d960_0 .alias "Q_OUT", 0 0, v0x24c9880_0; -S_0x2297ec0 .scope module, "h_l_lockVec_0_nextId_dummy2_1" "RevertReg" 4 804, 5 7, S_0x23c0270; - .timescale 0 0; -P_0x2297fb8 .param/l "init" 5 10, C4<1>; -P_0x2297fe0 .param/l "width" 5 9, C4<00000000000000000000000000000001>; -v0x22980d0_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x2285240_0 .alias "D_IN", 0 0, v0x24c9930_0; -v0x22546a0_0 .alias "EN", 0 0, v0x24c99e0_0; -v0x2254720_0 .alias "Q_OUT", 0 0, v0x24c9a90_0; -S_0x2411d70 .scope module, "h_l_lockVec_1_nextId_dummy2_0" "RevertReg" 4 811, 5 7, S_0x23c0270; - .timescale 0 0; -P_0x2411e68 .param/l "init" 5 10, C4<1>; -P_0x2411e90 .param/l "width" 5 9, C4<00000000000000000000000000000001>; -v0x23f51b0_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x2285050_0 .alias "D_IN", 0 0, v0x24ca160_0; -v0x22850f0_0 .alias "EN", 0 0, v0x24ca210_0; -v0x2285190_0 .alias "Q_OUT", 0 0, v0x24ca2c0_0; -S_0x241bf10 .scope module, "h_l_lockVec_1_nextId_dummy2_1" "RevertReg" 4 818, 5 7, S_0x23c0270; - .timescale 0 0; -P_0x2286568 .param/l "init" 5 10, C4<1>; -P_0x2286590 .param/l "width" 5 9, C4<00000000000000000000000000000001>; -v0x24188b0_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x2418950_0 .alias "D_IN", 0 0, v0x24ca370_0; -v0x23f5060_0 .alias "EN", 0 0, v0x24ca420_0; -v0x23f5100_0 .alias "Q_OUT", 0 0, v0x24ca4d0_0; -S_0x247e060 .scope module, "h_l_lockVec_2_nextId_dummy2_0" "RevertReg" 4 825, 5 7, S_0x23c0270; - .timescale 0 0; -P_0x247e158 .param/l "init" 5 10, C4<1>; -P_0x247e180 .param/l "width" 5 9, C4<00000000000000000000000000000001>; -v0x23e10f0_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x23e11b0_0 .alias "D_IN", 0 0, v0x24cabf0_0; -v0x23e1230_0 .alias "EN", 0 0, v0x24caca0_0; -v0x241be60_0 .alias "Q_OUT", 0 0, v0x24cad50_0; -S_0x2401a50 .scope module, "h_l_lockVec_2_nextId_dummy2_1" "RevertReg" 4 832, 5 7, S_0x23c0270; - .timescale 0 0; -P_0x2456a58 .param/l "init" 5 10, C4<1>; -P_0x2456a80 .param/l "width" 5 9, C4<00000000000000000000000000000001>; -v0x2404880_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x2401b80_0 .alias "D_IN", 0 0, v0x24cadd0_0; -v0x22863d0_0 .alias "EN", 0 0, v0x24cae80_0; -v0x2286470_0 .alias "Q_OUT", 0 0, v0x24caf00_0; -S_0x2407410 .scope module, "h_l_lockVec_3_nextId_dummy2_0" "RevertReg" 4 839, 5 7, S_0x23c0270; - .timescale 0 0; -P_0x241a338 .param/l "init" 5 10, C4<1>; -P_0x241a360 .param/l "width" 5 9, C4<00000000000000000000000000000001>; -v0x2407540_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x240a210_0 .alias "D_IN", 0 0, v0x24cb610_0; -v0x2404730_0 .alias "EN", 0 0, v0x24cb6c0_0; -v0x24047d0_0 .alias "Q_OUT", 0 0, v0x24cb740_0; -S_0x2454170 .scope module, "h_l_lockVec_3_nextId_dummy2_1" "RevertReg" 4 846, 5 7, S_0x23c0270; - .timescale 0 0; -P_0x2455668 .param/l "init" 5 10, C4<1>; -P_0x2455690 .param/l "width" 5 9, C4<00000000000000000000000000000001>; -v0x2452d80_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x2452e00_0 .alias "D_IN", 0 0, v0x24cb7f0_0; -v0x240a0f0_0 .alias "EN", 0 0, v0x24cb8a0_0; -v0x240a190_0 .alias "Q_OUT", 0 0, v0x24cb950_0; -S_0x23856f0 .scope module, "hg_fifo_Stage__0_TO_Stage__1" "FIFO2" 4 853, 6 28, S_0x23c0270; - .timescale 0 0; -P_0x23857e8 .param/l "guarded" 6 39, C4<1>; -P_0x2385810 .param/l "width" 6 38, C4<00000000000000000000000000110000>; -L_0x24d87f0 .functor BUFZ 1, v0x2458b40_0, C4<0>, C4<0>, C4<0>; -L_0x24d8e30 .functor BUFZ 1, v0x24569d0_0, C4<0>, C4<0>, C4<0>; -L_0x24d9080 .functor AND 1, L_0x24f4880, L_0x24d8f90, C4<1>, C4<1>; -L_0x24d9180 .functor AND 1, L_0x24f4880, L_0x24f48e0, C4<1>, C4<1>; -L_0x24d9230 .functor AND 1, L_0x24d9180, v0x2458b40_0, C4<1>, C4<1>; -L_0x24d9330 .functor OR 1, L_0x24d9080, L_0x24d9230, C4<0>, C4<0>; -L_0x24d94d0 .functor AND 1, L_0x24f48e0, L_0x24d9430, C4<1>, C4<1>; -L_0x24d9830 .functor AND 1, L_0x24d95d0, L_0x24d9700, C4<1>, C4<1>; -L_0x24d9930 .functor AND 1, L_0x24d9890, v0x24569d0_0, C4<1>, C4<1>; -L_0x24d9a40 .functor OR 1, L_0x24d9830, L_0x24d9930, C4<0>, C4<0>; -L_0x24d9b90 .functor AND 1, L_0x24d9af0, v0x2458b40_0, C4<1>, C4<1>; -L_0x24d99e0 .functor OR 1, L_0x24d9a40, L_0x24d9b90, C4<0>, C4<0>; -L_0x24d9d20 .functor AND 1, L_0x24f4880, v0x24569d0_0, C4<1>, C4<1>; -v0x23c9a80_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x23c9b20_0 .alias "CLR", 0 0, v0x24cc370_0; -v0x23d1330_0 .alias "DEQ", 0 0, v0x24cc3f0_0; -v0x23d13d0_0 .alias "D_IN", 47 0, v0x24cc470_0; -v0x23d0da0_0 .alias "D_OUT", 47 0, v0x24cc520_0; -v0x23d0e40_0 .alias "EMPTY_N", 0 0, v0x24cc5d0_0; -v0x23d0810_0 .alias "ENQ", 0 0, v0x24cc680_0; -v0x23d08b0_0 .alias "FULL_N", 0 0, v0x24cc730_0; -v0x23d67b0_0 .alias "RST", 0 0, v0x24d4be0_0; -v0x23d6830_0 .net *"_s10", 0 0, L_0x24d9180; 1 drivers -v0x2429140_0 .net *"_s12", 0 0, L_0x24d9230; 1 drivers -v0x24291e0_0 .net *"_s17", 0 0, L_0x24d9430; 1 drivers -v0x2393ba0_0 .net *"_s21", 0 0, L_0x24d95d0; 1 drivers -v0x2393c40_0 .net *"_s23", 0 0, L_0x24d9700; 1 drivers -v0x2410400_0 .net *"_s24", 0 0, L_0x24d9830; 1 drivers -v0x240c890_0 .net *"_s27", 0 0, L_0x24d9890; 1 drivers -v0x2410360_0 .net *"_s28", 0 0, L_0x24d9930; 1 drivers -v0x2489de0_0 .net *"_s30", 0 0, L_0x24d9a40; 1 drivers -v0x240c910_0 .net *"_s33", 0 0, L_0x24d9af0; 1 drivers -v0x2470e80_0 .net *"_s34", 0 0, L_0x24d9b90; 1 drivers -v0x2470f20_0 .net *"_s7", 0 0, L_0x24d8f90; 1 drivers -v0x2459820_0 .net *"_s8", 0 0, L_0x24d9080; 1 drivers -v0x2489e60_0 .net "d0d1", 0 0, L_0x24d94d0; 1 drivers -v0x2458ac0_0 .net "d0di", 0 0, L_0x24d9330; 1 drivers -v0x24598a0_0 .net "d0h", 0 0, L_0x24d99e0; 1 drivers -v0x2457d40_0 .net "d1di", 0 0, L_0x24d9d20; 1 drivers -v0x2457dc0_0 .var "data0_reg", 47 0; -v0x2456950_0 .var "data1_reg", 47 0; -v0x24569d0_0 .var "empty_reg", 0 0; -v0x2458b40_0 .var "full_reg", 0 0; -L_0x24d8f90 .reduce/nor v0x24569d0_0; -L_0x24d9430 .reduce/nor v0x2458b40_0; -L_0x24d95d0 .reduce/nor L_0x24f48e0; -L_0x24d9700 .reduce/nor L_0x24f4880; -L_0x24d9890 .reduce/nor L_0x24f48e0; -L_0x24d9af0 .reduce/nor L_0x24f4880; -S_0x23ca5a0 .scope begin, "error_checks" "error_checks" 6 132, 6 132, S_0x23856f0; - .timescale 0 0; -v0x23ca010_0 .var "deqerror", 0 0; -v0x23ca0d0_0 .var "enqerror", 0 0; -S_0x242b3f0 .scope module, "hg_fifo_Stage__1_TO_Stage__2" "FIFO2" 4 865, 6 28, S_0x23c0270; - .timescale 0 0; -P_0x242b4e8 .param/l "guarded" 6 39, C4<1>; -P_0x242b510 .param/l "width" 6 38, C4<00000000000000000000000000000011>; -L_0x24d9e10 .functor BUFZ 1, v0x2385cf0_0, C4<0>, C4<0>, C4<0>; -L_0x24d9e70 .functor BUFZ 1, v0x2385c50_0, C4<0>, C4<0>, C4<0>; -L_0x24da0c0 .functor AND 1, L_0x24f3180, L_0x24d9fd0, C4<1>, C4<1>; -L_0x24da1c0 .functor AND 1, L_0x24f3180, L_0x24f44b0, C4<1>, C4<1>; -L_0x24da270 .functor AND 1, L_0x24da1c0, v0x2385cf0_0, C4<1>, C4<1>; -L_0x24da3b0 .functor OR 1, L_0x24da0c0, L_0x24da270, C4<0>, C4<0>; -L_0x24da550 .functor AND 1, L_0x24f44b0, L_0x24da4b0, C4<1>, C4<1>; -L_0x24da8b0 .functor AND 1, L_0x24da650, L_0x24da780, C4<1>, C4<1>; -L_0x24da9b0 .functor AND 1, L_0x24da910, v0x2385c50_0, C4<1>, C4<1>; -L_0x24daac0 .functor OR 1, L_0x24da8b0, L_0x24da9b0, C4<0>, C4<0>; -L_0x24dac10 .functor AND 1, L_0x24dab70, v0x2385cf0_0, C4<1>, C4<1>; -L_0x24daa60 .functor OR 1, L_0x24daac0, L_0x24dac10, C4<0>, C4<0>; -L_0x24dada0 .functor AND 1, L_0x24f3180, v0x2385c50_0, C4<1>, C4<1>; -v0x2426050_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x24260f0_0 .alias "CLR", 0 0, v0x24cc7e0_0; -v0x2425dd0_0 .alias "DEQ", 0 0, v0x24cc860_0; -v0x2425e70_0 .alias "D_IN", 2 0, v0x24cc8e0_0; -v0x2425570_0 .alias "D_OUT", 2 0, v0x24cc990_0; -v0x2425610_0 .alias "EMPTY_N", 0 0, v0x24cca40_0; -v0x2424e90_0 .alias "ENQ", 0 0, v0x24ccaf0_0; -v0x2424f30_0 .alias "FULL_N", 0 0, v0x24ccb70_0; -v0x2410b00_0 .alias "RST", 0 0, v0x24d4be0_0; -v0x2410b80_0 .net *"_s10", 0 0, L_0x24da1c0; 1 drivers -v0x23ecc80_0 .net *"_s12", 0 0, L_0x24da270; 1 drivers -v0x23ecd20_0 .net *"_s17", 0 0, L_0x24da4b0; 1 drivers -v0x23ec920_0 .net *"_s21", 0 0, L_0x24da650; 1 drivers -v0x23ec9c0_0 .net *"_s23", 0 0, L_0x24da780; 1 drivers -v0x23ec6a0_0 .net *"_s24", 0 0, L_0x24da8b0; 1 drivers -v0x247da40_0 .net *"_s27", 0 0, L_0x24da910; 1 drivers -v0x23ec600_0 .net *"_s28", 0 0, L_0x24da9b0; 1 drivers -v0x2383c10_0 .net *"_s30", 0 0, L_0x24daac0; 1 drivers -v0x2383cb0_0 .net *"_s33", 0 0, L_0x24dab70; 1 drivers -v0x2384170_0 .net *"_s34", 0 0, L_0x24dac10; 1 drivers -v0x247dac0_0 .net *"_s7", 0 0, L_0x24d9fd0; 1 drivers -v0x23846d0_0 .net *"_s8", 0 0, L_0x24da0c0; 1 drivers -v0x23841f0_0 .net "d0d1", 0 0, L_0x24da550; 1 drivers -v0x2384c30_0 .net "d0di", 0 0, L_0x24da3b0; 1 drivers -v0x2384cd0_0 .net "d0h", 0 0, L_0x24daa60; 1 drivers -v0x2385190_0 .net "d1di", 0 0, L_0x24dada0; 1 drivers -v0x2385210_0 .var "data0_reg", 2 0; -v0x2384750_0 .var "data1_reg", 2 0; -v0x2385c50_0 .var "empty_reg", 0 0; -v0x2385cf0_0 .var "full_reg", 0 0; -L_0x24d9fd0 .reduce/nor v0x2385c50_0; -L_0x24da4b0 .reduce/nor v0x2385cf0_0; -L_0x24da650 .reduce/nor L_0x24f44b0; -L_0x24da780 .reduce/nor L_0x24f3180; -L_0x24da910 .reduce/nor L_0x24f44b0; -L_0x24dab70 .reduce/nor L_0x24f3180; -S_0x2428ec0 .scope begin, "error_checks" "error_checks" 6 132, 6 132, S_0x242b3f0; - .timescale 0 0; -v0x2428b00_0 .var "deqerror", 0 0; -v0x2428bc0_0 .var "enqerror", 0 0; -S_0x24261e0 .scope module, "hg_fifo_Start_TO_Stage__0" "FIFO2" 4 877, 6 28, S_0x23c0270; - .timescale 0 0; -P_0x23ac6a8 .param/l "guarded" 6 39, C4<1>; -P_0x23ac6d0 .param/l "width" 6 38, C4<00000000000000000000000000101101>; -L_0x24daf10 .functor BUFZ 1, v0x242b1e0_0, C4<0>, C4<0>, C4<0>; -L_0x24daf70 .functor BUFZ 1, v0x242b140_0, C4<0>, C4<0>, C4<0>; -L_0x24db1c0 .functor AND 1, L_0x24f5030, L_0x24db0d0, C4<1>, C4<1>; -L_0x24db2c0 .functor AND 1, L_0x24f5030, L_0x24f50e0, C4<1>, C4<1>; -L_0x24db370 .functor AND 1, L_0x24db2c0, v0x242b1e0_0, C4<1>, C4<1>; -L_0x24db4b0 .functor OR 1, L_0x24db1c0, L_0x24db370, C4<0>, C4<0>; -L_0x24db650 .functor AND 1, L_0x24f50e0, L_0x24db5b0, C4<1>, C4<1>; -L_0x24db9b0 .functor AND 1, L_0x24db750, L_0x24db880, C4<1>, C4<1>; -L_0x24dbab0 .functor AND 1, L_0x24dba10, v0x242b140_0, C4<1>, C4<1>; -L_0x24dbbc0 .functor OR 1, L_0x24db9b0, L_0x24dbab0, C4<0>, C4<0>; -L_0x24dbd10 .functor AND 1, L_0x24dbc70, v0x242b1e0_0, C4<1>, C4<1>; -L_0x24dbb60 .functor OR 1, L_0x24dbbc0, L_0x24dbd10, C4<0>, C4<0>; -L_0x24dbea0 .functor AND 1, L_0x24f5030, v0x242b140_0, C4<1>, C4<1>; -v0x23f6cb0_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x23f6d30_0 .alias "CLR", 0 0, v0x24ccc20_0; -v0x23aa940_0 .alias "DEQ", 0 0, v0x24ccca0_0; -v0x23aa9e0_0 .alias "D_IN", 44 0, v0x24ccd20_0; -v0x23b2090_0 .alias "D_OUT", 44 0, v0x24ccdd0_0; -v0x23b2130_0 .alias "EMPTY_N", 0 0, v0x24cce80_0; -v0x241a4a0_0 .alias "ENQ", 0 0, v0x24ccf30_0; -v0x241a540_0 .alias "FULL_N", 0 0, v0x24ccfe0_0; -v0x2414620_0 .alias "RST", 0 0, v0x24d4be0_0; -v0x24146a0_0 .net *"_s10", 0 0, L_0x24db2c0; 1 drivers -v0x241a390_0 .net *"_s12", 0 0, L_0x24db370; 1 drivers -v0x23fa160_0 .net *"_s17", 0 0, L_0x24db5b0; 1 drivers -v0x23fa200_0 .net *"_s21", 0 0, L_0x24db750; 1 drivers -v0x23f8650_0 .net *"_s23", 0 0, L_0x24db880; 1 drivers -v0x23f6b40_0 .net *"_s24", 0 0, L_0x24db9b0; 1 drivers -v0x23f6bc0_0 .net *"_s27", 0 0, L_0x24dba10; 1 drivers -v0x24a1600_0 .net *"_s28", 0 0, L_0x24dbab0; 1 drivers -v0x24a1680_0 .net *"_s30", 0 0, L_0x24dbbc0; 1 drivers -v0x23f86d0_0 .net *"_s33", 0 0, L_0x24dbc70; 1 drivers -v0x24a0f10_0 .net *"_s34", 0 0, L_0x24dbd10; 1 drivers -v0x2431640_0 .net *"_s7", 0 0, L_0x24db0d0; 1 drivers -v0x24a0e70_0 .net *"_s8", 0 0, L_0x24db1c0; 1 drivers -v0x24310f0_0 .net "d0d1", 0 0, L_0x24db650; 1 drivers -v0x24315b0_0 .net "d0di", 0 0, L_0x24db4b0; 1 drivers -v0x2431030_0 .net "d0h", 0 0, L_0x24dbb60; 1 drivers -v0x242c430_0 .net "d1di", 0 0, L_0x24dbea0; 1 drivers -v0x242c4b0_0 .var "data0_reg", 44 0; -v0x242cd20_0 .var "data1_reg", 44 0; -v0x242b140_0 .var "empty_reg", 0 0; -v0x242b1e0_0 .var "full_reg", 0 0; -L_0x24db0d0 .reduce/nor v0x242b140_0; -L_0x24db5b0 .reduce/nor v0x242b1e0_0; -L_0x24db750 .reduce/nor L_0x24f50e0; -L_0x24db880 .reduce/nor L_0x24f5030; -L_0x24dba10 .reduce/nor L_0x24f50e0; -L_0x24dbc70 .reduce/nor L_0x24f5030; -S_0x23fa2d0 .scope begin, "error_checks" "error_checks" 6 132, 6 132, S_0x24261e0; - .timescale 0 0; -v0x23f87c0_0 .var "deqerror", 0 0; -v0x23f8860_0 .var "enqerror", 0 0; -S_0x23fa720 .scope module, "hg_outputQueue_nextTag_dummy2_0" "RevertReg" 4 889, 5 7, S_0x23c0270; - .timescale 0 0; -P_0x24708f8 .param/l "init" 5 10, C4<1>; -P_0x2470920 .param/l "width" 5 9, C4<00000000000000000000000000000001>; -v0x23f5a40_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x2452470_0 .alias "D_IN", 0 0, v0x24cd610_0; -v0x2452510_0 .alias "EN", 0 0, v0x24cd6c0_0; -v0x23ac5f0_0 .alias "Q_OUT", 0 0, v0x24cd770_0; -S_0x24292d0 .scope module, "hg_outputQueue_nextTag_dummy2_1" "RevertReg" 4 896, 5 7, S_0x23c0270; - .timescale 0 0; -P_0x23c3338 .param/l "init" 5 10, C4<1>; -P_0x23c3360 .param/l "width" 5 9, C4<00000000000000000000000000000001>; -v0x241b810_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x241b8b0_0 .alias "D_IN", 0 0, v0x24cd7f0_0; -v0x2419750_0 .alias "EN", 0 0, v0x24cd8a0_0; -v0x24197d0_0 .alias "Q_OUT", 0 0, v0x24cd950_0; -S_0x23ae380 .scope module, "o_fifo_Stage__1_TO_Stage__3" "FIFO2" 4 903, 6 28, S_0x23c0270; - .timescale 0 0; -P_0x23a3ac8 .param/l "guarded" 6 39, C4<1>; -P_0x23a3af0 .param/l "width" 6 38, C4<00000000000000000000000000000101>; -L_0x24d8d90 .functor BUFZ 1, v0x23c8cf0_0, C4<0>, C4<0>, C4<0>; -L_0x24dc1e0 .functor BUFZ 1, v0x23cfa30_0, C4<0>, C4<0>, C4<0>; -L_0x24dc430 .functor AND 1, L_0x24f5690, L_0x24dc340, C4<1>, C4<1>; -L_0x24dc530 .functor AND 1, L_0x24f5690, L_0x24f56f0, C4<1>, C4<1>; -L_0x24dc5e0 .functor AND 1, L_0x24dc530, v0x23c8cf0_0, C4<1>, C4<1>; -L_0x24dc6e0 .functor OR 1, L_0x24dc430, L_0x24dc5e0, C4<0>, C4<0>; -L_0x24dc880 .functor AND 1, L_0x24f56f0, L_0x24dc7e0, C4<1>, C4<1>; -L_0x24dcbe0 .functor AND 1, L_0x24dc980, L_0x24dcab0, C4<1>, C4<1>; -L_0x24dcce0 .functor AND 1, L_0x24dcc40, v0x23cfa30_0, C4<1>, C4<1>; -L_0x24dcdf0 .functor OR 1, L_0x24dcbe0, L_0x24dcce0, C4<0>, C4<0>; -L_0x24dcf40 .functor AND 1, L_0x24dcea0, v0x23c8cf0_0, C4<1>, C4<1>; -L_0x24dcd90 .functor OR 1, L_0x24dcdf0, L_0x24dcf40, C4<0>, C4<0>; -L_0x24dd0d0 .functor AND 1, L_0x24f5690, v0x23cfa30_0, C4<1>, C4<1>; -v0x23b28e0_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x23b2980_0 .alias "CLR", 0 0, v0x24ce560_0; -v0x23b5ad0_0 .alias "DEQ", 0 0, v0x24ce610_0; -v0x23b5b70_0 .alias "D_IN", 4 0, v0x24ce690_0; -v0x23b5750_0 .alias "D_OUT", 4 0, v0x24ce740_0; -v0x23b57f0_0 .alias "EMPTY_N", 0 0, v0x24ce7f0_0; -v0x23b3da0_0 .alias "ENQ", 0 0, v0x24ce8a0_0; -v0x23b3750_0 .alias "FULL_N", 0 0, v0x24ce950_0; -v0x23b37d0_0 .alias "RST", 0 0, v0x24d4be0_0; -v0x23b1da0_0 .net *"_s10", 0 0, L_0x24dc530; 1 drivers -v0x23ba070_0 .net *"_s12", 0 0, L_0x24dc5e0; 1 drivers -v0x23ba110_0 .net *"_s17", 0 0, L_0x24dc7e0; 1 drivers -v0x23bd310_0 .net *"_s21", 0 0, L_0x24dc980; 1 drivers -v0x23bb4f0_0 .net *"_s23", 0 0, L_0x24dcab0; 1 drivers -v0x23b9460_0 .net *"_s24", 0 0, L_0x24dcbe0; 1 drivers -v0x23b9500_0 .net *"_s27", 0 0, L_0x24dcc40; 1 drivers -v0x23bb570_0 .net *"_s28", 0 0, L_0x24dcce0; 1 drivers -v0x23c2160_0 .net *"_s30", 0 0, L_0x24dcdf0; 1 drivers -v0x23c2710_0 .net *"_s33", 0 0, L_0x24dcea0; 1 drivers -v0x23c3820_0 .net *"_s34", 0 0, L_0x24dcf40; 1 drivers -v0x23c38a0_0 .net *"_s7", 0 0, L_0x24dc340; 1 drivers -v0x23c21e0_0 .net *"_s8", 0 0, L_0x24dc430; 1 drivers -v0x23c2cc0_0 .net "d0d1", 0 0, L_0x24dc880; 1 drivers -v0x23c2d60_0 .net "d0di", 0 0, L_0x24dc6e0; 1 drivers -v0x23c3270_0 .net "d0h", 0 0, L_0x24dcd90; 1 drivers -v0x23c7fd0_0 .net "d1di", 0 0, L_0x24dd0d0; 1 drivers -v0x23c8070_0 .var "data0_reg", 4 0; -v0x23cf9b0_0 .var "data1_reg", 4 0; -v0x23cfa30_0 .var "empty_reg", 0 0; -v0x23c8cf0_0 .var "full_reg", 0 0; -L_0x24dc340 .reduce/nor v0x23cfa30_0; -L_0x24dc7e0 .reduce/nor v0x23c8cf0_0; -L_0x24dc980 .reduce/nor L_0x24f56f0; -L_0x24dcab0 .reduce/nor L_0x24f5690; -L_0x24dcc40 .reduce/nor L_0x24f56f0; -L_0x24dcea0 .reduce/nor L_0x24f5690; -S_0x23ac000 .scope begin, "error_checks" "error_checks" 6 132, 6 132, S_0x23ae380; - .timescale 0 0; -v0x23aa5c0_0 .var "deqerror", 0 0; -v0x23aa640_0 .var "enqerror", 0 0; -S_0x238fee0 .scope module, "o_fifo_Start_TO_Stage__1" "FIFO2" 4 915, 6 28, S_0x23c0270; - .timescale 0 0; -P_0x2437148 .param/l "guarded" 6 39, C4<1>; -P_0x2437170 .param/l "width" 6 38, C4<00000000000000000000000000001111>; -L_0x24dd240 .functor BUFZ 1, v0x23a4e80_0, C4<0>, C4<0>, C4<0>; -L_0x24dd2a0 .functor BUFZ 1, v0x23ab210_0, C4<0>, C4<0>, C4<0>; -L_0x24dd4f0 .functor AND 1, L_0x24f5400, L_0x24dd400, C4<1>, C4<1>; -L_0x24dd5f0 .functor AND 1, L_0x24f5400, L_0x24f5460, C4<1>, C4<1>; -L_0x24dd6a0 .functor AND 1, L_0x24dd5f0, v0x23a4e80_0, C4<1>, C4<1>; -L_0x24dd7e0 .functor OR 1, L_0x24dd4f0, L_0x24dd6a0, C4<0>, C4<0>; -L_0x24dd980 .functor AND 1, L_0x24f5460, L_0x24dd8e0, C4<1>, C4<1>; -L_0x24ddce0 .functor AND 1, L_0x24dda80, L_0x24ddbb0, C4<1>, C4<1>; -L_0x24ddde0 .functor AND 1, L_0x24ddd40, v0x23ab210_0, C4<1>, C4<1>; -L_0x24ddef0 .functor OR 1, L_0x24ddce0, L_0x24ddde0, C4<0>, C4<0>; -L_0x24de040 .functor AND 1, L_0x24ddfa0, v0x23a4e80_0, C4<1>, C4<1>; -L_0x24dde90 .functor OR 1, L_0x24ddef0, L_0x24de040, C4<0>, C4<0>; -L_0x24de1d0 .functor AND 1, L_0x24f5400, v0x23ab210_0, C4<1>, C4<1>; -v0x238df80_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x238c480_0 .alias "CLR", 0 0, v0x24cea00_0; -v0x238c520_0 .alias "DEQ", 0 0, v0x24ceab0_0; -v0x2394460_0 .alias "D_IN", 14 0, v0x24ceb60_0; -v0x2397630_0 .alias "D_OUT", 14 0, v0x24cec10_0; -v0x23976d0_0 .alias "EMPTY_N", 0 0, v0x24cecc0_0; -v0x23972b0_0 .alias "ENQ", 0 0, v0x24ced70_0; -v0x2397350_0 .alias "FULL_N", 0 0, v0x24cee20_0; -v0x23958c0_0 .alias "RST", 0 0, v0x24d4be0_0; -v0x2395940_0 .net *"_s10", 0 0, L_0x24dd5f0; 1 drivers -v0x23952d0_0 .net *"_s12", 0 0, L_0x24dd6a0; 1 drivers -v0x2393820_0 .net *"_s17", 0 0, L_0x24dd8e0; 1 drivers -v0x23938c0_0 .net *"_s21", 0 0, L_0x24dda80; 1 drivers -v0x239c2a0_0 .net *"_s23", 0 0, L_0x24ddbb0; 1 drivers -v0x239f520_0 .net *"_s24", 0 0, L_0x24ddce0; 1 drivers -v0x239f5c0_0 .net *"_s27", 0 0, L_0x24ddd40; 1 drivers -v0x239c320_0 .net *"_s28", 0 0, L_0x24ddde0; 1 drivers -v0x239d720_0 .net *"_s30", 0 0, L_0x24ddef0; 1 drivers -v0x239bf70_0 .net *"_s33", 0 0, L_0x24ddfa0; 1 drivers -v0x239bc40_0 .net *"_s34", 0 0, L_0x24de040; 1 drivers -v0x239bcc0_0 .net *"_s7", 0 0, L_0x24dd400; 1 drivers -v0x239d7a0_0 .net *"_s8", 0 0, L_0x24dd4f0; 1 drivers -v0x23a6c80_0 .net "d0d1", 0 0, L_0x24dd980; 1 drivers -v0x23a6d20_0 .net "d0di", 0 0, L_0x24dd7e0; 1 drivers -v0x23a3a00_0 .net "d0h", 0 0, L_0x24dde90; 1 drivers -v0x23a2df0_0 .net "d1di", 0 0, L_0x24de1d0; 1 drivers -v0x23a2e70_0 .var "data0_reg", 14 0; -v0x23ab190_0 .var "data1_reg", 14 0; -v0x23ab210_0 .var "empty_reg", 0 0; -v0x23a4e80_0 .var "full_reg", 0 0; -L_0x24dd400 .reduce/nor v0x23ab210_0; -L_0x24dd8e0 .reduce/nor v0x23a4e80_0; -L_0x24dda80 .reduce/nor L_0x24f5460; -L_0x24ddbb0 .reduce/nor L_0x24f5400; -L_0x24ddd40 .reduce/nor L_0x24f5460; -L_0x24ddfa0 .reduce/nor L_0x24f5400; -S_0x238e4d0 .scope begin, "error_checks" "error_checks" 6 132, 6 132, S_0x238fee0; - .timescale 0 0; -v0x23902e0_0 .var "deqerror", 0 0; -v0x238dee0_0 .var "enqerror", 0 0; -S_0x2454810 .scope module, "o_fifo_Start_TO_Stage__3" "FIFO2" 4 926, 6 28, S_0x23c0270; - .timescale 0 0; -P_0x23e46a8 .param/l "guarded" 6 39, C4<1>; -P_0x23e46d0 .param/l "width" 6 38, C4<00000000000000000000000000000011>; -L_0x24de340 .functor BUFZ 1, v0x2390260_0, C4<0>, C4<0>, C4<0>; -L_0x24de3a0 .functor BUFZ 1, v0x23862f0_0, C4<0>, C4<0>, C4<0>; -L_0x24de5f0 .functor AND 1, L_0x24f60b0, L_0x24de500, C4<1>, C4<1>; -L_0x24de6f0 .functor AND 1, L_0x24f60b0, L_0x24f6110, C4<1>, C4<1>; -L_0x24de7a0 .functor AND 1, L_0x24de6f0, v0x2390260_0, C4<1>, C4<1>; -L_0x24de8e0 .functor OR 1, L_0x24de5f0, L_0x24de7a0, C4<0>, C4<0>; -L_0x24dea80 .functor AND 1, L_0x24f6110, L_0x24de9e0, C4<1>, C4<1>; -L_0x24dede0 .functor AND 1, L_0x24deb80, L_0x24decb0, C4<1>, C4<1>; -L_0x24deee0 .functor AND 1, L_0x24dee40, v0x23862f0_0, C4<1>, C4<1>; -L_0x24deff0 .functor OR 1, L_0x24dede0, L_0x24deee0, C4<0>, C4<0>; -L_0x24df140 .functor AND 1, L_0x24df0a0, v0x2390260_0, C4<1>, C4<1>; -L_0x24def90 .functor OR 1, L_0x24deff0, L_0x24df140, C4<0>, C4<0>; -L_0x24df2d0 .functor AND 1, L_0x24f60b0, v0x23862f0_0, C4<1>, C4<1>; -v0x244ee70_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x244ef10_0 .alias "CLR", 0 0, v0x24ceed0_0; -v0x244e440_0 .alias "DEQ", 0 0, v0x24cef80_0; -v0x244e4e0_0 .alias "D_IN", 2 0, v0x24cf000_0; -v0x244daa0_0 .alias "D_OUT", 2 0, v0x24cf0b0_0; -v0x244d0e0_0 .alias "EMPTY_N", 0 0, v0x24cf160_0; -v0x23e2c60_0 .alias "ENQ", 0 0, v0x24cf210_0; -v0x23e2d00_0 .alias "FULL_N", 0 0, v0x24cf2c0_0; -v0x2383180_0 .alias "RST", 0 0, v0x24d4be0_0; -v0x2383200_0 .net *"_s10", 0 0, L_0x24de6f0; 1 drivers -v0x23e28e0_0 .net *"_s12", 0 0, L_0x24de7a0; 1 drivers -v0x23e2960_0 .net *"_s17", 0 0, L_0x24de9e0; 1 drivers -v0x23e22d0_0 .net *"_s21", 0 0, L_0x24deb80; 1 drivers -v0x23e2370_0 .net *"_s23", 0 0, L_0x24decb0; 1 drivers -v0x24419c0_0 .net *"_s24", 0 0, L_0x24dede0; 1 drivers -v0x23e1960_0 .net *"_s27", 0 0, L_0x24dee40; 1 drivers -v0x2441920_0 .net *"_s28", 0 0, L_0x24deee0; 1 drivers -v0x243ada0_0 .net *"_s30", 0 0, L_0x24deff0; 1 drivers -v0x2438ed0_0 .net *"_s33", 0 0, L_0x24df0a0; 1 drivers -v0x2438f70_0 .net *"_s34", 0 0, L_0x24df140; 1 drivers -v0x23e19e0_0 .net *"_s7", 0 0, L_0x24de500; 1 drivers -v0x2382e10_0 .net *"_s8", 0 0, L_0x24de5f0; 1 drivers -v0x2382eb0_0 .net "d0d1", 0 0, L_0x24dea80; 1 drivers -v0x2381ef0_0 .net "d0di", 0 0, L_0x24de8e0; 1 drivers -v0x2381f70_0 .net "d0h", 0 0, L_0x24def90; 1 drivers -v0x2437080_0 .net "d1di", 0 0, L_0x24df2d0; 1 drivers -v0x2387990_0 .var "data0_reg", 2 0; -v0x2387a10_0 .var "data1_reg", 2 0; -v0x23862f0_0 .var "empty_reg", 0 0; -v0x2390260_0 .var "full_reg", 0 0; -L_0x24de500 .reduce/nor v0x23862f0_0; -L_0x24de9e0 .reduce/nor v0x2390260_0; -L_0x24deb80 .reduce/nor L_0x24f6110; -L_0x24decb0 .reduce/nor L_0x24f60b0; -L_0x24dee40 .reduce/nor L_0x24f6110; -L_0x24df0a0 .reduce/nor L_0x24f60b0; -S_0x24505f0 .scope begin, "error_checks" "error_checks" 6 132, 6 132, S_0x2454810; - .timescale 0 0; -v0x244f840_0 .var "deqerror", 0 0; -v0x244f8c0_0 .var "enqerror", 0 0; -S_0x2478f70 .scope module, "o_fifo_Start_TO_Stage__3_1" "FIFO2" 4 938, 6 28, S_0x23c0270; - .timescale 0 0; -P_0x2475c08 .param/l "guarded" 6 39, C4<1>; -P_0x2475c30 .param/l "width" 6 38, C4<00000000000000000000000000000010>; -L_0x24df440 .functor BUFZ 1, v0x24581f0_0, C4<0>, C4<0>, C4<0>; -L_0x24df4a0 .functor BUFZ 1, v0x2455c80_0, C4<0>, C4<0>, C4<0>; -L_0x24df6a0 .functor AND 1, L_0x24f4450, L_0x24df5b0, C4<1>, C4<1>; -L_0x24df7a0 .functor AND 1, L_0x24f4450, L_0x24f5880, C4<1>, C4<1>; -L_0x24df850 .functor AND 1, L_0x24df7a0, v0x24581f0_0, C4<1>, C4<1>; -L_0x24df950 .functor OR 1, L_0x24df6a0, L_0x24df850, C4<0>, C4<0>; -L_0x24dfaf0 .functor AND 1, L_0x24f5880, L_0x24dfa50, C4<1>, C4<1>; -L_0x24dfe50 .functor AND 1, L_0x24dfbf0, L_0x24dfd20, C4<1>, C4<1>; -L_0x24dff50 .functor AND 1, L_0x24dfeb0, v0x2455c80_0, C4<1>, C4<1>; -L_0x24e0060 .functor OR 1, L_0x24dfe50, L_0x24dff50, C4<0>, C4<0>; -L_0x24e01b0 .functor AND 1, L_0x24e0110, v0x24581f0_0, C4<1>, C4<1>; -L_0x24e0000 .functor OR 1, L_0x24e0060, L_0x24e01b0, C4<0>, C4<0>; -L_0x24e0340 .functor AND 1, L_0x24f4450, v0x2455c80_0, C4<1>, C4<1>; -v0x24737d0_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x24730c0_0 .alias "CLR", 0 0, v0x24cf370_0; -v0x2473160_0 .alias "DEQ", 0 0, v0x24cf420_0; -v0x2472a50_0 .alias "D_IN", 1 0, v0x24cf4d0_0; -v0x2472ad0_0 .net "D_OUT", 1 0, v0x2457070_0; 1 drivers -v0x2472340_0 .alias "EMPTY_N", 0 0, v0x24cf580_0; -v0x2471ca0_0 .alias "ENQ", 0 0, v0x24d1360_0; -v0x2471d40_0 .alias "FULL_N", 0 0, v0x24d13e0_0; -v0x2471590_0 .alias "RST", 0 0, v0x24d4be0_0; -v0x2471610_0 .net *"_s10", 0 0, L_0x24df7a0; 1 drivers -v0x2470950_0 .net *"_s12", 0 0, L_0x24df850; 1 drivers -v0x246df20_0 .net *"_s17", 0 0, L_0x24dfa50; 1 drivers -v0x246dfa0_0 .net *"_s21", 0 0, L_0x24dfbf0; 1 drivers -v0x246bad0_0 .net *"_s23", 0 0, L_0x24dfd20; 1 drivers -v0x246a900_0 .net *"_s24", 0 0, L_0x24dfe50; 1 drivers -v0x246a9a0_0 .net *"_s27", 0 0, L_0x24dfeb0; 1 drivers -v0x246bb50_0 .net *"_s28", 0 0, L_0x24dff50; 1 drivers -v0x23e4900_0 .net *"_s30", 0 0, L_0x24e0060; 1 drivers -v0x23e5970_0 .net *"_s33", 0 0, L_0x24e0110; 1 drivers -v0x2459c90_0 .net *"_s34", 0 0, L_0x24e01b0; 1 drivers -v0x2459d10_0 .net *"_s7", 0 0, L_0x24df5b0; 1 drivers -v0x23e4980_0 .net *"_s8", 0 0, L_0x24df6a0; 1 drivers -v0x2458f30_0 .net "d0d1", 0 0, L_0x24dfaf0; 1 drivers -v0x2458fd0_0 .net "d0di", 0 0, L_0x24df950; 1 drivers -v0x23e45e0_0 .net "d0h", 0 0, L_0x24e0000; 1 drivers -v0x2456ff0_0 .net "d1di", 0 0, L_0x24e0340; 1 drivers -v0x2457070_0 .var "data0_reg", 1 0; -v0x2455c00_0 .var "data1_reg", 1 0; -v0x2455c80_0 .var "empty_reg", 0 0; -v0x24581f0_0 .var "full_reg", 0 0; -L_0x24df5b0 .reduce/nor v0x2455c80_0; -L_0x24dfa50 .reduce/nor v0x24581f0_0; -L_0x24dfbf0 .reduce/nor L_0x24f5880; -L_0x24dfd20 .reduce/nor L_0x24f4450; -L_0x24dfeb0 .reduce/nor L_0x24f5880; -L_0x24e0110 .reduce/nor L_0x24f4450; -S_0x2473da0 .scope begin, "error_checks" "error_checks" 6 132, 6 132, S_0x2478f70; - .timescale 0 0; -v0x2474800_0 .var "deqerror", 0 0; -v0x2473730_0 .var "enqerror", 0 0; -S_0x23f5f60 .scope module, "o_fifo__input__TO_Start_f" "FIFO2" 4 950, 6 28, S_0x23c0270; - .timescale 0 0; -P_0x23f65c8 .param/l "guarded" 6 39, C4<1>; -P_0x23f65f0 .param/l "width" 6 38, C4<00000000000000000000000000001100>; -L_0x24e04b0 .functor BUFZ 1, v0x2475b80_0, C4<0>, C4<0>, C4<0>; -L_0x24e0510 .functor BUFZ 1, v0x2477650_0, C4<0>, C4<0>, C4<0>; -L_0x24e0710 .functor AND 1, L_0x24f5a70, L_0x24e0620, C4<1>, C4<1>; -L_0x24e0810 .functor AND 1, L_0x24f5a70, L_0x24f5b20, C4<1>, C4<1>; -L_0x24e08c0 .functor AND 1, L_0x24e0810, v0x2475b80_0, C4<1>, C4<1>; -L_0x24e09c0 .functor OR 1, L_0x24e0710, L_0x24e08c0, C4<0>, C4<0>; -L_0x24e0b60 .functor AND 1, L_0x24f5b20, L_0x24e0ac0, C4<1>, C4<1>; -L_0x24e0ec0 .functor AND 1, L_0x24e0c60, L_0x24e0d90, C4<1>, C4<1>; -L_0x24e0fc0 .functor AND 1, L_0x24e0f20, v0x2477650_0, C4<1>, C4<1>; -L_0x24e10d0 .functor OR 1, L_0x24e0ec0, L_0x24e0fc0, C4<0>, C4<0>; -L_0x24e1220 .functor AND 1, L_0x24e1180, v0x2475b80_0, C4<1>, C4<1>; -L_0x24e1070 .functor OR 1, L_0x24e10d0, L_0x24e1220, C4<0>, C4<0>; -L_0x24e13b0 .functor AND 1, L_0x24f5a70, v0x2477650_0, C4<1>, C4<1>; -v0x23f1830_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x23f18d0_0 .alias "CLR", 0 0, v0x24cf8b0_0; -v0x23f0eb0_0 .alias "DEQ", 0 0, v0x24cf960_0; -v0x23f0f50_0 .alias "D_IN", 11 0, v0x24cfa10_0; -v0x23d93f0_0 .alias "D_OUT", 11 0, v0x24cfac0_0; -v0x23d9490_0 .alias "EMPTY_N", 0 0, v0x24cfb70_0; -v0x23f0a80_0 .alias "ENQ", 0 0, v0x24cfc20_0; -v0x23f0130_0 .alias "FULL_N", 0 0, v0x24cfcd0_0; -v0x23f01d0_0 .alias "RST", 0 0, v0x24d4be0_0; -v0x23eeab0_0 .net *"_s10", 0 0, L_0x24e0810; 1 drivers -v0x23ed2e0_0 .net *"_s12", 0 0, L_0x24e08c0; 1 drivers -v0x23ed360_0 .net *"_s17", 0 0, L_0x24e0ac0; 1 drivers -v0x23ec310_0 .net *"_s21", 0 0, L_0x24e0c60; 1 drivers -v0x23ec3b0_0 .net *"_s23", 0 0, L_0x24e0d90; 1 drivers -v0x23ec0c0_0 .net *"_s24", 0 0, L_0x24e0ec0; 1 drivers -v0x23ebc50_0 .net *"_s27", 0 0, L_0x24e0f20; 1 drivers -v0x23ec020_0 .net *"_s28", 0 0, L_0x24e0fc0; 1 drivers -v0x23ebcd0_0 .net *"_s30", 0 0, L_0x24e10d0; 1 drivers -v0x248be40_0 .net *"_s33", 0 0, L_0x24e1180; 1 drivers -v0x23e9f60_0 .net *"_s34", 0 0, L_0x24e1220; 1 drivers -v0x248bda0_0 .net *"_s7", 0 0, L_0x24e0620; 1 drivers -v0x2486860_0 .net *"_s8", 0 0, L_0x24e0710; 1 drivers -v0x24868e0_0 .net "d0d1", 0 0, L_0x24e0b60; 1 drivers -v0x2487e50_0 .net "d0di", 0 0, L_0x24e09c0; 1 drivers -v0x247a930_0 .net "d0h", 0 0, L_0x24e1070; 1 drivers -v0x247a9d0_0 .net "d1di", 0 0, L_0x24e13b0; 1 drivers -v0x247f0f0_0 .var "data0_reg", 11 0; -v0x24775b0_0 .var "data1_reg", 11 0; -v0x2477650_0 .var "empty_reg", 0 0; -v0x2475b80_0 .var "full_reg", 0 0; -L_0x24e0620 .reduce/nor v0x2477650_0; -L_0x24e0ac0 .reduce/nor v0x2475b80_0; -L_0x24e0c60 .reduce/nor L_0x24f5b20; -L_0x24e0d90 .reduce/nor L_0x24f5a70; -L_0x24e0f20 .reduce/nor L_0x24f5b20; -L_0x24e1180 .reduce/nor L_0x24f5a70; -S_0x23f5610 .scope begin, "error_checks" "error_checks" 6 132, 6 132, S_0x23f5f60; - .timescale 0 0; -v0x23f1ed0_0 .var "deqerror", 0 0; -v0x23f1f70_0 .var "enqerror", 0 0; -S_0x23f7870 .scope module, "o_nextId_dummy2_0" "RevertReg" 4 961, 5 7, S_0x23c0270; - .timescale 0 0; -P_0x23f7b28 .param/l "init" 5 10, C4<1>; -P_0x23f7b50 .param/l "width" 5 9, C4<00000000000000000000000000000001>; -v0x23f7510_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x23f7100_0 .alias "D_IN", 0 0, v0x24d0000_0; -v0x23f7180_0 .alias "EN", 0 0, v0x24d00b0_0; -v0x23f6510_0 .alias "Q_OUT", 0 0, v0x24d0160_0; -S_0x23f93b0 .scope module, "o_nextId_dummy2_1" "RevertReg" 4 967, 5 7, S_0x23c0270; - .timescale 0 0; -P_0x23f8fc8 .param/l "init" 5 10, C4<1>; -P_0x23f8ff0 .param/l "width" 5 9, C4<00000000000000000000000000000001>; -v0x23f8c10_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x23f8020_0 .alias "D_IN", 0 0, v0x24d0210_0; -v0x23f80c0_0 .alias "EN", 0 0, v0x24d02c0_0; -v0x23f7a70_0 .alias "Q_OUT", 0 0, v0x24d0370_0; -S_0x23fae90 .scope module, "o_outputQueue_nextTag_dummy2_0" "RevertReg" 4 974, 5 7, S_0x23c0270; - .timescale 0 0; -P_0x23faad8 .param/l "init" 5 10, C4<1>; -P_0x23fab00 .param/l "width" 5 9, C4<00000000000000000000000000000001>; -v0x23f9b30_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x23f9bb0_0 .alias "D_IN", 0 0, v0x24d05a0_0; -v0x23f9580_0 .alias "EN", 0 0, v0x24d0650_0; -v0x23f9620_0 .alias "Q_OUT", 0 0, v0x24d0700_0; -S_0x23fb640 .scope module, "o_outputQueue_nextTag_dummy2_1" "RevertReg" 4 981, 5 7, S_0x23c0270; - .timescale 0 0; -P_0x2414ab8 .param/l "init" 5 10, C4<1>; -P_0x2414ae0 .param/l "width" 5 9, C4<00000000000000000000000000000001>; -v0x2382460_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x23fd320_0 .alias "D_IN", 0 0, v0x24d07b0_0; -v0x23fb090_0 .alias "EN", 0 0, v0x24d0860_0; -v0x23fb130_0 .alias "Q_OUT", 0 0, v0x24d0910_0; -S_0x2407c70 .scope module, "tf_rf" "RegFileLoad" 4 992, 7 14, S_0x23c0270; - .timescale 0 0; -P_0x2406a98 .param/l "addr_width" 7 23, C4<00000000000000000000000000001010>; -P_0x2406ac0 .param/l "binary" 7 27, C4<0>; -P_0x2406ae8 .param/l "data_width" 7 24, C4<00000000000000000000000000010000>; -P_0x2406b10 .param/str "file" 7 22, "f"; -P_0x2406b38 .param/l "hi" 7 26, C4<1111111111>; -P_0x2406b60 .param/l "lo" 7 25, C4<0000000000>; -L_0x24e1860 .functor BUFZ 16, L_0x24e15f0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; -L_0x24e1a50 .functor BUFZ 16, L_0x24e1960, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; -L_0x24e1bf0 .functor BUFZ 16, L_0x24e1b00, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; -L_0x24e1d90 .functor BUFZ 16, L_0x24e1ca0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; -L_0x24e1f30 .functor BUFZ 16, L_0x24e1e40, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; -v0x2406260_0 .alias "ADDR_1", 9 0, v0x24d0e40_0; -v0x2404f90_0 .alias "ADDR_2", 9 0, v0x24d0ef0_0; -v0x2405030_0 .alias "ADDR_3", 9 0, v0x24d0fa0_0; -v0x2403db0_0 .alias "ADDR_4", 9 0, v0x24d1050_0; -v0x2403e30_0 .alias "ADDR_5", 9 0, v0x24d10d0_0; -v0x2403b00_0 .alias "ADDR_IN", 9 0, v0x24d1180_0; -v0x2403780_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x2403800_0 .alias "D_IN", 15 0, v0x24d1230_0; -v0x2403580_0 .alias "D_OUT_1", 15 0, v0x24d12e0_0; -v0x2403620_0 .net "D_OUT_2", 15 0, L_0x24e1a50; 1 drivers -v0x24022b0_0 .net "D_OUT_3", 15 0, L_0x24e1bf0; 1 drivers -v0x2402350_0 .net "D_OUT_4", 15 0, L_0x24e1d90; 1 drivers -v0x23daf00_0 .net "D_OUT_5", 15 0, L_0x24e1f30; 1 drivers -v0x23daf80_0 .alias "WE", 0 0, v0x24d3210_0; -v0x2400000_0 .net *"_s0", 15 0, L_0x24e15f0; 1 drivers -v0x23823e0_0 .net *"_s12", 15 0, L_0x24e1ca0; 1 drivers -v0x23fff80_0 .net *"_s16", 15 0, L_0x24e1e40; 1 drivers -v0x23fe910_0 .net *"_s4", 15 0, L_0x24e1960; 1 drivers -v0x23fe990_0 .net *"_s8", 15 0, L_0x24e1b00; 1 drivers -v0x23fd2a0 .array "arr", 1023 0, 15 0; -L_0x24e15f0 .array/port v0x23fd2a0, L_0x24f6440; -L_0x24e1960 .array/port v0x23fd2a0, C4<0000000000>; -L_0x24e1b00 .array/port v0x23fd2a0, C4<0000000000>; -L_0x24e1ca0 .array/port v0x23fd2a0, C4<0000000000>; -L_0x24e1e40 .array/port v0x23fd2a0, C4<0000000000>; -S_0x2406460 .scope begin, "init_rom_block" "init_rom_block" 7 53, 7 53, S_0x2407c70; - .timescale 0 0; -S_0x24067e0 .scope begin, "runtime_check" "runtime_check" 7 75, 7 75, S_0x2407c70; - .timescale 0 0; -v0x2409540_0 .var "enable_check", 0 0; -S_0x240f820 .scope module, "th_rf" "RegFileLoad" 4 1013, 7 14, S_0x23c0270; - .timescale 0 0; -P_0x240e318 .param/l "addr_width" 7 23, C4<00000000000000000000000000001010>; -P_0x240e340 .param/l "binary" 7 27, C4<0>; -P_0x240e368 .param/l "data_width" 7 24, C4<00000000000000000000000000100000>; -P_0x240e390 .param/str "file" 7 22, "h"; -P_0x240e3b8 .param/l "hi" 7 26, C4<1111111111>; -P_0x240e3e0 .param/l "lo" 7 25, C4<0000000000>; -L_0x24e20d0 .functor BUFZ 32, L_0x24e1fe0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; -L_0x24e22c0 .functor BUFZ 32, L_0x24e21d0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; -L_0x24e2460 .functor BUFZ 32, L_0x24e2370, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; -L_0x24e2600 .functor BUFZ 32, L_0x24e2510, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; -L_0x24e27a0 .functor BUFZ 32, L_0x24e26b0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; -v0x240cf80_0 .alias "ADDR_1", 9 0, v0x24d1460_0; -v0x240cd80_0 .alias "ADDR_2", 9 0, v0x24d1510_0; -v0x240ce20_0 .alias "ADDR_3", 9 0, v0x24d15c0_0; -v0x240c420_0 .alias "ADDR_4", 9 0, v0x24d1670_0; -v0x240c4a0_0 .alias "ADDR_5", 9 0, v0x24d16f0_0; -v0x240c170_0 .alias "ADDR_IN", 9 0, v0x24d17a0_0; -v0x240bdf0_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x240be70_0 .alias "D_IN", 31 0, v0x24d1850_0; -v0x240bbf0_0 .alias "D_OUT_1", 31 0, v0x24d1900_0; -v0x240bc90_0 .net "D_OUT_2", 31 0, L_0x24e22c0; 1 drivers -v0x240b800_0 .net "D_OUT_3", 31 0, L_0x24e2460; 1 drivers -v0x240b8a0_0 .net "D_OUT_4", 31 0, L_0x24e2600; 1 drivers -v0x240a950_0 .net "D_OUT_5", 31 0, L_0x24e27a0; 1 drivers -v0x240a9f0_0 .alias "WE", 0 0, v0x24d19b0_0; -v0x2409810_0 .net *"_s0", 31 0, L_0x24e1fe0; 1 drivers -v0x24094c0_0 .net *"_s12", 31 0, L_0x24e2510; 1 drivers -v0x2409770_0 .net *"_s16", 31 0, L_0x24e26b0; 1 drivers -v0x2409140_0 .net *"_s4", 31 0, L_0x24e21d0; 1 drivers -v0x24091e0_0 .net *"_s8", 31 0, L_0x24e2370; 1 drivers -v0x2408f40 .array "arr", 1023 0, 31 0; -L_0x24e1fe0 .array/port v0x2408f40, L_0x24f4340; -L_0x24e21d0 .array/port v0x2408f40, C4<0000000000>; -L_0x24e2370 .array/port v0x2408f40, C4<0000000000>; -L_0x24e2510 .array/port v0x2408f40, C4<0000000000>; -L_0x24e26b0 .array/port v0x2408f40, C4<0000000000>; -S_0x240d5e0 .scope begin, "init_rom_block" "init_rom_block" 7 53, 7 53, S_0x240f820; - .timescale 0 0; -S_0x240dd90 .scope begin, "runtime_check" "runtime_check" 7 75, 7 75, S_0x240f820; - .timescale 0 0; -v0x240d7e0_0 .var "enable_check", 0 0; -S_0x241aca0 .scope module, "tw_rf" "RegFileLoad" 4 1034, 7 14, S_0x23c0270; - .timescale 0 0; -P_0x241a8f8 .param/l "addr_width" 7 23, C4<00000000000000000000000000001010>; -P_0x241a920 .param/l "binary" 7 27, C4<0>; -P_0x241a948 .param/l "data_width" 7 24, C4<00000000000000000000000000100000>; -P_0x241a970 .param/str "file" 7 22, "w"; -P_0x241a998 .param/l "hi" 7 26, C4<1111111111>; -P_0x241a9c0 .param/l "lo" 7 25, C4<0000000000>; -L_0x24e2940 .functor BUFZ 32, L_0x24e2850, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; -L_0x24e2b30 .functor BUFZ 32, L_0x24e2a40, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; -L_0x24e2cd0 .functor BUFZ 32, L_0x24e2be0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; -L_0x24e2e70 .functor BUFZ 32, L_0x24e2d80, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; -L_0x24e3010 .functor BUFZ 32, L_0x24e2f20, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; -v0x24155a0_0 .alias "ADDR_1", 9 0, v0x24d1ae0_0; -v0x2415180_0 .alias "ADDR_2", 9 0, v0x24d1b90_0; -v0x2415220_0 .alias "ADDR_3", 9 0, v0x24d1c40_0; -v0x24149f0_0 .alias "ADDR_4", 9 0, v0x24d1cf0_0; -v0x2414400_0 .alias "ADDR_5", 9 0, v0x24d1d70_0; -v0x24144a0_0 .alias "ADDR_IN", 9 0, v0x24d1e20_0; -v0x2414080_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x2422000_0 .alias "D_IN", 31 0, v0x24d1ed0_0; -v0x2414100_0 .alias "D_OUT_1", 31 0, v0x24d1f80_0; -v0x2413820_0 .net "D_OUT_2", 31 0, L_0x24e2b30; 1 drivers -v0x24138a0_0 .net "D_OUT_3", 31 0, L_0x24e2cd0; 1 drivers -v0x24134e0_0 .net "D_OUT_4", 31 0, L_0x24e2e70; 1 drivers -v0x2412630_0 .net "D_OUT_5", 31 0, L_0x24e3010; 1 drivers -v0x24126d0_0 .alias "WE", 0 0, v0x24d2030_0; -v0x23827c0_0 .net *"_s0", 31 0, L_0x24e2850; 1 drivers -v0x24112f0_0 .net *"_s12", 31 0, L_0x24e2d80; 1 drivers -v0x2382720_0 .net *"_s16", 31 0, L_0x24e2f20; 1 drivers -v0x2410850_0 .net *"_s4", 31 0, L_0x24e2a40; 1 drivers -v0x24108f0_0 .net *"_s8", 31 0, L_0x24e2be0; 1 drivers -v0x240fb60 .array "arr", 1023 0, 31 0; -E_0x2419550 .event posedge, v0x22b62d0_0; -L_0x24e2850 .array/port v0x240fb60, L_0x24f7090; -L_0x24e2a40 .array/port v0x240fb60, C4<0000000000>; -L_0x24e2be0 .array/port v0x240fb60, C4<0000000000>; -L_0x24e2d80 .array/port v0x240fb60, C4<0000000000>; -L_0x24e2f20 .array/port v0x240fb60, C4<0000000000>; -S_0x2415850 .scope begin, "init_rom_block" "init_rom_block" 7 53, 7 53, S_0x241aca0; - .timescale 0 0; -S_0x24191b0 .scope begin, "runtime_check" "runtime_check" 7 75, 7 75, S_0x241aca0; - .timescale 0 0; -v0x2418e00_0 .var "enable_check", 0 0; -S_0x241c7a0 .scope module, "w_l_lockVec_0_nextId_dummy2_0" "RevertReg" 4 1051, 5 7, S_0x23c0270; - .timescale 0 0; -P_0x241cc18 .param/l "init" 5 10, C4<1>; -P_0x241cc40 .param/l "width" 5 9, C4<00000000000000000000000000000001>; -v0x241b260_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x241b2e0_0 .alias "D_IN", 0 0, v0x24d2a60_0; -v0x241b060_0 .alias "EN", 0 0, v0x24d2b10_0; -v0x241b100_0 .net "Q_OUT", 0 0, C4<1>; 1 drivers -S_0x241df10 .scope module, "w_l_lockVec_0_nextId_dummy2_1" "RevertReg" 4 1058, 5 7, S_0x23c0270; - .timescale 0 0; -P_0x241e358 .param/l "init" 5 10, C4<1>; -P_0x241e380 .param/l "width" 5 9, C4<00000000000000000000000000000001>; -v0x241d370_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x241cd60_0 .alias "D_IN", 0 0, v0x24d2bc0_0; -v0x241cde0_0 .alias "EN", 0 0, v0x24d2c70_0; -v0x241cb60_0 .alias "Q_OUT", 0 0, v0x24d2d20_0; -S_0x241f3b0 .scope module, "w_l_lockVec_1_nextId_dummy2_0" "RevertReg" 4 1065, 5 7, S_0x23c0270; - .timescale 0 0; -P_0x241ee18 .param/l "init" 5 10, C4<1>; -P_0x241ee40 .param/l "width" 5 9, C4<00000000000000000000000000000001>; -v0x241e860_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x241e660_0 .alias "D_IN", 0 0, v0x24d3290_0; -v0x241e700_0 .alias "EN", 0 0, v0x24d3340_0; -v0x241e2a0_0 .net "Q_OUT", 0 0, C4<1>; 1 drivers -S_0x2422a60 .scope module, "w_l_lockVec_1_nextId_dummy2_1" "RevertReg" 4 1072, 5 7, S_0x23c0270; - .timescale 0 0; -P_0x24233d8 .param/l "init" 5 10, C4<1>; -P_0x2423400 .param/l "width" 5 9, C4<00000000000000000000000000000001>; -v0x2422920_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x2422090_0 .alias "D_IN", 0 0, v0x24d33f0_0; -v0x2421e60_0 .alias "EN", 0 0, v0x24d34a0_0; -v0x2421f00_0 .alias "Q_OUT", 0 0, v0x24d3550_0; -S_0x2423f20 .scope module, "w_l_lockVec_2_nextId_dummy2_0" "RevertReg" 4 1079, 5 7, S_0x23c0270; - .timescale 0 0; -P_0x24253a8 .param/l "init" 5 10, C4<1>; -P_0x24253d0 .param/l "width" 5 9, C4<00000000000000000000000000000001>; -v0x2423d80_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x24234c0_0 .alias "D_IN", 0 0, v0x24d3a80_0; -v0x2423560_0 .alias "EN", 0 0, v0x24d3b30_0; -v0x2423320_0 .net "Q_OUT", 0 0, C4<1>; 1 drivers -S_0x2427a70 .scope module, "w_l_lockVec_2_nextId_dummy2_1" "RevertReg" 4 1086, 5 7, S_0x23c0270; - .timescale 0 0; -P_0x2426b68 .param/l "init" 5 10, C4<1>; -P_0x2426b90 .param/l "width" 5 9, C4<00000000000000000000000000000001>; -v0x2425b80_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x2425720_0 .alias "D_IN", 0 0, v0x24d3be0_0; -v0x24257c0_0 .alias "EN", 0 0, v0x24d3c90_0; -v0x2425320_0 .alias "Q_OUT", 0 0, v0x24d3d40_0; -S_0x242a520 .scope module, "w_l_lockVec_3_nextId_dummy2_0" "RevertReg" 4 1093, 5 7, S_0x23c0270; - .timescale 0 0; -P_0x242b638 .param/l "init" 5 10, C4<1>; -P_0x242b660 .param/l "width" 5 9, C4<00000000000000000000000000000001>; -v0x242a1e0_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x2428260_0 .alias "D_IN", 0 0, v0x24d4270_0; -v0x2428090_0 .alias "EN", 0 0, v0x24d4320_0; -v0x2428130_0 .net "Q_OUT", 0 0, C4<1>; 1 drivers -S_0x24a10a0 .scope module, "w_l_lockVec_3_nextId_dummy2_1" "RevertReg" 4 1100, 5 7, S_0x23c0270; - .timescale 0 0; -P_0x2430ef8 .param/l "init" 5 10, C4<1>; -P_0x2430f20 .param/l "width" 5 9, C4<00000000000000000000000000000001>; -v0x22b62d0_0 .alias "CLK", 0 0, v0x24d4b60_0; -v0x242b9e0_0 .alias "D_IN", 0 0, v0x24d43d0_0; -v0x242ba80_0 .alias "EN", 0 0, v0x24d4480_0; -v0x242b580_0 .alias "Q_OUT", 0 0, v0x24d4530_0; - .scope S_0x23856f0; -T_0 ; - %movi 8, 2863311530, 32; - %movi 40, 43690, 16; - %set/v v0x2457dc0_0, 8, 48; - %movi 56, 2863311530, 32; - %movi 88, 43690, 16; - %set/v v0x2456950_0, 56, 48; - %set/v v0x24569d0_0, 0, 1; - %set/v v0x2458b40_0, 1, 1; - %end; - .thread T_0; - .scope S_0x23856f0; -T_1 ; - %wait E_0x2419550; - %load/v 8, v0x23d67b0_0, 1; - %cmpi/u 8, 0, 1; - %jmp/0xz T_1.0, 4; - %ix/load 0, 1, 0; - %assign/v0 v0x24569d0_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x2458b40_0, 0, 1; - %jmp T_1.1; -T_1.0 ; - %load/v 8, v0x23c9b20_0, 1; - %jmp/0xz T_1.2, 8; - %ix/load 0, 1, 0; - %assign/v0 v0x24569d0_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x2458b40_0, 0, 1; - %jmp T_1.3; -T_1.2 ; - %load/v 8, v0x23d0810_0, 1; - %load/v 9, v0x23d1330_0, 1; - %inv 9, 1; - %and 8, 9, 1; - %jmp/0xz T_1.4, 8; - %ix/load 0, 1, 0; - %assign/v0 v0x24569d0_0, 0, 1; - %load/v 8, v0x24569d0_0, 1; - %inv 8, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x2458b40_0, 0, 8; - %jmp T_1.5; -T_1.4 ; - %load/v 8, v0x23d1330_0, 1; - %load/v 9, v0x23d0810_0, 1; - %inv 9, 1; - %and 8, 9, 1; - %jmp/0xz T_1.6, 8; - %ix/load 0, 1, 0; - %assign/v0 v0x2458b40_0, 0, 1; - %load/v 8, v0x2458b40_0, 1; - %inv 8, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x24569d0_0, 0, 8; -T_1.6 ; -T_1.5 ; -T_1.3 ; -T_1.1 ; - %jmp T_1; - .thread T_1; - .scope S_0x23856f0; -T_2 ; - %wait E_0x2419550; - %load/v 8, v0x2458ac0_0, 1; - %mov 55, 8, 1; Repetition 48 - %mov 54, 8, 1; Repetition 47 - %mov 53, 8, 1; Repetition 46 - %mov 52, 8, 1; Repetition 45 - %mov 51, 8, 1; Repetition 44 - %mov 50, 8, 1; Repetition 43 - %mov 49, 8, 1; Repetition 42 - %mov 48, 8, 1; Repetition 41 - %mov 47, 8, 1; Repetition 40 - %mov 46, 8, 1; Repetition 39 - %mov 45, 8, 1; Repetition 38 - %mov 44, 8, 1; Repetition 37 - %mov 43, 8, 1; Repetition 36 - %mov 42, 8, 1; Repetition 35 - %mov 41, 8, 1; Repetition 34 - %mov 40, 8, 1; Repetition 33 - %mov 39, 8, 1; Repetition 32 - %mov 38, 8, 1; Repetition 31 - %mov 37, 8, 1; Repetition 30 - %mov 36, 8, 1; Repetition 29 - %mov 35, 8, 1; Repetition 28 - %mov 34, 8, 1; Repetition 27 - %mov 33, 8, 1; Repetition 26 - %mov 32, 8, 1; Repetition 25 - %mov 31, 8, 1; Repetition 24 - %mov 30, 8, 1; Repetition 23 - %mov 29, 8, 1; Repetition 22 - %mov 28, 8, 1; Repetition 21 - %mov 27, 8, 1; Repetition 20 - %mov 26, 8, 1; Repetition 19 - %mov 25, 8, 1; Repetition 18 - %mov 24, 8, 1; Repetition 17 - %mov 23, 8, 1; Repetition 16 - %mov 22, 8, 1; Repetition 15 - %mov 21, 8, 1; Repetition 14 - %mov 20, 8, 1; Repetition 13 - %mov 19, 8, 1; Repetition 12 - %mov 18, 8, 1; Repetition 11 - %mov 17, 8, 1; Repetition 10 - %mov 16, 8, 1; Repetition 9 - %mov 15, 8, 1; Repetition 8 - %mov 14, 8, 1; Repetition 7 - %mov 13, 8, 1; Repetition 6 - %mov 12, 8, 1; Repetition 5 - %mov 11, 8, 1; Repetition 4 - %mov 10, 8, 1; Repetition 3 - %mov 9, 8, 1; Repetition 2 - %load/v 56, v0x23d13d0_0, 48; - %and 8, 56, 48; - %load/v 56, v0x2489e60_0, 1; - %mov 103, 56, 1; Repetition 48 - %mov 102, 56, 1; Repetition 47 - %mov 101, 56, 1; Repetition 46 - %mov 100, 56, 1; Repetition 45 - %mov 99, 56, 1; Repetition 44 - %mov 98, 56, 1; Repetition 43 - %mov 97, 56, 1; Repetition 42 - %mov 96, 56, 1; Repetition 41 - %mov 95, 56, 1; Repetition 40 - %mov 94, 56, 1; Repetition 39 - %mov 93, 56, 1; Repetition 38 - %mov 92, 56, 1; Repetition 37 - %mov 91, 56, 1; Repetition 36 - %mov 90, 56, 1; Repetition 35 - %mov 89, 56, 1; Repetition 34 - %mov 88, 56, 1; Repetition 33 - %mov 87, 56, 1; Repetition 32 - %mov 86, 56, 1; Repetition 31 - %mov 85, 56, 1; Repetition 30 - %mov 84, 56, 1; Repetition 29 - %mov 83, 56, 1; Repetition 28 - %mov 82, 56, 1; Repetition 27 - %mov 81, 56, 1; Repetition 26 - %mov 80, 56, 1; Repetition 25 - %mov 79, 56, 1; Repetition 24 - %mov 78, 56, 1; Repetition 23 - %mov 77, 56, 1; Repetition 22 - %mov 76, 56, 1; Repetition 21 - %mov 75, 56, 1; Repetition 20 - %mov 74, 56, 1; Repetition 19 - %mov 73, 56, 1; Repetition 18 - %mov 72, 56, 1; Repetition 17 - %mov 71, 56, 1; Repetition 16 - %mov 70, 56, 1; Repetition 15 - %mov 69, 56, 1; Repetition 14 - %mov 68, 56, 1; Repetition 13 - %mov 67, 56, 1; Repetition 12 - %mov 66, 56, 1; Repetition 11 - %mov 65, 56, 1; Repetition 10 - %mov 64, 56, 1; Repetition 9 - %mov 63, 56, 1; Repetition 8 - %mov 62, 56, 1; Repetition 7 - %mov 61, 56, 1; Repetition 6 - %mov 60, 56, 1; Repetition 5 - %mov 59, 56, 1; Repetition 4 - %mov 58, 56, 1; Repetition 3 - %mov 57, 56, 1; Repetition 2 - %load/v 104, v0x2456950_0, 48; - %and 56, 104, 48; - %or 8, 56, 48; - %load/v 56, v0x24598a0_0, 1; - %mov 103, 56, 1; Repetition 48 - %mov 102, 56, 1; Repetition 47 - %mov 101, 56, 1; Repetition 46 - %mov 100, 56, 1; Repetition 45 - %mov 99, 56, 1; Repetition 44 - %mov 98, 56, 1; Repetition 43 - %mov 97, 56, 1; Repetition 42 - %mov 96, 56, 1; Repetition 41 - %mov 95, 56, 1; Repetition 40 - %mov 94, 56, 1; Repetition 39 - %mov 93, 56, 1; Repetition 38 - %mov 92, 56, 1; Repetition 37 - %mov 91, 56, 1; Repetition 36 - %mov 90, 56, 1; Repetition 35 - %mov 89, 56, 1; Repetition 34 - %mov 88, 56, 1; Repetition 33 - %mov 87, 56, 1; Repetition 32 - %mov 86, 56, 1; Repetition 31 - %mov 85, 56, 1; Repetition 30 - %mov 84, 56, 1; Repetition 29 - %mov 83, 56, 1; Repetition 28 - %mov 82, 56, 1; Repetition 27 - %mov 81, 56, 1; Repetition 26 - %mov 80, 56, 1; Repetition 25 - %mov 79, 56, 1; Repetition 24 - %mov 78, 56, 1; Repetition 23 - %mov 77, 56, 1; Repetition 22 - %mov 76, 56, 1; Repetition 21 - %mov 75, 56, 1; Repetition 20 - %mov 74, 56, 1; Repetition 19 - %mov 73, 56, 1; Repetition 18 - %mov 72, 56, 1; Repetition 17 - %mov 71, 56, 1; Repetition 16 - %mov 70, 56, 1; Repetition 15 - %mov 69, 56, 1; Repetition 14 - %mov 68, 56, 1; Repetition 13 - %mov 67, 56, 1; Repetition 12 - %mov 66, 56, 1; Repetition 11 - %mov 65, 56, 1; Repetition 10 - %mov 64, 56, 1; Repetition 9 - %mov 63, 56, 1; Repetition 8 - %mov 62, 56, 1; Repetition 7 - %mov 61, 56, 1; Repetition 6 - %mov 60, 56, 1; Repetition 5 - %mov 59, 56, 1; Repetition 4 - %mov 58, 56, 1; Repetition 3 - %mov 57, 56, 1; Repetition 2 - %load/v 104, v0x2457dc0_0, 48; - %and 56, 104, 48; - %or 8, 56, 48; - %ix/load 0, 48, 0; - %assign/v0 v0x2457dc0_0, 0, 8; - %load/v 8, v0x2457d40_0, 1; - %jmp/0 T_2.0, 8; - %load/v 9, v0x23d13d0_0, 48; - %jmp/1 T_2.2, 8; -T_2.0 ; End of true expr. - %load/v 57, v0x2456950_0, 48; - %jmp/0 T_2.1, 8; - ; End of false expr. - %blend 9, 57, 48; Condition unknown. - %jmp T_2.2; -T_2.1 ; - %mov 9, 57, 48; Return false value -T_2.2 ; - %ix/load 0, 48, 0; - %assign/v0 v0x2456950_0, 0, 9; - %jmp T_2; - .thread T_2; - .scope S_0x23856f0; -T_3 ; - %wait E_0x2419550; - %fork t_1, S_0x23ca5a0; - %jmp t_0; - .scope S_0x23ca5a0; -t_1 ; - %set/v v0x23ca010_0, 0, 1; - %set/v v0x23ca0d0_0, 0, 1; - %load/v 8, v0x23d67b0_0, 1; - %jmp/0xz T_3.0, 8; - %load/v 8, v0x24569d0_0, 1; - %inv 8, 1; - %load/v 9, v0x23d1330_0, 1; - %and 8, 9, 1; - %jmp/0xz T_3.2, 8; - %set/v v0x23ca010_0, 1, 1; - %vpi_call 6 142 "$display", "Warning: FIFO2: %m -- Dequeuing from empty fifo"; -T_3.2 ; - %load/v 8, v0x2458b40_0, 1; - %inv 8, 1; - %load/v 9, v0x23d0810_0, 1; - %and 8, 9, 1; - %load/v 9, v0x23d1330_0, 1; - %inv 9, 1; - %or 9, 1, 1; - %and 8, 9, 1; - %jmp/0xz T_3.4, 8; - %set/v v0x23ca0d0_0, 1, 1; - %vpi_call 6 147 "$display", "Warning: FIFO2: %m -- Enqueuing to a full fifo"; -T_3.4 ; -T_3.0 ; - %end; - .scope S_0x23856f0; -t_0 %join; - %jmp T_3; - .thread T_3; - .scope S_0x242b3f0; -T_4 ; - %movi 8, 10, 4; - %set/v v0x2385210_0, 8, 3; - %movi 8, 10, 4; - %set/v v0x2384750_0, 8, 3; - %set/v v0x2385c50_0, 0, 1; - %set/v v0x2385cf0_0, 1, 1; - %end; - .thread T_4; - .scope S_0x242b3f0; -T_5 ; - %wait E_0x2419550; - %load/v 8, v0x2410b00_0, 1; - %cmpi/u 8, 0, 1; - %jmp/0xz T_5.0, 4; - %ix/load 0, 1, 0; - %assign/v0 v0x2385c50_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x2385cf0_0, 0, 1; - %jmp T_5.1; -T_5.0 ; - %load/v 8, v0x24260f0_0, 1; - %jmp/0xz T_5.2, 8; - %ix/load 0, 1, 0; - %assign/v0 v0x2385c50_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x2385cf0_0, 0, 1; - %jmp T_5.3; -T_5.2 ; - %load/v 8, v0x2424e90_0, 1; - %load/v 9, v0x2425dd0_0, 1; - %inv 9, 1; - %and 8, 9, 1; - %jmp/0xz T_5.4, 8; - %ix/load 0, 1, 0; - %assign/v0 v0x2385c50_0, 0, 1; - %load/v 8, v0x2385c50_0, 1; - %inv 8, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x2385cf0_0, 0, 8; - %jmp T_5.5; -T_5.4 ; - %load/v 8, v0x2425dd0_0, 1; - %load/v 9, v0x2424e90_0, 1; - %inv 9, 1; - %and 8, 9, 1; - %jmp/0xz T_5.6, 8; - %ix/load 0, 1, 0; - %assign/v0 v0x2385cf0_0, 0, 1; - %load/v 8, v0x2385cf0_0, 1; - %inv 8, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x2385c50_0, 0, 8; -T_5.6 ; -T_5.5 ; -T_5.3 ; -T_5.1 ; - %jmp T_5; - .thread T_5; - .scope S_0x242b3f0; -T_6 ; - %wait E_0x2419550; - %load/v 8, v0x2384c30_0, 1; - %mov 10, 8, 1; Repetition 3 - %mov 9, 8, 1; Repetition 2 - %load/v 11, v0x2425e70_0, 3; - %and 8, 11, 3; - %load/v 11, v0x23841f0_0, 1; - %mov 13, 11, 1; Repetition 3 - %mov 12, 11, 1; Repetition 2 - %load/v 14, v0x2384750_0, 3; - %and 11, 14, 3; - %or 8, 11, 3; - %load/v 11, v0x2384cd0_0, 1; - %mov 13, 11, 1; Repetition 3 - %mov 12, 11, 1; Repetition 2 - %load/v 14, v0x2385210_0, 3; - %and 11, 14, 3; - %or 8, 11, 3; - %ix/load 0, 3, 0; - %assign/v0 v0x2385210_0, 0, 8; - %load/v 8, v0x2385190_0, 1; - %jmp/0 T_6.0, 8; - %load/v 9, v0x2425e70_0, 3; - %jmp/1 T_6.2, 8; -T_6.0 ; End of true expr. - %load/v 12, v0x2384750_0, 3; - %jmp/0 T_6.1, 8; - ; End of false expr. - %blend 9, 12, 3; Condition unknown. - %jmp T_6.2; -T_6.1 ; - %mov 9, 12, 3; Return false value -T_6.2 ; - %ix/load 0, 3, 0; - %assign/v0 v0x2384750_0, 0, 9; - %jmp T_6; - .thread T_6; - .scope S_0x242b3f0; -T_7 ; - %wait E_0x2419550; - %fork t_3, S_0x2428ec0; - %jmp t_2; - .scope S_0x2428ec0; -t_3 ; - %set/v v0x2428b00_0, 0, 1; - %set/v v0x2428bc0_0, 0, 1; - %load/v 8, v0x2410b00_0, 1; - %jmp/0xz T_7.0, 8; - %load/v 8, v0x2385c50_0, 1; - %inv 8, 1; - %load/v 9, v0x2425dd0_0, 1; - %and 8, 9, 1; - %jmp/0xz T_7.2, 8; - %set/v v0x2428b00_0, 1, 1; - %vpi_call 6 142 "$display", "Warning: FIFO2: %m -- Dequeuing from empty fifo"; -T_7.2 ; - %load/v 8, v0x2385cf0_0, 1; - %inv 8, 1; - %load/v 9, v0x2424e90_0, 1; - %and 8, 9, 1; - %load/v 9, v0x2425dd0_0, 1; - %inv 9, 1; - %or 9, 1, 1; - %and 8, 9, 1; - %jmp/0xz T_7.4, 8; - %set/v v0x2428bc0_0, 1, 1; - %vpi_call 6 147 "$display", "Warning: FIFO2: %m -- Enqueuing to a full fifo"; -T_7.4 ; -T_7.0 ; - %end; - .scope S_0x242b3f0; -t_2 %join; - %jmp T_7; - .thread T_7; - .scope S_0x24261e0; -T_8 ; - %movi 8, 2863311530, 32; - %movi 40, 10922, 14; - %set/v v0x242c4b0_0, 8, 45; - %movi 54, 2863311530, 32; - %movi 86, 10922, 14; - %set/v v0x242cd20_0, 54, 45; - %set/v v0x242b140_0, 0, 1; - %set/v v0x242b1e0_0, 1, 1; - %end; - .thread T_8; - .scope S_0x24261e0; -T_9 ; - %wait E_0x2419550; - %load/v 8, v0x2414620_0, 1; - %cmpi/u 8, 0, 1; - %jmp/0xz T_9.0, 4; - %ix/load 0, 1, 0; - %assign/v0 v0x242b140_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x242b1e0_0, 0, 1; - %jmp T_9.1; -T_9.0 ; - %load/v 8, v0x23f6d30_0, 1; - %jmp/0xz T_9.2, 8; - %ix/load 0, 1, 0; - %assign/v0 v0x242b140_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x242b1e0_0, 0, 1; - %jmp T_9.3; -T_9.2 ; - %load/v 8, v0x241a4a0_0, 1; - %load/v 9, v0x23aa940_0, 1; - %inv 9, 1; - %and 8, 9, 1; - %jmp/0xz T_9.4, 8; - %ix/load 0, 1, 0; - %assign/v0 v0x242b140_0, 0, 1; - %load/v 8, v0x242b140_0, 1; - %inv 8, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x242b1e0_0, 0, 8; - %jmp T_9.5; -T_9.4 ; - %load/v 8, v0x23aa940_0, 1; - %load/v 9, v0x241a4a0_0, 1; - %inv 9, 1; - %and 8, 9, 1; - %jmp/0xz T_9.6, 8; - %ix/load 0, 1, 0; - %assign/v0 v0x242b1e0_0, 0, 1; - %load/v 8, v0x242b1e0_0, 1; - %inv 8, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x242b140_0, 0, 8; -T_9.6 ; -T_9.5 ; -T_9.3 ; -T_9.1 ; - %jmp T_9; - .thread T_9; - .scope S_0x24261e0; -T_10 ; - %wait E_0x2419550; - %load/v 8, v0x24315b0_0, 1; - %mov 52, 8, 1; Repetition 45 - %mov 51, 8, 1; Repetition 44 - %mov 50, 8, 1; Repetition 43 - %mov 49, 8, 1; Repetition 42 - %mov 48, 8, 1; Repetition 41 - %mov 47, 8, 1; Repetition 40 - %mov 46, 8, 1; Repetition 39 - %mov 45, 8, 1; Repetition 38 - %mov 44, 8, 1; Repetition 37 - %mov 43, 8, 1; Repetition 36 - %mov 42, 8, 1; Repetition 35 - %mov 41, 8, 1; Repetition 34 - %mov 40, 8, 1; Repetition 33 - %mov 39, 8, 1; Repetition 32 - %mov 38, 8, 1; Repetition 31 - %mov 37, 8, 1; Repetition 30 - %mov 36, 8, 1; Repetition 29 - %mov 35, 8, 1; Repetition 28 - %mov 34, 8, 1; Repetition 27 - %mov 33, 8, 1; Repetition 26 - %mov 32, 8, 1; Repetition 25 - %mov 31, 8, 1; Repetition 24 - %mov 30, 8, 1; Repetition 23 - %mov 29, 8, 1; Repetition 22 - %mov 28, 8, 1; Repetition 21 - %mov 27, 8, 1; Repetition 20 - %mov 26, 8, 1; Repetition 19 - %mov 25, 8, 1; Repetition 18 - %mov 24, 8, 1; Repetition 17 - %mov 23, 8, 1; Repetition 16 - %mov 22, 8, 1; Repetition 15 - %mov 21, 8, 1; Repetition 14 - %mov 20, 8, 1; Repetition 13 - %mov 19, 8, 1; Repetition 12 - %mov 18, 8, 1; Repetition 11 - %mov 17, 8, 1; Repetition 10 - %mov 16, 8, 1; Repetition 9 - %mov 15, 8, 1; Repetition 8 - %mov 14, 8, 1; Repetition 7 - %mov 13, 8, 1; Repetition 6 - %mov 12, 8, 1; Repetition 5 - %mov 11, 8, 1; Repetition 4 - %mov 10, 8, 1; Repetition 3 - %mov 9, 8, 1; Repetition 2 - %load/v 53, v0x23aa9e0_0, 45; - %and 8, 53, 45; - %load/v 53, v0x24310f0_0, 1; - %mov 97, 53, 1; Repetition 45 - %mov 96, 53, 1; Repetition 44 - %mov 95, 53, 1; Repetition 43 - %mov 94, 53, 1; Repetition 42 - %mov 93, 53, 1; Repetition 41 - %mov 92, 53, 1; Repetition 40 - %mov 91, 53, 1; Repetition 39 - %mov 90, 53, 1; Repetition 38 - %mov 89, 53, 1; Repetition 37 - %mov 88, 53, 1; Repetition 36 - %mov 87, 53, 1; Repetition 35 - %mov 86, 53, 1; Repetition 34 - %mov 85, 53, 1; Repetition 33 - %mov 84, 53, 1; Repetition 32 - %mov 83, 53, 1; Repetition 31 - %mov 82, 53, 1; Repetition 30 - %mov 81, 53, 1; Repetition 29 - %mov 80, 53, 1; Repetition 28 - %mov 79, 53, 1; Repetition 27 - %mov 78, 53, 1; Repetition 26 - %mov 77, 53, 1; Repetition 25 - %mov 76, 53, 1; Repetition 24 - %mov 75, 53, 1; Repetition 23 - %mov 74, 53, 1; Repetition 22 - %mov 73, 53, 1; Repetition 21 - %mov 72, 53, 1; Repetition 20 - %mov 71, 53, 1; Repetition 19 - %mov 70, 53, 1; Repetition 18 - %mov 69, 53, 1; Repetition 17 - %mov 68, 53, 1; Repetition 16 - %mov 67, 53, 1; Repetition 15 - %mov 66, 53, 1; Repetition 14 - %mov 65, 53, 1; Repetition 13 - %mov 64, 53, 1; Repetition 12 - %mov 63, 53, 1; Repetition 11 - %mov 62, 53, 1; Repetition 10 - %mov 61, 53, 1; Repetition 9 - %mov 60, 53, 1; Repetition 8 - %mov 59, 53, 1; Repetition 7 - %mov 58, 53, 1; Repetition 6 - %mov 57, 53, 1; Repetition 5 - %mov 56, 53, 1; Repetition 4 - %mov 55, 53, 1; Repetition 3 - %mov 54, 53, 1; Repetition 2 - %load/v 98, v0x242cd20_0, 45; - %and 53, 98, 45; - %or 8, 53, 45; - %load/v 53, v0x2431030_0, 1; - %mov 97, 53, 1; Repetition 45 - %mov 96, 53, 1; Repetition 44 - %mov 95, 53, 1; Repetition 43 - %mov 94, 53, 1; Repetition 42 - %mov 93, 53, 1; Repetition 41 - %mov 92, 53, 1; Repetition 40 - %mov 91, 53, 1; Repetition 39 - %mov 90, 53, 1; Repetition 38 - %mov 89, 53, 1; Repetition 37 - %mov 88, 53, 1; Repetition 36 - %mov 87, 53, 1; Repetition 35 - %mov 86, 53, 1; Repetition 34 - %mov 85, 53, 1; Repetition 33 - %mov 84, 53, 1; Repetition 32 - %mov 83, 53, 1; Repetition 31 - %mov 82, 53, 1; Repetition 30 - %mov 81, 53, 1; Repetition 29 - %mov 80, 53, 1; Repetition 28 - %mov 79, 53, 1; Repetition 27 - %mov 78, 53, 1; Repetition 26 - %mov 77, 53, 1; Repetition 25 - %mov 76, 53, 1; Repetition 24 - %mov 75, 53, 1; Repetition 23 - %mov 74, 53, 1; Repetition 22 - %mov 73, 53, 1; Repetition 21 - %mov 72, 53, 1; Repetition 20 - %mov 71, 53, 1; Repetition 19 - %mov 70, 53, 1; Repetition 18 - %mov 69, 53, 1; Repetition 17 - %mov 68, 53, 1; Repetition 16 - %mov 67, 53, 1; Repetition 15 - %mov 66, 53, 1; Repetition 14 - %mov 65, 53, 1; Repetition 13 - %mov 64, 53, 1; Repetition 12 - %mov 63, 53, 1; Repetition 11 - %mov 62, 53, 1; Repetition 10 - %mov 61, 53, 1; Repetition 9 - %mov 60, 53, 1; Repetition 8 - %mov 59, 53, 1; Repetition 7 - %mov 58, 53, 1; Repetition 6 - %mov 57, 53, 1; Repetition 5 - %mov 56, 53, 1; Repetition 4 - %mov 55, 53, 1; Repetition 3 - %mov 54, 53, 1; Repetition 2 - %load/v 98, v0x242c4b0_0, 45; - %and 53, 98, 45; - %or 8, 53, 45; - %ix/load 0, 45, 0; - %assign/v0 v0x242c4b0_0, 0, 8; - %load/v 8, v0x242c430_0, 1; - %jmp/0 T_10.0, 8; - %load/v 9, v0x23aa9e0_0, 45; - %jmp/1 T_10.2, 8; -T_10.0 ; End of true expr. - %load/v 54, v0x242cd20_0, 45; - %jmp/0 T_10.1, 8; - ; End of false expr. - %blend 9, 54, 45; Condition unknown. - %jmp T_10.2; -T_10.1 ; - %mov 9, 54, 45; Return false value -T_10.2 ; - %ix/load 0, 45, 0; - %assign/v0 v0x242cd20_0, 0, 9; - %jmp T_10; - .thread T_10; - .scope S_0x24261e0; -T_11 ; - %wait E_0x2419550; - %fork t_5, S_0x23fa2d0; - %jmp t_4; - .scope S_0x23fa2d0; -t_5 ; - %set/v v0x23f87c0_0, 0, 1; - %set/v v0x23f8860_0, 0, 1; - %load/v 8, v0x2414620_0, 1; - %jmp/0xz T_11.0, 8; - %load/v 8, v0x242b140_0, 1; - %inv 8, 1; - %load/v 9, v0x23aa940_0, 1; - %and 8, 9, 1; - %jmp/0xz T_11.2, 8; - %set/v v0x23f87c0_0, 1, 1; - %vpi_call 6 142 "$display", "Warning: FIFO2: %m -- Dequeuing from empty fifo"; -T_11.2 ; - %load/v 8, v0x242b1e0_0, 1; - %inv 8, 1; - %load/v 9, v0x241a4a0_0, 1; - %and 8, 9, 1; - %load/v 9, v0x23aa940_0, 1; - %inv 9, 1; - %or 9, 1, 1; - %and 8, 9, 1; - %jmp/0xz T_11.4, 8; - %set/v v0x23f8860_0, 1, 1; - %vpi_call 6 147 "$display", "Warning: FIFO2: %m -- Enqueuing to a full fifo"; -T_11.4 ; -T_11.0 ; - %end; - .scope S_0x24261e0; -t_4 %join; - %jmp T_11; - .thread T_11; - .scope S_0x23ae380; -T_12 ; - %movi 8, 42, 6; - %set/v v0x23c8070_0, 8, 5; - %movi 8, 42, 6; - %set/v v0x23cf9b0_0, 8, 5; - %set/v v0x23cfa30_0, 0, 1; - %set/v v0x23c8cf0_0, 1, 1; - %end; - .thread T_12; - .scope S_0x23ae380; -T_13 ; - %wait E_0x2419550; - %load/v 8, v0x23b37d0_0, 1; - %cmpi/u 8, 0, 1; - %jmp/0xz T_13.0, 4; - %ix/load 0, 1, 0; - %assign/v0 v0x23cfa30_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x23c8cf0_0, 0, 1; - %jmp T_13.1; -T_13.0 ; - %load/v 8, v0x23b2980_0, 1; - %jmp/0xz T_13.2, 8; - %ix/load 0, 1, 0; - %assign/v0 v0x23cfa30_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x23c8cf0_0, 0, 1; - %jmp T_13.3; -T_13.2 ; - %load/v 8, v0x23b3da0_0, 1; - %load/v 9, v0x23b5ad0_0, 1; - %inv 9, 1; - %and 8, 9, 1; - %jmp/0xz T_13.4, 8; - %ix/load 0, 1, 0; - %assign/v0 v0x23cfa30_0, 0, 1; - %load/v 8, v0x23cfa30_0, 1; - %inv 8, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x23c8cf0_0, 0, 8; - %jmp T_13.5; -T_13.4 ; - %load/v 8, v0x23b5ad0_0, 1; - %load/v 9, v0x23b3da0_0, 1; - %inv 9, 1; - %and 8, 9, 1; - %jmp/0xz T_13.6, 8; - %ix/load 0, 1, 0; - %assign/v0 v0x23c8cf0_0, 0, 1; - %load/v 8, v0x23c8cf0_0, 1; - %inv 8, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x23cfa30_0, 0, 8; -T_13.6 ; -T_13.5 ; -T_13.3 ; -T_13.1 ; - %jmp T_13; - .thread T_13; - .scope S_0x23ae380; -T_14 ; - %wait E_0x2419550; - %load/v 8, v0x23c2d60_0, 1; - %mov 12, 8, 1; Repetition 5 - %mov 11, 8, 1; Repetition 4 - %mov 10, 8, 1; Repetition 3 - %mov 9, 8, 1; Repetition 2 - %load/v 13, v0x23b5b70_0, 5; - %and 8, 13, 5; - %load/v 13, v0x23c2cc0_0, 1; - %mov 17, 13, 1; Repetition 5 - %mov 16, 13, 1; Repetition 4 - %mov 15, 13, 1; Repetition 3 - %mov 14, 13, 1; Repetition 2 - %load/v 18, v0x23cf9b0_0, 5; - %and 13, 18, 5; - %or 8, 13, 5; - %load/v 13, v0x23c3270_0, 1; - %mov 17, 13, 1; Repetition 5 - %mov 16, 13, 1; Repetition 4 - %mov 15, 13, 1; Repetition 3 - %mov 14, 13, 1; Repetition 2 - %load/v 18, v0x23c8070_0, 5; - %and 13, 18, 5; - %or 8, 13, 5; - %ix/load 0, 5, 0; - %assign/v0 v0x23c8070_0, 0, 8; - %load/v 8, v0x23c7fd0_0, 1; - %jmp/0 T_14.0, 8; - %load/v 9, v0x23b5b70_0, 5; - %jmp/1 T_14.2, 8; -T_14.0 ; End of true expr. - %load/v 14, v0x23cf9b0_0, 5; - %jmp/0 T_14.1, 8; - ; End of false expr. - %blend 9, 14, 5; Condition unknown. - %jmp T_14.2; -T_14.1 ; - %mov 9, 14, 5; Return false value -T_14.2 ; - %ix/load 0, 5, 0; - %assign/v0 v0x23cf9b0_0, 0, 9; - %jmp T_14; - .thread T_14; - .scope S_0x23ae380; -T_15 ; - %wait E_0x2419550; - %fork t_7, S_0x23ac000; - %jmp t_6; - .scope S_0x23ac000; -t_7 ; - %set/v v0x23aa5c0_0, 0, 1; - %set/v v0x23aa640_0, 0, 1; - %load/v 8, v0x23b37d0_0, 1; - %jmp/0xz T_15.0, 8; - %load/v 8, v0x23cfa30_0, 1; - %inv 8, 1; - %load/v 9, v0x23b5ad0_0, 1; - %and 8, 9, 1; - %jmp/0xz T_15.2, 8; - %set/v v0x23aa5c0_0, 1, 1; - %vpi_call 6 142 "$display", "Warning: FIFO2: %m -- Dequeuing from empty fifo"; -T_15.2 ; - %load/v 8, v0x23c8cf0_0, 1; - %inv 8, 1; - %load/v 9, v0x23b3da0_0, 1; - %and 8, 9, 1; - %load/v 9, v0x23b5ad0_0, 1; - %inv 9, 1; - %or 9, 1, 1; - %and 8, 9, 1; - %jmp/0xz T_15.4, 8; - %set/v v0x23aa640_0, 1, 1; - %vpi_call 6 147 "$display", "Warning: FIFO2: %m -- Enqueuing to a full fifo"; -T_15.4 ; -T_15.0 ; - %end; - .scope S_0x23ae380; -t_6 %join; - %jmp T_15; - .thread T_15; - .scope S_0x238fee0; -T_16 ; - %movi 8, 43690, 16; - %set/v v0x23a2e70_0, 8, 15; - %movi 8, 43690, 16; - %set/v v0x23ab190_0, 8, 15; - %set/v v0x23ab210_0, 0, 1; - %set/v v0x23a4e80_0, 1, 1; - %end; - .thread T_16; - .scope S_0x238fee0; -T_17 ; - %wait E_0x2419550; - %load/v 8, v0x23958c0_0, 1; - %cmpi/u 8, 0, 1; - %jmp/0xz T_17.0, 4; - %ix/load 0, 1, 0; - %assign/v0 v0x23ab210_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x23a4e80_0, 0, 1; - %jmp T_17.1; -T_17.0 ; - %load/v 8, v0x238c480_0, 1; - %jmp/0xz T_17.2, 8; - %ix/load 0, 1, 0; - %assign/v0 v0x23ab210_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x23a4e80_0, 0, 1; - %jmp T_17.3; -T_17.2 ; - %load/v 8, v0x23972b0_0, 1; - %load/v 9, v0x238c520_0, 1; - %inv 9, 1; - %and 8, 9, 1; - %jmp/0xz T_17.4, 8; - %ix/load 0, 1, 0; - %assign/v0 v0x23ab210_0, 0, 1; - %load/v 8, v0x23ab210_0, 1; - %inv 8, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x23a4e80_0, 0, 8; - %jmp T_17.5; -T_17.4 ; - %load/v 8, v0x238c520_0, 1; - %load/v 9, v0x23972b0_0, 1; - %inv 9, 1; - %and 8, 9, 1; - %jmp/0xz T_17.6, 8; - %ix/load 0, 1, 0; - %assign/v0 v0x23a4e80_0, 0, 1; - %load/v 8, v0x23a4e80_0, 1; - %inv 8, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x23ab210_0, 0, 8; -T_17.6 ; -T_17.5 ; -T_17.3 ; -T_17.1 ; - %jmp T_17; - .thread T_17; - .scope S_0x238fee0; -T_18 ; - %wait E_0x2419550; - %load/v 8, v0x23a6d20_0, 1; - %mov 22, 8, 1; Repetition 15 - %mov 21, 8, 1; Repetition 14 - %mov 20, 8, 1; Repetition 13 - %mov 19, 8, 1; Repetition 12 - %mov 18, 8, 1; Repetition 11 - %mov 17, 8, 1; Repetition 10 - %mov 16, 8, 1; Repetition 9 - %mov 15, 8, 1; Repetition 8 - %mov 14, 8, 1; Repetition 7 - %mov 13, 8, 1; Repetition 6 - %mov 12, 8, 1; Repetition 5 - %mov 11, 8, 1; Repetition 4 - %mov 10, 8, 1; Repetition 3 - %mov 9, 8, 1; Repetition 2 - %load/v 23, v0x2394460_0, 15; - %and 8, 23, 15; - %load/v 23, v0x23a6c80_0, 1; - %mov 37, 23, 1; Repetition 15 - %mov 36, 23, 1; Repetition 14 - %mov 35, 23, 1; Repetition 13 - %mov 34, 23, 1; Repetition 12 - %mov 33, 23, 1; Repetition 11 - %mov 32, 23, 1; Repetition 10 - %mov 31, 23, 1; Repetition 9 - %mov 30, 23, 1; Repetition 8 - %mov 29, 23, 1; Repetition 7 - %mov 28, 23, 1; Repetition 6 - %mov 27, 23, 1; Repetition 5 - %mov 26, 23, 1; Repetition 4 - %mov 25, 23, 1; Repetition 3 - %mov 24, 23, 1; Repetition 2 - %load/v 38, v0x23ab190_0, 15; - %and 23, 38, 15; - %or 8, 23, 15; - %load/v 23, v0x23a3a00_0, 1; - %mov 37, 23, 1; Repetition 15 - %mov 36, 23, 1; Repetition 14 - %mov 35, 23, 1; Repetition 13 - %mov 34, 23, 1; Repetition 12 - %mov 33, 23, 1; Repetition 11 - %mov 32, 23, 1; Repetition 10 - %mov 31, 23, 1; Repetition 9 - %mov 30, 23, 1; Repetition 8 - %mov 29, 23, 1; Repetition 7 - %mov 28, 23, 1; Repetition 6 - %mov 27, 23, 1; Repetition 5 - %mov 26, 23, 1; Repetition 4 - %mov 25, 23, 1; Repetition 3 - %mov 24, 23, 1; Repetition 2 - %load/v 38, v0x23a2e70_0, 15; - %and 23, 38, 15; - %or 8, 23, 15; - %ix/load 0, 15, 0; - %assign/v0 v0x23a2e70_0, 0, 8; - %load/v 8, v0x23a2df0_0, 1; - %jmp/0 T_18.0, 8; - %load/v 9, v0x2394460_0, 15; - %jmp/1 T_18.2, 8; -T_18.0 ; End of true expr. - %load/v 24, v0x23ab190_0, 15; - %jmp/0 T_18.1, 8; - ; End of false expr. - %blend 9, 24, 15; Condition unknown. - %jmp T_18.2; -T_18.1 ; - %mov 9, 24, 15; Return false value -T_18.2 ; - %ix/load 0, 15, 0; - %assign/v0 v0x23ab190_0, 0, 9; - %jmp T_18; - .thread T_18; - .scope S_0x238fee0; -T_19 ; - %wait E_0x2419550; - %fork t_9, S_0x238e4d0; - %jmp t_8; - .scope S_0x238e4d0; -t_9 ; - %set/v v0x23902e0_0, 0, 1; - %set/v v0x238dee0_0, 0, 1; - %load/v 8, v0x23958c0_0, 1; - %jmp/0xz T_19.0, 8; - %load/v 8, v0x23ab210_0, 1; - %inv 8, 1; - %load/v 9, v0x238c520_0, 1; - %and 8, 9, 1; - %jmp/0xz T_19.2, 8; - %set/v v0x23902e0_0, 1, 1; - %vpi_call 6 142 "$display", "Warning: FIFO2: %m -- Dequeuing from empty fifo"; -T_19.2 ; - %load/v 8, v0x23a4e80_0, 1; - %inv 8, 1; - %load/v 9, v0x23972b0_0, 1; - %and 8, 9, 1; - %load/v 9, v0x238c520_0, 1; - %inv 9, 1; - %or 9, 1, 1; - %and 8, 9, 1; - %jmp/0xz T_19.4, 8; - %set/v v0x238dee0_0, 1, 1; - %vpi_call 6 147 "$display", "Warning: FIFO2: %m -- Enqueuing to a full fifo"; -T_19.4 ; -T_19.0 ; - %end; - .scope S_0x238fee0; -t_8 %join; - %jmp T_19; - .thread T_19; - .scope S_0x2454810; -T_20 ; - %movi 8, 10, 4; - %set/v v0x2387990_0, 8, 3; - %movi 8, 10, 4; - %set/v v0x2387a10_0, 8, 3; - %set/v v0x23862f0_0, 0, 1; - %set/v v0x2390260_0, 1, 1; - %end; - .thread T_20; - .scope S_0x2454810; -T_21 ; - %wait E_0x2419550; - %load/v 8, v0x2383180_0, 1; - %cmpi/u 8, 0, 1; - %jmp/0xz T_21.0, 4; - %ix/load 0, 1, 0; - %assign/v0 v0x23862f0_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x2390260_0, 0, 1; - %jmp T_21.1; -T_21.0 ; - %load/v 8, v0x244ef10_0, 1; - %jmp/0xz T_21.2, 8; - %ix/load 0, 1, 0; - %assign/v0 v0x23862f0_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x2390260_0, 0, 1; - %jmp T_21.3; -T_21.2 ; - %load/v 8, v0x23e2c60_0, 1; - %load/v 9, v0x244e440_0, 1; - %inv 9, 1; - %and 8, 9, 1; - %jmp/0xz T_21.4, 8; - %ix/load 0, 1, 0; - %assign/v0 v0x23862f0_0, 0, 1; - %load/v 8, v0x23862f0_0, 1; - %inv 8, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x2390260_0, 0, 8; - %jmp T_21.5; -T_21.4 ; - %load/v 8, v0x244e440_0, 1; - %load/v 9, v0x23e2c60_0, 1; - %inv 9, 1; - %and 8, 9, 1; - %jmp/0xz T_21.6, 8; - %ix/load 0, 1, 0; - %assign/v0 v0x2390260_0, 0, 1; - %load/v 8, v0x2390260_0, 1; - %inv 8, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x23862f0_0, 0, 8; -T_21.6 ; -T_21.5 ; -T_21.3 ; -T_21.1 ; - %jmp T_21; - .thread T_21; - .scope S_0x2454810; -T_22 ; - %wait E_0x2419550; - %load/v 8, v0x2381ef0_0, 1; - %mov 10, 8, 1; Repetition 3 - %mov 9, 8, 1; Repetition 2 - %load/v 11, v0x244e4e0_0, 3; - %and 8, 11, 3; - %load/v 11, v0x2382eb0_0, 1; - %mov 13, 11, 1; Repetition 3 - %mov 12, 11, 1; Repetition 2 - %load/v 14, v0x2387a10_0, 3; - %and 11, 14, 3; - %or 8, 11, 3; - %load/v 11, v0x2381f70_0, 1; - %mov 13, 11, 1; Repetition 3 - %mov 12, 11, 1; Repetition 2 - %load/v 14, v0x2387990_0, 3; - %and 11, 14, 3; - %or 8, 11, 3; - %ix/load 0, 3, 0; - %assign/v0 v0x2387990_0, 0, 8; - %load/v 8, v0x2437080_0, 1; - %jmp/0 T_22.0, 8; - %load/v 9, v0x244e4e0_0, 3; - %jmp/1 T_22.2, 8; -T_22.0 ; End of true expr. - %load/v 12, v0x2387a10_0, 3; - %jmp/0 T_22.1, 8; - ; End of false expr. - %blend 9, 12, 3; Condition unknown. - %jmp T_22.2; -T_22.1 ; - %mov 9, 12, 3; Return false value -T_22.2 ; - %ix/load 0, 3, 0; - %assign/v0 v0x2387a10_0, 0, 9; - %jmp T_22; - .thread T_22; - .scope S_0x2454810; -T_23 ; - %wait E_0x2419550; - %fork t_11, S_0x24505f0; - %jmp t_10; - .scope S_0x24505f0; -t_11 ; - %set/v v0x244f840_0, 0, 1; - %set/v v0x244f8c0_0, 0, 1; - %load/v 8, v0x2383180_0, 1; - %jmp/0xz T_23.0, 8; - %load/v 8, v0x23862f0_0, 1; - %inv 8, 1; - %load/v 9, v0x244e440_0, 1; - %and 8, 9, 1; - %jmp/0xz T_23.2, 8; - %set/v v0x244f840_0, 1, 1; - %vpi_call 6 142 "$display", "Warning: FIFO2: %m -- Dequeuing from empty fifo"; -T_23.2 ; - %load/v 8, v0x2390260_0, 1; - %inv 8, 1; - %load/v 9, v0x23e2c60_0, 1; - %and 8, 9, 1; - %load/v 9, v0x244e440_0, 1; - %inv 9, 1; - %or 9, 1, 1; - %and 8, 9, 1; - %jmp/0xz T_23.4, 8; - %set/v v0x244f8c0_0, 1, 1; - %vpi_call 6 147 "$display", "Warning: FIFO2: %m -- Enqueuing to a full fifo"; -T_23.4 ; -T_23.0 ; - %end; - .scope S_0x2454810; -t_10 %join; - %jmp T_23; - .thread T_23; - .scope S_0x2478f70; -T_24 ; - %movi 8, 2, 2; - %set/v v0x2457070_0, 8, 2; - %movi 8, 2, 2; - %set/v v0x2455c00_0, 8, 2; - %set/v v0x2455c80_0, 0, 1; - %set/v v0x24581f0_0, 1, 1; - %end; - .thread T_24; - .scope S_0x2478f70; -T_25 ; - %wait E_0x2419550; - %load/v 8, v0x2471590_0, 1; - %cmpi/u 8, 0, 1; - %jmp/0xz T_25.0, 4; - %ix/load 0, 1, 0; - %assign/v0 v0x2455c80_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x24581f0_0, 0, 1; - %jmp T_25.1; -T_25.0 ; - %load/v 8, v0x24730c0_0, 1; - %jmp/0xz T_25.2, 8; - %ix/load 0, 1, 0; - %assign/v0 v0x2455c80_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x24581f0_0, 0, 1; - %jmp T_25.3; -T_25.2 ; - %load/v 8, v0x2471ca0_0, 1; - %load/v 9, v0x2473160_0, 1; - %inv 9, 1; - %and 8, 9, 1; - %jmp/0xz T_25.4, 8; - %ix/load 0, 1, 0; - %assign/v0 v0x2455c80_0, 0, 1; - %load/v 8, v0x2455c80_0, 1; - %inv 8, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x24581f0_0, 0, 8; - %jmp T_25.5; -T_25.4 ; - %load/v 8, v0x2473160_0, 1; - %load/v 9, v0x2471ca0_0, 1; - %inv 9, 1; - %and 8, 9, 1; - %jmp/0xz T_25.6, 8; - %ix/load 0, 1, 0; - %assign/v0 v0x24581f0_0, 0, 1; - %load/v 8, v0x24581f0_0, 1; - %inv 8, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x2455c80_0, 0, 8; -T_25.6 ; -T_25.5 ; -T_25.3 ; -T_25.1 ; - %jmp T_25; - .thread T_25; - .scope S_0x2478f70; -T_26 ; - %wait E_0x2419550; - %load/v 8, v0x2458fd0_0, 1; - %mov 9, 8, 1; Repetition 2 - %load/v 10, v0x2472a50_0, 2; - %and 8, 10, 2; - %load/v 10, v0x2458f30_0, 1; - %mov 11, 10, 1; Repetition 2 - %load/v 12, v0x2455c00_0, 2; - %and 10, 12, 2; - %or 8, 10, 2; - %load/v 10, v0x23e45e0_0, 1; - %mov 11, 10, 1; Repetition 2 - %load/v 12, v0x2457070_0, 2; - %and 10, 12, 2; - %or 8, 10, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x2457070_0, 0, 8; - %load/v 8, v0x2456ff0_0, 1; - %jmp/0 T_26.0, 8; - %load/v 9, v0x2472a50_0, 2; - %jmp/1 T_26.2, 8; -T_26.0 ; End of true expr. - %load/v 11, v0x2455c00_0, 2; - %jmp/0 T_26.1, 8; - ; End of false expr. - %blend 9, 11, 2; Condition unknown. - %jmp T_26.2; -T_26.1 ; - %mov 9, 11, 2; Return false value -T_26.2 ; - %ix/load 0, 2, 0; - %assign/v0 v0x2455c00_0, 0, 9; - %jmp T_26; - .thread T_26; - .scope S_0x2478f70; -T_27 ; - %wait E_0x2419550; - %fork t_13, S_0x2473da0; - %jmp t_12; - .scope S_0x2473da0; -t_13 ; - %set/v v0x2474800_0, 0, 1; - %set/v v0x2473730_0, 0, 1; - %load/v 8, v0x2471590_0, 1; - %jmp/0xz T_27.0, 8; - %load/v 8, v0x2455c80_0, 1; - %inv 8, 1; - %load/v 9, v0x2473160_0, 1; - %and 8, 9, 1; - %jmp/0xz T_27.2, 8; - %set/v v0x2474800_0, 1, 1; - %vpi_call 6 142 "$display", "Warning: FIFO2: %m -- Dequeuing from empty fifo"; -T_27.2 ; - %load/v 8, v0x24581f0_0, 1; - %inv 8, 1; - %load/v 9, v0x2471ca0_0, 1; - %and 8, 9, 1; - %load/v 9, v0x2473160_0, 1; - %inv 9, 1; - %or 9, 1, 1; - %and 8, 9, 1; - %jmp/0xz T_27.4, 8; - %set/v v0x2473730_0, 1, 1; - %vpi_call 6 147 "$display", "Warning: FIFO2: %m -- Enqueuing to a full fifo"; -T_27.4 ; -T_27.0 ; - %end; - .scope S_0x2478f70; -t_12 %join; - %jmp T_27; - .thread T_27; - .scope S_0x23f5f60; -T_28 ; - %movi 8, 2730, 12; - %set/v v0x247f0f0_0, 8, 12; - %movi 8, 2730, 12; - %set/v v0x24775b0_0, 8, 12; - %set/v v0x2477650_0, 0, 1; - %set/v v0x2475b80_0, 1, 1; - %end; - .thread T_28; - .scope S_0x23f5f60; -T_29 ; - %wait E_0x2419550; - %load/v 8, v0x23f01d0_0, 1; - %cmpi/u 8, 0, 1; - %jmp/0xz T_29.0, 4; - %ix/load 0, 1, 0; - %assign/v0 v0x2477650_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x2475b80_0, 0, 1; - %jmp T_29.1; -T_29.0 ; - %load/v 8, v0x23f18d0_0, 1; - %jmp/0xz T_29.2, 8; - %ix/load 0, 1, 0; - %assign/v0 v0x2477650_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x2475b80_0, 0, 1; - %jmp T_29.3; -T_29.2 ; - %load/v 8, v0x23f0a80_0, 1; - %load/v 9, v0x23f0eb0_0, 1; - %inv 9, 1; - %and 8, 9, 1; - %jmp/0xz T_29.4, 8; - %ix/load 0, 1, 0; - %assign/v0 v0x2477650_0, 0, 1; - %load/v 8, v0x2477650_0, 1; - %inv 8, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x2475b80_0, 0, 8; - %jmp T_29.5; -T_29.4 ; - %load/v 8, v0x23f0eb0_0, 1; - %load/v 9, v0x23f0a80_0, 1; - %inv 9, 1; - %and 8, 9, 1; - %jmp/0xz T_29.6, 8; - %ix/load 0, 1, 0; - %assign/v0 v0x2475b80_0, 0, 1; - %load/v 8, v0x2475b80_0, 1; - %inv 8, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x2477650_0, 0, 8; -T_29.6 ; -T_29.5 ; -T_29.3 ; -T_29.1 ; - %jmp T_29; - .thread T_29; - .scope S_0x23f5f60; -T_30 ; - %wait E_0x2419550; - %load/v 8, v0x2487e50_0, 1; - %mov 19, 8, 1; Repetition 12 - %mov 18, 8, 1; Repetition 11 - %mov 17, 8, 1; Repetition 10 - %mov 16, 8, 1; Repetition 9 - %mov 15, 8, 1; Repetition 8 - %mov 14, 8, 1; Repetition 7 - %mov 13, 8, 1; Repetition 6 - %mov 12, 8, 1; Repetition 5 - %mov 11, 8, 1; Repetition 4 - %mov 10, 8, 1; Repetition 3 - %mov 9, 8, 1; Repetition 2 - %load/v 20, v0x23f0f50_0, 12; - %and 8, 20, 12; - %load/v 20, v0x24868e0_0, 1; - %mov 31, 20, 1; Repetition 12 - %mov 30, 20, 1; Repetition 11 - %mov 29, 20, 1; Repetition 10 - %mov 28, 20, 1; Repetition 9 - %mov 27, 20, 1; Repetition 8 - %mov 26, 20, 1; Repetition 7 - %mov 25, 20, 1; Repetition 6 - %mov 24, 20, 1; Repetition 5 - %mov 23, 20, 1; Repetition 4 - %mov 22, 20, 1; Repetition 3 - %mov 21, 20, 1; Repetition 2 - %load/v 32, v0x24775b0_0, 12; - %and 20, 32, 12; - %or 8, 20, 12; - %load/v 20, v0x247a930_0, 1; - %mov 31, 20, 1; Repetition 12 - %mov 30, 20, 1; Repetition 11 - %mov 29, 20, 1; Repetition 10 - %mov 28, 20, 1; Repetition 9 - %mov 27, 20, 1; Repetition 8 - %mov 26, 20, 1; Repetition 7 - %mov 25, 20, 1; Repetition 6 - %mov 24, 20, 1; Repetition 5 - %mov 23, 20, 1; Repetition 4 - %mov 22, 20, 1; Repetition 3 - %mov 21, 20, 1; Repetition 2 - %load/v 32, v0x247f0f0_0, 12; - %and 20, 32, 12; - %or 8, 20, 12; - %ix/load 0, 12, 0; - %assign/v0 v0x247f0f0_0, 0, 8; - %load/v 8, v0x247a9d0_0, 1; - %jmp/0 T_30.0, 8; - %load/v 9, v0x23f0f50_0, 12; - %jmp/1 T_30.2, 8; -T_30.0 ; End of true expr. - %load/v 21, v0x24775b0_0, 12; - %jmp/0 T_30.1, 8; - ; End of false expr. - %blend 9, 21, 12; Condition unknown. - %jmp T_30.2; -T_30.1 ; - %mov 9, 21, 12; Return false value -T_30.2 ; - %ix/load 0, 12, 0; - %assign/v0 v0x24775b0_0, 0, 9; - %jmp T_30; - .thread T_30; - .scope S_0x23f5f60; -T_31 ; - %wait E_0x2419550; - %fork t_15, S_0x23f5610; - %jmp t_14; - .scope S_0x23f5610; -t_15 ; - %set/v v0x23f1ed0_0, 0, 1; - %set/v v0x23f1f70_0, 0, 1; - %load/v 8, v0x23f01d0_0, 1; - %jmp/0xz T_31.0, 8; - %load/v 8, v0x2477650_0, 1; - %inv 8, 1; - %load/v 9, v0x23f0eb0_0, 1; - %and 8, 9, 1; - %jmp/0xz T_31.2, 8; - %set/v v0x23f1ed0_0, 1, 1; - %vpi_call 6 142 "$display", "Warning: FIFO2: %m -- Dequeuing from empty fifo"; -T_31.2 ; - %load/v 8, v0x2475b80_0, 1; - %inv 8, 1; - %load/v 9, v0x23f0a80_0, 1; - %and 8, 9, 1; - %load/v 9, v0x23f0eb0_0, 1; - %inv 9, 1; - %or 9, 1, 1; - %and 8, 9, 1; - %jmp/0xz T_31.4, 8; - %set/v v0x23f1f70_0, 1, 1; - %vpi_call 6 147 "$display", "Warning: FIFO2: %m -- Enqueuing to a full fifo"; -T_31.4 ; -T_31.0 ; - %end; - .scope S_0x23f5f60; -t_14 %join; - %jmp T_31; - .thread T_31; - .scope S_0x2407c70; -T_32 ; - %fork t_17, S_0x2406460; - %jmp t_16; - .scope S_0x2406460; -t_17 ; - %vpi_call 7 57 "$readmemh", P_0x2406b10, v0x23fd2a0, P_0x2406b60, P_0x2406b38; - %end; - .scope S_0x2407c70; -t_16 %join; - %end; - .thread T_32; - .scope S_0x2407c70; -T_33 ; - %wait E_0x2419550; - %load/v 8, v0x23daf80_0, 1; - %jmp/0xz T_33.0, 8; - %load/v 8, v0x2403800_0, 16; - %ix/getv 3, v0x2403b00_0; - %jmp/1 t_18, 4; - %ix/load 0, 16, 0; word width - %ix/load 1, 0, 0; part off - %assign/av v0x23fd2a0, 0, 8; -t_18 ; -T_33.0 ; - %jmp T_33; - .thread T_33; - .scope S_0x2407c70; -T_34 ; - %wait E_0x2419550; - %fork t_20, S_0x24067e0; - %jmp t_19; - .scope S_0x24067e0; -t_20 ; - %set/v v0x2409540_0, 0, 1; - %load/v 8, v0x2409540_0, 1; - %jmp/0xz T_34.0, 8; - %load/v 8, v0x2406260_0, 10; - %mov 18, 0, 1; - %cmpi/u 8, 0, 11; - %mov 8, 5, 1; - %movi 9, 1023, 11; - %load/v 20, v0x2406260_0, 10; - %mov 30, 0, 1; - %cmp/u 9, 20, 11; - %or 8, 5, 1; - %jmp/0xz T_34.2, 8; - %vpi_call 7 81 "$display", "Warning: RegFile: %m -- Address port 1 is out of bounds: %h", v0x2406260_0; -T_34.2 ; - %load/v 8, v0x2404f90_0, 10; - %mov 18, 0, 1; - %cmpi/u 8, 0, 11; - %mov 8, 5, 1; - %movi 9, 1023, 11; - %load/v 20, v0x2404f90_0, 10; - %mov 30, 0, 1; - %cmp/u 9, 20, 11; - %or 8, 5, 1; - %jmp/0xz T_34.4, 8; - %vpi_call 7 83 "$display", "Warning: RegFile: %m -- Address port 2 is out of bounds: %h", v0x2404f90_0; -T_34.4 ; - %load/v 8, v0x2405030_0, 10; - %mov 18, 0, 1; - %cmpi/u 8, 0, 11; - %mov 8, 5, 1; - %movi 9, 1023, 11; - %load/v 20, v0x2405030_0, 10; - %mov 30, 0, 1; - %cmp/u 9, 20, 11; - %or 8, 5, 1; - %jmp/0xz T_34.6, 8; - %vpi_call 7 85 "$display", "Warning: RegFile: %m -- Address port 3 is out of bounds: %h", v0x2405030_0; -T_34.6 ; - %load/v 8, v0x2403db0_0, 10; - %mov 18, 0, 1; - %cmpi/u 8, 0, 11; - %mov 8, 5, 1; - %movi 9, 1023, 11; - %load/v 20, v0x2403db0_0, 10; - %mov 30, 0, 1; - %cmp/u 9, 20, 11; - %or 8, 5, 1; - %jmp/0xz T_34.8, 8; - %vpi_call 7 87 "$display", "Warning: RegFile: %m -- Address port 4 is out of bounds: %h", v0x2403db0_0; -T_34.8 ; - %load/v 8, v0x2403e30_0, 10; - %mov 18, 0, 1; - %cmpi/u 8, 0, 11; - %mov 8, 5, 1; - %movi 9, 1023, 11; - %load/v 20, v0x2403e30_0, 10; - %mov 30, 0, 1; - %cmp/u 9, 20, 11; - %or 8, 5, 1; - %jmp/0xz T_34.10, 8; - %vpi_call 7 89 "$display", "Warning: RegFile: %m -- Address port 5 is out of bounds: %h", v0x2403e30_0; -T_34.10 ; - %load/v 8, v0x23daf80_0, 1; - %load/v 9, v0x2403b00_0, 10; - %mov 19, 0, 1; - %cmpi/u 9, 0, 11; - %mov 9, 5, 1; - %and 8, 9, 1; - %movi 9, 1023, 11; - %load/v 20, v0x2403b00_0, 10; - %mov 30, 0, 1; - %cmp/u 9, 20, 11; - %or 8, 5, 1; - %jmp/0xz T_34.12, 8; - %vpi_call 7 91 "$display", "Warning: RegFile: %m -- Write Address port is out of bounds: %h", v0x2403b00_0; -T_34.12 ; -T_34.0 ; - %end; - .scope S_0x2407c70; -t_19 %join; - %jmp T_34; - .thread T_34; - .scope S_0x240f820; -T_35 ; - %fork t_22, S_0x240d5e0; - %jmp t_21; - .scope S_0x240d5e0; -t_22 ; - %vpi_call 7 57 "$readmemh", P_0x240e390, v0x2408f40, P_0x240e3e0, P_0x240e3b8; - %end; - .scope S_0x240f820; -t_21 %join; - %end; - .thread T_35; - .scope S_0x240f820; -T_36 ; - %wait E_0x2419550; - %load/v 8, v0x240a9f0_0, 1; - %jmp/0xz T_36.0, 8; - %load/v 8, v0x240be70_0, 32; - %ix/getv 3, v0x240c170_0; - %jmp/1 t_23, 4; - %ix/load 0, 32, 0; word width - %ix/load 1, 0, 0; part off - %assign/av v0x2408f40, 0, 8; -t_23 ; -T_36.0 ; - %jmp T_36; - .thread T_36; - .scope S_0x240f820; -T_37 ; - %wait E_0x2419550; - %fork t_25, S_0x240dd90; - %jmp t_24; - .scope S_0x240dd90; -t_25 ; - %set/v v0x240d7e0_0, 0, 1; - %load/v 8, v0x240d7e0_0, 1; - %jmp/0xz T_37.0, 8; - %load/v 8, v0x240cf80_0, 10; - %mov 18, 0, 1; - %cmpi/u 8, 0, 11; - %mov 8, 5, 1; - %movi 9, 1023, 11; - %load/v 20, v0x240cf80_0, 10; - %mov 30, 0, 1; - %cmp/u 9, 20, 11; - %or 8, 5, 1; - %jmp/0xz T_37.2, 8; - %vpi_call 7 81 "$display", "Warning: RegFile: %m -- Address port 1 is out of bounds: %h", v0x240cf80_0; -T_37.2 ; - %load/v 8, v0x240cd80_0, 10; - %mov 18, 0, 1; - %cmpi/u 8, 0, 11; - %mov 8, 5, 1; - %movi 9, 1023, 11; - %load/v 20, v0x240cd80_0, 10; - %mov 30, 0, 1; - %cmp/u 9, 20, 11; - %or 8, 5, 1; - %jmp/0xz T_37.4, 8; - %vpi_call 7 83 "$display", "Warning: RegFile: %m -- Address port 2 is out of bounds: %h", v0x240cd80_0; -T_37.4 ; - %load/v 8, v0x240ce20_0, 10; - %mov 18, 0, 1; - %cmpi/u 8, 0, 11; - %mov 8, 5, 1; - %movi 9, 1023, 11; - %load/v 20, v0x240ce20_0, 10; - %mov 30, 0, 1; - %cmp/u 9, 20, 11; - %or 8, 5, 1; - %jmp/0xz T_37.6, 8; - %vpi_call 7 85 "$display", "Warning: RegFile: %m -- Address port 3 is out of bounds: %h", v0x240ce20_0; -T_37.6 ; - %load/v 8, v0x240c420_0, 10; - %mov 18, 0, 1; - %cmpi/u 8, 0, 11; - %mov 8, 5, 1; - %movi 9, 1023, 11; - %load/v 20, v0x240c420_0, 10; - %mov 30, 0, 1; - %cmp/u 9, 20, 11; - %or 8, 5, 1; - %jmp/0xz T_37.8, 8; - %vpi_call 7 87 "$display", "Warning: RegFile: %m -- Address port 4 is out of bounds: %h", v0x240c420_0; -T_37.8 ; - %load/v 8, v0x240c4a0_0, 10; - %mov 18, 0, 1; - %cmpi/u 8, 0, 11; - %mov 8, 5, 1; - %movi 9, 1023, 11; - %load/v 20, v0x240c4a0_0, 10; - %mov 30, 0, 1; - %cmp/u 9, 20, 11; - %or 8, 5, 1; - %jmp/0xz T_37.10, 8; - %vpi_call 7 89 "$display", "Warning: RegFile: %m -- Address port 5 is out of bounds: %h", v0x240c4a0_0; -T_37.10 ; - %load/v 8, v0x240a9f0_0, 1; - %load/v 9, v0x240c170_0, 10; - %mov 19, 0, 1; - %cmpi/u 9, 0, 11; - %mov 9, 5, 1; - %and 8, 9, 1; - %movi 9, 1023, 11; - %load/v 20, v0x240c170_0, 10; - %mov 30, 0, 1; - %cmp/u 9, 20, 11; - %or 8, 5, 1; - %jmp/0xz T_37.12, 8; - %vpi_call 7 91 "$display", "Warning: RegFile: %m -- Write Address port is out of bounds: %h", v0x240c170_0; -T_37.12 ; -T_37.0 ; - %end; - .scope S_0x240f820; -t_24 %join; - %jmp T_37; - .thread T_37; - .scope S_0x241aca0; -T_38 ; - %fork t_27, S_0x2415850; - %jmp t_26; - .scope S_0x2415850; -t_27 ; - %vpi_call 7 57 "$readmemh", P_0x241a970, v0x240fb60, P_0x241a9c0, P_0x241a998; - %end; - .scope S_0x241aca0; -t_26 %join; - %end; - .thread T_38; - .scope S_0x241aca0; -T_39 ; - %wait E_0x2419550; - %load/v 8, v0x24126d0_0, 1; - %jmp/0xz T_39.0, 8; - %load/v 8, v0x2422000_0, 32; - %ix/getv 3, v0x24144a0_0; - %jmp/1 t_28, 4; - %ix/load 0, 32, 0; word width - %ix/load 1, 0, 0; part off - %assign/av v0x240fb60, 0, 8; -t_28 ; -T_39.0 ; - %jmp T_39; - .thread T_39; - .scope S_0x241aca0; -T_40 ; - %wait E_0x2419550; - %fork t_30, S_0x24191b0; - %jmp t_29; - .scope S_0x24191b0; -t_30 ; - %set/v v0x2418e00_0, 0, 1; - %load/v 8, v0x2418e00_0, 1; - %jmp/0xz T_40.0, 8; - %load/v 8, v0x24155a0_0, 10; - %mov 18, 0, 1; - %cmpi/u 8, 0, 11; - %mov 8, 5, 1; - %movi 9, 1023, 11; - %load/v 20, v0x24155a0_0, 10; - %mov 30, 0, 1; - %cmp/u 9, 20, 11; - %or 8, 5, 1; - %jmp/0xz T_40.2, 8; - %vpi_call 7 81 "$display", "Warning: RegFile: %m -- Address port 1 is out of bounds: %h", v0x24155a0_0; -T_40.2 ; - %load/v 8, v0x2415180_0, 10; - %mov 18, 0, 1; - %cmpi/u 8, 0, 11; - %mov 8, 5, 1; - %movi 9, 1023, 11; - %load/v 20, v0x2415180_0, 10; - %mov 30, 0, 1; - %cmp/u 9, 20, 11; - %or 8, 5, 1; - %jmp/0xz T_40.4, 8; - %vpi_call 7 83 "$display", "Warning: RegFile: %m -- Address port 2 is out of bounds: %h", v0x2415180_0; -T_40.4 ; - %load/v 8, v0x2415220_0, 10; - %mov 18, 0, 1; - %cmpi/u 8, 0, 11; - %mov 8, 5, 1; - %movi 9, 1023, 11; - %load/v 20, v0x2415220_0, 10; - %mov 30, 0, 1; - %cmp/u 9, 20, 11; - %or 8, 5, 1; - %jmp/0xz T_40.6, 8; - %vpi_call 7 85 "$display", "Warning: RegFile: %m -- Address port 3 is out of bounds: %h", v0x2415220_0; -T_40.6 ; - %load/v 8, v0x24149f0_0, 10; - %mov 18, 0, 1; - %cmpi/u 8, 0, 11; - %mov 8, 5, 1; - %movi 9, 1023, 11; - %load/v 20, v0x24149f0_0, 10; - %mov 30, 0, 1; - %cmp/u 9, 20, 11; - %or 8, 5, 1; - %jmp/0xz T_40.8, 8; - %vpi_call 7 87 "$display", "Warning: RegFile: %m -- Address port 4 is out of bounds: %h", v0x24149f0_0; -T_40.8 ; - %load/v 8, v0x2414400_0, 10; - %mov 18, 0, 1; - %cmpi/u 8, 0, 11; - %mov 8, 5, 1; - %movi 9, 1023, 11; - %load/v 20, v0x2414400_0, 10; - %mov 30, 0, 1; - %cmp/u 9, 20, 11; - %or 8, 5, 1; - %jmp/0xz T_40.10, 8; - %vpi_call 7 89 "$display", "Warning: RegFile: %m -- Address port 5 is out of bounds: %h", v0x2414400_0; -T_40.10 ; - %load/v 8, v0x24126d0_0, 1; - %load/v 9, v0x24144a0_0, 10; - %mov 19, 0, 1; - %cmpi/u 9, 0, 11; - %mov 9, 5, 1; - %and 8, 9, 1; - %movi 9, 1023, 11; - %load/v 20, v0x24144a0_0, 10; - %mov 30, 0, 1; - %cmp/u 9, 20, 11; - %or 8, 5, 1; - %jmp/0xz T_40.12, 8; - %vpi_call 7 91 "$display", "Warning: RegFile: %m -- Write Address port is out of bounds: %h", v0x24144a0_0; -T_40.12 ; -T_40.0 ; - %end; - .scope S_0x241aca0; -t_29 %join; - %jmp T_40; - .thread T_40; - .scope S_0x23c0270; -T_41 ; - %wait E_0x23a0c80; - %load/v 8, v0x24d49e0_0, 2; - %cmpi/u 8, 0, 2; - %jmp/1 T_41.0, 6; - %cmpi/u 8, 1, 2; - %jmp/1 T_41.1, 6; - %cmpi/u 8, 2, 2; - %jmp/1 T_41.2, 6; - %cmpi/u 8, 3, 2; - %jmp/1 T_41.3, 6; - %jmp T_41.4; -T_41.0 ; - %load/v 8, v0x24c9540_0, 1; - %set/v v0x24af110_0, 8, 1; - %jmp T_41.4; -T_41.1 ; - %load/v 8, v0x24c9f80_0, 1; - %set/v v0x24af110_0, 8, 1; - %jmp T_41.4; -T_41.2 ; - %load/v 8, v0x24caa10_0, 1; - %set/v v0x24af110_0, 8, 1; - %jmp T_41.4; -T_41.3 ; - %load/v 8, v0x24cb430_0, 1; - %set/v v0x24af110_0, 8, 1; - %jmp T_41.4; -T_41.4 ; - %jmp T_41; - .thread T_41, $push; - .scope S_0x23c0270; -T_42 ; - %wait E_0x23afc50; - %load/v 8, v0x24d4ae0_0, 2; - %cmpi/u 8, 0, 2; - %jmp/1 T_42.0, 6; - %cmpi/u 8, 1, 2; - %jmp/1 T_42.1, 6; - %cmpi/u 8, 2, 2; - %jmp/1 T_42.2, 6; - %cmpi/u 8, 3, 2; - %jmp/1 T_42.3, 6; - %jmp T_42.4; -T_42.0 ; - %load/v 8, v0x24c9d40_0, 2; - %ix/load 1, 13, 0; - %mov 4, 0, 1; - %jmp/1 T_42.5, 4; - %load/x1p 10, v0x24cc520_0, 2; - %jmp T_42.6; -T_42.5 ; - %mov 10, 2, 2; -T_42.6 ; -; Save base=10 wid=2 in lookaside. - %cmp/u 8, 10, 2; - %mov 8, 4, 1; - %set/v v0x24aee90_0, 8, 1; - %jmp T_42.4; -T_42.1 ; - %load/v 8, v0x24cc070_0, 2; - %ix/load 1, 13, 0; - %mov 4, 0, 1; - %jmp/1 T_42.7, 4; - %load/x1p 10, v0x24cc520_0, 2; - %jmp T_42.8; -T_42.7 ; - %mov 10, 2, 2; -T_42.8 ; -; Save base=10 wid=2 in lookaside. - %cmp/u 8, 10, 2; - %mov 8, 4, 1; - %set/v v0x24aee90_0, 8, 1; - %jmp T_42.4; -T_42.2 ; - %load/v 8, v0x24cb1b0_0, 2; - %ix/load 1, 13, 0; - %mov 4, 0, 1; - %jmp/1 T_42.9, 4; - %load/x1p 10, v0x24cc520_0, 2; - %jmp T_42.10; -T_42.9 ; - %mov 10, 2, 2; -T_42.10 ; -; Save base=10 wid=2 in lookaside. - %cmp/u 8, 10, 2; - %mov 8, 4, 1; - %set/v v0x24aee90_0, 8, 1; - %jmp T_42.4; -T_42.3 ; - %load/v 8, v0x24cbc00_0, 2; - %ix/load 1, 13, 0; - %mov 4, 0, 1; - %jmp/1 T_42.11, 4; - %load/x1p 10, v0x24cc520_0, 2; - %jmp T_42.12; -T_42.11 ; - %mov 10, 2, 2; -T_42.12 ; -; Save base=10 wid=2 in lookaside. - %cmp/u 8, 10, 2; - %mov 8, 4, 1; - %set/v v0x24aee90_0, 8, 1; - %jmp T_42.4; -T_42.4 ; - %jmp T_42; - .thread T_42, $push; - .scope S_0x23c0270; -T_43 ; - %wait E_0x23a8450; - %load/v 8, v0x24d49e0_0, 2; - %cmpi/u 8, 0, 2; - %jmp/1 T_43.0, 6; - %cmpi/u 8, 1, 2; - %jmp/1 T_43.1, 6; - %cmpi/u 8, 2, 2; - %jmp/1 T_43.2, 6; - %cmpi/u 8, 3, 2; - %jmp/1 T_43.3, 6; - %jmp T_43.4; -T_43.0 ; - %load/v 8, v0x24ad430_0, 2; - %set/v v0x23b1d10_0, 8, 2; - %jmp T_43.4; -T_43.1 ; - %load/v 8, v0x24ad770_0, 2; - %set/v v0x23b1d10_0, 8, 2; - %jmp T_43.4; -T_43.2 ; - %load/v 8, v0x24ad810_0, 2; - %set/v v0x23b1d10_0, 8, 2; - %jmp T_43.4; -T_43.3 ; - %load/v 8, v0x24adbc0_0, 2; - %set/v v0x23b1d10_0, 8, 2; - %jmp T_43.4; -T_43.4 ; - %jmp T_43; - .thread T_43, $push; - .scope S_0x23c0270; -T_44 ; - %wait E_0x2398f30; - %load/v 8, v0x24d4a60_0, 2; - %cmpi/u 8, 0, 2; - %jmp/1 T_44.0, 6; - %cmpi/u 8, 1, 2; - %jmp/1 T_44.1, 6; - %cmpi/u 8, 2, 2; - %jmp/1 T_44.2, 6; - %cmpi/u 8, 3, 2; - %jmp/1 T_44.3, 6; - %jmp T_44.4; -T_44.0 ; - %load/v 8, v0x24ad430_0, 2; - %set/v v0x24aed20_0, 8, 2; - %jmp T_44.4; -T_44.1 ; - %load/v 8, v0x24ad770_0, 2; - %set/v v0x24aed20_0, 8, 2; - %jmp T_44.4; -T_44.2 ; - %load/v 8, v0x24ad810_0, 2; - %set/v v0x24aed20_0, 8, 2; - %jmp T_44.4; -T_44.3 ; - %load/v 8, v0x24adbc0_0, 2; - %set/v v0x24aed20_0, 8, 2; - %jmp T_44.4; -T_44.4 ; - %jmp T_44; - .thread T_44, $push; - .scope S_0x23c0270; -T_45 ; - %wait E_0x2391990; - %load/v 8, v0x24d48e0_0, 2; - %cmpi/u 8, 0, 2; - %jmp/1 T_45.0, 6; - %cmpi/u 8, 1, 2; - %jmp/1 T_45.1, 6; - %cmpi/u 8, 2, 2; - %jmp/1 T_45.2, 6; - %cmpi/u 8, 3, 2; - %jmp/1 T_45.3, 6; - %jmp T_45.4; -T_45.0 ; - %load/v 8, v0x24c6940_0, 1; - %set/v v0x24af070_0, 8, 1; - %jmp T_45.4; -T_45.1 ; - %load/v 8, v0x24c71a0_0, 1; - %set/v v0x24af070_0, 8, 1; - %jmp T_45.4; -T_45.2 ; - %load/v 8, v0x24c9060_0, 1; - %set/v v0x24af070_0, 8, 1; - %jmp T_45.4; -T_45.3 ; - %load/v 8, v0x24c8200_0, 1; - %set/v v0x24af070_0, 8, 1; - %jmp T_45.4; -T_45.4 ; - %jmp T_45; - .thread T_45, $push; - .scope S_0x23c0270; -T_46 ; - %wait E_0x238a5c0; - %load/v 8, v0x24d4960_0, 2; - %cmpi/u 8, 0, 2; - %jmp/1 T_46.0, 6; - %cmpi/u 8, 1, 2; - %jmp/1 T_46.1, 6; - %cmpi/u 8, 2, 2; - %jmp/1 T_46.2, 6; - %cmpi/u 8, 3, 2; - %jmp/1 T_46.3, 6; - %jmp T_46.4; -T_46.0 ; - %load/v 8, v0x24d28e0_0, 1; - %set/v v0x24aef30_0, 8, 1; - %jmp T_46.4; -T_46.1 ; - %load/v 8, v0x24d30d0_0, 1; - %set/v v0x24aef30_0, 8, 1; - %jmp T_46.4; -T_46.2 ; - %load/v 8, v0x24d3900_0, 1; - %set/v v0x24aef30_0, 8, 1; - %jmp T_46.4; -T_46.3 ; - %load/v 8, v0x24d40f0_0, 1; - %set/v v0x24aef30_0, 8, 1; - %jmp T_46.4; -T_46.4 ; - %jmp T_46; - .thread T_46, $push; - .scope S_0x23c0270; -T_47 ; - %wait E_0x2419550; - %load/v 8, v0x24aedf0_0, 1; - %cmpi/u 8, 0, 1; - %jmp/0xz T_47.0, 4; - %movi 8, 682, 11; - %ix/load 0, 11, 0; - %assign/v0 v0x24c5e70_0, 0, 8; - %movi 8, 682, 11; - %ix/load 0, 11, 0; - %assign/v0 v0x24c60f0_0, 0, 8; - %movi 8, 682, 11; - %ix/load 0, 11, 0; - %assign/v0 v0x24c7990_0, 0, 8; - %movi 8, 682, 11; - %ix/load 0, 11, 0; - %assign/v0 v0x24c6760_0, 0, 8; - %ix/load 0, 1, 0; - %assign/v0 v0x24c6940_0, 0, 1; - %ix/load 0, 2, 0; - %assign/v0 v0x24c6e60_0, 0, 0; - %ix/load 0, 2, 0; - %assign/v0 v0x24c6fe0_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x24c71a0_0, 0, 1; - %ix/load 0, 2, 0; - %assign/v0 v0x24c76f0_0, 0, 0; - %ix/load 0, 2, 0; - %assign/v0 v0x24c7870_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x24c9060_0, 0, 1; - %ix/load 0, 2, 0; - %assign/v0 v0x24c7ee0_0, 0, 0; - %ix/load 0, 2, 0; - %assign/v0 v0x24c8060_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x24c8200_0, 0, 1; - %ix/load 0, 2, 0; - %assign/v0 v0x24c8750_0, 0, 0; - %ix/load 0, 2, 0; - %assign/v0 v0x24c88d0_0, 0, 0; - %movi 8, 682, 11; - %ix/load 0, 11, 0; - %assign/v0 v0x24c8a70_0, 0, 8; - %movi 8, 682, 11; - %ix/load 0, 11, 0; - %assign/v0 v0x24c8c50_0, 0, 8; - %movi 8, 682, 11; - %ix/load 0, 11, 0; - %assign/v0 v0x24c8e30_0, 0, 8; - %movi 8, 682, 11; - %ix/load 0, 11, 0; - %assign/v0 v0x24c9220_0, 0, 8; - %ix/load 0, 1, 0; - %assign/v0 v0x24c9540_0, 0, 1; - %ix/load 0, 2, 0; - %assign/v0 v0x24c9bc0_0, 0, 0; - %ix/load 0, 2, 0; - %assign/v0 v0x24c9d40_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x24c9f80_0, 0, 1; - %ix/load 0, 2, 0; - %assign/v0 v0x24ca600_0, 0, 0; - %ix/load 0, 2, 0; - %assign/v0 v0x24cc070_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x24caa10_0, 0, 1; - %ix/load 0, 2, 0; - %assign/v0 v0x24cb030_0, 0, 0; - %ix/load 0, 2, 0; - %assign/v0 v0x24cb1b0_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x24cb430_0, 0, 1; - %ix/load 0, 2, 0; - %assign/v0 v0x24cba80_0, 0, 0; - %ix/load 0, 2, 0; - %assign/v0 v0x24cbc00_0, 0, 0; - %ix/load 0, 3, 0; - %assign/v0 v0x24cda60_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x24cc190_0, 0, 1; - %movi 8, 2730, 14; - %ix/load 0, 14, 0; - %assign/v0 v0x24cd090_0, 0, 8; - %ix/load 0, 1, 0; - %assign/v0 v0x24cd490_0, 0, 1; - %ix/load 0, 3, 0; - %assign/v0 v0x24cf630_0, 0, 0; - %ix/load 0, 2, 0; - %assign/v0 v0x24cdbe0_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x24cdd60_0, 0, 1; - %ix/load 0, 2, 0; - %assign/v0 v0x24cdf20_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x24ce100_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x24ce380_0, 0, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x24cfe80_0, 0, 1; - %ix/load 0, 2, 0; - %assign/v0 v0x24d0420_0, 0, 0; - %ix/load 0, 2, 0; - %assign/v0 v0x24d09c0_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x24d0b40_0, 0, 0; - %ix/load 0, 2, 0; - %assign/v0 v0x24d0cc0_0, 0, 0; - %movi 8, 682, 11; - %ix/load 0, 11, 0; - %assign/v0 v0x24d20e0_0, 0, 8; - %movi 8, 682, 11; - %ix/load 0, 11, 0; - %assign/v0 v0x24d22e0_0, 0, 8; - %movi 8, 682, 11; - %ix/load 0, 11, 0; - %assign/v0 v0x24d24e0_0, 0, 8; - %movi 8, 682, 11; - %ix/load 0, 11, 0; - %assign/v0 v0x24d2760_0, 0, 8; - %ix/load 0, 1, 0; - %assign/v0 v0x24d28e0_0, 0, 1; - %ix/load 0, 2, 0; - %assign/v0 v0x24d2dd0_0, 0, 0; - %ix/load 0, 2, 0; - %assign/v0 v0x24d2f50_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x24d30d0_0, 0, 1; - %ix/load 0, 2, 0; - %assign/v0 v0x24d3600_0, 0, 0; - %ix/load 0, 2, 0; - %assign/v0 v0x24d3780_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x24d3900_0, 0, 1; - %ix/load 0, 2, 0; - %assign/v0 v0x24d3df0_0, 0, 0; - %ix/load 0, 2, 0; - %assign/v0 v0x24d3f70_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x24d40f0_0, 0, 1; - %ix/load 0, 2, 0; - %assign/v0 v0x24d45e0_0, 0, 0; - %ix/load 0, 2, 0; - %assign/v0 v0x24d4760_0, 0, 0; - %jmp T_47.1; -T_47.0 ; - %load/v 8, v0x24c5fb0_0, 1; - %jmp/0xz T_47.2, 8; - %load/v 8, v0x24c5f10_0, 11; - %ix/load 0, 11, 0; - %assign/v0 v0x24c5e70_0, 0, 8; -T_47.2 ; - %load/v 8, v0x24c6230_0, 1; - %jmp/0xz T_47.4, 8; - %load/v 8, v0x24c6190_0, 11; - %ix/load 0, 11, 0; - %assign/v0 v0x24c60f0_0, 0, 8; -T_47.4 ; - %load/v 8, v0x24c6580_0, 1; - %jmp/0xz T_47.6, 8; - %load/v 8, v0x24c64e0_0, 11; - %ix/load 0, 11, 0; - %assign/v0 v0x24c7990_0, 0, 8; -T_47.6 ; - %load/v 8, v0x24c68a0_0, 1; - %jmp/0xz T_47.8, 8; - %load/v 8, v0x24c6800_0, 11; - %ix/load 0, 11, 0; - %assign/v0 v0x24c6760_0, 0, 8; -T_47.8 ; - %load/v 8, v0x24c6a80_0, 1; - %jmp/0xz T_47.10, 8; - %load/v 8, v0x24c69e0_0, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x24c6940_0, 0, 8; -T_47.10 ; - %load/v 8, v0x24c6f60_0, 1; - %jmp/0xz T_47.12, 8; - %load/v 8, v0x24c6ee0_0, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x24c6e60_0, 0, 8; -T_47.12 ; - %load/v 8, v0x24c7100_0, 1; - %jmp/0xz T_47.14, 8; - %load/v 8, v0x24c7060_0, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x24c6fe0_0, 0, 8; -T_47.14 ; - %load/v 8, v0x24c72e0_0, 1; - %jmp/0xz T_47.16, 8; - %load/v 8, v0x24c7240_0, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x24c71a0_0, 0, 8; -T_47.16 ; - %load/v 8, v0x24c77f0_0, 1; - %jmp/0xz T_47.18, 8; - %load/v 8, v0x24c7770_0, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x24c76f0_0, 0, 8; -T_47.18 ; - %load/v 8, v0x24c8fe0_0, 1; - %jmp/0xz T_47.20, 8; - %load/v 8, v0x24c78f0_0, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x24c7870_0, 0, 8; -T_47.20 ; - %load/v 8, v0x24c7ad0_0, 1; - %jmp/0xz T_47.22, 8; - %load/v 8, v0x24c7a30_0, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x24c9060_0, 0, 8; -T_47.22 ; - %load/v 8, v0x24c7fe0_0, 1; - %jmp/0xz T_47.24, 8; - %load/v 8, v0x24c7f60_0, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x24c7ee0_0, 0, 8; -T_47.24 ; - %load/v 8, v0x24c8160_0, 1; - %jmp/0xz T_47.26, 8; - %load/v 8, v0x24c80e0_0, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x24c8060_0, 0, 8; -T_47.26 ; - %load/v 8, v0x24c8340_0, 1; - %jmp/0xz T_47.28, 8; - %load/v 8, v0x24c82a0_0, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x24c8200_0, 0, 8; -T_47.28 ; - %load/v 8, v0x24c8850_0, 1; - %jmp/0xz T_47.30, 8; - %load/v 8, v0x24c87d0_0, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x24c8750_0, 0, 8; -T_47.30 ; - %load/v 8, v0x24c89d0_0, 1; - %jmp/0xz T_47.32, 8; - %load/v 8, v0x24c8950_0, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x24c88d0_0, 0, 8; -T_47.32 ; - %load/v 8, v0x24c8bb0_0, 1; - %jmp/0xz T_47.34, 8; - %load/v 8, v0x24c8b10_0, 11; - %ix/load 0, 11, 0; - %assign/v0 v0x24c8a70_0, 0, 8; -T_47.34 ; - %load/v 8, v0x24c8d90_0, 1; - %jmp/0xz T_47.36, 8; - %load/v 8, v0x24c8cf0_0, 11; - %ix/load 0, 11, 0; - %assign/v0 v0x24c8c50_0, 0, 8; -T_47.36 ; - %load/v 8, v0x24ca7d0_0, 1; - %jmp/0xz T_47.38, 8; - %load/v 8, v0x24c8ed0_0, 11; - %ix/load 0, 11, 0; - %assign/v0 v0x24c8e30_0, 0, 8; -T_47.38 ; - %load/v 8, v0x24c9360_0, 1; - %jmp/0xz T_47.40, 8; - %load/v 8, v0x24c92c0_0, 11; - %ix/load 0, 11, 0; - %assign/v0 v0x24c9220_0, 0, 8; -T_47.40 ; - %load/v 8, v0x24c9680_0, 1; - %jmp/0xz T_47.42, 8; - %load/v 8, v0x24c95e0_0, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x24c9540_0, 0, 8; -T_47.42 ; - %load/v 8, v0x24c9cc0_0, 1; - %jmp/0xz T_47.44, 8; - %load/v 8, v0x24c9c40_0, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x24c9bc0_0, 0, 8; -T_47.44 ; - %load/v 8, v0x24c9e40_0, 1; - %jmp/0xz T_47.46, 8; - %load/v 8, v0x24c9dc0_0, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x24c9d40_0, 0, 8; -T_47.46 ; - %load/v 8, v0x24ca0c0_0, 1; - %jmp/0xz T_47.48, 8; - %load/v 8, v0x24ca020_0, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x24c9f80_0, 0, 8; -T_47.48 ; - %load/v 8, v0x24ca700_0, 1; - %jmp/0xz T_47.50, 8; - %load/v 8, v0x24ca680_0, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x24ca600_0, 0, 8; -T_47.50 ; - %load/v 8, v0x24ca8d0_0, 1; - %jmp/0xz T_47.52, 8; - %load/v 8, v0x24ca850_0, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x24cc070_0, 0, 8; -T_47.52 ; - %load/v 8, v0x24cab50_0, 1; - %jmp/0xz T_47.54, 8; - %load/v 8, v0x24caab0_0, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x24caa10_0, 0, 8; -T_47.54 ; - %load/v 8, v0x24cb130_0, 1; - %jmp/0xz T_47.56, 8; - %load/v 8, v0x24cb0b0_0, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x24cb030_0, 0, 8; -T_47.56 ; - %load/v 8, v0x24cb2f0_0, 1; - %jmp/0xz T_47.58, 8; - %load/v 8, v0x24cb250_0, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x24cb1b0_0, 0, 8; -T_47.58 ; - %load/v 8, v0x24cb570_0, 1; - %jmp/0xz T_47.60, 8; - %load/v 8, v0x24cb4d0_0, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x24cb430_0, 0, 8; -T_47.60 ; - %load/v 8, v0x24cbb80_0, 1; - %jmp/0xz T_47.62, 8; - %load/v 8, v0x24cbb00_0, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x24cba80_0, 0, 8; -T_47.62 ; - %load/v 8, v0x24cbd20_0, 1; - %jmp/0xz T_47.64, 8; - %load/v 8, v0x24cbc80_0, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x24cbc00_0, 0, 8; -T_47.64 ; - %load/v 8, v0x24cc0f0_0, 1; - %jmp/0xz T_47.66, 8; - %load/v 8, v0x24cdae0_0, 3; - %ix/load 0, 3, 0; - %assign/v0 v0x24cda60_0, 0, 8; -T_47.66 ; - %load/v 8, v0x24cc2d0_0, 1; - %jmp/0xz T_47.68, 8; - %load/v 8, v0x24cc230_0, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x24cc190_0, 0, 8; -T_47.68 ; - %load/v 8, v0x24cd190_0, 1; - %jmp/0xz T_47.70, 8; - %load/v 8, v0x24cd110_0, 14; - %ix/load 0, 14, 0; - %assign/v0 v0x24cd090_0, 0, 8; -T_47.70 ; - %load/v 8, v0x24cd590_0, 1; - %jmp/0xz T_47.72, 8; - %load/v 8, v0x24cd510_0, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x24cd490_0, 0, 8; -T_47.72 ; - %load/v 8, v0x24cdb60_0, 1; - %jmp/0xz T_47.74, 8; - %load/v 8, v0x24cf6b0_0, 3; - %ix/load 0, 3, 0; - %assign/v0 v0x24cf630_0, 0, 8; -T_47.74 ; - %load/v 8, v0x24cdce0_0, 1; - %jmp/0xz T_47.76, 8; - %load/v 8, v0x24cdc60_0, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x24cdbe0_0, 0, 8; -T_47.76 ; - %load/v 8, v0x24cde80_0, 1; - %jmp/0xz T_47.78, 8; - %load/v 8, v0x24cdde0_0, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x24cdd60_0, 0, 8; -T_47.78 ; - %load/v 8, v0x24ce060_0, 1; - %jmp/0xz T_47.80, 8; - %load/v 8, v0x24cdfc0_0, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x24cdf20_0, 0, 8; -T_47.80 ; - %load/v 8, v0x24ce240_0, 1; - %jmp/0xz T_47.82, 8; - %load/v 8, v0x24ce1a0_0, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x24ce100_0, 0, 8; -T_47.82 ; - %load/v 8, v0x24ce4c0_0, 1; - %jmp/0xz T_47.84, 8; - %load/v 8, v0x24ce420_0, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x24ce380_0, 0, 8; -T_47.84 ; - %load/v 8, v0x24cff80_0, 1; - %jmp/0xz T_47.86, 8; - %load/v 8, v0x24cff00_0, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x24cfe80_0, 0, 8; -T_47.86 ; - %load/v 8, v0x24d0520_0, 1; - %jmp/0xz T_47.88, 8; - %load/v 8, v0x24d04a0_0, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x24d0420_0, 0, 8; -T_47.88 ; - %load/v 8, v0x24d0ac0_0, 1; - %jmp/0xz T_47.90, 8; - %load/v 8, v0x24d0a40_0, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x24d09c0_0, 0, 8; -T_47.90 ; - %load/v 8, v0x24d0c40_0, 1; - %jmp/0xz T_47.92, 8; - %load/v 8, v0x24d0bc0_0, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x24d0b40_0, 0, 8; -T_47.92 ; - %load/v 8, v0x24d0dc0_0, 1; - %jmp/0xz T_47.94, 8; - %load/v 8, v0x24d0d40_0, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x24d0cc0_0, 0, 8; -T_47.94 ; - %load/v 8, v0x24d21e0_0, 1; - %jmp/0xz T_47.96, 8; - %load/v 8, v0x24d2160_0, 11; - %ix/load 0, 11, 0; - %assign/v0 v0x24d20e0_0, 0, 8; -T_47.96 ; - %load/v 8, v0x24d23e0_0, 1; - %jmp/0xz T_47.98, 8; - %load/v 8, v0x24d2360_0, 11; - %ix/load 0, 11, 0; - %assign/v0 v0x24d22e0_0, 0, 8; -T_47.98 ; - %load/v 8, v0x24d25e0_0, 1; - %jmp/0xz T_47.100, 8; - %load/v 8, v0x24d2560_0, 11; - %ix/load 0, 11, 0; - %assign/v0 v0x24d24e0_0, 0, 8; -T_47.100 ; - %load/v 8, v0x24d2860_0, 1; - %jmp/0xz T_47.102, 8; - %load/v 8, v0x24d27e0_0, 11; - %ix/load 0, 11, 0; - %assign/v0 v0x24d2760_0, 0, 8; -T_47.102 ; - %load/v 8, v0x24d29e0_0, 1; - %jmp/0xz T_47.104, 8; - %load/v 8, v0x24d2960_0, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x24d28e0_0, 0, 8; -T_47.104 ; - %load/v 8, v0x24d2ed0_0, 1; - %jmp/0xz T_47.106, 8; - %load/v 8, v0x24d2e50_0, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x24d2dd0_0, 0, 8; -T_47.106 ; - %load/v 8, v0x24d3050_0, 1; - %jmp/0xz T_47.108, 8; - %load/v 8, v0x24d2fd0_0, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x24d2f50_0, 0, 8; -T_47.108 ; - %load/v 8, v0x24d51e0_0, 1; - %jmp/0xz T_47.110, 8; - %load/v 8, v0x24d3150_0, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x24d30d0_0, 0, 8; -T_47.110 ; - %load/v 8, v0x24d3700_0, 1; - %jmp/0xz T_47.112, 8; - %load/v 8, v0x24d3680_0, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x24d3600_0, 0, 8; -T_47.112 ; - %load/v 8, v0x24d3880_0, 1; - %jmp/0xz T_47.114, 8; - %load/v 8, v0x24d3800_0, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x24d3780_0, 0, 8; -T_47.114 ; - %load/v 8, v0x24d3a00_0, 1; - %jmp/0xz T_47.116, 8; - %load/v 8, v0x24d3980_0, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x24d3900_0, 0, 8; -T_47.116 ; - %load/v 8, v0x24d3ef0_0, 1; - %jmp/0xz T_47.118, 8; - %load/v 8, v0x24d3e70_0, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x24d3df0_0, 0, 8; -T_47.118 ; - %load/v 8, v0x24d4070_0, 1; - %jmp/0xz T_47.120, 8; - %load/v 8, v0x24d3ff0_0, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x24d3f70_0, 0, 8; -T_47.120 ; - %load/v 8, v0x24d41f0_0, 1; - %jmp/0xz T_47.122, 8; - %load/v 8, v0x24d4170_0, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x24d40f0_0, 0, 8; -T_47.122 ; - %load/v 8, v0x24d46e0_0, 1; - %jmp/0xz T_47.124, 8; - %load/v 8, v0x24d4660_0, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x24d45e0_0, 0, 8; -T_47.124 ; - %load/v 8, v0x24d4860_0, 1; - %jmp/0xz T_47.126, 8; - %load/v 8, v0x24d47e0_0, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x24d4760_0, 0, 8; -T_47.126 ; -T_47.1 ; - %jmp T_47; - .thread T_47; - .scope S_0x23c0270; -T_48 ; - %movi 8, 682, 11; - %set/v v0x24c5e70_0, 8, 11; - %movi 8, 682, 11; - %set/v v0x24c60f0_0, 8, 11; - %movi 8, 682, 11; - %set/v v0x24c7990_0, 8, 11; - %movi 8, 682, 11; - %set/v v0x24c6760_0, 8, 11; - %set/v v0x24c6940_0, 0, 1; - %movi 8, 2, 2; - %set/v v0x24c6e60_0, 8, 2; - %movi 8, 2, 2; - %set/v v0x24c6fe0_0, 8, 2; - %set/v v0x24c71a0_0, 0, 1; - %movi 8, 2, 2; - %set/v v0x24c76f0_0, 8, 2; - %movi 8, 2, 2; - %set/v v0x24c7870_0, 8, 2; - %set/v v0x24c9060_0, 0, 1; - %movi 8, 2, 2; - %set/v v0x24c7ee0_0, 8, 2; - %movi 8, 2, 2; - %set/v v0x24c8060_0, 8, 2; - %set/v v0x24c8200_0, 0, 1; - %movi 8, 2, 2; - %set/v v0x24c8750_0, 8, 2; - %movi 8, 2, 2; - %set/v v0x24c88d0_0, 8, 2; - %movi 8, 682, 11; - %set/v v0x24c8a70_0, 8, 11; - %movi 8, 682, 11; - %set/v v0x24c8c50_0, 8, 11; - %movi 8, 682, 11; - %set/v v0x24c8e30_0, 8, 11; - %movi 8, 682, 11; - %set/v v0x24c9220_0, 8, 11; - %set/v v0x24c9540_0, 0, 1; - %movi 8, 2, 2; - %set/v v0x24c9bc0_0, 8, 2; - %movi 8, 2, 2; - %set/v v0x24c9d40_0, 8, 2; - %set/v v0x24c9f80_0, 0, 1; - %movi 8, 2, 2; - %set/v v0x24ca600_0, 8, 2; - %movi 8, 2, 2; - %set/v v0x24cc070_0, 8, 2; - %set/v v0x24caa10_0, 0, 1; - %movi 8, 2, 2; - %set/v v0x24cb030_0, 8, 2; - %movi 8, 2, 2; - %set/v v0x24cb1b0_0, 8, 2; - %set/v v0x24cb430_0, 0, 1; - %movi 8, 2, 2; - %set/v v0x24cba80_0, 8, 2; - %movi 8, 2, 2; - %set/v v0x24cbc00_0, 8, 2; - %movi 8, 2, 3; - %set/v v0x24cda60_0, 8, 3; - %set/v v0x24cc190_0, 0, 1; - %movi 8, 10922, 14; - %set/v v0x24cd090_0, 8, 14; - %set/v v0x24cd490_0, 0, 1; - %movi 8, 2, 3; - %set/v v0x24cf630_0, 8, 3; - %movi 8, 2, 2; - %set/v v0x24cdbe0_0, 8, 2; - %set/v v0x24cdd60_0, 0, 1; - %movi 8, 2, 2; - %set/v v0x24cdf20_0, 8, 2; - %set/v v0x24ce100_0, 0, 1; - %set/v v0x24ce380_0, 0, 1; - %set/v v0x24cfe80_0, 0, 1; - %movi 8, 2, 2; - %set/v v0x24d0420_0, 8, 2; - %movi 8, 2, 2; - %set/v v0x24d09c0_0, 8, 2; - %set/v v0x24d0b40_0, 0, 1; - %movi 8, 2, 2; - %set/v v0x24d0cc0_0, 8, 2; - %movi 8, 682, 11; - %set/v v0x24d20e0_0, 8, 11; - %movi 8, 682, 11; - %set/v v0x24d22e0_0, 8, 11; - %movi 8, 682, 11; - %set/v v0x24d24e0_0, 8, 11; - %movi 8, 682, 11; - %set/v v0x24d2760_0, 8, 11; - %set/v v0x24d28e0_0, 0, 1; - %movi 8, 2, 2; - %set/v v0x24d2dd0_0, 8, 2; - %movi 8, 2, 2; - %set/v v0x24d2f50_0, 8, 2; - %set/v v0x24d30d0_0, 0, 1; - %movi 8, 2, 2; - %set/v v0x24d3600_0, 8, 2; - %movi 8, 2, 2; - %set/v v0x24d3780_0, 8, 2; - %set/v v0x24d3900_0, 0, 1; - %movi 8, 2, 2; - %set/v v0x24d3df0_0, 8, 2; - %movi 8, 2, 2; - %set/v v0x24d3f70_0, 8, 2; - %set/v v0x24d40f0_0, 0, 1; - %movi 8, 2, 2; - %set/v v0x24d45e0_0, 8, 2; - %movi 8, 2, 2; - %set/v v0x24d4760_0, 8, 2; - %end; - .thread T_48; - .scope S_0x23c0270; -T_49 ; - %wait E_0x24a1a60; - %delay 0, 0; - %load/v 8, v0x24aedf0_0, 1; - %jmp/0xz T_49.0, 8; - %load/v 8, v0x24af2f0_0, 1; - %jmp/0xz T_49.2, 8; - %load/v 8, v0x24d1a60_0, 32; - %vpi_call 4 2658 "$display", T<8,32,u>; -T_49.2 ; -T_49.0 ; - %jmp T_49; - .thread T_49; - .scope S_0x239a640; -T_50 ; - %wait E_0x2419550; - %load/v 8, v0x24d4be0_0, 1; - %cmpi/u 8, 0, 1; - %jmp/0xz T_50.0, 4; - %ix/load 0, 2, 0; - %assign/v0 v0x24d74f0_0, 0, 0; - %ix/load 0, 1, 0; - %assign/v0 v0x24d7570_0, 0, 0; - %ix/load 0, 32, 0; - %assign/v0 v0x24d78a0_0, 0, 0; - %jmp T_50.1; -T_50.0 ; - %load/v 8, v0x24d7670_0, 1; - %jmp/0xz T_50.2, 8; - %load/v 8, v0x24d75f0_0, 2; - %ix/load 0, 2, 0; - %assign/v0 v0x24d74f0_0, 0, 8; -T_50.2 ; - %load/v 8, v0x24d76f0_0, 1; - %jmp/0xz T_50.4, 8; - %load/v 8, v0x24d7780_0, 1; - %ix/load 0, 1, 0; - %assign/v0 v0x24d7570_0, 0, 8; -T_50.4 ; - %load/v 8, v0x24d79d0_0, 1; - %jmp/0xz T_50.6, 8; - %load/v 8, v0x24d7800_0, 32; - %ix/load 0, 32, 0; - %assign/v0 v0x24d78a0_0, 0, 8; -T_50.6 ; -T_50.1 ; - %jmp T_50; - .thread T_50; - .scope S_0x239a640; -T_51 ; - %movi 8, 2, 2; - %set/v v0x24d74f0_0, 8, 2; - %set/v v0x24d7570_0, 0, 1; - %movi 8, 2863311530, 32; - %set/v v0x24d78a0_0, 8, 32; - %end; - .thread T_51; - .scope S_0x239a640; -T_52 ; - %wait E_0x24a1a60; - %delay 0, 0; - %load/v 8, v0x24d4be0_0, 1; - %jmp/0xz T_52.0, 8; - %movi 8, 1000000, 32; - %load/v 40, v0x24d78a0_0, 32; - %cmp/u 8, 40, 32; - %or 5, 4, 1; - %mov 8, 5, 1; - %load/v 9, v0x24d50b0_0, 1; - %or 8, 9, 1; - %jmp/0xz T_52.2, 8; - %vpi_call 3 123 "$finish", 32'b00000000000000000000000000000001; -T_52.2 ; -T_52.0 ; - %jmp T_52; - .thread T_52; - .scope S_0x23eaf70; -T_53 ; - %set/v v0x24d7bb0_0, 0, 32; - %vpi_func 2 63 "$test$plusargs", 8, 32, "bscvcd"; - %set/v v0x24d7e40_0, 8, 1; - %vpi_func 2 64 "$test$plusargs", 8, 32, "bscfst"; - %set/v v0x24d7da0_0, 8, 1; - %vpi_func 2 65 "$test$plusargs", 8, 32, "bscfsdb"; - %set/v v0x24d7d00_0, 8, 1; - %vpi_func 2 66 "$test$plusargs", 8, 32, "bsccycle"; - %set/v v0x24d7c50_0, 8, 1; - %vpi_func 2 68 "$value$plusargs", 8, 32, "bscvcd=%s", v0x24d7ee0_0; - %cmpi/u 8, 0, 32; - %inv 4, 1; - %jmp/0xz T_53.0, 4; - %set/v v0x24d7e40_0, 1, 1; - %jmp T_53.1; -T_53.0 ; - %load/v 8, v0x24d7e40_0, 1; - %jmp/0xz T_53.2, 8; - %movi 8, 779510628, 32; - %movi 40, 1685417328, 32; - %movi 72, 0, 32; - %movi 104, 0, 32; - %movi 136, 0, 32; - %movi 168, 0, 32; - %movi 200, 0, 32; - %movi 232, 0, 32; - %movi 264, 0, 32; - %movi 296, 0, 32; - %movi 328, 0, 32; - %movi 360, 0, 32; - %movi 392, 0, 32; - %movi 424, 0, 32; - %movi 456, 0, 32; - %movi 488, 0, 32; - %movi 520, 0, 32; - %movi 552, 0, 32; - %movi 584, 0, 32; - %movi 616, 0, 32; - %movi 648, 0, 32; - %movi 680, 0, 32; - %movi 712, 0, 32; - %movi 744, 0, 32; - %movi 776, 0, 32; - %movi 808, 0, 32; - %movi 840, 0, 32; - %movi 872, 0, 32; - %movi 904, 0, 32; - %movi 936, 0, 32; - %movi 968, 0, 32; - %movi 1000, 0, 32; - %movi 1032, 0, 32; - %movi 1064, 0, 32; - %movi 1096, 0, 32; - %movi 1128, 0, 32; - %movi 1160, 0, 32; - %movi 1192, 0, 32; - %movi 1224, 0, 32; - %movi 1256, 0, 32; - %movi 1288, 0, 32; - %movi 1320, 0, 32; - %movi 1352, 0, 32; - %movi 1384, 0, 32; - %movi 1416, 0, 32; - %movi 1448, 0, 32; - %movi 1480, 0, 32; - %movi 1512, 0, 32; - %movi 1544, 0, 32; - %movi 1576, 0, 32; - %movi 1608, 0, 32; - %movi 1640, 0, 32; - %movi 1672, 0, 32; - %movi 1704, 0, 32; - %movi 1736, 0, 32; - %movi 1768, 0, 32; - %movi 1800, 0, 32; - %movi 1832, 0, 32; - %movi 1864, 0, 32; - %movi 1896, 0, 32; - %movi 1928, 0, 32; - %movi 1960, 0, 32; - %movi 1992, 0, 32; - %movi 2024, 0, 32; - %set/v v0x24d7ee0_0, 8, 2048; -T_53.2 ; -T_53.1 ; - %vpi_func 2 73 "$value$plusargs", 8, 32, "bscfsdb=%s", v0x24d7ee0_0; - %cmpi/u 8, 0, 32; - %inv 4, 1; - %jmp/0xz T_53.4, 4; - %set/v v0x24d7d00_0, 1, 1; - %jmp T_53.5; -T_53.4 ; - %load/v 8, v0x24d7d00_0, 1; - %jmp/0xz T_53.6, 8; - %movi 8, 1718838370, 32; - %movi 40, 1970106414, 32; - %movi 72, 100, 32; - %movi 104, 0, 32; - %movi 136, 0, 32; - %movi 168, 0, 32; - %movi 200, 0, 32; - %movi 232, 0, 32; - %movi 264, 0, 32; - %movi 296, 0, 32; - %movi 328, 0, 32; - %movi 360, 0, 32; - %movi 392, 0, 32; - %movi 424, 0, 32; - %movi 456, 0, 32; - %movi 488, 0, 32; - %movi 520, 0, 32; - %movi 552, 0, 32; - %movi 584, 0, 32; - %movi 616, 0, 32; - %movi 648, 0, 32; - %movi 680, 0, 32; - %movi 712, 0, 32; - %movi 744, 0, 32; - %movi 776, 0, 32; - %movi 808, 0, 32; - %movi 840, 0, 32; - %movi 872, 0, 32; - %movi 904, 0, 32; - %movi 936, 0, 32; - %movi 968, 0, 32; - %movi 1000, 0, 32; - %movi 1032, 0, 32; - %movi 1064, 0, 32; - %movi 1096, 0, 32; - %movi 1128, 0, 32; - %movi 1160, 0, 32; - %movi 1192, 0, 32; - %movi 1224, 0, 32; - %movi 1256, 0, 32; - %movi 1288, 0, 32; - %movi 1320, 0, 32; - %movi 1352, 0, 32; - %movi 1384, 0, 32; - %movi 1416, 0, 32; - %movi 1448, 0, 32; - %movi 1480, 0, 32; - %movi 1512, 0, 32; - %movi 1544, 0, 32; - %movi 1576, 0, 32; - %movi 1608, 0, 32; - %movi 1640, 0, 32; - %movi 1672, 0, 32; - %movi 1704, 0, 32; - %movi 1736, 0, 32; - %movi 1768, 0, 32; - %movi 1800, 0, 32; - %movi 1832, 0, 32; - %movi 1864, 0, 32; - %movi 1896, 0, 32; - %movi 1928, 0, 32; - %movi 1960, 0, 32; - %movi 1992, 0, 32; - %movi 2024, 0, 32; - %set/v v0x24d7ee0_0, 8, 2048; -T_53.6 ; -T_53.5 ; - %load/v 8, v0x24d7e40_0, 1; - %jmp/0xz T_53.8, 8; - %vpi_call 2 91 "$dumpfile", v0x24d7ee0_0; - %vpi_call 2 92 "$dumpvars", 1'sb0, S_0x23eaf70; -T_53.8 ; - %delay 0, 0; - %set/v v0x24d7b30_0, 0, 1; - %delay 1, 0; - %set/v v0x24d7940_0, 1, 1; - %delay 1, 0; - %set/v v0x24d7b30_0, 1, 1; - %end; - .thread T_53; - .scope S_0x23eaf70; -T_54 ; - %delay 1, 0; - %load/v 8, v0x24d7c50_0, 1; - %jmp/0xz T_54.0, 8; - %vpi_call 2 114 "$display", "cycle %0d", v0x24d7bb0_0; -T_54.0 ; - %load/v 8, v0x24d7bb0_0, 32; - %mov 40, 0, 1; - %addi 8, 1, 33; - %set/v v0x24d7bb0_0, 8, 32; - %delay 4, 0; - %set/v v0x24d7940_0, 0, 1; - %delay 5, 0; - %set/v v0x24d7940_0, 1, 1; - %jmp T_54; - .thread T_54; -# The file index is used to find the file name in the following table. -:file_names 8; - "N/A"; - ""; - "/home/drew/volume/bluespec/bsc/inst/lib/Verilog/main.v"; - "Circuit_verilog/mkTB.v"; - "Circuit_verilog/mkCircuit.v"; - "/home/drew/volume/bluespec/bsc/src/Verilog/RevertReg.v"; - "/home/drew/volume/bluespec/bsc/src/Verilog/FIFO2.v"; - "/home/drew/volume/bluespec/bsc/src/Verilog/RegFileLoad.v"; diff --git a/src/test/tests/histogram/w b/src/test/tests/histogram/w deleted file mode 100644 index fb229e85..00000000 --- a/src/test/tests/histogram/w +++ /dev/null @@ -1,1024 +0,0 @@ -e35d -4d32 -7da9 -8f6c -476e -5ca3 -4cf2 -dd3 -7bca -1ae6 -e4df -1c1a -c660 -3c92 -c5ed -b870 -683f -5f21 -4ab5 -6b1a -5b14 -2b70 -3045 -1e82 -7f29 -58c8 -2849 -75ba -fe8c -f130 -1a03 -9a44 -5c4 -b596 -6287 -6f5 -35fd -9042 -d44c -6e7e -c4a1 -4245 -705a -16fb -92c1 -537 -13ed -9a7b -7034 -9a13 -4b68 -dcd -9c91 -1868 -8a33 -dc98 -a02b -f2f7 -859c -da82 -1250 -bfe3 -eaf1 -e70c -6d78 -d7d2 -1d0f -3af0 -df0b -4837 -c7e0 -dcd2 -1457 -9e6b -8f19 -85ba -7a02 -faf9 -c4bd -46cf -a4c4 -ab1b -3a90 -c70b -a9d3 -4202 -eae1 -d39c -e11b -2057 -5886 -674 -cc30 -56c9 -4e24 -5e8e -e7d6 -6c9b -b207 -1abc -d4a0 -6560 -c849 -ecec -2ab7 -4553 -c0aa -869e -2e3e -aaed -4b56 -8a68 -82be -1c2 -16f6 -77b8 -8d7c -7fad -2e7e -303e -e5b5 -f517 -c4f0 -2728 -8859 -6cd2 -e48d -2ca8 -5f49 -5b1d -ec51 -89a2 -7c8d -66d4 -be01 -d276 -74ed -a73c -df34 -7301 -e499 -500 -b42e -92fb -8f5 -89be -f346 -f81 -bdc3 -175c -be29 -6a9 -26b2 -cb83 -aac0 -db46 -a6c -4c2c -db57 -d305 -de7e -34a2 -f3b4 -ed6 -cd49 -aeb6 -d2cc -cec7 -7dfd -e9c -57e -cd8d -135b -a906 -a1ea -3f5f -fdfe -771d -d356 -415e -c3d4 -dad5 -b7e2 -8d27 -74c1 -a476 -225f -354f -f61e -87d5 -6709 -55fb -b89f -714a -10a7 -ae75 -7fc6 -9804 -681e -5802 -2440 -112 -41f6 -7983 -4508 -24cc -e702 -48e6 -9ae6 -137d -f670 -a117 -9822 -5605 -5370 -4fc0 -8083 -a8d1 -646 -4754 -9cc9 -e22e -1bb6 -8272 -568d -edbd -1d18 -6b8e -3654 -dd6e -8a8a -793c -13db -158 -96c2 -bafb -807c -a32b -3c6e -c5c4 -1af1 -c3c -e9c -a9bf -33cb -8e51 -44a -dcde -e781 -4be6 -986 -b7c2 -a010 -e48c -a226 -ccc5 -291b -29da -223d -f31e -1871 -d122 -6228 -eb9f -63e -3237 -c6c2 -8025 -c602 -8c1a -954f -8473 -b051 -c1a8 -e4eb -2d3f -d6e8 -d2e6 -d885 -6af0 -462e -8eee -db55 -df1e -e970 -a7cc -49fe -48a1 -4047 -c86d -a356 -f016 -63aa -e5a3 -2002 -6885 -4697 -5a77 -6fa1 -738d -2173 -95bd -8f99 -c00f -5ddd -1735 -eac0 -acd0 -83ef -1e10 -94ba -f708 -ced5 -e57b -d793 -eec9 -76e0 -4de1 -f8ec -39ec -774 -cfdd -157a -885a -7172 -797 -e87c -b4a3 -fb54 -c9ce -f0da -5759 -d14b -c67d -81be -adbc -35d3 -44aa -381b -1a82 -3006 -8788 -cf3 -5c82 -e5a1 -3ae8 -c459 -a0c4 -7c6a -ac6b -f6d0 -bea0 -a6a6 -2be0 -465 -82c5 -b1fc -489e -3ac0 -e424 -b495 -9eda -9fc6 -2992 -2c6 -e815 -a556 -6306 -7d8b -2859 -76e3 -83bc -2864 -47c5 -3a92 -e5a2 -418a -98cf -1c81 -f06c -5ac2 -a844 -16e5 -11b6 -88b8 -f02c -643a -962c -1c17 -5b1e -5524 -57ce -bfab -ee0b -c8a1 -915f -a2f8 -eba4 -decc -9548 -3632 -9a4b -3b2e -24be -2ca5 -cc52 -8f3e -d53a -1257 -ee74 -672f -5c44 -eae4 -c217 -bdee -e6ff -869a -dc2d -9056 -615b -9205 -5f1a -169a -f325 -bf94 -4999 -fc9a -154b -c4ea -bec3 -a204 -b205 -8a89 -4077 -488d -6525 -be28 -5d1e -4cc -6948 -ab98 -793f -1c5c -30b0 -9eaa -53ee -455d -600c -3788 -9faf -7711 -8c1d -bb57 -8002 -dd13 -b8a -a6c -2a76 -2cd8 -9a86 -1cb0 -1193 -7409 -d053 -a197 -63ef -4456 -3d69 -2468 -d2cd -6a27 -d698 -349a -4e29 -9661 -5bba -f66a -ffc6 -3b7f -1a0f -e647 -6099 -7290 -913b -d3c8 -e383 -e0f1 -905f -4bf2 -ba3e -1286 -ad26 -f86 -8dd2 -89b3 -fb38 -566b -4718 -54ee -8563 -a655 -de0d -6d3f -bd6b -dd67 -842f -907f -49d6 -cb8e -cf21 -a4 -d4ba -ab5c -199 -4e8a -b17e -ef13 -695e -8d69 -ec2a -ecfb -7e2c -63de -116b -d8ea -fee9 -357 -550c -54d0 -7cd6 -2e10 -abcd -78ad -5fe3 -e1eb -9714 -18be -7fc4 -b26a -4ba1 -f02c -8396 -414d -3225 -2c48 -a9d7 -fb13 -8fb1 -31d1 -bc34 -55f3 -1eb4 -bfec -6309 -5632 -1dfe -44b3 -eb02 -4569 -93de -1b0b -c0c2 -a1c -56c5 -e15b -5303 -c5dd -9c9b -5b0c -df44 -a8d4 -4a2 -a3a4 -9867 -cd4f -fad -7fc0 -da9 -6c67 -f5a3 -7f53 -335d -88af -902d -7238 -aa20 -ecf5 -5f38 -7e30 -1d1a -ee2e -56d2 -6092 -d05c -105d -6d4c -fc9 -c61d -8181 -a660 -de67 -8865 -4af3 -6310 -5c38 -750d -4c05 -f7d8 -b6eb -f843 -27b4 -422c -1c78 -5b7 -9dd6 -1d4f -42d8 -372e -95c6 -35e -743c -a00f -e85e -d488 -61c7 -c539 -a855 -9ce -2a44 -6732 -e5f2 -84be -eb88 -56a9 -4d13 -a093 -65a4 -50d1 -4d74 -2d35 -8b96 -966a -fce3 -2a -c78b -4d7a -841c -dc7c -7dc4 -bf56 -917a -8fe7 -525c -aab5 -1ad6 -6278 -90b4 -703a -3a06 -d59d -104b -1fe5 -67db -51aa -27c5 -ead1 -15 -cc00 -d4be -4758 -3878 -ce41 -b374 -227 -6d61 -2685 -c51b -5d09 -6a20 -1be5 -3c6d -5914 -aa28 -5fbd -8eda -fce9 -353c -555a -2ac2 -35bb -db3d -4d79 -51f4 -42cc -1767 -3b57 -680a -1b4d -9e05 -5c26 -5009 -1e3a -95ed -9245 -5855 -8f76 -3fec -8133 -61d6 -e4c2 -84d1 -18a9 -eb3a -ed29 -b62d -6a80 -dda -2da0 -19ad -ba82 -3376 -eac5 -69dc -6f0f -dc3c -c9c4 -d527 -47d9 -88d5 -85b0 -a399 -4b85 -2d52 -3b8f -38d9 -9f3a -355f -59f9 -c15d -c338 -6963 -69d5 -52dd -eef7 -13fd -897 -683d -d4c4 -d97a -69fc -6363 -6a49 -5427 -3342 -9322 -4f78 -da68 -2542 -43ff -91c3 -cb2f -c122 -b6c2 -3d18 -644b -4d84 -c397 -f8af -d949 -93ae -326d -c1a8 -123a -8e10 -dd18 -4331 -ed73 -8f87 -ec6a -c958 -eee7 -255a -8a62 -f368 -20bb -e12e -47f7 -1ac4 -4c5c -1ca5 -f80e -7dcf -36a3 -b1d1 -9a34 -2a13 -d625 -22ef -9ff -7a2 -8d98 -149c -e285 -57aa -de81 -a8b7 -73e8 -240f -2fb9 -d147 -d22c -1b85 -a07a -3a69 -2423 -df5e -4162 -d4c7 -1e36 -fc72 -d1f6 -3f87 -6298 -6979 -803e -7d61 -adf1 -18a5 -6a28 -34db -d093 -bb6b -62d4 -ab85 -7784 -7378 -f1e5 -3051 -69ab -a5bc -adc7 -7d33 -c36f -3253 -cd0 -fd39 -c139 -cfd1 -14c -ddc3 -1ef6 -70f9 -2b67 -6811 -faf3 -52a7 -f685 -a064 -7ccf -5bbb -7f4d -611f -68a5 -c398 -e1c5 -af9d -e28b -cc63 -5c72 -757d -4a26 -b601 -33ed -f8aa -8899 -bcc6 -2ae8 -be4d -e802 -f4f2 -c267 -1d7e -81d5 -8044 -ee8e -ce4c -246d -f849 -f270 -a4c5 -d708 -dbc3 -32dc -55f0 -a984 -62d2 -e1ac -5337 -81c8 -c1d7 -da6f -2ec1 -eec -a95c -2b49 -9602 -d997 -af25 -eb36 -3ead -ac49 -5cdb -d617 -6a2d -d540 -613c -f151 -2c73 -5138 -f3f8 -4d62 -f93f -f9be -e86d -fc00 -2e70 -c6a7 -5abd -37f -3779 -ef3b -e356 -8938 -5562 -d0c7 -12b -8244 -2c77 -7be6 -937 -edc4 -94fa -63f7 -9bf3 -3af0 -3314 -13c0 -642 -e8f8 -7446 -e252 -4c9e -5c27 -69cd -438c -136b -1c65 -c040 -82d2 -70de -521e -c10d -fc86 -a181 -1118 -d32d -7627 -eacb -5a0b -911f -2d9d -e58c -4d48 -37d -f8bb -4e51 -bf6f -65b3 -2642 -12b6 -be87 -9557 -4475 -213 -eeec -b91c -f608 -9437 -65d3 -1a17 -4046 -c77 -8794 -add5 -5bb4 -a817 -c422 -8153 -de87 -f7b8 -f907 -70dc -dd78 -51b8 -ff40 -3f3c -56b0 -f21e -9b9 -d3f8 -5361 -b976 -1816 -d466 -c9f9 -11bf -d636 -dafe -8452 -b4d2 -d4c3 -b34e -6de7 -6d6d diff --git a/src/test/tests/risc-pipe/Circuit.bsv b/src/test/tests/risc-pipe/Circuit.bsv deleted file mode 100644 index 8077f065..00000000 --- a/src/test/tests/risc-pipe/Circuit.bsv +++ /dev/null @@ -1,56 +0,0 @@ -import ClientServer :: *; -import Connectable :: *; -import Locks :: *; -import Memories :: *; -import VerilogLibs :: *; -import RegFile :: *; -import BRAMCore :: *; -import Multi_stg_div :: *; -import Cpu :: *; -import Functions :: *; - - - -interface TopMod; - interface Client#( Tuple3#( Bit#(4), UInt#(16), Int#(32) ), Int#(32) ) _intti; - interface Client#( Tuple3#( Bit#(4), UInt#(16), Int#(32) ), Int#(32) ) _inttd; - interface Cpu _intc; -endinterface - -(* synthesize *) -module mkTB ( Empty _unused_ ) provisos( ); - Reg#( Bool ) started <- mkReg ( False ); - Reg#( UInt#(32) ) timer <- mkReg ( 0 ); - TopMod _topMod <- mkCircuit ( ); - BramPort#( UInt#(16), Int#(32), MemId#(8), 4 ) ti <- mkBramPort ( True, "ti4" ); - BramPort#( UInt#(16), Int#(32), MemId#(8), 4 ) td <- mkBramPort ( True, "td4" ); - Reg#( UInt#(3) ) reg_unused_0 <- mkReg ( 0 ); - mkConnection(_topMod._intti, ti.bram_server); - mkConnection(_topMod._inttd, td.bram_server); - rule initTB (( ! started )); - UInt#(3) _unused_0 = ?; - _unused_0 <- _topMod._intc.req(16'd0); - reg_unused_0 <= _unused_0; - started <= True; - endrule - rule timerCount ; - timer <= ( timer + 1 ); - endrule - rule stopTB (( ( timer >= 32'd1000000 ) || _topMod._intc.checkHandle(reg_unused_0) )); - $finish(); - endrule -endmodule - -(* synthesize *) -module mkCircuit ( TopMod _unused_ ) provisos( ); - AsyncMem#( UInt#(16), Int#(32), MemId#(8), 4 ) ti <- mkAsyncMem ( ); - QueueLockAsyncMem#( UInt#(16), Int#(32), MemId#(8), 4, LockId#(4) ) i <- mkQueueLockAsyncMem ( ti ); - AsyncMem#( UInt#(16), Int#(32), MemId#(8), 4 ) td <- mkAsyncMem ( ); - RegFile#( UInt#(5), Int#(32) ) rf <- mkRegFile ( True, "rf" ); - BypassLockCombMem#( UInt#(5), Int#(32), LockId#(4), 4 ) r <- mkBypassLockCombMem ( rf ); - Multi_stg_div div <- mkMulti_stg_div ( ); - Cpu c <- mkCpu ( r, i, td, div ); - interface Client _intti = ti.bram_client; - interface Client _inttd = td.bram_client; - interface Cpu _intc = c; -endmodule diff --git a/src/test/tests/risc-pipe/Circuit_verilog/mkMulti_stg_div.v b/src/test/tests/risc-pipe/Circuit_verilog/mkMulti_stg_div.v deleted file mode 100644 index c0dd96af..00000000 --- a/src/test/tests/risc-pipe/Circuit_verilog/mkMulti_stg_div.v +++ /dev/null @@ -1,346 +0,0 @@ -// -// Generated by Bluespec Compiler -// -// -// Ports: -// Name I/O size props -// req O 1 reg -// RDY_req O 1 -// RDY_resp O 1 const -// checkHandle O 1 -// RDY_checkHandle O 1 const -// peek O 32 reg -// RDY_peek O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// req_num I 32 -// req_denom I 32 -// req_quot I 32 -// req_acc I 32 -// req_cnt I 5 -// req_retQuot I 1 -// checkHandle_handle I 1 -// EN_resp I 1 -// EN_req I 1 -// -// Combinational paths from inputs to outputs: -// checkHandle_handle -> checkHandle -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkMulti_stg_div(CLK, - RST_N, - - req_num, - req_denom, - req_quot, - req_acc, - req_cnt, - req_retQuot, - EN_req, - req, - RDY_req, - - EN_resp, - RDY_resp, - - checkHandle_handle, - checkHandle, - RDY_checkHandle, - - peek, - RDY_peek); - input CLK; - input RST_N; - - // actionvalue method req - input [31 : 0] req_num; - input [31 : 0] req_denom; - input [31 : 0] req_quot; - input [31 : 0] req_acc; - input [4 : 0] req_cnt; - input req_retQuot; - input EN_req; - output req; - output RDY_req; - - // action method resp - input EN_resp; - output RDY_resp; - - // value method checkHandle - input checkHandle_handle; - output checkHandle; - output RDY_checkHandle; - - // value method peek - output [31 : 0] peek; - output RDY_peek; - - // signals for module outputs - wire [31 : 0] peek; - wire RDY_checkHandle, RDY_peek, RDY_req, RDY_resp, checkHandle, req; - - // inlined wires - wire [134 : 0] fifo__input__TO_Start_enq_data$wget; - wire fifo__input__TO_Start_enq_data$whas; - - // register _unnamed_ - reg _unnamed_; - wire _unnamed_$D_IN, _unnamed_$EN; - - // register busyReg - reg busyReg; - wire busyReg$D_IN, busyReg$EN; - - // register outputQueue_nextTag_rl - reg outputQueue_nextTag_rl; - wire outputQueue_nextTag_rl$D_IN, outputQueue_nextTag_rl$EN; - - // register outputQueue_val - reg [32 : 0] outputQueue_val; - wire [32 : 0] outputQueue_val$D_IN; - wire outputQueue_val$EN; - - // ports of submodule fifo__input__TO_Start_f - wire [134 : 0] fifo__input__TO_Start_f$D_IN, fifo__input__TO_Start_f$D_OUT; - wire fifo__input__TO_Start_f$CLR, - fifo__input__TO_Start_f$DEQ, - fifo__input__TO_Start_f$EMPTY_N, - fifo__input__TO_Start_f$ENQ, - fifo__input__TO_Start_f$FULL_N; - - // ports of submodule outputQueue_nextTag_dummy2_0 - wire outputQueue_nextTag_dummy2_0$D_IN, - outputQueue_nextTag_dummy2_0$EN, - outputQueue_nextTag_dummy2_0$Q_OUT; - - // ports of submodule outputQueue_nextTag_dummy2_1 - wire outputQueue_nextTag_dummy2_1$D_IN, - outputQueue_nextTag_dummy2_1$EN, - outputQueue_nextTag_dummy2_1$Q_OUT; - - // rule scheduling signals - wire WILL_FIRE_RL_s_Start_execute; - - // inputs to muxes for submodule ports - wire [134 : 0] MUX_fifo__input__TO_Start_enq_data$wset_1__VAL_1, - MUX_fifo__input__TO_Start_enq_data$wset_1__VAL_2; - wire [32 : 0] MUX_outputQueue_val$write_1__VAL_1; - wire MUX_busyReg$write_1__SEL_1, - MUX_fifo__input__TO_Start_enq_data$wset_1__SEL_1; - - // remaining internal signals - wire [31 : 0] IF_fifo__input__TO_Start_f_first__3_BITS_37_TO_ETC___d36, - b__h1819; - wire IF_outputQueue_nextTag_lat_0_whas_THEN_outputQ_ETC___d10, - b__h1320, - fifo__input__TO_Start_f_first__3_BITS_37_TO_7__ETC___d32; - - // actionvalue method req - assign req = _unnamed_ ; - assign RDY_req = !busyReg && fifo__input__TO_Start_f$FULL_N ; - - // action method resp - assign RDY_resp = 1'd1 ; - - // value method checkHandle - assign checkHandle = - (outputQueue_nextTag_dummy2_0$Q_OUT && - outputQueue_nextTag_dummy2_1$Q_OUT && - outputQueue_nextTag_rl) == - checkHandle_handle && - outputQueue_val[32] ; - assign RDY_checkHandle = 1'd1 ; - - // value method peek - assign peek = outputQueue_val[31:0] ; - assign RDY_peek = 1'd1 ; - - // submodule fifo__input__TO_Start_f - FIFO2 #(.width(32'd135), - .guarded(1'd1)) fifo__input__TO_Start_f(.RST(RST_N), - .CLK(CLK), - .D_IN(fifo__input__TO_Start_f$D_IN), - .ENQ(fifo__input__TO_Start_f$ENQ), - .DEQ(fifo__input__TO_Start_f$DEQ), - .CLR(fifo__input__TO_Start_f$CLR), - .D_OUT(fifo__input__TO_Start_f$D_OUT), - .FULL_N(fifo__input__TO_Start_f$FULL_N), - .EMPTY_N(fifo__input__TO_Start_f$EMPTY_N)); - - // submodule outputQueue_nextTag_dummy2_0 - RevertReg #(.width(32'd1), - .init(1'd1)) outputQueue_nextTag_dummy2_0(.CLK(CLK), - .D_IN(outputQueue_nextTag_dummy2_0$D_IN), - .EN(outputQueue_nextTag_dummy2_0$EN), - .Q_OUT(outputQueue_nextTag_dummy2_0$Q_OUT)); - - // submodule outputQueue_nextTag_dummy2_1 - RevertReg #(.width(32'd1), - .init(1'd1)) outputQueue_nextTag_dummy2_1(.CLK(CLK), - .D_IN(outputQueue_nextTag_dummy2_1$D_IN), - .EN(outputQueue_nextTag_dummy2_1$EN), - .Q_OUT(outputQueue_nextTag_dummy2_1$Q_OUT)); - - // rule RL_s_Start_execute - assign WILL_FIRE_RL_s_Start_execute = - fifo__input__TO_Start_f$EMPTY_N && - (fifo__input__TO_Start_f$D_OUT[6:2] == 5'd31 || - fifo__input__TO_Start_f$FULL_N) && - (fifo__input__TO_Start_f$D_OUT[6:2] != 5'd31 || - (outputQueue_nextTag_dummy2_1$Q_OUT && - IF_outputQueue_nextTag_lat_0_whas_THEN_outputQ_ETC___d10) == - fifo__input__TO_Start_f$D_OUT[0]) ; - - // inputs to muxes for submodule ports - assign MUX_busyReg$write_1__SEL_1 = - WILL_FIRE_RL_s_Start_execute && - fifo__input__TO_Start_f$D_OUT[6:2] == 5'd31 ; - assign MUX_fifo__input__TO_Start_enq_data$wset_1__SEL_1 = - WILL_FIRE_RL_s_Start_execute && - fifo__input__TO_Start_f$D_OUT[6:2] != 5'd31 ; - assign MUX_fifo__input__TO_Start_enq_data$wset_1__VAL_1 = - { fifo__input__TO_Start_f$D_OUT[133:103], - 1'd0, - fifo__input__TO_Start_f$D_OUT[102:71], - fifo__input__TO_Start_f$D_OUT[69:39], - !fifo__input__TO_Start_f_first__3_BITS_37_TO_7__ETC___d32, - IF_fifo__input__TO_Start_f_first__3_BITS_37_TO_ETC___d36, - fifo__input__TO_Start_f$D_OUT[6:2] + 5'd1, - fifo__input__TO_Start_f$D_OUT[1:0] } ; - assign MUX_fifo__input__TO_Start_enq_data$wset_1__VAL_2 = - { req_num, - req_denom, - req_quot, - req_acc, - req_cnt, - req_retQuot, - _unnamed_ } ; - assign MUX_outputQueue_val$write_1__VAL_1 = - { 1'd1, - fifo__input__TO_Start_f$D_OUT[1] ? - { fifo__input__TO_Start_f$D_OUT[69:39], - !fifo__input__TO_Start_f_first__3_BITS_37_TO_7__ETC___d32 } : - IF_fifo__input__TO_Start_f_first__3_BITS_37_TO_ETC___d36 } ; - - // inlined wires - assign fifo__input__TO_Start_enq_data$wget = - MUX_fifo__input__TO_Start_enq_data$wset_1__SEL_1 ? - MUX_fifo__input__TO_Start_enq_data$wset_1__VAL_1 : - MUX_fifo__input__TO_Start_enq_data$wset_1__VAL_2 ; - assign fifo__input__TO_Start_enq_data$whas = - WILL_FIRE_RL_s_Start_execute && - fifo__input__TO_Start_f$D_OUT[6:2] != 5'd31 || - EN_req ; - - // register _unnamed_ - assign _unnamed_$D_IN = _unnamed_ + 1'd1 ; - assign _unnamed_$EN = EN_req ; - - // register busyReg - assign busyReg$D_IN = !MUX_busyReg$write_1__SEL_1 ; - assign busyReg$EN = - WILL_FIRE_RL_s_Start_execute && - fifo__input__TO_Start_f$D_OUT[6:2] == 5'd31 || - EN_req ; - - // register outputQueue_nextTag_rl - assign outputQueue_nextTag_rl$D_IN = - IF_outputQueue_nextTag_lat_0_whas_THEN_outputQ_ETC___d10 ; - assign outputQueue_nextTag_rl$EN = 1'd1 ; - - // register outputQueue_val - assign outputQueue_val$D_IN = - MUX_busyReg$write_1__SEL_1 ? - MUX_outputQueue_val$write_1__VAL_1 : - 33'h0AAAAAAAA ; - assign outputQueue_val$EN = - WILL_FIRE_RL_s_Start_execute && - fifo__input__TO_Start_f$D_OUT[6:2] == 5'd31 || - EN_resp ; - - // submodule fifo__input__TO_Start_f - assign fifo__input__TO_Start_f$D_IN = fifo__input__TO_Start_enq_data$wget ; - assign fifo__input__TO_Start_f$ENQ = - fifo__input__TO_Start_f$FULL_N && - fifo__input__TO_Start_enq_data$whas ; - assign fifo__input__TO_Start_f$DEQ = WILL_FIRE_RL_s_Start_execute ; - assign fifo__input__TO_Start_f$CLR = 1'b0 ; - - // submodule outputQueue_nextTag_dummy2_0 - assign outputQueue_nextTag_dummy2_0$D_IN = 1'd1 ; - assign outputQueue_nextTag_dummy2_0$EN = EN_resp ; - - // submodule outputQueue_nextTag_dummy2_1 - assign outputQueue_nextTag_dummy2_1$D_IN = 1'b0 ; - assign outputQueue_nextTag_dummy2_1$EN = 1'b0 ; - - // remaining internal signals - assign IF_fifo__input__TO_Start_f_first__3_BITS_37_TO_ETC___d36 = - fifo__input__TO_Start_f_first__3_BITS_37_TO_7__ETC___d32 ? - b__h1819 : - b__h1819 - fifo__input__TO_Start_f$D_OUT[102:71] ; - assign IF_outputQueue_nextTag_lat_0_whas_THEN_outputQ_ETC___d10 = - EN_resp ? b__h1320 : outputQueue_nextTag_rl ; - assign b__h1320 = - (outputQueue_nextTag_dummy2_0$Q_OUT && - outputQueue_nextTag_dummy2_1$Q_OUT && - outputQueue_nextTag_rl) + - 1'd1 ; - assign b__h1819 = - { fifo__input__TO_Start_f$D_OUT[37:7], - fifo__input__TO_Start_f$D_OUT[134] } ; - assign fifo__input__TO_Start_f_first__3_BITS_37_TO_7__ETC___d32 = - b__h1819 < fifo__input__TO_Start_f$D_OUT[102:71] ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - _unnamed_ <= `BSV_ASSIGNMENT_DELAY 1'd0; - busyReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - outputQueue_nextTag_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; - outputQueue_val <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; - end - else - begin - if (_unnamed_$EN) _unnamed_ <= `BSV_ASSIGNMENT_DELAY _unnamed_$D_IN; - if (busyReg$EN) busyReg <= `BSV_ASSIGNMENT_DELAY busyReg$D_IN; - if (outputQueue_nextTag_rl$EN) - outputQueue_nextTag_rl <= `BSV_ASSIGNMENT_DELAY - outputQueue_nextTag_rl$D_IN; - if (outputQueue_val$EN) - outputQueue_val <= `BSV_ASSIGNMENT_DELAY outputQueue_val$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - _unnamed_ = 1'h0; - busyReg = 1'h0; - outputQueue_nextTag_rl = 1'h0; - outputQueue_val = 33'h0AAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkMulti_stg_div - diff --git a/src/test/tests/risc-pipe/Cpu.bsv b/src/test/tests/risc-pipe/Cpu.bsv deleted file mode 100644 index b85a415c..00000000 --- a/src/test/tests/risc-pipe/Cpu.bsv +++ /dev/null @@ -1,544 +0,0 @@ -import FIFOF :: *; -import SpecialFIFOs :: *; -import SpecialQueues :: *; -import Locks :: *; -import Memories :: *; -import VerilogLibs :: *; -import Speculation :: *; -import RegFile :: *; -import Functions :: *; -import Multi_stg_div :: *; - -export Cpu (..); -export mkCpu ; - -typedef struct { Int#(16) pc; UInt#(3) _threadID; Maybe#( SpecId#(4) ) _specId ; } E__input__TO_Start deriving( Bits,Eq ); -typedef struct { MemId#(8) _request_0; Int#(16) _s_0; SpecId#(4) s; Int#(16) pc; UInt#(3) _threadID; Maybe#( SpecId#(4) ) _specId ; } E_Start_TO_Stage__0 deriving( Bits,Eq ); -typedef struct { Int#(32) rf2; Int#(32) rf1; Int#(32) immU; Bool isMul; Maybe#( _lidTyp_rf ) _lock_id_rf_rd_rs; Int#(16) pc; Bool isLui; UInt#(3) funct3; Int#(32) linkpc; Bool isStore; Bool isDiv; Bool done; Bool isJalr; UInt#(5) rd; Bool isJal; Int#(32) mulres; Bool writerd; Int#(32) insn; Int#(32) alu_res; Bool isLoad; UInt#(3) _threadID; Maybe#( SpecId#(4) ) _specId ; } E_Stage__0_TO_Stage__37#( type _lidTyp_rf ) deriving( Bits,Eq ); -typedef struct { UInt#(2) __condStage__50; Bool writerd; MemId#(8) _request_3; UInt#(2) boff; UInt#(1) __condStage__45; Int#(16) pc; MemId#(8) _request_4; UInt#(3) funct3; Bool invertRes; Bool done; UInt#(5) rd; Int#(32) wdata; Int#(32) rddata; Maybe#( _lidTyp_rf ) _lock_id_rf_rd_op; Maybe#( _lidTyp_rf ) _lock_id_rf_rd_rs; UInt#(32) udivout; Bool isDiv; Int#(32) insn; UInt#(1) _request_2; Bool isLoad; UInt#(3) _threadID; Maybe#( SpecId#(4) ) _specId ; } E_Stage__37_TO_Stage__51#( type _lidTyp_rf ) deriving( Bits,Eq ); - -interface Cpu; - method ActionValue#(UInt#(3)) req ( Int#(16) pc ) ; - method Action resp ( ) ; - method Bool checkHandle ( UInt#(3) handle ) ; - method Bool peek ( ) ; -endinterface - - -module mkCpu ( BypassLockCombMem#( UInt#(5), Int#(32), _lidTyp_rf, _szParam_0_rf ) rf, QueueLockAsyncMem#( UInt#(16), Int#(32), MemId#(8), 4, _lidTyp_imem ) imem, AsyncMem#( UInt#(16), Int#(32), MemId#(8), 4 ) dmem, Multi_stg_div div, Cpu _unused_ ) provisos( Bits#(_lidTyp_rf,_sz_lidTyp_rf),Bits#(_lidTyp_imem,_sz_lidTyp_imem) ); - FIFOF#( E__input__TO_Start ) fifo__input__TO_Start <- mkNBFIFOF ( ); - FIFOF#( E_Start_TO_Stage__0 ) fifo_Start_TO_Stage__0 <- mkFIFOF ( ); - FIFOF#( E_Stage__0_TO_Stage__37#(_lidTyp_rf) ) fifo_Stage__0_TO_Stage__37 <- mkFIFOF ( ); - FIFOF#( E_Stage__37_TO_Stage__51#(_lidTyp_rf) ) fifo_Stage__37_TO_Stage__51 <- mkFIFOF ( ); - Reg#( Bool ) rf_lock_region <- mkReg ( True ); - Reg#( Bool ) imem_lock_region <- mkReg ( True ); - Reg#( Bool ) dmem_lock_region <- mkReg ( True ); - Reg#( Bool ) div_lock_region <- mkReg ( True ); - CheckpointQueueLock#( LockId#(4), LockId#(4) ) _lock_div <- mkCheckpointQueueLock ( ); - Reg#( Bool ) busyReg <- mkReg ( False ); - SpecTable#( SpecId#(4), 2 ) _specTable <- mkSpecTable ( ); - OutputQ#( UInt#(3), Bool ) outputQueue <- mkOutputFIFOF ( 0 ); - Reg#( UInt#(3) ) _threadID <- mkReg ( 0 ); - Int#(16) _Start_pc = fifo__input__TO_Start.first.pc; - UInt#(3) _Start__threadID = fifo__input__TO_Start.first._threadID; - Maybe#( SpecId#(4) ) _Start__specId = fifo__input__TO_Start.first._specId; - UInt#(16) _Start__tmp_0 = ?; - UInt#(16) _Start_pcaddr = ?; - Int#(16) _Start__s_0 = ?; - _Start__tmp_0 = unpack( pack( _Start_pc ) ); - _Start_pcaddr = _Start__tmp_0; - _Start__s_0 = ( _Start_pc + 16'd1 ); - MemId#(8) _Stage__0__request_0 = fifo_Start_TO_Stage__0.first._request_0; - Int#(16) _Stage__0__s_0 = fifo_Start_TO_Stage__0.first._s_0; - SpecId#(4) _Stage__0_s = fifo_Start_TO_Stage__0.first.s; - Int#(16) _Stage__0_pc = fifo_Start_TO_Stage__0.first.pc; - UInt#(3) _Stage__0__threadID = fifo_Start_TO_Stage__0.first._threadID; - Maybe#( SpecId#(4) ) _Stage__0__specId = fifo_Start_TO_Stage__0.first._specId; - Int#(32) _Stage__0_insn = ?; - Bool _Stage__0_done = ?; - Int#(7) _Stage__0_opcode = ?; - UInt#(5) _Stage__0__tmp_1 = ?; - UInt#(5) _Stage__0_rs1 = ?; - UInt#(5) _Stage__0__tmp_2 = ?; - UInt#(5) _Stage__0_rs2 = ?; - UInt#(5) _Stage__0__tmp_3 = ?; - UInt#(5) _Stage__0_rd = ?; - UInt#(7) _Stage__0__tmp_4 = ?; - UInt#(7) _Stage__0_funct7 = ?; - UInt#(3) _Stage__0__tmp_5 = ?; - UInt#(3) _Stage__0_funct3 = ?; - Int#(1) _Stage__0_flipBit = ?; - Int#(32) _Stage__0__tmp_6 = ?; - Int#(32) _Stage__0_immI = ?; - Int#(32) _Stage__0__tmp_7 = ?; - Int#(32) _Stage__0_immS = ?; - Int#(13) _Stage__0_immBTmp = ?; - Int#(16) _Stage__0__tmp_8 = ?; - Int#(16) _Stage__0_immB = ?; - Int#(21) _Stage__0_immJTmp = ?; - Int#(32) _Stage__0__tmp_9 = ?; - Int#(32) _Stage__0_immJ = ?; - Int#(12) _Stage__0_immJRTmp = ?; - Int#(16) _Stage__0__tmp_10 = ?; - Int#(16) _Stage__0_immJR = ?; - Int#(32) _Stage__0_immU = ?; - UInt#(3) _Stage__0_doAdd = ?; - Bool _Stage__0_isOpImm = ?; - Bool _Stage__0_flip = ?; - Bool _Stage__0_isLui = ?; - Bool _Stage__0_isAui = ?; - Bool _Stage__0_isOp = ?; - Bool _Stage__0_isJal = ?; - Bool _Stage__0_isJalr = ?; - Bool _Stage__0_isBranch = ?; - Bool _Stage__0_isStore = ?; - Bool _Stage__0_isLoad = ?; - Bool _Stage__0_isMDiv = ?; - Bool _Stage__0_isDiv = ?; - Bool _Stage__0_isMul = ?; - Bool _Stage__0_needrs1 = ?; - Bool _Stage__0_needrs2 = ?; - Bool _Stage__0_writerd = ?; - Bool _Stage__0_notBranch = ?; - UInt#(1) _Stage__0___condStage__4 = ?; - UInt#(1) _Stage__0___condStage__8 = ?; - Int#(32) _Stage__0_rf1 = ?; - UInt#(1) _Stage__0___condStage__12 = ?; - Int#(32) _Stage__0_rf2 = ?; - UInt#(1) _Stage__0___condStage__16 = ?; - Bool _Stage__0_take = ?; - UInt#(1) _Stage__0___condStage__28 = ?; - Int#(16) _Stage__0_offpc = ?; - Int#(16) _Stage__0_npc = ?; - UInt#(1) _Stage__0___condStage__26 = ?; - Int#(32) _Stage__0__tmp_11 = ?; - Int#(32) _Stage__0_npc32 = ?; - UInt#(1) _Stage__0___condStage__24 = ?; - UInt#(1) _Stage__0___condStage__36 = ?; - UInt#(1) _Stage__0___condStage__33 = ?; - Int#(16) _Stage__0_carg_340 = ?; - Int#(32) _Stage__0_alu_arg1 = ?; - Int#(32) _Stage__0_alu_arg2 = ?; - Bool _Stage__0_alu_flip = ?; - UInt#(3) _Stage__0_alu_funct3 = ?; - Int#(32) _Stage__0_alu_res = ?; - Int#(16) _Stage__0_tmppc = ?; - Int#(32) _Stage__0_linkpc = ?; - Int#(32) _Stage__0_mulres = ?; - _Stage__0_insn = imem.mem.peekResp1(_Stage__0__request_0); - _Stage__0_done = ( _Stage__0_insn == 32'h6f ); - _Stage__0_opcode = unpack( pack( _Stage__0_insn ) [ 6 : 0 ] ); - _Stage__0__tmp_1 = unpack( pack( _Stage__0_insn ) [ 19 : 15 ] ); - _Stage__0_rs1 = _Stage__0__tmp_1; - _Stage__0__tmp_2 = unpack( pack( _Stage__0_insn ) [ 24 : 20 ] ); - _Stage__0_rs2 = _Stage__0__tmp_2; - _Stage__0__tmp_3 = unpack( pack( _Stage__0_insn ) [ 11 : 7 ] ); - _Stage__0_rd = _Stage__0__tmp_3; - _Stage__0__tmp_4 = unpack( pack( _Stage__0_insn ) [ 31 : 25 ] ); - _Stage__0_funct7 = _Stage__0__tmp_4; - _Stage__0__tmp_5 = unpack( pack( _Stage__0_insn ) [ 14 : 12 ] ); - _Stage__0_funct3 = _Stage__0__tmp_5; - _Stage__0_flipBit = unpack( pack( _Stage__0_insn ) [ 30 : 30 ] ); - _Stage__0__tmp_6 = signExtend( unpack( pack( _Stage__0_insn ) [ 31 : 20 ] ) ); - _Stage__0_immI = _Stage__0__tmp_6; - _Stage__0__tmp_7 = signExtend( unpack( { pack( _Stage__0_insn ) [ 31 : 25 ], pack( _Stage__0_insn ) [ 11 : 7 ] } ) ); - _Stage__0_immS = _Stage__0__tmp_7; - _Stage__0_immBTmp = unpack( { pack( _Stage__0_insn ) [ 31 : 31 ], { pack( _Stage__0_insn ) [ 7 : 7 ], { pack( _Stage__0_insn ) [ 30 : 25 ], { pack( _Stage__0_insn ) [ 11 : 8 ], pack( 1'd0 ) } } } } ); - _Stage__0__tmp_8 = signExtend( _Stage__0_immBTmp ); - _Stage__0_immB = _Stage__0__tmp_8; - _Stage__0_immJTmp = unpack( { pack( _Stage__0_insn ) [ 31 : 31 ], { pack( _Stage__0_insn ) [ 19 : 12 ], { pack( _Stage__0_insn ) [ 20 : 20 ], { pack( _Stage__0_insn ) [ 30 : 21 ], pack( 1'd0 ) } } } } ); - _Stage__0__tmp_9 = signExtend( _Stage__0_immJTmp ); - _Stage__0_immJ = _Stage__0__tmp_9; - _Stage__0_immJRTmp = unpack( pack( _Stage__0_insn ) [ 31 : 20 ] ); - _Stage__0__tmp_10 = signExtend( _Stage__0_immJRTmp ); - _Stage__0_immJR = _Stage__0__tmp_10; - _Stage__0_immU = unpack( { pack( _Stage__0_insn ) [ 31 : 12 ], pack( 12'd0 ) } ); - _Stage__0_doAdd = 3'd0; - _Stage__0_isOpImm = ( _Stage__0_opcode == 7'b10011 ); - _Stage__0_flip = ( ( ! _Stage__0_isOpImm ) && ( _Stage__0_flipBit == 1'd1 ) ); - _Stage__0_isLui = ( _Stage__0_opcode == 7'b110111 ); - _Stage__0_isAui = ( _Stage__0_opcode == 7'b10111 ); - _Stage__0_isOp = ( _Stage__0_opcode == 7'b110011 ); - _Stage__0_isJal = ( _Stage__0_opcode == 7'b1101111 ); - _Stage__0_isJalr = ( _Stage__0_opcode == 7'b1100111 ); - _Stage__0_isBranch = ( _Stage__0_opcode == 7'b1100011 ); - _Stage__0_isStore = ( _Stage__0_opcode == 7'b100011 ); - _Stage__0_isLoad = ( _Stage__0_opcode == 7'b11 ); - _Stage__0_isMDiv = ( ( _Stage__0_funct7 == 7'd1 ) && _Stage__0_isOp ); - _Stage__0_isDiv = ( _Stage__0_isMDiv && ( _Stage__0_funct3 >= 3'd4 ) ); - _Stage__0_isMul = ( _Stage__0_isMDiv && ( _Stage__0_funct3 < 3'd4 ) ); - _Stage__0_needrs1 = ( ! _Stage__0_isJal ); - _Stage__0_needrs2 = ( ( ( _Stage__0_isOp || _Stage__0_isBranch ) || _Stage__0_isStore ) || _Stage__0_isJalr ); - _Stage__0_writerd = ( ( _Stage__0_rd != 5'd0 ) && ( ( ( ( ( ( _Stage__0_isOp || _Stage__0_isOpImm ) || _Stage__0_isLoad ) || _Stage__0_isJal ) || _Stage__0_isJalr ) || _Stage__0_isLui ) || _Stage__0_isAui ) ); - _Stage__0_notBranch = ( ( ( ! _Stage__0_isBranch ) && ( ! _Stage__0_isJal ) ) && ( ! _Stage__0_isJalr ) ); - _Stage__0___condStage__4 = ( ( ( ! _Stage__0_done ) && _Stage__0_notBranch ) ? 1'd0 : 1'd1 ); - _Stage__0___condStage__8 = ( _Stage__0_needrs1 ? 1'd0 : 1'd1 ); - if ( ( _Stage__0___condStage__8 == 1'd0 )) - begin - _Stage__0_rf1 = rf.atom_r(_Stage__0_rs1); - end - if ( ( _Stage__0___condStage__8 == 1'd1 )) - begin - _Stage__0_rf1 = 32'd0; - end - _Stage__0___condStage__12 = ( _Stage__0_needrs2 ? 1'd0 : 1'd1 ); - if ( ( _Stage__0___condStage__12 == 1'd0 )) - begin - _Stage__0_rf2 = rf.atom_r(_Stage__0_rs2); - end - if ( ( _Stage__0___condStage__12 == 1'd1 )) - begin - _Stage__0_rf2 = 32'd0; - end - _Stage__0___condStage__16 = ( _Stage__0_writerd ? 1'd0 : 1'd1 ); - _Stage__0_take = br(_Stage__0_funct3, _Stage__0_rf1, _Stage__0_rf2); - _Stage__0___condStage__28 = ( _Stage__0_isBranch ? 1'd0 : 1'd1 ); - if ( ( _Stage__0___condStage__28 == 1'd0 )) - begin - _Stage__0_offpc = ( _Stage__0_pc + ( _Stage__0_immB >> 2'd2 ) ); - _Stage__0_npc = ( _Stage__0_take ? _Stage__0_offpc : ( _Stage__0_pc + 16'd1 ) ); - end - if ( ( _Stage__0___condStage__28 == 1'd1 )) - begin - _Stage__0___condStage__26 = ( _Stage__0_isJal ? 1'd0 : 1'd1 ); - end - if ( ( ( _Stage__0___condStage__28 == 1'd1 ) && ( _Stage__0___condStage__26 == 1'd0 ) )) - begin - _Stage__0__tmp_11 = signExtend( _Stage__0_pc ); - _Stage__0_npc32 = ( _Stage__0__tmp_11 + ( _Stage__0_immJ >> 2'd2 ) ); - _Stage__0_npc = unpack( pack( _Stage__0_npc32 ) [ 15 : 0 ] ); - end - if ( ( ( _Stage__0___condStage__28 == 1'd1 ) && ( _Stage__0___condStage__26 == 1'd1 ) )) - begin - _Stage__0___condStage__24 = ( _Stage__0_isJalr ? 1'd0 : 1'd1 ); - end - if ( ( ( _Stage__0___condStage__28 == 1'd1 ) && ( ( _Stage__0___condStage__26 == 1'd1 ) && ( _Stage__0___condStage__24 == 1'd0 ) ) )) - begin - _Stage__0_npc = ( ( unpack( pack( _Stage__0_rf1 ) [ 15 : 0 ] ) + _Stage__0_immJR ) >> 2'd2 ); - end - if ( ( ( _Stage__0___condStage__28 == 1'd1 ) && ( ( _Stage__0___condStage__26 == 1'd1 ) && ( _Stage__0___condStage__24 == 1'd1 ) ) )) - begin - _Stage__0_npc = ( _Stage__0_pc + 16'd1 ); - end - _Stage__0___condStage__36 = ( ( ! _Stage__0_done ) ? 1'd0 : 1'd1 ); - if ( ( _Stage__0___condStage__36 == 1'd0 )) - begin - _Stage__0___condStage__33 = ( ( ! _Stage__0_notBranch ) ? 1'd0 : 1'd1 ); - end - if ( ( ( _Stage__0___condStage__36 == 1'd0 ) && ( _Stage__0___condStage__33 == 1'd0 ) )) - begin - _Stage__0_carg_340 = _Stage__0_npc; - end - _Stage__0_alu_arg1 = ( _Stage__0_isAui ? ( unpack( { pack( 16'd0 ), pack( _Stage__0_pc ) } ) << 2'd2 ) : _Stage__0_rf1 ); - _Stage__0_alu_arg2 = ( _Stage__0_isAui ? _Stage__0_immU : ( _Stage__0_isStore ? _Stage__0_immS : ( ( _Stage__0_isOpImm || _Stage__0_isLoad ) ? _Stage__0_immI : _Stage__0_rf2 ) ) ); - _Stage__0_alu_flip = ( ( ( _Stage__0_isStore || _Stage__0_isLoad ) || _Stage__0_isAui ) ? False : _Stage__0_flip ); - _Stage__0_alu_funct3 = ( ( ( _Stage__0_isStore || _Stage__0_isLoad ) || _Stage__0_isAui ) ? _Stage__0_doAdd : _Stage__0_funct3 ); - _Stage__0_alu_res = alu(_Stage__0_alu_arg1, _Stage__0_alu_arg2, _Stage__0_alu_funct3, _Stage__0_alu_flip); - _Stage__0_tmppc = ( _Stage__0_pc + 16'd1 ); - _Stage__0_linkpc = unpack( { pack( 16'd0 ), pack( ( _Stage__0_tmppc << 2'd2 ) ) } ); - _Stage__0_mulres = mul(_Stage__0_rf1, _Stage__0_rf2, _Stage__0_funct3); - Int#(32) _Stage__37_rf2 = fifo_Stage__0_TO_Stage__37.first.rf2; - Int#(32) _Stage__37_rf1 = fifo_Stage__0_TO_Stage__37.first.rf1; - Int#(32) _Stage__37_immU = fifo_Stage__0_TO_Stage__37.first.immU; - Bool _Stage__37_isMul = fifo_Stage__0_TO_Stage__37.first.isMul; - Maybe#( _lidTyp_rf ) _Stage__37__lock_id_rf_rd_rs = fifo_Stage__0_TO_Stage__37.first._lock_id_rf_rd_rs; - Int#(16) _Stage__37_pc = fifo_Stage__0_TO_Stage__37.first.pc; - Bool _Stage__37_isLui = fifo_Stage__0_TO_Stage__37.first.isLui; - UInt#(3) _Stage__37_funct3 = fifo_Stage__0_TO_Stage__37.first.funct3; - Int#(32) _Stage__37_linkpc = fifo_Stage__0_TO_Stage__37.first.linkpc; - Bool _Stage__37_isStore = fifo_Stage__0_TO_Stage__37.first.isStore; - Bool _Stage__37_isDiv = fifo_Stage__0_TO_Stage__37.first.isDiv; - Bool _Stage__37_done = fifo_Stage__0_TO_Stage__37.first.done; - Bool _Stage__37_isJalr = fifo_Stage__0_TO_Stage__37.first.isJalr; - UInt#(5) _Stage__37_rd = fifo_Stage__0_TO_Stage__37.first.rd; - Bool _Stage__37_isJal = fifo_Stage__0_TO_Stage__37.first.isJal; - Int#(32) _Stage__37_mulres = fifo_Stage__0_TO_Stage__37.first.mulres; - Bool _Stage__37_writerd = fifo_Stage__0_TO_Stage__37.first.writerd; - Int#(32) _Stage__37_insn = fifo_Stage__0_TO_Stage__37.first.insn; - Int#(32) _Stage__37_alu_res = fifo_Stage__0_TO_Stage__37.first.alu_res; - Bool _Stage__37_isLoad = fifo_Stage__0_TO_Stage__37.first.isLoad; - UInt#(3) _Stage__37__threadID = fifo_Stage__0_TO_Stage__37.first._threadID; - Maybe#( SpecId#(4) ) _Stage__37__specId = fifo_Stage__0_TO_Stage__37.first._specId; - UInt#(1) _Stage__37___condStage__41 = ?; - Maybe#( _lidTyp_rf ) _Stage__37__lock_id_rf_rd_aq = ?; - Int#(32) _Stage__37_rddata = ?; - Maybe#( _lidTyp_rf ) _Stage__37__lock_id_rf_rd_op = ?; - UInt#(1) _Stage__37___condStage__45 = ?; - Int#(32) _Stage__37_sdividend = ?; - Int#(32) _Stage__37_sdivisor = ?; - Bool _Stage__37_isSignedDiv = ?; - UInt#(32) _Stage__37__tmp_12 = ?; - UInt#(32) _Stage__37__tmp_13 = ?; - UInt#(32) _Stage__37_dividend = ?; - UInt#(32) _Stage__37__tmp_14 = ?; - UInt#(32) _Stage__37__tmp_15 = ?; - UInt#(32) _Stage__37_divisor = ?; - Bool _Stage__37_retQuot = ?; - Bool _Stage__37_invertRes = ?; - UInt#(32) _Stage__37_carg_341 = ?; - UInt#(32) _Stage__37_carg_342 = ?; - UInt#(32) _Stage__37_carg_343 = ?; - UInt#(32) _Stage__37_carg_344 = ?; - UInt#(5) _Stage__37_carg_345 = ?; - Bool _Stage__37_carg_346 = ?; - UInt#(32) _Stage__37_udivout = ?; - UInt#(32) _Stage__37__tmp_16 = ?; - UInt#(32) _Stage__37_tmpaddr = ?; - UInt#(32) _Stage__37__tmp_17 = ?; - UInt#(16) _Stage__37_memaddr = ?; - UInt#(2) _Stage__37__tmp_18 = ?; - UInt#(2) _Stage__37_boff = ?; - UInt#(2) _Stage__37___condStage__50 = ?; - UInt#(16) _Stage__37_raddr = ?; - UInt#(16) _Stage__37_waddr = ?; - UInt#(5) _Stage__37_nboff = ?; - Int#(32) _Stage__37_msg_347 = ?; - Int#(32) _Stage__37_wdata = ?; - _Stage__37___condStage__41 = ( ( ( _Stage__37_writerd && ( ! _Stage__37_isLoad ) ) && ( ! _Stage__37_isDiv ) ) ? 1'd0 : 1'd1 ); - if ( ( _Stage__37___condStage__41 == 1'd0 )) - begin - _Stage__37__lock_id_rf_rd_aq = _Stage__37__lock_id_rf_rd_rs; - _Stage__37_rddata = ( _Stage__37_isLui ? _Stage__37_immU : ( _Stage__37_isMul ? _Stage__37_mulres : ( ( _Stage__37_isJal || _Stage__37_isJalr ) ? _Stage__37_linkpc : _Stage__37_alu_res ) ) ); - _Stage__37__lock_id_rf_rd_op = _Stage__37__lock_id_rf_rd_aq; - end - if ( ( _Stage__37___condStage__41 == 1'd1 )) - begin - _Stage__37_rddata = 32'd0; - end - _Stage__37___condStage__45 = ( _Stage__37_isDiv ? 1'd0 : 1'd1 ); - if ( ( _Stage__37___condStage__45 == 1'd0 )) - begin - _Stage__37_sdividend = signum(_Stage__37_rf1); - _Stage__37_sdivisor = ( ( _Stage__37_funct3 == 3'd6 ) ? 32'd1 : signum(_Stage__37_rf2) ); - _Stage__37_isSignedDiv = ( ( _Stage__37_funct3 == 3'd4 ) || ( _Stage__37_funct3 == 3'd6 ) ); - _Stage__37__tmp_12 = unpack( pack( abs(_Stage__37_rf1) ) ); - _Stage__37__tmp_13 = unpack( pack( _Stage__37_rf1 ) ); - _Stage__37_dividend = ( _Stage__37_isSignedDiv ? _Stage__37__tmp_12 : _Stage__37__tmp_13 ); - _Stage__37__tmp_14 = unpack( pack( abs(_Stage__37_rf2) ) ); - _Stage__37__tmp_15 = unpack( pack( _Stage__37_rf2 ) ); - _Stage__37_divisor = ( _Stage__37_isSignedDiv ? _Stage__37__tmp_14 : _Stage__37__tmp_15 ); - _Stage__37_retQuot = ( _Stage__37_funct3 <= 3'd5 ); - _Stage__37_invertRes = ( _Stage__37_isSignedDiv && ( _Stage__37_sdividend != _Stage__37_sdivisor ) ); - _Stage__37_carg_341 = _Stage__37_dividend; - _Stage__37_carg_342 = _Stage__37_divisor; - _Stage__37_carg_343 = 32'd0; - _Stage__37_carg_344 = 32'd0; - _Stage__37_carg_345 = 5'd0; - _Stage__37_carg_346 = _Stage__37_retQuot; - end - if ( ( _Stage__37___condStage__45 == 1'd1 )) - begin - _Stage__37_invertRes = False; - _Stage__37_udivout = 32'd0; - end - _Stage__37__tmp_16 = unpack( pack( _Stage__37_alu_res ) ); - _Stage__37_tmpaddr = _Stage__37__tmp_16; - _Stage__37__tmp_17 = ( _Stage__37_tmpaddr >> 2'd2 ); - _Stage__37_memaddr = unpack( pack( _Stage__37__tmp_17 ) [ 15 : 0 ] ); - _Stage__37__tmp_18 = unpack( pack( _Stage__37_alu_res ) [ 1 : 0 ] ); - _Stage__37_boff = _Stage__37__tmp_18; - _Stage__37___condStage__50 = ( _Stage__37_isLoad ? 2'd0 : ( _Stage__37_isStore ? 2'd1 : 2'd2 ) ); - if ( ( _Stage__37___condStage__50 == 2'd0 )) - begin - _Stage__37_raddr = _Stage__37_memaddr; - end - if ( ( _Stage__37___condStage__50 == 2'd1 )) - begin - _Stage__37_waddr = _Stage__37_memaddr; - _Stage__37_nboff = unpack( { pack( _Stage__37_boff ), pack( 3'd0 ) } ); - _Stage__37_msg_347 = ( _Stage__37_rf2 << _Stage__37_nboff ); - _Stage__37_wdata = 32'd0; - end - if ( ( _Stage__37___condStage__50 == 2'd2 )) - begin - _Stage__37_wdata = 32'd0; - end - UInt#(2) _Stage__51___condStage__50 = fifo_Stage__37_TO_Stage__51.first.__condStage__50; - Bool _Stage__51_writerd = fifo_Stage__37_TO_Stage__51.first.writerd; - MemId#(8) _Stage__51__request_3 = fifo_Stage__37_TO_Stage__51.first._request_3; - UInt#(2) _Stage__51_boff = fifo_Stage__37_TO_Stage__51.first.boff; - UInt#(1) _Stage__51___condStage__45 = fifo_Stage__37_TO_Stage__51.first.__condStage__45; - Int#(16) _Stage__51_pc = fifo_Stage__37_TO_Stage__51.first.pc; - MemId#(8) _Stage__51__request_4 = fifo_Stage__37_TO_Stage__51.first._request_4; - UInt#(3) _Stage__51_funct3 = fifo_Stage__37_TO_Stage__51.first.funct3; - Bool _Stage__51_invertRes = fifo_Stage__37_TO_Stage__51.first.invertRes; - Bool _Stage__51_done = fifo_Stage__37_TO_Stage__51.first.done; - UInt#(5) _Stage__51_rd = fifo_Stage__37_TO_Stage__51.first.rd; - Int#(32) _Stage__51_wdata = fifo_Stage__37_TO_Stage__51.first.wdata; - Int#(32) _Stage__51_rddata = fifo_Stage__37_TO_Stage__51.first.rddata; - Maybe#( _lidTyp_rf ) _Stage__51__lock_id_rf_rd_op = fifo_Stage__37_TO_Stage__51.first._lock_id_rf_rd_op; - Maybe#( _lidTyp_rf ) _Stage__51__lock_id_rf_rd_rs = fifo_Stage__37_TO_Stage__51.first._lock_id_rf_rd_rs; - UInt#(32) _Stage__51_udivout = fifo_Stage__37_TO_Stage__51.first.udivout; - Bool _Stage__51_isDiv = fifo_Stage__37_TO_Stage__51.first.isDiv; - Int#(32) _Stage__51_insn = fifo_Stage__37_TO_Stage__51.first.insn; - UInt#(1) _Stage__51__request_2 = fifo_Stage__37_TO_Stage__51.first._request_2; - Bool _Stage__51_isLoad = fifo_Stage__37_TO_Stage__51.first.isLoad; - UInt#(3) _Stage__51__threadID = fifo_Stage__37_TO_Stage__51.first._threadID; - Maybe#( SpecId#(4) ) _Stage__51__specId = fifo_Stage__37_TO_Stage__51.first._specId; - UInt#(1) _Stage__51___condStage__59 = ?; - Maybe#( _lidTyp_rf ) _Stage__51__lock_id_rf_rd_aq = ?; - UInt#(1) _Stage__51___condStage__56 = ?; - Int#(32) _Stage__51_insnout = ?; - Int#(32) _Stage__51__tmp_19 = ?; - Int#(32) _Stage__51__tmp_20 = ?; - Int#(32) _Stage__51_divout = ?; - UInt#(1) _Stage__51___condStage__63 = ?; - UInt#(1) _Stage__51___condStage__67 = ?; - if ( ( _Stage__51___condStage__45 == 1'd0 )) - begin - _Stage__51_udivout = div.peek; - end - if ( ( _Stage__51___condStage__50 == 2'd0 )) - begin - _Stage__51_wdata = dmem.peekResp1(_Stage__51__request_3); - end - _Stage__51___condStage__59 = ( ( _Stage__51_writerd && ( _Stage__51_isLoad || _Stage__51_isDiv ) ) ? 1'd0 : 1'd1 ); - if ( ( _Stage__51___condStage__59 == 1'd0 )) - begin - _Stage__51__lock_id_rf_rd_aq = _Stage__51__lock_id_rf_rd_rs; - _Stage__51___condStage__56 = ( _Stage__51_isLoad ? 1'd0 : 1'd1 ); - end - if ( ( ( _Stage__51___condStage__59 == 1'd0 ) && ( _Stage__51___condStage__56 == 1'd0 ) )) - begin - _Stage__51_insnout = maskLoad(_Stage__51_wdata, _Stage__51_funct3, _Stage__51_boff); - end - if ( ( ( _Stage__51___condStage__59 == 1'd0 ) && ( _Stage__51___condStage__56 == 1'd1 ) )) - begin - _Stage__51__tmp_19 = unpack( pack( _Stage__51_udivout ) ); - _Stage__51__tmp_20 = unpack( pack( _Stage__51_udivout ) ); - _Stage__51_divout = ( _Stage__51_invertRes ? ( - _Stage__51__tmp_19 ) : _Stage__51__tmp_20 ); - _Stage__51_insnout = _Stage__51_divout; - end - if ( ( _Stage__51___condStage__59 == 1'd0 )) - begin - _Stage__51__lock_id_rf_rd_op = _Stage__51__lock_id_rf_rd_aq; - end - if ( ( _Stage__51___condStage__59 == 1'd1 )) - begin - _Stage__51_insnout = _Stage__51_rddata; - end - _Stage__51___condStage__63 = ( _Stage__51_writerd ? 1'd0 : 1'd1 ); - _Stage__51___condStage__67 = ( _Stage__51_done ? 1'd0 : 1'd1 ); - rule s_Start_execute (( ( ! isValid( _Start__specId ) ) || fromMaybe( True , _specTable.check(fromMaybe( ? , _Start__specId ), 1) ) )); - SpecId#(4) _Start_s = ?; - MemId#(8) _Start__request_0 = ?; - _Start_s <- _specTable.alloc; - fifo__input__TO_Start.enq(E__input__TO_Start { pc : _Start__s_0,_threadID : _Start__threadID,_specId : tagged Valid _Start_s }); - _Start__request_0 <- imem.mem.req1(_Start_pcaddr, ?, 0); - fifo__input__TO_Start.deq; - fifo_Start_TO_Stage__0.enq(E_Start_TO_Stage__0 { pc : _Start_pc,_specId : _Start__specId,_request_0 : _Start__request_0,_threadID : _Start__threadID,s : _Start_s,_s_0 : _Start__s_0 }); - endrule - rule s_Start_kill (( isValid( _Start__specId ) && ( ! fromMaybe( True , _specTable.check(fromMaybe( ? , _Start__specId ), 1) ) ) )); - fifo__input__TO_Start.deq; - _specTable.free(fromMaybe( ? , _Start__specId )); - endrule - rule s_Stage__0_execute (( ( ! isValid( _Stage__0__specId ) ) || fromMaybe( False , _specTable.check(fromMaybe( ? , _Stage__0__specId ), 0) ) ) && ( ( ! ( _Stage__0___condStage__8 == 1'd0 ) ) || rf.canAtom_r1(_Stage__0_rs1) ) && ( ( ! ( _Stage__0___condStage__12 == 1'd0 ) ) || rf.canAtom_r2(_Stage__0_rs2) ) && ( ( ! ( _Stage__0___condStage__16 == 1'd0 ) ) || rf.canRes_w1(_Stage__0_rd) ) && imem.mem.checkRespId1(_Stage__0__request_0)); - Maybe#( _lidTyp_rf ) _Stage__0__lock_id_rf_rd_rs = tagged Invalid; - imem.mem.resp1(_Stage__0__request_0); - if ( isValid( _Stage__0__specId )) - begin - _specTable.free(fromMaybe( ? , _Stage__0__specId )); - end - if ( ( _Stage__0___condStage__4 == 1'd0 )) - begin - if ( ( True && ( ( _Stage__0_pc + 16'd1 ) == _Stage__0__s_0 ) )) - begin - _specTable.validate(_Stage__0_s, 0); - end - else - begin - _specTable.invalidate(_Stage__0_s, 0); - fifo__input__TO_Start.enq(E__input__TO_Start { pc : ( _Stage__0_pc + 16'd1 ),_threadID : _Stage__0__threadID,_specId : tagged Invalid }); - end - end - if ( ( _Stage__0___condStage__4 == 1'd1 )) - begin - _specTable.invalidate(_Stage__0_s, 0); - end - if ( ( _Stage__0___condStage__16 == 1'd0 )) - begin - let __tmp_0 <- rf.res_w1(_Stage__0_rd); - _Stage__0__lock_id_rf_rd_rs = tagged Valid __tmp_0; - end - if ( ( ( _Stage__0___condStage__36 == 1'd0 ) && ( _Stage__0___condStage__33 == 1'd0 ) )) - begin - fifo__input__TO_Start.enq(E__input__TO_Start { pc : _Stage__0_carg_340,_threadID : _Stage__0__threadID,_specId : tagged Invalid }); - end - fifo_Start_TO_Stage__0.deq; - fifo_Stage__0_TO_Stage__37.enq(E_Stage__0_TO_Stage__37 { pc : _Stage__0_pc,alu_res : _Stage__0_alu_res,isLoad : _Stage__0_isLoad,isStore : _Stage__0_isStore,_specId : _Stage__0__specId,linkpc : _Stage__0_linkpc,isDiv : _Stage__0_isDiv,_lock_id_rf_rd_rs : _Stage__0__lock_id_rf_rd_rs,done : _Stage__0_done,writerd : _Stage__0_writerd,isJalr : _Stage__0_isJalr,immU : _Stage__0_immU,rd : _Stage__0_rd,rf1 : _Stage__0_rf1,isLui : _Stage__0_isLui,insn : _Stage__0_insn,isMul : _Stage__0_isMul,rf2 : _Stage__0_rf2,_threadID : _Stage__0__threadID,mulres : _Stage__0_mulres,isJal : _Stage__0_isJal,funct3 : _Stage__0_funct3 }); - endrule - rule s_Stage__0_kill (( isValid( _Stage__0__specId ) && ( ! fromMaybe( True , _specTable.check(fromMaybe( ? , _Stage__0__specId ), 0) ) ) ) && imem.mem.checkRespId1(_Stage__0__request_0)); - fifo_Start_TO_Stage__0.deq; - imem.mem.resp1(_Stage__0__request_0); - _specTable.free(fromMaybe( ? , _Stage__0__specId )); - endrule - rule s_Stage__37_execute (( ( ! ( _Stage__37___condStage__41 == 1'd0 ) ) || rf.owns_w1(fromMaybe( ? , _Stage__37__lock_id_rf_rd_rs )) )); - UInt#(1) _Stage__37__request_2 = ?; - MemId#(8) _Stage__37__request_3 = ?; - MemId#(8) _Stage__37__request_4 = ?; - if ( ( _Stage__37___condStage__41 == 1'd0 )) - begin - rf.write(fromMaybe( ? , _Stage__37__lock_id_rf_rd_aq ), _Stage__37_rddata); - end - if ( ( _Stage__37___condStage__45 == 1'd0 )) - begin - _Stage__37__request_2 <- div.req(_Stage__37_carg_341, _Stage__37_carg_342, _Stage__37_carg_343, _Stage__37_carg_344, _Stage__37_carg_345, _Stage__37_carg_346); - end - if ( ( _Stage__37___condStage__50 == 2'd0 )) - begin - _Stage__37__request_3 <- dmem.req1(_Stage__37_raddr, ?, 0); - end - if ( ( _Stage__37___condStage__50 == 2'd1 )) - begin - _Stage__37__request_4 <- dmem.req1(_Stage__37_waddr, _Stage__37_msg_347, pack( storeMask(_Stage__37_boff, _Stage__37_funct3) )); - end - fifo_Stage__0_TO_Stage__37.deq; - fifo_Stage__37_TO_Stage__51.enq(E_Stage__37_TO_Stage__51 { insn : _Stage__37_insn,rddata : _Stage__37_rddata,writerd : _Stage__37_writerd,_lock_id_rf_rd_rs : _Stage__37__lock_id_rf_rd_rs,isLoad : _Stage__37_isLoad,done : _Stage__37_done,_specId : _Stage__37__specId,_request_3 : _Stage__37__request_3,__condStage__50 : _Stage__37___condStage__50,rd : _Stage__37_rd,__condStage__45 : _Stage__37___condStage__45,isDiv : _Stage__37_isDiv,_lock_id_rf_rd_op : _Stage__37__lock_id_rf_rd_op,_threadID : _Stage__37__threadID,_request_2 : _Stage__37__request_2,_request_4 : _Stage__37__request_4,boff : _Stage__37_boff,funct3 : _Stage__37_funct3,pc : _Stage__37_pc,udivout : _Stage__37_udivout,invertRes : _Stage__37_invertRes,wdata : _Stage__37_wdata }); - endrule - rule s_Stage__51_execute (( ( ! ( _Stage__51___condStage__59 == 1'd0 ) ) || rf.owns_w1(fromMaybe( ? , _Stage__51__lock_id_rf_rd_rs )) ) && ( ( ! ( _Stage__51___condStage__67 == 1'd0 ) ) || outputQueue.canWrite(_Stage__51__threadID) ) && ( ( ! ( _Stage__51___condStage__45 == 1'd0 ) ) || div.checkHandle(_Stage__51__request_2) ) && ( ( ! ( _Stage__51___condStage__50 == 2'd1 ) ) || dmem.checkRespId1(_Stage__51__request_4) ) && ( ( ! ( _Stage__51___condStage__50 == 2'd0 ) ) || dmem.checkRespId1(_Stage__51__request_3) )); - if ( ( _Stage__51___condStage__45 == 1'd0 )) - begin - div.resp; - end - if ( ( _Stage__51___condStage__50 == 2'd1 )) - begin - dmem.resp1(_Stage__51__request_4); - end - if ( ( _Stage__51___condStage__50 == 2'd0 )) - begin - dmem.resp1(_Stage__51__request_3); - end - $display( "PC: %h",( _Stage__51_pc << 2'd2 ) ); - $display( "INSN: %h",_Stage__51_insn ); - if ( ( _Stage__51___condStage__59 == 1'd0 )) - begin - rf.write(fromMaybe( ? , _Stage__51__lock_id_rf_rd_aq ), _Stage__51_insnout); - end - if ( ( _Stage__51___condStage__63 == 1'd0 )) - begin - $display( "Writing %d to r%d",_Stage__51_insnout,_Stage__51_rd ); - rf.rel_w1(fromMaybe( ? , _Stage__51__lock_id_rf_rd_op )); - end - if ( ( _Stage__51___condStage__67 == 1'd0 )) - begin - busyReg <= False; - outputQueue.enq(True); - end - fifo_Stage__37_TO_Stage__51.deq; - endrule - method ActionValue#(UInt#(3)) req ( Int#(16) pc ) if( ( ! busyReg ) ); - fifo__input__TO_Start.enq(E__input__TO_Start { pc : pc,_threadID : _threadID,_specId : tagged Invalid }); - busyReg <= True; - _threadID <= ( _threadID + 1 ); - return _threadID; - endmethod - method Action resp ( ) ; - outputQueue.deq; - endmethod - method Bool peek ( ) ; - return outputQueue.first; - endmethod - method Bool checkHandle ( UInt#(3) handle ) ; - return outputQueue.canRead(handle); - endmethod -endmodule diff --git a/src/test/tests/risc-pipe/Functions.bsv b/src/test/tests/risc-pipe/Functions.bsv deleted file mode 100644 index 55e6a5de..00000000 --- a/src/test/tests/risc-pipe/Functions.bsv +++ /dev/null @@ -1,221 +0,0 @@ -export alu ; -function Int#(32) alu ( Int#(32) arg1, Int#(32) arg2, UInt#(3) op, Bool flip ) ; - UInt#(5) _tmp_22 = unpack( pack( arg2 ) [ 4 : 0 ] ); - UInt#(5) shamt = _tmp_22; - if ( ( op == 3'd0 )) - begin - if ( ( ! flip )) - begin - return ( arg1 + arg2 ); - end - else - begin - return ( arg1 - arg2 ); - end - end - else - begin - if ( ( op == 3'd1 )) - begin - return ( arg1 << shamt ); - end - else - begin - if ( ( op == 3'd2 )) - begin - return ( ( arg1 < arg2 ) ? 32'd1 : 32'd0 ); - end - else - begin - if ( ( op == 3'd3 )) - begin - UInt#(32) _tmp_23 = unpack( pack( arg1 ) ); - UInt#(32) un1 = _tmp_23; - UInt#(32) _tmp_24 = unpack( pack( arg2 ) ); - UInt#(32) un2 = _tmp_24; - return ( ( un1 < un2 ) ? 32'd1 : 32'd0 ); - end - else - begin - if ( ( op == 3'd4 )) - begin - return ( arg1 ^ arg2 ); - end - else - begin - if ( ( op == 3'd5 )) - begin - if ( ( ! flip )) - begin - UInt#(32) _tmp_25 = unpack( pack( arg1 ) ); - Int#(32) _tmp_26 = unpack( pack( ( _tmp_25 >> shamt ) ) ); - return _tmp_26; - end - else - begin - return ( arg1 >> shamt ); - end - end - else - begin - if ( ( op == 3'd6 )) - begin - return ( arg1 | arg2 ); - end - else - begin - return ( arg1 & arg2 ); - end - end - end - end - end - end - end -endfunction -export maskLoad ; -function Int#(32) maskLoad ( Int#(32) data, UInt#(3) op, UInt#(2) start ) ; - UInt#(5) boff = unpack( { pack( start ), pack( 3'd0 ) } ); - Int#(32) tmp = ( data >> boff ); - UInt#(8) _tmp_29 = unpack( pack( truncate( tmp ) ) ); - UInt#(8) bdata = _tmp_29; - UInt#(16) _tmp_30 = unpack( pack( truncate( tmp ) ) ); - UInt#(16) hdata = _tmp_30; - if ( ( op == 3'd0 )) - begin - Int#(32) _tmp_31 = unpack( pack( signExtend( bdata ) ) ); - return _tmp_31; - end - else - begin - if ( ( op == 3'd1 )) - begin - Int#(32) _tmp_32 = unpack( pack( signExtend( hdata ) ) ); - return _tmp_32; - end - else - begin - if ( ( op == 3'd2 )) - begin - return data; - end - else - begin - if ( ( op == 3'd4 )) - begin - UInt#(32) _tmp_33 = zeroExtend( bdata ); - UInt#(32) zext = _tmp_33; - Int#(32) _tmp_34 = unpack( pack( zext ) ); - return _tmp_34; - end - else - begin - if ( ( op == 3'd5 )) - begin - UInt#(32) _tmp_35 = zeroExtend( hdata ); - UInt#(32) zext = _tmp_35; - Int#(32) _tmp_36 = unpack( pack( zext ) ); - return _tmp_36; - end - else - begin - return 32'd0; - end - end - end - end - end -endfunction -export br ; -function Bool br ( UInt#(3) op, Int#(32) arg1, Int#(32) arg2 ) ; - if ( ( op == 3'd0 )) - begin - return ( arg1 == arg2 ); - end - else - begin - if ( ( op == 3'd1 )) - begin - return ( arg1 != arg2 ); - end - else - begin - if ( ( op == 3'd4 )) - begin - return ( arg1 < arg2 ); - end - else - begin - if ( ( op == 3'd5 )) - begin - return ( arg1 >= arg2 ); - end - else - begin - if ( ( op == 3'd6 )) - begin - UInt#(32) _tmp_26 = unpack( pack( arg1 ) ); - UInt#(32) un1 = _tmp_26; - UInt#(32) _tmp_27 = unpack( pack( arg2 ) ); - UInt#(32) un2 = _tmp_27; - return ( un1 < un2 ); - end - else - begin - if ( ( op == 3'd7 )) - begin - UInt#(32) _tmp_28 = unpack( pack( arg1 ) ); - UInt#(32) un1 = _tmp_28; - UInt#(32) _tmp_29 = unpack( pack( arg2 ) ); - UInt#(32) un2 = _tmp_29; - return ( un1 >= un2 ); - end - else - begin - return False; - end - end - end - end - end - end -endfunction -export mul ; -function Int#(32) mul ( Int#(32) arg1, Int#(32) arg2, UInt#(3) op ) ; - UInt#(32) _tmp_20 = unpack( pack( abs(arg1) ) ); - UInt#(32) mag1 = _tmp_20; - UInt#(32) _tmp_21 = unpack( pack( abs(arg2) ) ); - UInt#(32) mag2 = _tmp_21; - Int#(32) s1 = ( ( op == 3'd3 ) ? 32'd1 : signum(arg1) ); - Int#(32) s2 = ( ( op >= 3'd2 ) ? 32'd1 : signum(arg2) ); - Int#(64) _tmp_22 = unpack( pack( unsignedMul( mag1 , mag2 ) ) ); - Int#(64) magRes = _tmp_22; - Int#(64) m = ( ( s1 == s2 ) ? magRes : ( - magRes ) ); - if ( ( op == 3'd0 )) - begin - return unpack( pack( m ) [ 31 : 0 ] ); - end - else - begin - return unpack( pack( m ) [ 63 : 32 ] ); - end -endfunction -export storeMask ; -function UInt#(4) storeMask ( UInt#(2) off, UInt#(3) op ) ; - if ( ( op == 3'd0 )) - begin - return ( 4'b1 << off ); - end - else - begin - if ( ( op == 3'd1 )) - begin - UInt#(2) shamt = unpack( { pack( off ) [ 1 : 1 ], pack( 1'd0 ) } ); - return ( 4'b11 << shamt ); - end - else - begin - return 4'b1111; - end - end -endfunction diff --git a/src/test/tests/risc-pipe/Multi_stg_div.bsv b/src/test/tests/risc-pipe/Multi_stg_div.bsv deleted file mode 100644 index 0364037b..00000000 --- a/src/test/tests/risc-pipe/Multi_stg_div.bsv +++ /dev/null @@ -1,93 +0,0 @@ -import FIFOF :: *; -import SpecialFIFOs :: *; -import SpecialQueues :: *; -import Locks :: *; -import Memories :: *; -import VerilogLibs :: *; -import Speculation :: *; -import RegFile :: *; -import Functions :: *; - -export Multi_stg_div (..); -export mkMulti_stg_div ; - -typedef struct { UInt#(32) num; UInt#(32) denom; UInt#(32) quot; UInt#(32) acc; UInt#(5) cnt; Bool retQuot; UInt#(1) _threadID ; } E__input__TO_Start deriving( Bits,Eq ); - -interface Multi_stg_div; - method ActionValue#(UInt#(1)) req ( UInt#(32) num, UInt#(32) denom, UInt#(32) quot, UInt#(32) acc, UInt#(5) cnt, Bool retQuot ) ; - method Action resp ( ) ; - method Bool checkHandle ( UInt#(1) handle ) ; - method UInt#(32) peek ( ) ; -endinterface - - -(* synthesize *) -module mkMulti_stg_div ( Multi_stg_div _unused_ ) provisos( ); - FIFOF#( E__input__TO_Start ) fifo__input__TO_Start <- mkNBFIFOF ( ); - Reg#( Bool ) busyReg <- mkReg ( False ); - OutputQ#( UInt#(1), UInt#(32) ) outputQueue <- mkOutputFIFOF ( 0 ); - Reg#( UInt#(1) ) _threadID <- mkReg ( 0 ); - UInt#(32) _Start_quot = fifo__input__TO_Start.first.quot; - UInt#(5) _Start_cnt = fifo__input__TO_Start.first.cnt; - Bool _Start_retQuot = fifo__input__TO_Start.first.retQuot; - UInt#(32) _Start_acc = fifo__input__TO_Start.first.acc; - UInt#(32) _Start_num = fifo__input__TO_Start.first.num; - UInt#(32) _Start_denom = fifo__input__TO_Start.first.denom; - UInt#(1) _Start__threadID = fifo__input__TO_Start.first._threadID; - UInt#(32) _Start_tmp = ?; - UInt#(32) _Start_na = ?; - UInt#(32) _Start__tmp_0 = ?; - UInt#(32) _Start_nq = ?; - UInt#(32) _Start_nnum = ?; - Bool _Start_done = ?; - UInt#(1) _Start___condStage__3 = ?; - UInt#(32) _Start_carg_334 = ?; - UInt#(32) _Start_carg_335 = ?; - UInt#(32) _Start_carg_336 = ?; - UInt#(32) _Start_carg_337 = ?; - UInt#(5) _Start_carg_338 = ?; - Bool _Start_carg_339 = ?; - _Start_tmp = unpack( { pack( _Start_acc ) [ 30 : 0 ], pack( _Start_num ) [ 31 : 31 ] } ); - _Start_na = ( ( _Start_tmp >= _Start_denom ) ? ( _Start_tmp - _Start_denom ) : _Start_tmp ); - _Start__tmp_0 = ( _Start_quot << 1'd1 ); - _Start_nq = ( ( _Start_tmp >= _Start_denom ) ? unpack( { pack( _Start__tmp_0 ) [ 31 : 1 ], pack( 1'd1 ) } ) : ( _Start_quot << 1'd1 ) ); - _Start_nnum = ( _Start_num << 1'd1 ); - _Start_done = ( _Start_cnt == 5'd31 ); - _Start___condStage__3 = ( _Start_done ? 1'd0 : 1'd1 ); - if ( ( _Start___condStage__3 == 1'd1 )) - begin - _Start_carg_334 = _Start_nnum; - _Start_carg_335 = _Start_denom; - _Start_carg_336 = _Start_nq; - _Start_carg_337 = _Start_na; - _Start_carg_338 = ( _Start_cnt + 5'd1 ); - _Start_carg_339 = _Start_retQuot; - end - rule s_Start_execute (( ( ! ( _Start___condStage__3 == 1'd0 ) ) || outputQueue.canWrite(_Start__threadID) )); - if ( ( _Start___condStage__3 == 1'd0 )) - begin - busyReg <= False; - outputQueue.enq(( _Start_retQuot ? _Start_nq : _Start_na )); - end - if ( ( _Start___condStage__3 == 1'd1 )) - begin - fifo__input__TO_Start.enq(E__input__TO_Start { denom : _Start_carg_335,quot : _Start_carg_336,acc : _Start_carg_337,retQuot : _Start_carg_339,_threadID : _Start__threadID,num : _Start_carg_334,cnt : _Start_carg_338 }); - end - fifo__input__TO_Start.deq; - endrule - method ActionValue#(UInt#(1)) req ( UInt#(32) num, UInt#(32) denom, UInt#(32) quot, UInt#(32) acc, UInt#(5) cnt, Bool retQuot ) if( ( ! busyReg ) ); - fifo__input__TO_Start.enq(E__input__TO_Start { num : num,acc : acc,quot : quot,_threadID : _threadID,denom : denom,retQuot : retQuot,cnt : cnt }); - busyReg <= True; - _threadID <= ( _threadID + 1 ); - return _threadID; - endmethod - method Action resp ( ) ; - outputQueue.deq; - endmethod - method UInt#(32) peek ( ) ; - return outputQueue.first; - endmethod - method Bool checkHandle ( UInt#(1) handle ) ; - return outputQueue.canRead(handle); - endmethod -endmodule diff --git a/src/test/tests/risc-pipe/cmem b/src/test/tests/risc-pipe/cmem deleted file mode 100644 index e4f73979..00000000 --- a/src/test/tests/risc-pipe/cmem +++ /dev/null @@ -1,256 +0,0 @@ -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 diff --git a/src/test/tests/risc-pipe/mm4 b/src/test/tests/risc-pipe/mm4 deleted file mode 100644 index e69de29b..00000000 diff --git a/src/test/tests/risc-pipe/rf b/src/test/tests/risc-pipe/rf deleted file mode 100644 index a546baf6..00000000 --- a/src/test/tests/risc-pipe/rf +++ /dev/null @@ -1,32 +0,0 @@ -0 -0 -400 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 \ No newline at end of file diff --git a/src/test/tests/risc-pipe/td4 b/src/test/tests/risc-pipe/td4 deleted file mode 100644 index e69de29b..00000000 diff --git a/src/test/tests/risc-pipe/ti4 b/src/test/tests/risc-pipe/ti4 deleted file mode 100644 index 6d0c3b09..00000000 --- a/src/test/tests/risc-pipe/ti4 +++ /dev/null @@ -1,15 +0,0 @@ -010000ef -0000006f -00000000 -00000000 -ff010113 -fb500793 -00f12623 -01700793 -00f12423 -00c12703 -00812783 -02f757b3 -00078513 -01010113 -00008067 diff --git a/src/test/tests/speculation/Circuit.bsv b/src/test/tests/speculation/Circuit.bsv deleted file mode 100644 index 97036735..00000000 --- a/src/test/tests/speculation/Circuit.bsv +++ /dev/null @@ -1,48 +0,0 @@ -import ClientServer :: *; -import Connectable :: *; -import Locks :: *; -import Memories :: *; -import VerilogLibs :: *; -import RegFile :: *; -import BRAMCore :: *; -import Testwrite :: *; -import Functions :: *; - - - -interface TopMod; - interface Client#( Tuple3#( Bit#(4), UInt#(8), Int#(32) ), Int#(32) ) _intti; - interface Testwrite _intt; -endinterface - -(* synthesize *) -module mkTB ( Empty _unused_ ) provisos( ); - Reg#( Bool ) started <- mkReg ( False ); - Reg#( UInt#(32) ) timer <- mkReg ( 0 ); - TopMod _topMod <- mkCircuit ( ); - BramPort#( UInt#(8), Int#(32), MemId#(8), 4 ) ti <- mkBramPort ( True, "ti" ); - Reg#( UInt#(3) ) reg_unused_0 <- mkReg ( 0 ); - mkConnection(_topMod._intti, ti.bram_server); - rule initTB (( ! started )); - UInt#(3) _unused_0 = ?; - _unused_0 <- _topMod._intt.req(8'd0); - reg_unused_0 <= _unused_0; - started <= True; - endrule - rule timerCount ; - timer <= ( timer + 1 ); - endrule - rule stopTB (( ( timer >= 32'd1000000 ) || _topMod._intt.checkHandle(reg_unused_0) )); - $finish(); - endrule -endmodule - -(* synthesize *) -module mkCircuit ( TopMod _unused_ ) provisos( ); - AsyncMem#( UInt#(8), Int#(32), MemId#(8), 4 ) ti <- mkAsyncMem ( ); - RegFile#( UInt#(5), Int#(32) ) rename <- mkRegFile ( True, "rename" ); - CheckpointQueueLockCombMem#( UInt#(5), Int#(32), LockId#(4), LockId#(4) ) qrf <- mkCheckpointQueueLockCombMem ( rename ); - Testwrite t <- mkTestwrite ( qrf, ti ); - interface Client _intti = ti.bram_client; - interface Testwrite _intt = t; -endmodule diff --git a/src/test/tests/speculation/Functions.bsv b/src/test/tests/speculation/Functions.bsv deleted file mode 100644 index e69de29b..00000000 diff --git a/src/test/tests/speculation/Testwrite.bsv b/src/test/tests/speculation/Testwrite.bsv deleted file mode 100644 index 335d0caa..00000000 --- a/src/test/tests/speculation/Testwrite.bsv +++ /dev/null @@ -1,309 +0,0 @@ -import FIFOF :: *; -import SpecialFIFOs :: *; -import SpecialQueues :: *; -import Locks :: *; -import Memories :: *; -import VerilogLibs :: *; -import Speculation :: *; -import RegFile :: *; -import Functions :: *; - -export Testwrite (..); -export mkTestwrite ; - -typedef struct { Int#(8) pc; UInt#(3) _threadID; Maybe#( SpecId#(4) ) _specId ; } E__input__TO_Start deriving( Bits,Eq ); -typedef struct { Int#(1) op; Int#(8) _s_0; SpecId#(4) s; Int#(8) brImm; Int#(8) pc; Int#(32) a1; Bool done; UInt#(5) rd; Int#(32) a2; chk_lidTyp_rf _checkpoint_rf; Int#(32) out; Maybe#( _lidTyp_rf ) _lock_id_rf_rd_op; UInt#(3) _threadID; Maybe#( SpecId#(4) ) _specId ; } E_Stage__9_TO_Stage__18#( type chk_lidTyp_rf,type _lidTyp_rf ) deriving( Bits,Eq ); -typedef struct { MemId#(8) _request_0; Int#(8) _s_0; SpecId#(4) s; Int#(8) pc; UInt#(3) _threadID; Maybe#( SpecId#(4) ) _specId ; } E_Start_TO_Stage__0 deriving( Bits,Eq ); -typedef struct { Int#(1) op; Int#(8) npc; Bool done; UInt#(5) rd; Int#(32) out; Maybe#( _lidTyp_rf ) _lock_id_rf_rd_op; UInt#(3) _threadID; Maybe#( SpecId#(4) ) _specId ; } E_Stage__19_TO_Stage__28#( type _lidTyp_rf ) deriving( Bits,Eq ); -typedef struct { Int#(1) op; Int#(8) _s_0; SpecId#(4) s; Maybe#( _lidTyp_rf ) _lock_id_rf_rd_rs; Int#(8) brImm; Int#(8) pc; Int#(32) a1; Bool done; UInt#(5) rd; Int#(32) a2; chk_lidTyp_rf _checkpoint_rf; UInt#(3) _threadID; Maybe#( SpecId#(4) ) _specId ; } E_Stage__0_TO_Stage__9#( type _lidTyp_rf,type chk_lidTyp_rf ) deriving( Bits,Eq ); -typedef struct { Bool done; UInt#(3) _threadID; Maybe#( SpecId#(4) ) _specId ; } E_Stage__28_TO_Stage__37 deriving( Bits,Eq ); -typedef struct { Int#(1) op; Int#(8) _s_0; SpecId#(4) s; Int#(8) brImm; Int#(8) pc; Int#(32) a1; Bool done; UInt#(5) rd; Int#(32) a2; chk_lidTyp_rf _checkpoint_rf; Int#(32) out; Maybe#( _lidTyp_rf ) _lock_id_rf_rd_op; UInt#(3) _threadID; Maybe#( SpecId#(4) ) _specId ; } E_Stage__18_TO_Stage__19#( type chk_lidTyp_rf,type _lidTyp_rf ) deriving( Bits,Eq ); - -interface Testwrite; - method ActionValue#(UInt#(3)) req ( Int#(8) pc ) ; - method Action resp ( ) ; - method Bool checkHandle ( UInt#(3) handle ) ; - method Bool peek ( ) ; -endinterface - - -module mkTestwrite ( CheckpointQueueLockCombMem#( UInt#(5), Int#(32), _lidTyp_rf, chk_lidTyp_rf ) rf, AsyncMem#( UInt#(8), Int#(32), MemId#(8), 4 ) imem, Testwrite _unused_ ) provisos( Bits#(_lidTyp_rf,_sz_lidTyp_rf),Bits#(chk_lidTyp_rf,chk_sz_lidTyp_rf) ); - FIFOF#( E__input__TO_Start ) fifo__input__TO_Start <- mkNBFIFOF ( ); - FIFOF#( E_Stage__9_TO_Stage__18#(chk_lidTyp_rf, _lidTyp_rf) ) fifo_Stage__9_TO_Stage__18 <- mkFIFOF ( ); - FIFOF#( E_Start_TO_Stage__0 ) fifo_Start_TO_Stage__0 <- mkFIFOF ( ); - FIFOF#( E_Stage__19_TO_Stage__28#(_lidTyp_rf) ) fifo_Stage__19_TO_Stage__28 <- mkFIFOF ( ); - FIFOF#( E_Stage__0_TO_Stage__9#(_lidTyp_rf, chk_lidTyp_rf) ) fifo_Stage__0_TO_Stage__9 <- mkFIFOF ( ); - FIFOF#( E_Stage__28_TO_Stage__37 ) fifo_Stage__28_TO_Stage__37 <- mkFIFOF ( ); - FIFOF#( E_Stage__18_TO_Stage__19#(chk_lidTyp_rf, _lidTyp_rf) ) fifo_Stage__18_TO_Stage__19 <- mkFIFOF ( ); - Reg#( Bool ) rf_lock_region <- mkReg ( True ); - Reg#( Bool ) imem_lock_region <- mkReg ( True ); - Reg#( Bool ) busyReg <- mkReg ( False ); - SpecTable#( SpecId#(4), 4 ) _specTable <- mkSpecTable ( ); - OutputQ#( UInt#(3), Bool ) outputQueue <- mkOutputFIFOF ( 0 ); - Reg#( UInt#(3) ) _threadID <- mkReg ( 0 ); - Int#(1) _Stage__19_op = fifo_Stage__18_TO_Stage__19.first.op; - Int#(8) _Stage__19__s_0 = fifo_Stage__18_TO_Stage__19.first._s_0; - SpecId#(4) _Stage__19_s = fifo_Stage__18_TO_Stage__19.first.s; - Int#(8) _Stage__19_brImm = fifo_Stage__18_TO_Stage__19.first.brImm; - Int#(8) _Stage__19_pc = fifo_Stage__18_TO_Stage__19.first.pc; - Int#(32) _Stage__19_a1 = fifo_Stage__18_TO_Stage__19.first.a1; - Bool _Stage__19_done = fifo_Stage__18_TO_Stage__19.first.done; - UInt#(5) _Stage__19_rd = fifo_Stage__18_TO_Stage__19.first.rd; - Int#(32) _Stage__19_a2 = fifo_Stage__18_TO_Stage__19.first.a2; - chk_lidTyp_rf _Stage__19__checkpoint_rf = fifo_Stage__18_TO_Stage__19.first._checkpoint_rf; - Int#(32) _Stage__19_out = fifo_Stage__18_TO_Stage__19.first.out; - Maybe#( _lidTyp_rf ) _Stage__19__lock_id_rf_rd_op = fifo_Stage__18_TO_Stage__19.first._lock_id_rf_rd_op; - UInt#(3) _Stage__19__threadID = fifo_Stage__18_TO_Stage__19.first._threadID; - Maybe#( SpecId#(4) ) _Stage__19__specId = fifo_Stage__18_TO_Stage__19.first._specId; - Int#(8) _Stage__19_npc = ?; - UInt#(1) _Stage__19___condStage__27 = ?; - UInt#(1) _Stage__19___condStage__24 = ?; - _Stage__19_npc = ( ( _Stage__19_a1 == _Stage__19_a2 ) ? ( _Stage__19_pc + _Stage__19_brImm ) : ( _Stage__19_pc + 8'd1 ) ); - _Stage__19___condStage__27 = ( ( ! _Stage__19_done ) ? 1'd0 : 1'd1 ); - if ( ( _Stage__19___condStage__27 == 1'd0 )) - begin - _Stage__19___condStage__24 = ( ( _Stage__19_op != 1'd0 ) ? 1'd0 : 1'd1 ); - end - MemId#(8) _Stage__0__request_0 = fifo_Start_TO_Stage__0.first._request_0; - Int#(8) _Stage__0__s_0 = fifo_Start_TO_Stage__0.first._s_0; - SpecId#(4) _Stage__0_s = fifo_Start_TO_Stage__0.first.s; - Int#(8) _Stage__0_pc = fifo_Start_TO_Stage__0.first.pc; - UInt#(3) _Stage__0__threadID = fifo_Start_TO_Stage__0.first._threadID; - Maybe#( SpecId#(4) ) _Stage__0__specId = fifo_Start_TO_Stage__0.first._specId; - Int#(32) _Stage__0_insn = ?; - Bool _Stage__0_done = ?; - Int#(1) _Stage__0_op = ?; - Int#(8) _Stage__0_brImm = ?; - UInt#(5) _Stage__0__tmp_1 = ?; - UInt#(5) _Stage__0_rs1 = ?; - UInt#(5) _Stage__0__tmp_2 = ?; - UInt#(5) _Stage__0_rs2 = ?; - UInt#(5) _Stage__0__tmp_3 = ?; - UInt#(5) _Stage__0_rd = ?; - UInt#(1) _Stage__0___condStage__8 = ?; - Int#(32) _Stage__0_a1 = ?; - Int#(32) _Stage__0_a2 = ?; - UInt#(1) _Stage__0___condStage__5 = ?; - _Stage__0_insn = imem.peekResp1(_Stage__0__request_0); - _Stage__0_done = ( unpack( pack( _Stage__0_insn ) [ 31 : 31 ] ) == 1'd1 ); - _Stage__0_op = unpack( pack( _Stage__0_insn ) [ 0 : 0 ] ); - _Stage__0_brImm = unpack( { pack( 4'd0 ), pack( _Stage__0_insn ) [ 4 : 1 ] } ); - _Stage__0__tmp_1 = unpack( pack( _Stage__0_insn ) [ 9 : 5 ] ); - _Stage__0_rs1 = _Stage__0__tmp_1; - _Stage__0__tmp_2 = unpack( pack( _Stage__0_insn ) [ 14 : 10 ] ); - _Stage__0_rs2 = _Stage__0__tmp_2; - _Stage__0__tmp_3 = unpack( pack( _Stage__0_insn ) [ 19 : 15 ] ); - _Stage__0_rd = _Stage__0__tmp_3; - _Stage__0___condStage__8 = ( ( ! _Stage__0_done ) ? 1'd0 : 1'd1 ); - if ( ( _Stage__0___condStage__8 == 1'd0 )) - begin - _Stage__0_a1 = rf.atom_r(_Stage__0_rs1); - _Stage__0_a2 = rf.atom_r(_Stage__0_rs2); - _Stage__0___condStage__5 = ( ( _Stage__0_op == 1'd0 ) ? 1'd0 : 1'd1 ); - end - if ( ( _Stage__0___condStage__8 == 1'd1 )) - begin - _Stage__0_a1 = 32'd0; - _Stage__0_a2 = 32'd0; - end - Int#(1) _Stage__28_op = fifo_Stage__19_TO_Stage__28.first.op; - Int#(8) _Stage__28_npc = fifo_Stage__19_TO_Stage__28.first.npc; - Bool _Stage__28_done = fifo_Stage__19_TO_Stage__28.first.done; - UInt#(5) _Stage__28_rd = fifo_Stage__19_TO_Stage__28.first.rd; - Int#(32) _Stage__28_out = fifo_Stage__19_TO_Stage__28.first.out; - Maybe#( _lidTyp_rf ) _Stage__28__lock_id_rf_rd_op = fifo_Stage__19_TO_Stage__28.first._lock_id_rf_rd_op; - UInt#(3) _Stage__28__threadID = fifo_Stage__19_TO_Stage__28.first._threadID; - Maybe#( SpecId#(4) ) _Stage__28__specId = fifo_Stage__19_TO_Stage__28.first._specId; - UInt#(1) _Stage__28___condStage__36 = ?; - UInt#(1) _Stage__28___condStage__33 = ?; - _Stage__28___condStage__36 = ( ( ! _Stage__28_done ) ? 1'd0 : 1'd1 ); - if ( ( _Stage__28___condStage__36 == 1'd0 )) - begin - _Stage__28___condStage__33 = ( ( _Stage__28_op == 1'd0 ) ? 1'd0 : 1'd1 ); - end - Bool _Stage__37_done = fifo_Stage__28_TO_Stage__37.first.done; - UInt#(3) _Stage__37__threadID = fifo_Stage__28_TO_Stage__37.first._threadID; - Maybe#( SpecId#(4) ) _Stage__37__specId = fifo_Stage__28_TO_Stage__37.first._specId; - UInt#(1) _Stage__37___condStage__41 = ?; - _Stage__37___condStage__41 = ( _Stage__37_done ? 1'd0 : 1'd1 ); - Int#(8) _Start_pc = fifo__input__TO_Start.first.pc; - UInt#(3) _Start__threadID = fifo__input__TO_Start.first._threadID; - Maybe#( SpecId#(4) ) _Start__specId = fifo__input__TO_Start.first._specId; - UInt#(8) _Start__tmp_0 = ?; - Int#(8) _Start__s_0 = ?; - _Start__tmp_0 = unpack( pack( _Start_pc ) ); - _Start__s_0 = ( _Start_pc + 8'd1 ); - Int#(1) _Stage__18_op = fifo_Stage__9_TO_Stage__18.first.op; - Int#(8) _Stage__18__s_0 = fifo_Stage__9_TO_Stage__18.first._s_0; - SpecId#(4) _Stage__18_s = fifo_Stage__9_TO_Stage__18.first.s; - Int#(8) _Stage__18_brImm = fifo_Stage__9_TO_Stage__18.first.brImm; - Int#(8) _Stage__18_pc = fifo_Stage__9_TO_Stage__18.first.pc; - Int#(32) _Stage__18_a1 = fifo_Stage__9_TO_Stage__18.first.a1; - Bool _Stage__18_done = fifo_Stage__9_TO_Stage__18.first.done; - UInt#(5) _Stage__18_rd = fifo_Stage__9_TO_Stage__18.first.rd; - Int#(32) _Stage__18_a2 = fifo_Stage__9_TO_Stage__18.first.a2; - chk_lidTyp_rf _Stage__18__checkpoint_rf = fifo_Stage__9_TO_Stage__18.first._checkpoint_rf; - Int#(32) _Stage__18_out = fifo_Stage__9_TO_Stage__18.first.out; - Maybe#( _lidTyp_rf ) _Stage__18__lock_id_rf_rd_op = fifo_Stage__9_TO_Stage__18.first._lock_id_rf_rd_op; - UInt#(3) _Stage__18__threadID = fifo_Stage__9_TO_Stage__18.first._threadID; - Maybe#( SpecId#(4) ) _Stage__18__specId = fifo_Stage__9_TO_Stage__18.first._specId; - Int#(1) _Stage__9_op = fifo_Stage__0_TO_Stage__9.first.op; - Int#(8) _Stage__9__s_0 = fifo_Stage__0_TO_Stage__9.first._s_0; - SpecId#(4) _Stage__9_s = fifo_Stage__0_TO_Stage__9.first.s; - Maybe#( _lidTyp_rf ) _Stage__9__lock_id_rf_rd_rs = fifo_Stage__0_TO_Stage__9.first._lock_id_rf_rd_rs; - Int#(8) _Stage__9_brImm = fifo_Stage__0_TO_Stage__9.first.brImm; - Int#(8) _Stage__9_pc = fifo_Stage__0_TO_Stage__9.first.pc; - Int#(32) _Stage__9_a1 = fifo_Stage__0_TO_Stage__9.first.a1; - Bool _Stage__9_done = fifo_Stage__0_TO_Stage__9.first.done; - UInt#(5) _Stage__9_rd = fifo_Stage__0_TO_Stage__9.first.rd; - Int#(32) _Stage__9_a2 = fifo_Stage__0_TO_Stage__9.first.a2; - chk_lidTyp_rf _Stage__9__checkpoint_rf = fifo_Stage__0_TO_Stage__9.first._checkpoint_rf; - UInt#(3) _Stage__9__threadID = fifo_Stage__0_TO_Stage__9.first._threadID; - Maybe#( SpecId#(4) ) _Stage__9__specId = fifo_Stage__0_TO_Stage__9.first._specId; - Int#(32) _Stage__9_out = ?; - UInt#(1) _Stage__9___condStage__17 = ?; - UInt#(1) _Stage__9___condStage__14 = ?; - Maybe#( _lidTyp_rf ) _Stage__9__lock_id_rf_rd_aq = ?; - Maybe#( _lidTyp_rf ) _Stage__9__lock_id_rf_rd_op = ?; - _Stage__9_out = ( _Stage__9_a1 + _Stage__9_a2 ); - _Stage__9___condStage__17 = ( ( ! _Stage__9_done ) ? 1'd0 : 1'd1 ); - if ( ( _Stage__9___condStage__17 == 1'd0 )) - begin - _Stage__9___condStage__14 = ( ( _Stage__9_op == 1'd0 ) ? 1'd0 : 1'd1 ); - end - if ( ( ( _Stage__9___condStage__17 == 1'd0 ) && ( _Stage__9___condStage__14 == 1'd0 ) )) - begin - _Stage__9__lock_id_rf_rd_aq = _Stage__9__lock_id_rf_rd_rs; - _Stage__9__lock_id_rf_rd_op = _Stage__9__lock_id_rf_rd_aq; - end - rule s_Stage__19_execute (( ( ! isValid( _Stage__19__specId ) ) || fromMaybe( False , _specTable.check(fromMaybe( ? , _Stage__19__specId ), 0) ) )); - if ( isValid( _Stage__19__specId )) - begin - _specTable.free(fromMaybe( ? , _Stage__19__specId )); - end - if ( ( ( _Stage__19___condStage__27 == 1'd0 ) && ( _Stage__19___condStage__24 == 1'd0 ) )) - begin - if ( ( True && ( _Stage__19_npc == _Stage__19__s_0 ) )) - begin - _specTable.validate(_Stage__19_s, 0); - rf.lock.rollback(_Stage__19__checkpoint_rf, False, True); - end - else - begin - _specTable.invalidate(_Stage__19_s, 0); - fifo__input__TO_Start.enq(E__input__TO_Start { pc : _Stage__19_npc,_threadID : _Stage__19__threadID,_specId : tagged Invalid }); - rf.lock.rollback(_Stage__19__checkpoint_rf, True, True); - end - end - if ( ( ( _Stage__19___condStage__27 == 1'd0 ) && ( _Stage__19___condStage__24 == 1'd1 ) )) - begin - if ( ( True && ( ( _Stage__19_pc + 8'd1 ) == _Stage__19__s_0 ) )) - begin - _specTable.validate(_Stage__19_s, 0); - rf.lock.rollback(_Stage__19__checkpoint_rf, False, True); - end - else - begin - _specTable.invalidate(_Stage__19_s, 0); - fifo__input__TO_Start.enq(E__input__TO_Start { pc : ( _Stage__19_pc + 8'd1 ),_threadID : _Stage__19__threadID,_specId : tagged Invalid }); - rf.lock.rollback(_Stage__19__checkpoint_rf, True, True); - end - end - fifo_Stage__18_TO_Stage__19.deq; - fifo_Stage__19_TO_Stage__28.enq(E_Stage__19_TO_Stage__28 { _threadID : _Stage__19__threadID,_lock_id_rf_rd_op : _Stage__19__lock_id_rf_rd_op,rd : _Stage__19_rd,done : _Stage__19_done,_specId : _Stage__19__specId,out : _Stage__19_out,npc : _Stage__19_npc,op : _Stage__19_op }); - endrule - rule s_Stage__19_kill (( isValid( _Stage__19__specId ) && ( ! fromMaybe( True , _specTable.check(fromMaybe( ? , _Stage__19__specId ), 0) ) ) )); - fifo_Stage__18_TO_Stage__19.deq; - _specTable.free(fromMaybe( ? , _Stage__19__specId )); - endrule - rule s_Stage__0_execute (( ( ! isValid( _Stage__0__specId ) ) || fromMaybe( True , _specTable.check(fromMaybe( ? , _Stage__0__specId ), 2) ) ) && imem.checkRespId1(_Stage__0__request_0)); - chk_lidTyp_rf _Stage__0__checkpoint_rf = ?; - Maybe#( _lidTyp_rf ) _Stage__0__lock_id_rf_rd_rs = tagged Invalid; - imem.resp1(_Stage__0__request_0); - if ( ( _Stage__0___condStage__8 == 1'd0 )) - begin - _Stage__0__checkpoint_rf <- rf.lock.checkpoint; - end - if ( ( ( _Stage__0___condStage__8 == 1'd0 ) && ( _Stage__0___condStage__5 == 1'd0 ) )) - begin - let __tmp_0 <- rf.lock.res1; - _Stage__0__lock_id_rf_rd_rs = tagged Valid __tmp_0; - end - if ( ( _Stage__0___condStage__8 == 1'd1 )) - begin - _specTable.invalidate(_Stage__0_s, 2); - end - fifo_Start_TO_Stage__0.deq; - fifo_Stage__0_TO_Stage__9.enq(E_Stage__0_TO_Stage__9 { pc : _Stage__0_pc,a1 : _Stage__0_a1,s : _Stage__0_s,_specId : _Stage__0__specId,_checkpoint_rf : _Stage__0__checkpoint_rf,brImm : _Stage__0_brImm,_s_0 : _Stage__0__s_0,_lock_id_rf_rd_rs : _Stage__0__lock_id_rf_rd_rs,_threadID : _Stage__0__threadID,done : _Stage__0_done,op : _Stage__0_op,rd : _Stage__0_rd,a2 : _Stage__0_a2 }); - endrule - rule s_Stage__0_kill (( isValid( _Stage__0__specId ) && ( ! fromMaybe( True , _specTable.check(fromMaybe( ? , _Stage__0__specId ), 2) ) ) ) && imem.checkRespId1(_Stage__0__request_0)); - fifo_Start_TO_Stage__0.deq; - imem.resp1(_Stage__0__request_0); - _specTable.free(fromMaybe( ? , _Stage__0__specId )); - endrule - rule s_Stage__28_execute ; - if ( ( ( _Stage__28___condStage__36 == 1'd0 ) && ( _Stage__28___condStage__33 == 1'd0 ) )) - begin - $display( _Stage__28_out ); - rf.lock.rel1(fromMaybe( ? , _Stage__28__lock_id_rf_rd_op )); - end - if ( ( ( _Stage__28___condStage__36 == 1'd0 ) && ( _Stage__28___condStage__33 == 1'd1 ) )) - begin - $display( _Stage__28_npc ); - end - fifo_Stage__19_TO_Stage__28.deq; - fifo_Stage__28_TO_Stage__37.enq(E_Stage__28_TO_Stage__37 { done : _Stage__28_done,_threadID : _Stage__28__threadID,_specId : _Stage__28__specId }); - endrule - rule s_Stage__37_execute (( ( ! ( _Stage__37___condStage__41 == 1'd0 ) ) || outputQueue.canWrite(_Stage__37__threadID) )); - if ( ( _Stage__37___condStage__41 == 1'd0 )) - begin - busyReg <= False; - outputQueue.enq(True); - end - fifo_Stage__28_TO_Stage__37.deq; - endrule - rule s_Start_execute (( ( ! isValid( _Start__specId ) ) || fromMaybe( True , _specTable.check(fromMaybe( ? , _Start__specId ), 3) ) )); - SpecId#(4) _Start_s = ?; - MemId#(8) _Start__request_0 = ?; - _Start_s <- _specTable.alloc; - fifo__input__TO_Start.enq(E__input__TO_Start { pc : _Start__s_0,_threadID : _Start__threadID,_specId : tagged Valid _Start_s }); - _Start__request_0 <- imem.req1(_Start__tmp_0, ?, 0); - fifo__input__TO_Start.deq; - fifo_Start_TO_Stage__0.enq(E_Start_TO_Stage__0 { pc : _Start_pc,_specId : _Start__specId,_request_0 : _Start__request_0,_threadID : _Start__threadID,s : _Start_s,_s_0 : _Start__s_0 }); - endrule - rule s_Start_kill (( isValid( _Start__specId ) && ( ! fromMaybe( True , _specTable.check(fromMaybe( ? , _Start__specId ), 3) ) ) )); - fifo__input__TO_Start.deq; - _specTable.free(fromMaybe( ? , _Start__specId )); - endrule - rule s_Stage__18_execute ; - fifo_Stage__18_TO_Stage__19.enq(E_Stage__18_TO_Stage__19 { _checkpoint_rf : _Stage__18__checkpoint_rf,_specId : _Stage__18__specId,a2 : _Stage__18_a2,brImm : _Stage__18_brImm,_lock_id_rf_rd_op : _Stage__18__lock_id_rf_rd_op,out : _Stage__18_out,a1 : _Stage__18_a1,rd : _Stage__18_rd,_threadID : _Stage__18__threadID,op : _Stage__18_op,done : _Stage__18_done,s : _Stage__18_s,pc : _Stage__18_pc,_s_0 : _Stage__18__s_0 }); - fifo_Stage__9_TO_Stage__18.deq; - endrule - rule s_Stage__9_execute (( ( ! isValid( _Stage__9__specId ) ) || fromMaybe( True , _specTable.check(fromMaybe( ? , _Stage__9__specId ), 1) ) ) && ( ( ! ( ( _Stage__9___condStage__17 == 1'd0 ) && ( _Stage__9___condStage__14 == 1'd0 ) ) ) || rf.lock.owns1(fromMaybe( ? , _Stage__9__lock_id_rf_rd_rs )) )); - if ( ( ( _Stage__9___condStage__17 == 1'd0 ) && ( _Stage__9___condStage__14 == 1'd0 ) )) - begin - rf.write(_Stage__9_rd, _Stage__9_out); - end - fifo_Stage__0_TO_Stage__9.deq; - fifo_Stage__9_TO_Stage__18.enq(E_Stage__9_TO_Stage__18 { _specId : _Stage__9__specId,op : _Stage__9_op,out : _Stage__9_out,a2 : _Stage__9_a2,_threadID : _Stage__9__threadID,done : _Stage__9_done,pc : _Stage__9_pc,s : _Stage__9_s,rd : _Stage__9_rd,brImm : _Stage__9_brImm,_checkpoint_rf : _Stage__9__checkpoint_rf,_lock_id_rf_rd_op : _Stage__9__lock_id_rf_rd_op,_s_0 : _Stage__9__s_0,a1 : _Stage__9_a1 }); - endrule - rule s_Stage__9_kill (( isValid( _Stage__9__specId ) && ( ! fromMaybe( True , _specTable.check(fromMaybe( ? , _Stage__9__specId ), 1) ) ) )); - fifo_Stage__0_TO_Stage__9.deq; - _specTable.free(fromMaybe( ? , _Stage__9__specId )); - endrule - method ActionValue#(UInt#(3)) req ( Int#(8) pc ) if( ( ! busyReg ) ); - fifo__input__TO_Start.enq(E__input__TO_Start { pc : pc,_threadID : _threadID,_specId : tagged Invalid }); - busyReg <= True; - _threadID <= ( _threadID + 1 ); - return _threadID; - endmethod - method Action resp ( ) ; - outputQueue.deq; - endmethod - method Bool peek ( ) ; - return outputQueue.first; - endmethod - method Bool checkHandle ( UInt#(3) handle ) ; - return outputQueue.canRead(handle); - endmethod -endmodule diff --git a/src/test/tests/speculation/rename b/src/test/tests/speculation/rename deleted file mode 100644 index 5c240de2..00000000 --- a/src/test/tests/speculation/rename +++ /dev/null @@ -1,32 +0,0 @@ -0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -a -b -c -d -e -f -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -1a -1b -1c -1d -1e -1f \ No newline at end of file diff --git a/src/test/tests/speculation/ti b/src/test/tests/speculation/ti deleted file mode 100644 index 5f5c8d62..00000000 --- a/src/test/tests/speculation/ti +++ /dev/null @@ -1,14 +0,0 @@ -// 1111 1111 1111 11111 11111 11111 1111 1 -// rd rs2 rs1 brImm op -00000000 // rf[0] <= rf[0] + rf[0] ; pc + 1 PRED CORRECT (print 0) -00000000 // rf[0] <= rf[0] + rf[0] ; pc + 1 PRED CORRECT (print 0) -00000005 // beq rf[0], rf[0], pc + 2 ; pc + 2 PRED WRONG -00000005 // beq rf[0], rf[0], pc + 2 ; SKIPPED -00008420 // rf[1] <= rf[1] + rf[1] ; pc + 1 PRED CORRECT (print 2) -00000025 // beq rf[0], rf[1], pc + 2 ; pc + 1 PRED CORRECT -00000425 // beq rf[1], rf[1], pc + 2 ; pc + 2 PRED WRONG -00000420 // rf[0] <= rf[1] + rf[1] ; pc + 1 SKIPPED -00000845 // beq rf[2], rf[2], pc + 2 ; pc + 2 PRED WRONG -00000000 // w/e SKIPPED -00000420 // rf[0] <= rf[1] + rf[1] ; pc + 1 PRED CORRECT (print 4) -ffffffff // END \ No newline at end of file