From c390a740a41cd8c21c2d3f53ca3040795c89e636 Mon Sep 17 00:00:00 2001
From: Andrew Ferraiuolo <af433@cornell.edu>
Date: Thu, 24 Aug 2017 18:06:49 -0400
Subject: [PATCH] conditional labels

---
 chiselFrontend/src/main/scala/chisel3/core/Label.scala | 6 ++++++
 src/main/scala/chisel3/package.scala                   | 1 +
 2 files changed, 7 insertions(+)

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Label.scala b/chiselFrontend/src/main/scala/chisel3/core/Label.scala
index 5a26d59..26a79b0 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Label.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Label.scala
@@ -90,6 +90,12 @@ object HLevel {
   }
 }
 
+case class IfL(id: HasId)(tc: LabelComp)(fc: LabelComp) extends LabelComp {
+  def name = s"IFL(${id.getRef.name})(${tc.name})(${fc.name})"
+  def fullName(ctx: Component) =
+    s"IFL(${id.getRef.fullName(ctx)})(${tc.fullName(ctx)})(${fc.fullName(ctx)})"
+}
+
 case class VLabel(id: HasId) extends LabelComp {
   def name = s"[[${id.getRef.name}]]V"
   def fullName(ctx: Component) = s"[[${id.getRef.fullName(ctx)}]]V"
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index a094d18..6863a44 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -33,6 +33,7 @@ package object chisel3 {    // scalastyle:ignore package.object.name
   val VLabel = chisel3.core.VLabel
   val JoinLabelComp = chisel3.core.JoinLabelComp
   val MeetLabelComp = chisel3.core.MeetLabelComp
+  val IfL = chisel3.core.IfL
   val Declassify = chisel3.core.Declassify
   val Endorse = chisel3.core.Endorse
   val Next = chisel3.core.Next