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hw/drivers/i2s: Add I2S driver for STM32F7 family
Code implements I2S driver for STM32F7xx MCUs that have it. Signed-off-by: Jerzy Kasenberg <[email protected]>
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‎hw/drivers/i2s/i2s_stm32f7/include/i2s_stm32f7/i2s_stm32f7.h

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/*
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* Licensed to the Apache Software Foundation (ASF) under one
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* or more contributor license agreements. See the NOTICE file
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* distributed with this work for additional information
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* regarding copyright ownership. The ASF licenses this file
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* to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance
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* with the License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing,
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* software distributed under the License is distributed on an
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* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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* KIND, either express or implied. See the License for the
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* specific language governing permissions and limitations
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* under the License.
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*/
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#ifndef _I2S_STM32_H
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#define _I2S_STM32_H
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#include <stm32f7xx_hal.h>
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#include <i2s_stm32f7/stm32_pin_cfg.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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struct i2s;
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struct i2s_cfg;
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struct stm32_spi_cfg;
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struct stm32_i2s_pins {
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stm32_pin_cfg_t ck_pin;
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stm32_pin_cfg_t ws_pin;
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stm32_pin_cfg_t sd_pin;
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stm32_pin_cfg_t mck_pin;
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};
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#define I2S_PIN(n, port, pin) &(I2S ## n ## _P ## port ## pin)
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#define I2S_CK_PIN(n, port, pin) &(I2S ## n ## _CK_P ## port ## pin)
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#define I2S_WS_PIN(n, port, pin) &(I2S ## n ## _WS_P ## port ## pin)
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#define I2S_SD_PIN(n, port, pin) &(I2S ## n ## _SD_P ## port ## pin)
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struct stm32_dma_cfg {
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uint8_t dma_num;
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IRQn_Type dma_stream_irq;
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DMA_Stream_TypeDef *dma_stream;
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uint32_t dma_channel;
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};
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struct i2s_cfg {
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uint32_t mode;
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uint32_t standard;
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uint32_t data_format;
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uint32_t sample_rate;
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struct i2s_buffer_pool *pool;
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const struct stm32_spi_cfg *spi_cfg;
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const struct stm32_dma_cfg *dma_cfg;
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struct stm32_i2s_pins pins;
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};
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#define SPI_CFG(n) &(spi ## n ## _cfg)
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struct stm32_i2s {
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I2S_HandleTypeDef hi2s;
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DMA_HandleTypeDef *hdma_spi;
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struct i2s *i2s;
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struct i2s_sample_buffer *dma_buffers[2];
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uint8_t dma_buffer_count;
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};
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#define DMA_CFG(dma, ch, st, name) &(name ## _stream ## st ## _channel ## ch)
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#define DMA_STREAM_DECLARE(dma, ch, st, name) \
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extern const struct stm32_dma_cfg name ## _stream ## st ## _channel ## ch
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DMA_STREAM_DECLARE(1, 0, 0, spi3_rx);
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DMA_STREAM_DECLARE(1, 0, 1, spdifrx_dt);
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DMA_STREAM_DECLARE(1, 0, 2, spi3_rx);
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DMA_STREAM_DECLARE(1, 0, 3, spi2_rx);
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DMA_STREAM_DECLARE(1, 0, 4, spi2_tx);
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DMA_STREAM_DECLARE(1, 0, 5, spi3_tx);
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DMA_STREAM_DECLARE(1, 0, 6, spdifrx_cs);
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DMA_STREAM_DECLARE(1, 0, 7, spi3_tx);
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DMA_STREAM_DECLARE(1, 1, 0, i2c1_rx);
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DMA_STREAM_DECLARE(1, 1, 1, i2c3_rx);
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DMA_STREAM_DECLARE(1, 1, 2, tim7_up);
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DMA_STREAM_DECLARE(1, 1, 4, tim7_up);
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DMA_STREAM_DECLARE(1, 1, 5, i2c1_rx);
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DMA_STREAM_DECLARE(1, 1, 6, i2c1_tx);
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DMA_STREAM_DECLARE(1, 1, 7, i2c1_tx);
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DMA_STREAM_DECLARE(1, 2, 0, tim4_ch1);
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DMA_STREAM_DECLARE(1, 2, 2, i2c4_rx);
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DMA_STREAM_DECLARE(1, 2, 3, tim4_ch2);
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DMA_STREAM_DECLARE(1, 2, 5, i2c4_rx);
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DMA_STREAM_DECLARE(1, 2, 6, tim4_up);
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DMA_STREAM_DECLARE(1, 2, 7, tim4_ch3);
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DMA_STREAM_DECLARE(1, 3, 1, tim2_up);
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DMA_STREAM_DECLARE(1, 3, 1, tim2_ch3);
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DMA_STREAM_DECLARE(1, 3, 2, i2c3_rx);
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DMA_STREAM_DECLARE(1, 3, 4, i2c3_tx);
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DMA_STREAM_DECLARE(1, 3, 5, tim2_ch1);
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DMA_STREAM_DECLARE(1, 3, 6, tim2_ch2);
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DMA_STREAM_DECLARE(1, 3, 6, tim2_ch4);
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DMA_STREAM_DECLARE(1, 3, 7, tim2_up);
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DMA_STREAM_DECLARE(1, 3, 7, tim2_ch4);
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DMA_STREAM_DECLARE(1, 4, 0, uart5_rx);
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DMA_STREAM_DECLARE(1, 4, 1, usart3_rx);
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DMA_STREAM_DECLARE(1, 4, 2, uart4_rx);
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DMA_STREAM_DECLARE(1, 4, 3, usart3_tx);
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DMA_STREAM_DECLARE(1, 4, 4, uart4_tx);
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DMA_STREAM_DECLARE(1, 4, 5, usart2_rx);
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DMA_STREAM_DECLARE(1, 4, 6, usart2_tx);
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DMA_STREAM_DECLARE(1, 4, 7, uart5_tx);
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DMA_STREAM_DECLARE(1, 5, 0, uart8_tx);
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DMA_STREAM_DECLARE(1, 5, 1, uart7_tx);
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DMA_STREAM_DECLARE(1, 5, 2, tim3_ch4);
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DMA_STREAM_DECLARE(1, 5, 2, tim3_up);
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DMA_STREAM_DECLARE(1, 5, 3, uart7_rx);
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DMA_STREAM_DECLARE(1, 5, 4, tim3_ch1);
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DMA_STREAM_DECLARE(1, 5, 4, tim3_trig);
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DMA_STREAM_DECLARE(1, 5, 5, tim3_ch2);
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DMA_STREAM_DECLARE(1, 5, 6, uart8_rx);
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DMA_STREAM_DECLARE(1, 5, 7, tim3_ch3);
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DMA_STREAM_DECLARE(1, 6, 0, tim5_ch3);
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DMA_STREAM_DECLARE(1, 6, 0, tim5_up);
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DMA_STREAM_DECLARE(1, 6, 1, tim5_ch4);
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DMA_STREAM_DECLARE(1, 6, 1, tim5_trig);
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DMA_STREAM_DECLARE(1, 6, 2, tim5_ch1);
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DMA_STREAM_DECLARE(1, 6, 2, tim3_up);
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DMA_STREAM_DECLARE(1, 6, 3, tim5_ch4);
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DMA_STREAM_DECLARE(1, 6, 3, tim5_trig);
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DMA_STREAM_DECLARE(1, 6, 4, tim5_ch2);
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DMA_STREAM_DECLARE(1, 6, 6, tim5_up);
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DMA_STREAM_DECLARE(1, 7, 1, tim6_up);
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DMA_STREAM_DECLARE(1, 7, 2, i2c2_rx);
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DMA_STREAM_DECLARE(1, 7, 3, i2c2_rx);
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DMA_STREAM_DECLARE(1, 7, 4, usart3_tx);
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DMA_STREAM_DECLARE(1, 7, 5, dac1);
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DMA_STREAM_DECLARE(1, 7, 6, dac2);
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DMA_STREAM_DECLARE(1, 7, 7, i2c2_tx);
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DMA_STREAM_DECLARE(1, 8, 0, i2c3_tx);
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DMA_STREAM_DECLARE(1, 8, 1, i2c4_rx);
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DMA_STREAM_DECLARE(1, 8, 4, i2c2_tx);
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DMA_STREAM_DECLARE(1, 8, 6, i2c4_tx);
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DMA_STREAM_DECLARE(1, 9, 1, i2c2_rx);
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DMA_STREAM_DECLARE(1, 9, 6, i2c2_tx);
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DMA_STREAM_DECLARE(2, 0, 0, adc1);
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DMA_STREAM_DECLARE(2, 0, 1, sai1_a);
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DMA_STREAM_DECLARE(2, 0, 2, tim8_ch1);
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DMA_STREAM_DECLARE(2, 0, 2, tim8_ch2);
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DMA_STREAM_DECLARE(2, 0, 2, tim8_ch3);
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DMA_STREAM_DECLARE(2, 0, 3, sai1_a);
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DMA_STREAM_DECLARE(2, 0, 4, adc1);
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DMA_STREAM_DECLARE(2, 0, 5, sai1_b);
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DMA_STREAM_DECLARE(2, 0, 6, tim1_ch1);
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DMA_STREAM_DECLARE(2, 0, 6, tim1_ch2);
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DMA_STREAM_DECLARE(2, 0, 6, tim1_ch3);
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DMA_STREAM_DECLARE(2, 0, 7, sai1_b);
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DMA_STREAM_DECLARE(2, 1, 1, dcmi);
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DMA_STREAM_DECLARE(2, 1, 2, adc2);
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DMA_STREAM_DECLARE(2, 1, 3, adc2);
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DMA_STREAM_DECLARE(2, 1, 4, sai1_b);
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DMA_STREAM_DECLARE(2, 1, 5, spi6_tx);
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DMA_STREAM_DECLARE(2, 1, 6, spi6_rx);
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DMA_STREAM_DECLARE(2, 1, 7, dcmi);
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DMA_STREAM_DECLARE(2, 2, 0, adc3);
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DMA_STREAM_DECLARE(2, 2, 1, adc3);
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DMA_STREAM_DECLARE(2, 2, 3, spi5_rx);
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DMA_STREAM_DECLARE(2, 2, 4, spi5_tx);
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DMA_STREAM_DECLARE(2, 2, 5, cryp_out);
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DMA_STREAM_DECLARE(2, 2, 6, cryp_in);
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DMA_STREAM_DECLARE(2, 2, 7, hash_in);
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DMA_STREAM_DECLARE(2, 3, 0, spi1_rx);
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DMA_STREAM_DECLARE(2, 3, 2, spi1_rx);
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DMA_STREAM_DECLARE(2, 3, 3, spi1_tx);
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DMA_STREAM_DECLARE(2, 3, 4, sai2_a);
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DMA_STREAM_DECLARE(2, 3, 5, spi1_tx);
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DMA_STREAM_DECLARE(2, 3, 6, sai2_b);
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DMA_STREAM_DECLARE(2, 3, 7, quadspi);
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DMA_STREAM_DECLARE(2, 4, 0, spi4_rx);
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DMA_STREAM_DECLARE(2, 4, 1, spi4_tx);
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DMA_STREAM_DECLARE(2, 4, 2, usart1_rx);
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DMA_STREAM_DECLARE(2, 4, 3, sdmmc1);
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DMA_STREAM_DECLARE(2, 4, 5, usart1_rx);
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DMA_STREAM_DECLARE(2, 4, 6, sdmmc1);
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DMA_STREAM_DECLARE(2, 4, 7, usart1_tx);
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DMA_STREAM_DECLARE(2, 5, 1, usart6_rx);
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DMA_STREAM_DECLARE(2, 5, 2, usart6_rx);
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DMA_STREAM_DECLARE(2, 5, 3, spi4_rx);
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DMA_STREAM_DECLARE(2, 5, 4, spi4_tx);
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DMA_STREAM_DECLARE(2, 5, 5, spi5_tx);
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DMA_STREAM_DECLARE(2, 5, 6, usart6_tx);
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DMA_STREAM_DECLARE(2, 5, 7, usart6_tx);
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DMA_STREAM_DECLARE(2, 6, 0, tim1_trig);
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DMA_STREAM_DECLARE(2, 6, 1, tim1_ch1);
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DMA_STREAM_DECLARE(2, 6, 2, tim1_ch2);
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DMA_STREAM_DECLARE(2, 6, 3, tim1_ch1);
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DMA_STREAM_DECLARE(2, 6, 4, tim1_ch4);
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DMA_STREAM_DECLARE(2, 6, 4, tim1_trig);
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DMA_STREAM_DECLARE(2, 6, 4, tim1_com);
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DMA_STREAM_DECLARE(2, 6, 5, tim1_up);
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DMA_STREAM_DECLARE(2, 6, 6, tim1_ch3);
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DMA_STREAM_DECLARE(2, 7, 1, tim8_up);
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DMA_STREAM_DECLARE(2, 7, 2, tim8_ch1);
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DMA_STREAM_DECLARE(2, 7, 3, tim8_ch2);
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DMA_STREAM_DECLARE(2, 7, 4, tim8_ch3);
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DMA_STREAM_DECLARE(2, 7, 5, spi5_rx);
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DMA_STREAM_DECLARE(2, 7, 6, spi5_tx);
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DMA_STREAM_DECLARE(2, 7, 7, tim8_ch4);
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DMA_STREAM_DECLARE(2, 7, 7, tim8_trig);
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DMA_STREAM_DECLARE(2, 7, 7, tim8_com);
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DMA_STREAM_DECLARE(2, 8, 0, dfsdm1_flt0);
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DMA_STREAM_DECLARE(2, 8, 1, dfsdm1_flt1);
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DMA_STREAM_DECLARE(2, 8, 2, dfsdm1_flt2);
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DMA_STREAM_DECLARE(2, 8, 3, dfsdm1_flt3);
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DMA_STREAM_DECLARE(2, 8, 4, dfsdm1_flt0);
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DMA_STREAM_DECLARE(2, 8, 5, dfsdm1_flt1);
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DMA_STREAM_DECLARE(2, 8, 6, dfsdm1_flt2);
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DMA_STREAM_DECLARE(2, 8, 7, dfsdm1_flt3);
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DMA_STREAM_DECLARE(2, 9, 0, jpeg_in);
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DMA_STREAM_DECLARE(2, 9, 1, jpeg_out);
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DMA_STREAM_DECLARE(2, 9, 2, spi4_tx);
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DMA_STREAM_DECLARE(2, 9, 3, jpeg_in);
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DMA_STREAM_DECLARE(2, 9, 4, jpeg_out);
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DMA_STREAM_DECLARE(2, 9, 5, spi5_rx);
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DMA_STREAM_DECLARE(2, 10, 0, sai1_b);
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DMA_STREAM_DECLARE(2, 10, 1, sai2_b);
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DMA_STREAM_DECLARE(2, 10, 2, sai2_a);
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DMA_STREAM_DECLARE(2, 10, 6, sai1_a);
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DMA_STREAM_DECLARE(2, 11, 0, sdmmc2);
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DMA_STREAM_DECLARE(2, 11, 2, suadspi);
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DMA_STREAM_DECLARE(2, 11, 5, sdmmc2);
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#define SPI_CFG_DECLARE(n) \
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extern struct stm32_spi_cfg spi ## n ## _cfg;
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SPI_CFG_DECLARE(1);
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SPI_CFG_DECLARE(2);
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SPI_CFG_DECLARE(3);
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SPI_CFG_DECLARE(4);
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SPI_CFG_DECLARE(5);
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#define I2S_PIN_DECLARE(n, port, pin) \
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extern const struct stm32_pin_cfg I2S ## n ## _P ## port ## pin;
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#define I2S_CK_PIN_DECLARE(n, port, pin) \
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extern const struct stm32_pin_cfg I2S ## n ## _CK_P ## port ## pin;
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#define I2S_WS_PIN_DECLARE(n, port, pin) \
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extern const struct stm32_pin_cfg I2S ## n ## _WS_P ## port ## pin;
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#define I2S_SD_PIN_DECLARE(n, port, pin) \
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extern const struct stm32_pin_cfg I2S ## n ## _SD_P ## port ## pin;
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/* I2S1 Possible CK pins */
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I2S_CK_PIN_DECLARE(1, A, 5);
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I2S_CK_PIN_DECLARE(1, B, 3);
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I2S_CK_PIN_DECLARE(1, G, 11);
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/* I2S1 possible WS pins */
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I2S_WS_PIN_DECLARE(1, A, 4);
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I2S_WS_PIN_DECLARE(1, A, 15);
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I2S_WS_PIN_DECLARE(1, G, 10);
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/* I2S1 possible SD pins */
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I2S_SD_PIN_DECLARE(1, B, 5);
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I2S_SD_PIN_DECLARE(1, A, 7);
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I2S_SD_PIN_DECLARE(1, D, 7);
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/* I2S1 possible MCK pins */
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I2S_SD_PIN_DECLARE(1, C, 4);
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/* I2S2 Possible CKIN pins */
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I2S_PIN_DECLARE(2, C, 9);
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/* I2S2 Possible MCK pins */
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#ifdef GPIO_AF5_SPI2
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I2S_PIN_DECLARE(2, C, 6);
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#endif
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/* I2S2 Possible CK pins */
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I2S_CK_PIN_DECLARE(2, A, 9);
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I2S_CK_PIN_DECLARE(2, A, 12);
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I2S_CK_PIN_DECLARE(2, B, 10);
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I2S_CK_PIN_DECLARE(2, B, 13);
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I2S_CK_PIN_DECLARE(2, D, 3);
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I2S_CK_PIN_DECLARE(2, I, 1);
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/* I2S2 possible WS pins */
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I2S_WS_PIN_DECLARE(2, A, 11);
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I2S_WS_PIN_DECLARE(2, B, 4);
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I2S_WS_PIN_DECLARE(2, B, 9);
317+
I2S_WS_PIN_DECLARE(2, B, 12);
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I2S_WS_PIN_DECLARE(2, I, 0);
319+
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/* I2S2 possible SD pins */
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I2S_SD_PIN_DECLARE(2, B, 15);
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I2S_SD_PIN_DECLARE(2, C, 1);
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I2S_SD_PIN_DECLARE(2, C, 3);
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I2S_SD_PIN_DECLARE(2, I, 3);
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/* I2S3 possible CK pins */
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I2S_CK_PIN_DECLARE(3, B, 3);
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I2S_CK_PIN_DECLARE(3, C, 10);
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/* I2S3 possible WS pins */
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I2S_WS_PIN_DECLARE(3, A, 4);
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I2S_WS_PIN_DECLARE(3, A, 15);
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/* I2S3 possible SD pins */
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I2S_SD_PIN_DECLARE(3, B, 2);
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I2S_SD_PIN_DECLARE(3, B, 5);
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I2S_SD_PIN_DECLARE(3, C, 12);
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#ifdef GPIO_AF5_SPI3
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I2S_SD_PIN_DECLARE(3, D, 6);
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* _I2S_STM32_H */

‎hw/drivers/i2s/i2s_stm32f7/include/i2s_stm32f7/stm32_pin_cfg.h

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/*
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* Licensed to the Apache Software Foundation (ASF) under one
3+
* or more contributor license agreements. See the NOTICE file
4+
* distributed with this work for additional information
5+
* regarding copyright ownership. The ASF licenses this file
6+
* to you under the Apache License, Version 2.0 (the
7+
* "License"); you may not use this file except in compliance
8+
* with the License. You may obtain a copy of the License at
9+
*
10+
* http://www.apache.org/licenses/LICENSE-2.0
11+
*
12+
* Unless required by applicable law or agreed to in writing,
13+
* software distributed under the License is distributed on an
14+
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
15+
* KIND, either express or implied. See the License for the
16+
* specific language governing permissions and limitations
17+
* under the License.
18+
*/
19+
20+
#ifndef _STM32_PIN_CFG_H
21+
#define _STM32_PIN_CFG_H
22+
23+
#include <stdint.h>
24+
#include <mcu/stm32_hal.h>
25+
26+
#ifdef __cplusplus
27+
extern "C" {
28+
#endif
29+
30+
struct stm32_pin_cfg {
31+
int8_t pin;
32+
GPIO_InitTypeDef hal_init;
33+
};
34+
35+
typedef const struct stm32_pin_cfg *stm32_pin_cfg_t;
36+
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#ifdef __cplusplus
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}
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#endif
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#endif /* _STM32_PIN_CFG_H */

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