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| 1 | +// dotProduct.c |
| 2 | + |
| 3 | +#include <stdio.h> |
| 4 | +#include <arm_neon.h> |
| 5 | + |
| 6 | +#ifdef __ARM_ACLE |
| 7 | +#include <arm_acle.h> |
| 8 | +#endif |
| 9 | + |
| 10 | +#if (defined(__ARM_FEATURE_SVE) && !defined(__APPLE__)) |
| 11 | +#include <arm_sve.h> |
| 12 | +/* |
| 13 | + * Unrolled and vectorized int8 dotProduct implementation using SVE instructions |
| 14 | + * NOTE: Clang 15.0 compiler on Apple M3 Max compiles the code below sucessfully |
| 15 | + * with '-march=native+sve' option but throws "Illegal Hardware Instruction" error |
| 16 | + * Looks like Apple M3 does not implement SVE and Apple's official documentation |
| 17 | + * is not explicit about this or at least I could not find it. |
| 18 | + * |
| 19 | + */ |
| 20 | +int32_t vdot8s_sve(int8_t *vec1, int8_t *vec2, int32_t limit) { |
| 21 | + int32_t result = 0; |
| 22 | + int32_t i = 0; |
| 23 | + // Vectors of 8-bit signed integers |
| 24 | + svint8_t va1, va2, va3, va4; |
| 25 | + svint8_t vb1, vb2, vb3, vb4; |
| 26 | + // Init accumulators |
| 27 | + svint32_t acc1 = svdup_n_s32(0); |
| 28 | + svint32_t acc2 = svdup_n_s32(0); |
| 29 | + svint32_t acc3 = svdup_n_s32(0); |
| 30 | + svint32_t acc4 = svdup_n_s32(0); |
| 31 | + |
| 32 | + // Number of 8-bits elements in the SVE vector |
| 33 | + int32_t vec_length = svcntb(); |
| 34 | + |
| 35 | + // Manually unroll the loop |
| 36 | + for (i = 0; i + 4 * vec_length <= limit; i += 4 * vec_length) { |
| 37 | + // Load vectors into the Z registers which can range from 128-bit to 2048-bit wide |
| 38 | + // The predicate register - P determines which bytes are active |
| 39 | + // svptrue_b8() returns a predictae in which every element is true |
| 40 | + // |
| 41 | + va1 = svld1_s8(svptrue_b8(), vec1 + i); |
| 42 | + vb1 = svld1_s8(svptrue_b8(), vec2 + i); |
| 43 | + |
| 44 | + va2 = svld1_s8(svptrue_b8(), vec1 + i + vec_length); |
| 45 | + vb2 = svld1_s8(svptrue_b8(), vec2 + i + vec_length); |
| 46 | + |
| 47 | + va3 = svld1_s8(svptrue_b8(), vec1 + i + 2 * vec_length); |
| 48 | + vb3 = svld1_s8(svptrue_b8(), vec2 + i + 2 * vec_length); |
| 49 | + |
| 50 | + va4 = svld1_s8(svptrue_b8(), vec1 + i + 3 * vec_length); |
| 51 | + vb4 = svld1_s8(svptrue_b8(), vec2 + i + 3 * vec_length); |
| 52 | + |
| 53 | + // Dot product using SDOT instruction on Z vectors |
| 54 | + acc1 = svdot_s32(acc1, va1, vb1); |
| 55 | + acc2 = svdot_s32(acc2, va2, vb2); |
| 56 | + acc3 = svdot_s32(acc3, va3, vb3); |
| 57 | + acc4 = svdot_s32(acc4, va4, vb4); |
| 58 | + } |
| 59 | + // Add correspponding active elements in each of the vectors |
| 60 | + acc1 = svadd_s32_x(svptrue_b8() , acc1, acc2); |
| 61 | + acc3 = svadd_s32_x(svptrue_b8() , acc3, acc4); |
| 62 | + acc1 = svadd_s32_x(svptrue_b8(), acc1, acc3); |
| 63 | + |
| 64 | + // REDUCE: Add every vector element in target and write result to scalar |
| 65 | + result = svaddv_s32(svptrue_b8(), acc1); |
| 66 | + |
| 67 | + // Scalar tail. TODO: Use FMA |
| 68 | + for (; i < limit; i++) { |
| 69 | + result += vec1[i] * vec2[i]; |
| 70 | + } |
| 71 | + return result; |
| 72 | +} |
| 73 | +#endif |
| 74 | + |
| 75 | +// https://developer.arm.com/architectures/instruction-sets/intrinsics/ |
| 76 | +int32_t vdot8s_neon(int8_t* vec1, int8_t* vec2, int32_t limit) { |
| 77 | + int32_t result = 0; |
| 78 | + int32x4_t acc1 = vdupq_n_s32(0); |
| 79 | + int32x4_t acc2 = vdupq_n_s32(0); |
| 80 | + int32x4_t acc3 = vdupq_n_s32(0); |
| 81 | + int32x4_t acc4 = vdupq_n_s32(0); |
| 82 | + int32_t i = 0; |
| 83 | + int8x16_t va1, va2, va3, va4; |
| 84 | + int8x16_t vb1, vb2, vb3, vb4; |
| 85 | + |
| 86 | + for (; i + 64 <= limit; i += 64 ) { |
| 87 | + // Read into 8 (bit) x 16 (values) vector |
| 88 | + va1 = vld1q_s8((const void*) (vec1 + i)); |
| 89 | + vb1 = vld1q_s8((const void*) (vec2 + i)); |
| 90 | + |
| 91 | + va2 = vld1q_s8((const void*) (vec1 + i + 16)); |
| 92 | + vb2 = vld1q_s8((const void*) (vec2 + i + 16)); |
| 93 | + |
| 94 | + va3 = vld1q_s8((const void*) (vec1 + i + 32)); |
| 95 | + vb3 = vld1q_s8((const void*) (vec2 + i + 32)); |
| 96 | + |
| 97 | + va4 = vld1q_s8((const void*) (vec1 + i + 48)); |
| 98 | + vb4 = vld1q_s8((const void*) (vec2 + i + 48)); |
| 99 | + |
| 100 | + // Dot product using SDOT instruction |
| 101 | + // GCC 7.3 does not define the intrinsic below so we get compile time error. |
| 102 | + acc1 = vdotq_s32(acc1, va1, vb1); |
| 103 | + acc2 = vdotq_s32(acc2, va2, vb2); |
| 104 | + acc3 = vdotq_s32(acc3, va3, vb3); |
| 105 | + acc4 = vdotq_s32(acc4, va4, vb4); |
| 106 | + } |
| 107 | + // Add corresponding elements in each vectors |
| 108 | + acc1 = vaddq_s32(acc1, acc2); |
| 109 | + acc3 = vaddq_s32(acc3, acc4); |
| 110 | + acc1 = vaddq_s32(acc1, acc3); |
| 111 | + |
| 112 | + // REDUCE: Add every vector element in target and write result to scalar |
| 113 | + result += vaddvq_s32(acc1); |
| 114 | + |
| 115 | + // Scalar tail. TODO: Use FMA |
| 116 | + for (; i < limit; i++) { |
| 117 | + result += vec1[i] * vec2[i]; |
| 118 | + } |
| 119 | + return result; |
| 120 | +} |
| 121 | + |
| 122 | +int32_t dot8s(int8_t* vec1, int8_t* vec2, int32_t limit) { |
| 123 | + int32_t result = 0; |
| 124 | + for (int32_t i = 0; i < limit; i++) { |
| 125 | + result += vec1[i] * vec2[i]; |
| 126 | + } |
| 127 | + return result; |
| 128 | +} |
| 129 | + |
| 130 | +/* |
| 131 | +int main(int argc, const char* arrgs[]) { |
| 132 | + int8_t a[128]; |
| 133 | + int8_t b[128]; |
| 134 | + for (int i =0; i < 128; i++) { |
| 135 | + a[i] = 2; |
| 136 | + b[i] = 3; |
| 137 | + } |
| 138 | + printf("Sum (Vectorized - SVE) = %d\n", vdot8s_sve(&a, &b, 128)); |
| 139 | + printf("Sum (Vectorized - NEON) = %d\n", vdot8s_neon(&a, &b, 128)); |
| 140 | + printf("Sum (Scalar) = %d\n", dot8s(&a, &b, 128)); |
| 141 | +}*/ |
| 142 | + |
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