Initial commit

Author: antoinevg

.cargo/config

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+[build]
+# target = "thumbv6m-none-eabi"    # Cortex-M0 and Cortex-M0+
+# target = "thumbv7m-none-eabi"    # Cortex-M3
+# target = "thumbv7em-none-eabi"   # Cortex-M4 and Cortex-M7 (no FPU)
+target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
+
+[target.'cfg(all(target_arch = "arm", target_os = "none"))']
+runner = "arm-none-eabi-gdb -q -x openocd.gdb"
+
+rustflags = [
+  # LLD (shipped with the Rust toolchain) is used as the default linker
+  "-C", "link-arg=-Tlink.x",
+
+  # if you run into problems with LLD switch to the GNU linker by commenting out
+  # this line
+  # "-C", "linker=arm-none-eabi-ld",
+
+  # if you need to link to pre-compiled C libraries provided by a C toolchain
+  # use GCC as the linker by commenting out both lines above and then
+  # uncommenting the three lines below
+  # "-C", "linker=arm-none-eabi-gcc",
+  # "-C", "link-arg=-Wl,-Tlink.x",
+  # "-C", "link-arg=-nostartfiles",
+]

.gitignore

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+target/

Cargo.lock

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+[package]
+name = "flowdsp-blog"
+version = "0.1.0"
+authors = ["Antoine van Gelder <[email protected]>"]
+edition = "2018"
+
+[dependencies]
+cortex-m = "0.5.8"
+cortex-m-rt = "0.6.7"
+cortex-m-semihosting = "0.3.2"
+panic-semihosting = "0.5.1"
+
+[dependencies.lazy_static]
+features = ["spin_no_std"]
+version = "1.3.0"
+
+[dependencies.stm32f30x]
+features = ["rt"]
+version = "0.8.0"  # latest is 0.8.0!
+
+[[bin]]
+name = "stm32f3-01-interrupts"
+path = "src/stm32f3-01-interrupts.rs"

Cargo.toml

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+deps:
+	sudo port install arm-none-eabi-binutils arm-none-eabi-gcc arm-none-eabi-gdb
+	sudo port install openocd +stlink
+	rustup target add thumbv7em-none-eabihf
+	cargo install itm --vers 0.3.1
+
+deps-clean:
+	sudo port uninstall arm-none-eabi-binutils arm-none-eabi-gcc arm-none-eabi-gdb isl libmpc mpfr
+	sudo port uninstall openocd libusb
+
+clean:
+	find . -name "*.DS_Store" -exec rm '{}' ';'
+	find . -name "*~" -exec rm '{}' ';'
+
+distclean:
+	cargo clean
+
+openocd:
+	openocd -f interface/stlink-v2-1.cfg -f target/stm32f3x.cfg

Makefile

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+Source code for https://blog.flowdsp.io/ articles
+
+    git clone https://github.com/antoinevg/stm32fx-examples.git
+    cd stm32fx-examples
+    make deps
+
+    # run in one terminal
+    openocd -f openocd.cfg
+
+    # run in another terminal
+    cargo run

README.md

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+use std::env;
+use std::fs::File;
+use std::io::Write;
+use std::path::PathBuf;
+
+fn main() {
+    // Put the linker script somewhere the linker can find it
+    let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+    File::create(out.join("memory.x"))
+        .unwrap()
+        .write_all(include_bytes!("memory.x"))
+        .unwrap();
+    println!("cargo:rustc-link-search={}", out.display());
+
+    // Only re-run the build script when memory.x is changed,
+    // instead of when any part of the source code changes.
+    println!("cargo:rerun-if-changed=memory.x");
+}

build.rs

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+/* Linker script for the STM32F303VCT6 */
+MEMORY
+{
+  FLASH : ORIGIN = 0x08000000, LENGTH = 256K
+  RAM : ORIGIN = 0x20000000, LENGTH = 40K
+}

memory.x

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+# Sample OpenOCD configuration for the STM32F3DISCOVERY development board
+
+# Depending on the hardware revision you got you'll have to pick ONE of these
+# interfaces. At any time only one interface should be commented out.
+
+# Revision C (newer revision)
+source [find interface/stlink-v2-1.cfg]
+
+# Revision A and B (older revisions)
+# source [find interface/stlink-v2.cfg]
+
+source [find target/stm32f3x.cfg]

openocd.cfg

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+target extended-remote :3333
+
+# print demangled symbols
+set print asm-demangle on
+
+# set backtrace limit to not have infinite backtrace loops
+set backtrace limit 32
+
+# detect unhandled exceptions, hard faults and panics
+break DefaultHandler
+break HardFault
+break rust_begin_unwind
+
+# *try* to stop at the user entry point (it might be gone due to inlining)
+# break main
+
+monitor arm semihosting enable
+
+# # send captured ITM to the file itm.fifo
+# # (the microcontroller SWO pin must be connected to the programmer SWO pin)
+# # 8000000 must match the core clock frequency
+monitor tpiu config internal /tmp/itm.txt uart off 8000000
+
+# # OR: make the microcontroller SWO pin output compatible with UART (8N1)
+# # 8000000 must match the core clock frequency
+# # 2000000 is the frequency of the SWO pin
+#monitor tpiu config external uart off 8000000 2000000
+
+# # enable ITM port 0
+monitor itm port 0 on
+
+load
+
+# start the process but immediately halt the processor
+# stepi
+
+# start the process
+continue