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Add "const" keyword
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plugin/verilog_instance.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@
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keywords = []
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keywords.extend(["input", "output", "inout", "ref", "parameter", "localparam"])
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keywords.extend(["reg", "logic", "wire", "bit", "integer", "int", "string", "type"])
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keywords.extend(["unsigned"])
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keywords.extend(["const", "unsigned"])
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patterns = []
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patterns.append(re.compile(r'\[[^\[\]]*\]')) # port size, array size

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