Merge pull request YosysHQ#4704 from YosysHQ/krys/drop_ilang

Remove references to ilang

Author: KrystalDelusion

backends/btor/test_cells.sh

@@ -10,11 +10,11 @@ cd test_cells.tmp
 
 for fn in test_*.il; do
 	../../../yosys -p "
-		read_ilang $fn
+		read_rtlil $fn
 		rename gold gate
 		synth
 
-		read_ilang $fn
+		read_rtlil $fn
 		miter -equiv -make_assert -flatten gold gate main
 		hierarchy -top main
 		write_btor ${fn%.il}.btor

backends/rtlil/rtlil_backend.cc

@@ -464,21 +464,6 @@ struct RTLILBackend : public Backend {
 	}
 } RTLILBackend;
 
-struct IlangBackend : public Backend {
-	IlangBackend() : Backend("ilang", "(deprecated) alias of write_rtlil") { }
-	void help() override
-	{
-		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
-		log("\n");
-		log("See `help write_rtlil`.\n");
-		log("\n");
-	}
-	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
-	{
-		RTLILBackend.execute(f, filename, args, design);
-	}
-} IlangBackend;
-
 struct DumpPass : public Pass {
 	DumpPass() : Pass("dump", "print parts of the design in RTLIL format") { }
 	void help() override

backends/smt2/test_cells.sh

@@ -21,7 +21,7 @@ EOT
 for x in $(set +x; ls test_*.il | sort -R); do
 	x=${x%.il}
 	cat > $x.ys <<- EOT
-		read_ilang $x.il
+		read_rtlil $x.il
 		copy gold gate
 
 		cd gate

backends/smv/test_cells.sh

@@ -17,11 +17,11 @@ EOT
 
 for fn in test_*.il; do
 	../../../yosys -p "
-		read_ilang $fn
+		read_rtlil $fn
 		rename gold gate
 		synth
 
-		read_ilang $fn
+		read_rtlil $fn
 		miter -equiv -flatten gold gate main
 		hierarchy -top main
 		write_smv -tpl template.txt ${fn#.il}.smv

docs/source/_images/internals/overview_flow.tex

@@ -15,23 +15,23 @@
 	\tikzstyle{data} = [draw, fill=blue!10, ellipse, minimum height=3em, minimum width=7em, node distance=15em]
 	\node[process] (vlog) {Verilog Frontend};
 	\node[process, dashed, fill=green!5] (vhdl) [right of=vlog] {VHDL Frontend};
-	\node[process] (ilang) [right of=vhdl] {RTLIL Frontend};
+	\node[process] (rtlilfe) [right of=vhdl] {RTLIL Frontend};
 	\node[data] (ast) [below of=vlog, node distance=5em, xshift=7.5em] {AST};
 	\node[process] (astfe) [below of=ast, node distance=5em] {AST Frontend};
 	\node[data] (rtlil) [below of=astfe, node distance=5em, xshift=7.5em] {RTLIL};
 	\node[process] (pass) [right of=rtlil, node distance=5em, xshift=7.5em] {Passes};
 	\node[process] (vlbe) [below of=rtlil, node distance=7em, xshift=-13em] {Verilog Backend};
-	\node[process] (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] {RTLIL Backend};
+	\node[process] (rtlilbe) [below of=rtlil, node distance=7em, xshift=0em] {RTLIL Backend};
 	\node[process, dashed, fill=green!5] (otherbe) [below of=rtlil, node distance=7em, xshift=+13em] {Other Backends};
 
 	\draw[-latex] (vlog) -- (ast);
 	\draw[-latex] (vhdl) -- (ast);
 	\draw[-latex] (ast) -- (astfe);
 	\draw[-latex] (astfe) -- (rtlil);
-	\draw[-latex] (ilang) -- (rtlil);
+	\draw[-latex] (rtlilfe) -- (rtlil);
 	\draw[latex-latex] (rtlil) -- (pass);
 	\draw[-latex] (rtlil) -- (vlbe);
-	\draw[-latex] (rtlil) -- (ilangbe);
+	\draw[-latex] (rtlil) -- (rtlilbe);
 	\draw[-latex] (rtlil) -- (otherbe);
 \end{tikzpicture}
 \end{document}

frontends/rtlil/rtlil_frontend.cc

@@ -96,20 +96,5 @@ struct RTLILFrontend : public Frontend {
 	}
 } RTLILFrontend;
 
-struct IlangFrontend : public Frontend {
-	IlangFrontend() : Frontend("ilang", "(deprecated) alias of read_rtlil") { }
-	void help() override
-	{
-		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
-		log("\n");
-		log("See `help read_rtlil`.\n");
-		log("\n");
-	}
-	void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
-	{
-		RTLILFrontend.execute(f, filename, args, design);
-	}
-} IlangFrontend;
-
 YOSYS_NAMESPACE_END
 

tests/arch/ecp5/bug1630.ys

@@ -1,2 +1,2 @@
-read_ilang bug1630.il.gz
+read_rtlil bug1630.il.gz
 abc9 -lut 4

tests/arch/ecp5/opt_lut_ins.ys

@@ -1,4 +1,4 @@
-read_ilang << EOF
+read_rtlil << EOF
 
 module \top
 

tests/arch/ice40/bug1626.ys

@@ -1,4 +1,4 @@
-read_ilang <<EOT
+read_rtlil <<EOT
 # Generated by Yosys 0.9+1706 (git sha1 58ab9f60, clang 6.0.0-1ubuntu2 -fPIC -Os)
 autoidx 2815
 attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:9"

tests/arch/ice40/bug1644.ys

@@ -1,2 +1,2 @@
-read_ilang bug1644.il.gz
+read_rtlil bug1644.il.gz
 synth_ice40 -top top -dsp -json adc_dac_pass_through.json -run :map_bram

tests/arch/xilinx/opt_lut_ins.ys

@@ -1,4 +1,4 @@
-read_ilang << EOF
+read_rtlil << EOF
 
 module \top
 

tests/opt/bug2920.ys

@@ -1,4 +1,4 @@
-read_ilang <<EOT
+read_rtlil <<EOT
 
 module \mod
   wire input 1 \clk

tests/opt/memory_bmux2rom.ys

@@ -1,4 +1,4 @@
-read_ilang << EOT
+read_rtlil << EOT
 
 module \top
   wire width 4 input 0 \S

tests/opt/opt_lut_elim.ys

@@ -1,3 +1,3 @@
-read_ilang opt_lut_elim.il
+read_rtlil opt_lut_elim.il
 opt_lut
 select -assert-count 0 t:$lut

tests/opt/opt_lut_ins.ys

@@ -1,4 +1,4 @@
-read_ilang << EOF
+read_rtlil << EOF
 
 module \top
 

tests/opt/opt_lut_port.ys

@@ -1,3 +1,3 @@
-read_ilang opt_lut_port.il
+read_rtlil opt_lut_port.il
 opt_lut
 select -assert-count 2 t:$lut

tests/opt/opt_reduce_bmux.ys

@@ -1,4 +1,4 @@
-read_ilang << EOT
+read_rtlil << EOT
 
 module \top
   wire width 12 input 0 \A
@@ -22,7 +22,7 @@ select -assert-count 1 t:$bmux r:WIDTH=4 %i
 
 design -reset
 
-read_ilang << EOT
+read_rtlil << EOT
 
 module \top
   wire width 6 input 0 \A
@@ -46,7 +46,7 @@ select -assert-count 0 t:$bmux
 
 design -reset
 
-read_ilang << EOT
+read_rtlil << EOT
 
 module \top
   wire width 160 input 0 \A
@@ -70,7 +70,7 @@ select -assert-count 1 t:$bmux r:S_WIDTH=2 %i
 
 design -reset
 
-read_ilang << EOT
+read_rtlil << EOT
 
 module \top
   wire width 10 input 0 \A
@@ -95,7 +95,7 @@ select -assert-count 1 t:$mux
 
 design -reset
 
-read_ilang << EOT
+read_rtlil << EOT
 
 module \top
   wire width 5 input 0 \A

tests/opt/opt_reduce_demux.ys

@@ -1,4 +1,4 @@
-read_ilang << EOT
+read_rtlil << EOT
 
 module \top
   wire width 4 input 0 \A
@@ -22,7 +22,7 @@ select -assert-count 1 t:$demux r:WIDTH=4 %i
 
 design -reset
 
-read_ilang << EOT
+read_rtlil << EOT
 
 module \top
   wire width 2 input 1 \S
@@ -45,7 +45,7 @@ select -assert-count 0 t:$demux
 
 design -reset
 
-read_ilang << EOT
+read_rtlil << EOT
 
 module \top
   wire width 5 input 0 \A
@@ -69,7 +69,7 @@ select -assert-count 1 t:$demux r:S_WIDTH=2 %i
 
 design -reset
 
-read_ilang << EOT
+read_rtlil << EOT
 
 module \top
   wire width 5 input 0 \A

tests/proc/bug2962.ys

@@ -1,4 +1,4 @@
-read_ilang << EOT
+read_rtlil << EOT
 module \top
    wire width 4 input 1 \a
    wire width 2 input 2 \b

tests/proc/proc_rom.ys

@@ -188,7 +188,7 @@ equiv_opt -assert -run prepare: dummy
 
 design -reset
 
-read_ilang <<EOT
+read_rtlil <<EOT
 
 module \m
   wire width 3 input 1 \a

tests/rpc/frontend.py

@@ -5,7 +5,7 @@ def derive(module, parameters):
 	assert module == r"python_inv"
 	if parameters.keys() != {r"\width"}:
 		raise ValueError("Invalid parameters")
-	return "ilang", r"""
+	return "rtlil", r"""
 module \impl
 	wire width {width:d} input 1 \i
 	wire width {width:d} output 2 \o

tests/sat/bug2595.ys

@@ -1,4 +1,4 @@
-read_ilang <<EOT
+read_rtlil <<EOT
 module \top
   wire input 3 \A
   wire width 2 input 2 \B

tests/smv/run-single.sh

@@ -8,7 +8,7 @@ EOT
 cat > $1.ys <<EOT
 echo on
 
-read_ilang $1.il
+read_rtlil $1.il
 hierarchy; proc; opt
 rename -top uut
 design -save gold

tests/techmap/bmuxmap_pmux.ys

@@ -1,4 +1,4 @@
-read_ilang << EOT
+read_rtlil << EOT
 
 module \top
   wire width 4 input 0 \S
@@ -21,7 +21,7 @@ equiv_opt -assert bmuxmap -pmux
 ###
 design -reset
 
-read_ilang << EOT
+read_rtlil << EOT
 
 module \top
   wire width 10 input 0 \A

tests/various/autoname.ys

@@ -1,4 +1,4 @@
-read_ilang <<EOT
+read_rtlil <<EOT
 autoidx 2
 module \top
   wire output 3 $y

tests/various/bug1496.ys

@@ -1,4 +1,4 @@
-read_ilang << EOF
+read_rtlil << EOF
 module \top
   wire input 1 \A
   wire output 2 \Y

tests/various/equiv_opt_undef.ys

@@ -1,4 +1,4 @@
-read_ilang << EOT
+read_rtlil << EOT
 
 module \top
   wire $a

tests/verilog/assign_to_reg.ys

@@ -1,6 +1,6 @@
 # https://github.com/yosyshq/yosys/issues/2035
 
-read_ilang <<END
+read_rtlil <<END
 module \top
   wire width 1 input 0 \halfbrite
   wire width 2 output 1 \r_on