@@ -1588,7 +1588,7 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
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if (DstTy != LLT::vector (2 , 16 ))
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break ;
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- assert (MI.getNumOperands () == 3 && empty ( OpdMapper.getVRegs (0 )));
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+ assert (MI.getNumOperands () == 3 && OpdMapper.getVRegs (0 ). empty ( ));
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substituteSimpleCopyRegs (OpdMapper, 1 );
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substituteSimpleCopyRegs (OpdMapper, 2 );
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@@ -1644,7 +1644,7 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
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case AMDGPU::G_EXTRACT_VECTOR_ELT: {
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SmallVector<Register, 2 > DstRegs (OpdMapper.getVRegs (0 ));
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- assert (empty ( OpdMapper.getVRegs (1 )) && empty ( OpdMapper.getVRegs (2 )));
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+ assert (OpdMapper.getVRegs (1 ). empty ( ) && OpdMapper.getVRegs (2 ). empty ( ));
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if (DstRegs.empty ()) {
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applyDefaultMapping (OpdMapper);
@@ -1708,9 +1708,9 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
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case AMDGPU::G_INSERT_VECTOR_ELT: {
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SmallVector<Register, 2 > InsRegs (OpdMapper.getVRegs (2 ));
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- assert (empty ( OpdMapper.getVRegs (0 )));
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- assert (empty ( OpdMapper.getVRegs (1 )));
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- assert (empty ( OpdMapper.getVRegs (3 )));
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+ assert (OpdMapper.getVRegs (0 ). empty ( ));
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+ assert (OpdMapper.getVRegs (1 ). empty ( ));
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+ assert (OpdMapper.getVRegs (3 ). empty ( ));
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if (InsRegs.empty ()) {
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applyDefaultMapping (OpdMapper);
@@ -1785,18 +1785,18 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
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case Intrinsic::amdgcn_readlane: {
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substituteSimpleCopyRegs (OpdMapper, 2 );
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- assert (empty ( OpdMapper.getVRegs (0 )));
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- assert (empty ( OpdMapper.getVRegs (3 )));
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+ assert (OpdMapper.getVRegs (0 ). empty ( ));
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+ assert (OpdMapper.getVRegs (3 ). empty ( ));
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// Make sure the index is an SGPR. It doesn't make sense to run this in a
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// waterfall loop, so assume it's a uniform value.
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constrainOpWithReadfirstlane (MI, MRI, 3 ); // Index
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return ;
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}
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case Intrinsic::amdgcn_writelane: {
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- assert (empty ( OpdMapper.getVRegs (0 )));
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- assert (empty ( OpdMapper.getVRegs (2 )));
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- assert (empty ( OpdMapper.getVRegs (3 )));
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+ assert (OpdMapper.getVRegs (0 ). empty ( ));
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+ assert (OpdMapper.getVRegs (2 ). empty ( ));
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+ assert (OpdMapper.getVRegs (3 ). empty ( ));
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substituteSimpleCopyRegs (OpdMapper, 4 ); // VGPR input val
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constrainOpWithReadfirstlane (MI, MRI, 2 ); // Source value
@@ -1818,7 +1818,7 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
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case Intrinsic::amdgcn_ds_ordered_add:
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case Intrinsic::amdgcn_ds_ordered_swap: {
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// This is only allowed to execute with 1 lane, so readfirstlane is safe.
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- assert (empty ( OpdMapper.getVRegs (0 )));
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+ assert (OpdMapper.getVRegs (0 ). empty ( ));
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substituteSimpleCopyRegs (OpdMapper, 3 );
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constrainOpWithReadfirstlane (MI, MRI, 2 ); // M0
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return ;
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