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Signed-off-by: Istvan-Zsolt Szekely <[email protected]>
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‎README.md

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This repository contains testbenches and verification components for system level projects or components connected at block level from the [hdl](https://github.com/analogdevicesinc/hdl) repository.
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This repository is not a stand alone one. It must be cloned or linked as a submodule inside the [hdl](https://github.com/analogdevicesinc/hdl) repository you want to test.
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This repository is not a stand alone one. It must be cloned or linked as a submodule inside the [hdl](https://github.com/analogdevicesinc/hdl) repository you want to test.
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The folder structure of the hdl will look as follows:
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hdl
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- projects
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- library
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- testbenches
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## Setup
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The testbenches are built around Xilinx verification IPs so it requires Vivado to be set up according to the hdl repository requirenments.
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The testbenches are built around Xilinx verification IPs so it requires Vivado to be set up according to the hdl repository requirenments.
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Running the testbenches relies on the build mechanism from the hdl repository, make sure you have a proper setup for Xilinx flow described [here](https://wiki.analog.com/resources/fpga/docs/build)
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## Running a testbench:
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Change the workig directory to the testbench you want to run:
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Change the workig directory to the testbench you want to run:
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cd testbenches/fmcomms2
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The scripts first will build all components used from the hdl library, build the block design environment based on a configuration file that describes parameters of under test block, then will actually run the test.
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These steps are separated in ordrer to be able to run multiple tests on the same configuration without rebuilding the block desing every time.
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The scripts first will build all components used from the hdl library, build the block design environment based on a configuration file that describes parameters of under test block, then will actually run the test.
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These steps are separated in ordrer to be able to run multiple tests on the same configuration without rebuilding the block desing every time.
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### Run all tests in batch mode:
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‎docs/library/drivers/common/watchdog/index.rst

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system hanging. In this case it is more advisable have a watchdog timer
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stopped and started or reset each time a repetitive task is completed. This
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allows for a stricter watchdog timer value, which may stop a hanging
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simulation sooner without waiting for the whole process to finish.
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simulation sooner without waiting for the whole process to finish.
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.. include:: ../../../../common/support.rst

‎docs/library/index.rst

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Library
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===============================================================================
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Drivers
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-------------------------------------------------------------------------------
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:maxdepth: 1
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vip/index
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‎docs/library/vip/amd/axi_vip/adi_axi_agent.rst

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Overview
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-------------------------------------------------------------------------------
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The ADI AXI Agent uses the AMD (Xilinx) AXI VIP at its core with added
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The ADI AXI Agent uses the AMD (Xilinx) AXI VIP at its core with added
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sequencer, monitor and wrapper class. Has a master, slave and passthrough
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variant. Provides functions to start, stop and run the classes within. Its
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purpose is to create and contain everything under a single construct and not

‎docs/library/vip/amd/axi_vip/index.rst

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Overview
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-------------------------------------------------------------------------------
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The ADI AXI Agent uses the AMD (Xilinx) AXI VIP at its core with added
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The ADI AXI Agent uses the AMD (Xilinx) AXI VIP at its core with added
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sequencer, monitor and wrapper class.
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`[1] <https://docs.amd.com/r/en-US/pg267-axi-vip>`__
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‎docs/library/vip/amd/axis_vip/adi_axis_agent.rst

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Overview
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-------------------------------------------------------------------------------
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The ADI AXIS Agent uses the AMD (Xilinx) AXIS VIP at its core with added
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The ADI AXIS Agent uses the AMD (Xilinx) AXIS VIP at its core with added
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sequencer, monitor and wrapper class. Has a master, slave and passthrough
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variant. Provides functions to start, stop and run the classes within. Its
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purpose is to create and contain everything under a single construct and not

‎docs/library/vip/amd/axis_vip/index.rst

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Overview
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--------------------------------------------------------------------------------
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The ADI AXIS Agent VIP uses the AMD (Xilinx) AXIS VIP at its core with added
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The ADI AXIS Agent VIP uses the AMD (Xilinx) AXIS VIP at its core with added
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sequencer, monitor and wrapper class.
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`[1] <https://docs.amd.com/v/u/en-US/pg277-axi4stream-vip>`__
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‎docs/testbenches/common/dependency_common.rst

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.. list-table::
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:widths: 30 45 25
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:header-rows: 1
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* - SV dependency name
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- Source code link
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- Documentation link

‎docs/testbenches/ip_based/util_pack/index.rst

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.. note::
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The max width is calculated with: CHANNELS*SAMPLES*WIDTH and it cannot
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exceed 2048.
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exceed 2048.
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Build parameters
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

‎docs/testbenches/project_based/ad463x/index.rst

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Build parameters
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The parameters mentioned above can be configured when starting the build, like in
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the following example:
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.. shell::
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:showuser:
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$make CLK_MODE=0 NUM_OF_SDI=2 CAPTURE_ZONE=1 DDR_EN=0
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but we recommend using the already tested build configuration modes, that can be
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found in the ``cfg`` section.
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Configuration files
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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This test is used to check the communication with the AXI REGMAP module of the
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AD463X SPI Engine interface, by reading the core VERSION register, along with
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AD463X SPI Engine interface, by reading the core VERSION register, along with
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writing and reading the SCRATCH register.
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FIFO SPI test
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.. list-table::
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* - SV dependency name
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- Source code link
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- Documentation link

‎docs/testbenches/project_based/ad738x/index.rst

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- NUM_OF_SDI: defines the number of MOSI lines of the SPI interface:
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Options: 1 - Interleaved mode, 2 - 1 lane per channel,
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4 - 2 lanes per channel
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Build parameters
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The parameters mentioned above can be configured when starting the build, like in
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$make ALERT_SPI_N=0 NUM_OF_SDI=2
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but we recommend using the already tested build configuration modes, that can be
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Configuration files
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| | ALERT_SPI_N | NUM_OF_SDI |
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+=======================+=============+============+
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| cfg1 | 0 | 2 |
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+-----------------------+-------------+------------+
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Tests
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This test is used to check the communication with the AXI REGMAP module of the
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FIFO SPI test
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* - SV dependency name
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- Source code link
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- Documentation link

‎docs/testbenches/project_based/ad7606/index.rst

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- NUM_OF_SDI: defines the number of MOSI lines of the SPI interface:
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+-----------------------+------------+---------+------+------------+
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| cfg3 | 2 | 0 | 0 | 1 |
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+-----------------------+------------+---------+------+------------+
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.. admonition:: Legend
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‎docs/testbenches/project_based/ad7616/index.rst

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.. image:: ./ad7616_si_tb.svg
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:alt: AD7616 Serial Interface/Testbench block diagram
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‎docs/testbenches/project_based/fmcomms2/index.rst

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Tests
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- ---
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- ---

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