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spi_engine: update for hdl 1.4.0
Signed-off-by: Laez Barbosa <[email protected]>
1 parent bb7e91b commit 673b70a

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15 files changed

+991
-29
lines changed

15 files changed

+991
-29
lines changed

‎library/regmaps/adi_regmap_spi_engine_pkg.sv

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@
3333
// ***************************************************************************
3434
// ***************************************************************************
3535
/* Auto generated Register Map */
36-
/* Wed Jul 24 09:28:37 2024 */
36+
/* Wed Jan 29 16:40:28 2025 */
3737

3838
package adi_regmap_spi_engine_pkg;
3939
import adi_regmap_pkg::*;
@@ -43,8 +43,8 @@ package adi_regmap_spi_engine_pkg;
4343

4444
const reg_t AXI_SPI_ENGINE_VERSION = '{ 'h0000, "VERSION" , '{
4545
"VERSION_MAJOR": '{ 31, 16, RO, 'h00000001 },
46-
"VERSION_MINOR": '{ 15, 8, RO, 'h00000003 },
47-
"VERSION_PATCH": '{ 7, 0, RO, 'h00000001 }}};
46+
"VERSION_MINOR": '{ 15, 8, RO, 'h00000004 },
47+
"VERSION_PATCH": '{ 7, 0, RO, 'h00000000 }}};
4848
`define SET_AXI_SPI_ENGINE_VERSION_VERSION_MAJOR(x) SetField(AXI_SPI_ENGINE_VERSION,"VERSION_MAJOR",x)
4949
`define GET_AXI_SPI_ENGINE_VERSION_VERSION_MAJOR(x) GetField(AXI_SPI_ENGINE_VERSION,"VERSION_MAJOR",x)
5050
`define DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_MAJOR GetResetValue(AXI_SPI_ENGINE_VERSION,"VERSION_MAJOR")
@@ -167,7 +167,7 @@ package adi_regmap_spi_engine_pkg;
167167
`define UPDATE_AXI_SPI_ENGINE_IRQ_SOURCE_IRQ_SOURCE(x,y) UpdateField(AXI_SPI_ENGINE_IRQ_SOURCE,"IRQ_SOURCE",x,y)
168168

169169
const reg_t AXI_SPI_ENGINE_SYNC_ID = '{ 'h00c0, "SYNC_ID" , '{
170-
"SYNC_ID": '{ 31, 0, RO, 'hXXXXXXXX }}};
170+
"SYNC_ID": '{ 31, 0, RO, 'h00 }}};
171171
`define SET_AXI_SPI_ENGINE_SYNC_ID_SYNC_ID(x) SetField(AXI_SPI_ENGINE_SYNC_ID,"SYNC_ID",x)
172172
`define GET_AXI_SPI_ENGINE_SYNC_ID_SYNC_ID(x) GetField(AXI_SPI_ENGINE_SYNC_ID,"SYNC_ID",x)
173173
`define DEFAULT_AXI_SPI_ENGINE_SYNC_ID_SYNC_ID GetResetValue(AXI_SPI_ENGINE_SYNC_ID,"SYNC_ID")
@@ -202,35 +202,35 @@ package adi_regmap_spi_engine_pkg;
202202
`define UPDATE_AXI_SPI_ENGINE_SDI_FIFO_LEVEL_SDI_FIFO_LEVEL(x,y) UpdateField(AXI_SPI_ENGINE_SDI_FIFO_LEVEL,"SDI_FIFO_LEVEL",x,y)
203203

204204
const reg_t AXI_SPI_ENGINE_CMD_FIFO = '{ 'h00e0, "CMD_FIFO" , '{
205-
"CMD_FIFO": '{ 31, 0, WO, 'hXXXXXXXX }}};
205+
"CMD_FIFO": '{ 31, 0, WO, 'h00 }}};
206206
`define SET_AXI_SPI_ENGINE_CMD_FIFO_CMD_FIFO(x) SetField(AXI_SPI_ENGINE_CMD_FIFO,"CMD_FIFO",x)
207207
`define GET_AXI_SPI_ENGINE_CMD_FIFO_CMD_FIFO(x) GetField(AXI_SPI_ENGINE_CMD_FIFO,"CMD_FIFO",x)
208208
`define DEFAULT_AXI_SPI_ENGINE_CMD_FIFO_CMD_FIFO GetResetValue(AXI_SPI_ENGINE_CMD_FIFO,"CMD_FIFO")
209209
`define UPDATE_AXI_SPI_ENGINE_CMD_FIFO_CMD_FIFO(x,y) UpdateField(AXI_SPI_ENGINE_CMD_FIFO,"CMD_FIFO",x,y)
210210

211211
const reg_t AXI_SPI_ENGINE_SDO_FIFO = '{ 'h00e4, "SDO_FIFO" , '{
212-
"SDO_FIFO": '{ 31, 0, WO, 'hXXXXXXXX }}};
212+
"SDO_FIFO": '{ 31, 0, WO, 'h00 }}};
213213
`define SET_AXI_SPI_ENGINE_SDO_FIFO_SDO_FIFO(x) SetField(AXI_SPI_ENGINE_SDO_FIFO,"SDO_FIFO",x)
214214
`define GET_AXI_SPI_ENGINE_SDO_FIFO_SDO_FIFO(x) GetField(AXI_SPI_ENGINE_SDO_FIFO,"SDO_FIFO",x)
215215
`define DEFAULT_AXI_SPI_ENGINE_SDO_FIFO_SDO_FIFO GetResetValue(AXI_SPI_ENGINE_SDO_FIFO,"SDO_FIFO")
216216
`define UPDATE_AXI_SPI_ENGINE_SDO_FIFO_SDO_FIFO(x,y) UpdateField(AXI_SPI_ENGINE_SDO_FIFO,"SDO_FIFO",x,y)
217217

218218
const reg_t AXI_SPI_ENGINE_SDI_FIFO = '{ 'h00e8, "SDI_FIFO" , '{
219-
"SDI_FIFO": '{ 31, 0, RO, 'hXXXXXXXX }}};
219+
"SDI_FIFO": '{ 31, 0, RO, 'h00 }}};
220220
`define SET_AXI_SPI_ENGINE_SDI_FIFO_SDI_FIFO(x) SetField(AXI_SPI_ENGINE_SDI_FIFO,"SDI_FIFO",x)
221221
`define GET_AXI_SPI_ENGINE_SDI_FIFO_SDI_FIFO(x) GetField(AXI_SPI_ENGINE_SDI_FIFO,"SDI_FIFO",x)
222222
`define DEFAULT_AXI_SPI_ENGINE_SDI_FIFO_SDI_FIFO GetResetValue(AXI_SPI_ENGINE_SDI_FIFO,"SDI_FIFO")
223223
`define UPDATE_AXI_SPI_ENGINE_SDI_FIFO_SDI_FIFO(x,y) UpdateField(AXI_SPI_ENGINE_SDI_FIFO,"SDI_FIFO",x,y)
224224

225225
const reg_t AXI_SPI_ENGINE_SDI_FIFO_MSB = '{ 'h00ec, "SDI_FIFO_MSB" , '{
226-
"SDI_FIFO_MSB": '{ 31, 0, RO, 'hXXXXXXXX }}};
226+
"SDI_FIFO_MSB": '{ 31, 0, RO, 0 }}};
227227
`define SET_AXI_SPI_ENGINE_SDI_FIFO_MSB_SDI_FIFO_MSB(x) SetField(AXI_SPI_ENGINE_SDI_FIFO_MSB,"SDI_FIFO_MSB",x)
228228
`define GET_AXI_SPI_ENGINE_SDI_FIFO_MSB_SDI_FIFO_MSB(x) GetField(AXI_SPI_ENGINE_SDI_FIFO_MSB,"SDI_FIFO_MSB",x)
229229
`define DEFAULT_AXI_SPI_ENGINE_SDI_FIFO_MSB_SDI_FIFO_MSB GetResetValue(AXI_SPI_ENGINE_SDI_FIFO_MSB,"SDI_FIFO_MSB")
230230
`define UPDATE_AXI_SPI_ENGINE_SDI_FIFO_MSB_SDI_FIFO_MSB(x,y) UpdateField(AXI_SPI_ENGINE_SDI_FIFO_MSB,"SDI_FIFO_MSB",x,y)
231231

232232
const reg_t AXI_SPI_ENGINE_SDI_FIFO_PEEK = '{ 'h00f0, "SDI_FIFO_PEEK" , '{
233-
"SDI_FIFO_PEEK": '{ 31, 0, RO, 'hXXXXXXXX }}};
233+
"SDI_FIFO_PEEK": '{ 31, 0, RO, 'h00 }}};
234234
`define SET_AXI_SPI_ENGINE_SDI_FIFO_PEEK_SDI_FIFO_PEEK(x) SetField(AXI_SPI_ENGINE_SDI_FIFO_PEEK,"SDI_FIFO_PEEK",x)
235235
`define GET_AXI_SPI_ENGINE_SDI_FIFO_PEEK_SDI_FIFO_PEEK(x) GetField(AXI_SPI_ENGINE_SDI_FIFO_PEEK,"SDI_FIFO_PEEK",x)
236236
`define DEFAULT_AXI_SPI_ENGINE_SDI_FIFO_PEEK_SDI_FIFO_PEEK GetResetValue(AXI_SPI_ENGINE_SDI_FIFO_PEEK,"SDI_FIFO_PEEK")
@@ -258,14 +258,14 @@ package adi_regmap_spi_engine_pkg;
258258
`define UPDATE_AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET_OFFLOAD0_MEM_RESET(x,y) UpdateField(AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET,"OFFLOAD0_MEM_RESET",x,y)
259259

260260
const reg_t AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO = '{ 'h0110, "OFFLOAD0_CDM_FIFO" , '{
261-
"OFFLOAD0_CDM_FIFO": '{ 31, 0, WO, 'hXXXXXXXX }}};
261+
"OFFLOAD0_CDM_FIFO": '{ 31, 0, WO, 'h00 }}};
262262
`define SET_AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO_OFFLOAD0_CDM_FIFO(x) SetField(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO,"OFFLOAD0_CDM_FIFO",x)
263263
`define GET_AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO_OFFLOAD0_CDM_FIFO(x) GetField(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO,"OFFLOAD0_CDM_FIFO",x)
264264
`define DEFAULT_AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO_OFFLOAD0_CDM_FIFO GetResetValue(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO,"OFFLOAD0_CDM_FIFO")
265265
`define UPDATE_AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO_OFFLOAD0_CDM_FIFO(x,y) UpdateField(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO,"OFFLOAD0_CDM_FIFO",x,y)
266266

267267
const reg_t AXI_SPI_ENGINE_OFFLOAD0_SDO_FIFO = '{ 'h0114, "OFFLOAD0_SDO_FIFO" , '{
268-
"OFFLOAD0_SDO_FIFO": '{ 31, 0, WO, 'hXXXXXXXX }}};
268+
"OFFLOAD0_SDO_FIFO": '{ 31, 0, WO, 'h00 }}};
269269
`define SET_AXI_SPI_ENGINE_OFFLOAD0_SDO_FIFO_OFFLOAD0_SDO_FIFO(x) SetField(AXI_SPI_ENGINE_OFFLOAD0_SDO_FIFO,"OFFLOAD0_SDO_FIFO",x)
270270
`define GET_AXI_SPI_ENGINE_OFFLOAD0_SDO_FIFO_OFFLOAD0_SDO_FIFO(x) GetField(AXI_SPI_ENGINE_OFFLOAD0_SDO_FIFO,"OFFLOAD0_SDO_FIFO",x)
271271
`define DEFAULT_AXI_SPI_ENGINE_OFFLOAD0_SDO_FIFO_OFFLOAD0_SDO_FIFO GetResetValue(AXI_SPI_ENGINE_OFFLOAD0_SDO_FIFO,"OFFLOAD0_SDO_FIFO")

‎testbenches/ip/spi_engine/cfgs/cfg00.tcl

Lines changed: 58 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,58 @@
1+
global ad_project_params
2+
3+
# SPI Engine DUT parameters
4+
set ad_project_params(DATA_WIDTH) 32
5+
set ad_project_params(ASYNC_SPI_CLK) 1
6+
set ad_project_params(NUM_OF_CS) 1
7+
set ad_project_params(NUM_OF_SDI) 1
8+
set ad_project_params(NUM_OF_SDO) 1
9+
set ad_project_params(SDI_DELAY) 1
10+
set ad_project_params(ECHO_SCLK) 0
11+
set ad_project_params(CMD_MEM_ADDR_WIDTH) 4
12+
set ad_project_params(DATA_MEM_ADDR_WIDTH) 4
13+
set ad_project_params(SDI_FIFO_ADDR_WIDTH) 5
14+
set ad_project_params(SDO_FIFO_ADDR_WIDTH) 5
15+
set ad_project_params(SYNC_FIFO_ADDR_WIDTH) 4
16+
set ad_project_params(CMD_FIFO_ADDR_WIDTH) 4
17+
set ad_project_params(SDO_STREAMING) 0
18+
19+
# Test parameters
20+
set ad_project_params(DATA_DLENGTH) 16
21+
set ad_project_params(THREE_WIRE) 0
22+
set ad_project_params(CPOL) 0
23+
set ad_project_params(CPHA) 0
24+
set ad_project_params(SDO_IDLE_STATE) 0
25+
set ad_project_params(SLAVE_TIN) 0
26+
set ad_project_params(SLAVE_TOUT) 0
27+
set ad_project_params(MASTER_TIN) 0
28+
set ad_project_params(MASTER_TOUT) 0
29+
set ad_project_params(CS_TO_MISO) 0
30+
set ad_project_params(CLOCK_DIVIDER) 2
31+
set ad_project_params(NUM_OF_WORDS) 5
32+
set ad_project_params(NUM_OF_TRANSFERS) 5
33+
set ad_project_params(CS_ACTIVE_HIGH) 0
34+
set ad_project_params(ECHO_SCLK_DELAY) 0.1
35+
36+
set spi_s_vip_cfg [ list \
37+
MODE 0 \
38+
CPOL $ad_project_params(CPOL) \
39+
CPHA $ad_project_params(CPHA) \
40+
INV_CS $ad_project_params(CS_ACTIVE_HIGH) \
41+
SLAVE_TIN $ad_project_params(SLAVE_TIN) \
42+
SLAVE_TOUT $ad_project_params(SLAVE_TOUT) \
43+
MASTER_TIN $ad_project_params(MASTER_TIN) \
44+
MASTER_TOUT $ad_project_params(MASTER_TOUT) \
45+
CS_TO_MISO $ad_project_params(CS_TO_MISO) \
46+
DATA_DLENGTH $ad_project_params(DATA_DLENGTH) \
47+
]
48+
set ad_project_params(spi_s_vip_cfg) $spi_s_vip_cfg
49+
50+
set axis_sdo_src_vip_cfg [ list \
51+
INTERFACE_MODE {MASTER} \
52+
HAS_TREADY 1 \
53+
HAS_TLAST 0 \
54+
TDATA_NUM_BYTES [expr $ad_project_params(DATA_WIDTH)/8] \
55+
TDEST_WIDTH 0 \
56+
TID_WIDTH 0 \
57+
]
58+
set ad_project_params(axis_sdo_src_vip_cfg) $axis_sdo_src_vip_cfg

‎testbenches/ip/spi_engine/cfgs/cfg1.tcl renamed to ‎testbenches/ip/spi_engine/cfgs/cfg01.tcl

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,6 @@ set ad_project_params(NUM_OF_WORDS) 3
3232
set ad_project_params(NUM_OF_TRANSFERS) 5
3333
set ad_project_params(CS_ACTIVE_HIGH) 0
3434
set ad_project_params(ECHO_SCLK_DELAY) 0.1
35-
set ad_project_params(SDO_MEM_WORDS) 1
3635

3736
set spi_s_vip_cfg [ list \
3837
MODE 0 \

‎testbenches/ip/spi_engine/cfgs/cfg10.tcl

Lines changed: 58 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,58 @@
1+
global ad_project_params
2+
3+
# SPI Engine DUT parameters
4+
set ad_project_params(DATA_WIDTH) 32
5+
set ad_project_params(ASYNC_SPI_CLK) 1
6+
set ad_project_params(NUM_OF_CS) 1
7+
set ad_project_params(NUM_OF_SDI) 1
8+
set ad_project_params(NUM_OF_SDO) 1
9+
set ad_project_params(SDI_DELAY) 1
10+
set ad_project_params(ECHO_SCLK) 0
11+
set ad_project_params(CMD_MEM_ADDR_WIDTH) 4
12+
set ad_project_params(DATA_MEM_ADDR_WIDTH) 4
13+
set ad_project_params(SDI_FIFO_ADDR_WIDTH) 5
14+
set ad_project_params(SDO_FIFO_ADDR_WIDTH) 5
15+
set ad_project_params(SYNC_FIFO_ADDR_WIDTH) 4
16+
set ad_project_params(CMD_FIFO_ADDR_WIDTH) 4
17+
set ad_project_params(SDO_STREAMING) 0
18+
19+
# Test parameters
20+
set ad_project_params(DATA_DLENGTH) 18
21+
set ad_project_params(THREE_WIRE) 0
22+
set ad_project_params(CPOL) 1
23+
set ad_project_params(CPHA) 0
24+
set ad_project_params(SDO_IDLE_STATE) 0
25+
set ad_project_params(SLAVE_TIN) 0
26+
set ad_project_params(SLAVE_TOUT) 0
27+
set ad_project_params(MASTER_TIN) 0
28+
set ad_project_params(MASTER_TOUT) 0
29+
set ad_project_params(CS_TO_MISO) 0
30+
set ad_project_params(CLOCK_DIVIDER) 2
31+
set ad_project_params(NUM_OF_WORDS) 3
32+
set ad_project_params(NUM_OF_TRANSFERS) 5
33+
set ad_project_params(CS_ACTIVE_HIGH) 0
34+
set ad_project_params(ECHO_SCLK_DELAY) 0.1
35+
36+
set spi_s_vip_cfg [ list \
37+
MODE 0 \
38+
CPOL $ad_project_params(CPOL) \
39+
CPHA $ad_project_params(CPHA) \
40+
INV_CS $ad_project_params(CS_ACTIVE_HIGH) \
41+
SLAVE_TIN $ad_project_params(SLAVE_TIN) \
42+
SLAVE_TOUT $ad_project_params(SLAVE_TOUT) \
43+
MASTER_TIN $ad_project_params(MASTER_TIN) \
44+
MASTER_TOUT $ad_project_params(MASTER_TOUT) \
45+
CS_TO_MISO $ad_project_params(CS_TO_MISO) \
46+
DATA_DLENGTH $ad_project_params(DATA_DLENGTH) \
47+
]
48+
set ad_project_params(spi_s_vip_cfg) $spi_s_vip_cfg
49+
50+
set axis_sdo_src_vip_cfg [ list \
51+
INTERFACE_MODE {MASTER} \
52+
HAS_TREADY 1 \
53+
HAS_TLAST 0 \
54+
TDATA_NUM_BYTES [expr $ad_project_params(DATA_WIDTH)/8] \
55+
TDEST_WIDTH 0 \
56+
TID_WIDTH 0 \
57+
]
58+
set ad_project_params(axis_sdo_src_vip_cfg) $axis_sdo_src_vip_cfg

‎testbenches/ip/spi_engine/cfgs/cfg11.tcl

Lines changed: 58 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,58 @@
1+
global ad_project_params
2+
3+
# SPI Engine DUT parameters
4+
set ad_project_params(DATA_WIDTH) 32
5+
set ad_project_params(ASYNC_SPI_CLK) 1
6+
set ad_project_params(NUM_OF_CS) 1
7+
set ad_project_params(NUM_OF_SDI) 1
8+
set ad_project_params(NUM_OF_SDO) 1
9+
set ad_project_params(SDI_DELAY) 1
10+
set ad_project_params(ECHO_SCLK) 0
11+
set ad_project_params(CMD_MEM_ADDR_WIDTH) 4
12+
set ad_project_params(DATA_MEM_ADDR_WIDTH) 4
13+
set ad_project_params(SDI_FIFO_ADDR_WIDTH) 5
14+
set ad_project_params(SDO_FIFO_ADDR_WIDTH) 5
15+
set ad_project_params(SYNC_FIFO_ADDR_WIDTH) 4
16+
set ad_project_params(CMD_FIFO_ADDR_WIDTH) 4
17+
set ad_project_params(SDO_STREAMING) 0
18+
19+
# Test parameters
20+
set ad_project_params(DATA_DLENGTH) 18
21+
set ad_project_params(THREE_WIRE) 0
22+
set ad_project_params(CPOL) 1
23+
set ad_project_params(CPHA) 1
24+
set ad_project_params(SDO_IDLE_STATE) 0
25+
set ad_project_params(SLAVE_TIN) 0
26+
set ad_project_params(SLAVE_TOUT) 0
27+
set ad_project_params(MASTER_TIN) 0
28+
set ad_project_params(MASTER_TOUT) 0
29+
set ad_project_params(CS_TO_MISO) 0
30+
set ad_project_params(CLOCK_DIVIDER) 2
31+
set ad_project_params(NUM_OF_WORDS) 3
32+
set ad_project_params(NUM_OF_TRANSFERS) 5
33+
set ad_project_params(CS_ACTIVE_HIGH) 0
34+
set ad_project_params(ECHO_SCLK_DELAY) 0.1
35+
36+
set spi_s_vip_cfg [ list \
37+
MODE 0 \
38+
CPOL $ad_project_params(CPOL) \
39+
CPHA $ad_project_params(CPHA) \
40+
INV_CS $ad_project_params(CS_ACTIVE_HIGH) \
41+
SLAVE_TIN $ad_project_params(SLAVE_TIN) \
42+
SLAVE_TOUT $ad_project_params(SLAVE_TOUT) \
43+
MASTER_TIN $ad_project_params(MASTER_TIN) \
44+
MASTER_TOUT $ad_project_params(MASTER_TOUT) \
45+
CS_TO_MISO $ad_project_params(CS_TO_MISO) \
46+
DATA_DLENGTH $ad_project_params(DATA_DLENGTH) \
47+
]
48+
set ad_project_params(spi_s_vip_cfg) $spi_s_vip_cfg
49+
50+
set axis_sdo_src_vip_cfg [ list \
51+
INTERFACE_MODE {MASTER} \
52+
HAS_TREADY 1 \
53+
HAS_TLAST 0 \
54+
TDATA_NUM_BYTES [expr $ad_project_params(DATA_WIDTH)/8] \
55+
TDEST_WIDTH 0 \
56+
TID_WIDTH 0 \
57+
]
58+
set ad_project_params(axis_sdo_src_vip_cfg) $axis_sdo_src_vip_cfg

‎testbenches/ip/spi_engine/cfgs/cfg_inv_cs.tcl

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,6 @@ set ad_project_params(NUM_OF_WORDS) 3
3232
set ad_project_params(NUM_OF_TRANSFERS) 5
3333
set ad_project_params(CS_ACTIVE_HIGH) 1
3434
set ad_project_params(ECHO_SCLK_DELAY) 0.1
35-
set ad_project_params(SDO_MEM_WORDS) 2
3635

3736
set spi_s_vip_cfg [ list \
3837
MODE 0 \

‎testbenches/ip/spi_engine/cfgs/cfg_sdo_streaming.tcl

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,6 @@ set ad_project_params(NUM_OF_WORDS) 5
3232
set ad_project_params(NUM_OF_TRANSFERS) 3
3333
set ad_project_params(CS_ACTIVE_HIGH) 0
3434
set ad_project_params(ECHO_SCLK_DELAY) 0.1
35-
set ad_project_params(SDO_MEM_WORDS) 2
3635

3736
set spi_s_vip_cfg [ list \
3837
MODE 0 \

‎testbenches/ip/spi_engine/system_project.tcl

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@ adi_sim_project_files [list \
2727
"spi_environment.sv" \
2828
"tests/test_program.sv" \
2929
"tests/test_sleep_delay.sv" \
30+
"tests/test_slowdata.sv" \
3031
]
3132

3233
#set a default test program

‎testbenches/ip/spi_engine/tests/test_program.sv

Lines changed: 12 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// ***************************************************************************
22
// ***************************************************************************
3-
// Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
3+
// Copyright (C) 2023-2025 Analog Devices, Inc. All rights reserved.
44
//
55
// In this HDL repository, there are many different and unique modules, consisting
66
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -274,8 +274,6 @@ bit [`DATA_DLENGTH-1:0] sdi_read_data_store [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)
274274
bit [`DATA_DLENGTH-1:0] sdo_write_data_store [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1 :0];
275275
bit [`DATA_DLENGTH-1:0] rx_data;
276276
bit [`DATA_DLENGTH-1:0] tx_data;
277-
localparam sdo_mem_num = (`SDO_STREAMING) ? (`MIN((`NUM_OF_WORDS),(`SDO_MEM_WORDS))) : (`NUM_OF_WORDS);
278-
bit [`DATA_DLENGTH-1:0] one_shot_sdo_data [sdo_mem_num-1 :0] = '{default:'0};
279277

280278
task offload_spi_test();
281279
//Configure DMA
@@ -301,21 +299,21 @@ task offload_spi_test();
301299
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_SYNC | 2);
302300

303301
// Enqueue transfers transfers to DUT
304-
for (int i = 0; i<sdo_mem_num; i=i+1) begin
305-
one_shot_sdo_data[i] = $urandom;
306-
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_SDO_FIFO), one_shot_sdo_data[i]);
307-
end
308302
for (int i = 0; i<((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)) ; i=i+1) begin
309303
rx_data = $urandom;
310304
spi_send(rx_data);
311-
sdi_read_data_store[i] = rx_data;
312-
if (i%(`NUM_OF_WORDS)<sdo_mem_num) begin
313-
tx_data = one_shot_sdo_data[i%(`NUM_OF_WORDS)];
314-
end else begin
315-
tx_data = $urandom;
305+
sdi_read_data_store[i] = rx_data; tx_data = $urandom;
306+
`ifdef DEF_SDO_STREAMING
316307
sdo_stream_gen(tx_data);
317-
end
318-
sdo_write_data_store[i] = tx_data;
308+
sdo_write_data_store[i] = tx_data;
309+
`else
310+
if (i<(`NUM_OF_WORDS)) begin
311+
sdo_write_data_store[i] = tx_data;
312+
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_SDO_FIFO), sdo_write_data_store[i]);
313+
end else begin
314+
sdo_write_data_store[i] = sdo_write_data_store[i%(`NUM_OF_WORDS)];
315+
end
316+
`endif
319317
end
320318

321319
// Start the offload

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