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pwm_gen: Initial commit
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‎pwm_gen/Makefile

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####################################################################################
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####################################################################################
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## Copyright 2023(c) Analog Devices, Inc.
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####################################################################################
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####################################################################################
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# All test-bench dependencies except test programs
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SV_DEPS += ../common/sv/utils.svh
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SV_DEPS += ../common/sv/logger_pkg.sv
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SV_DEPS += ../common/sv/reg_accessor.sv
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SV_DEPS += ../common/sv/m_axis_sequencer.sv
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SV_DEPS += ../common/sv/s_axis_sequencer.sv
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SV_DEPS += ../common/sv/m_axi_sequencer.sv
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SV_DEPS += ../common/sv/s_axi_sequencer.sv
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SV_DEPS += ../common/sv/adi_regmap_pkg.sv
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SV_DEPS += ../common/sv/adi_regmap_common_pkg.sv
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SV_DEPS += ../common/sv/adi_regmap_pwm_gen_pkg.sv
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SV_DEPS += ../common/sv/test_harness_env.sv
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SV_DEPS += system_tb.sv
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ENV_DEPS +=../../library/util_cdc/sync_bits.v
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ENV_DEPS +=../../library/common/ad_edge_detect.v
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ENV_DEPS += system_project.tcl
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ENV_DEPS += system_bd.tcl
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ENV_DEPS +=../scripts/adi_sim.tcl
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ENV_DEPS +=../scripts/run_sim.tcl
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LIB_DEPS += axi_pwm_gen
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# default test program
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TP := test_program
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# config files should have the following format
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# cfg_<param1>_<param2>.tcl
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CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl))
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#$(warning $(CFG_FILES))
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# List of tests and configuration combinations that has to be run
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# Format is: <configuration>:<test name>
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TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(cfg):$(TP))
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#TESTS += cfg1_mm2mm_default:directed_test
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#TESTS += cfg1:test_program
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#TESTS += cfg2_fsync:test_program
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#TESTS += cfg2_fsync:test_frame_delay
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include ../scripts/project-sim.mk
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# usage :
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#
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# run specific test on a specific configuration in gui mode
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# make CFG=cfg2_fsync TST=test_frame_delay MODE=gui
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#
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# run all test from a configuration
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# make cfg1_mm2mm_default
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####################################################################################
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####################################################################################

‎pwm_gen/README.md

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Usage :
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Run all tests in batch mode:
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make
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Run all tests in GUI mode:
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make MODE=gui
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Run specific test on a specific configuration in gui mode:
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make CFG=<name of cfg> TST=<name of test> MODE=gui
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Run all test from a configuration:
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make <name of cfg>
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Where:
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* <name of cfg> is a file from the cfgs directory without the tcl extension of format cfg\*
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* <name of test> is a file from the tests directory without the tcl extension
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‎pwm_gen/cfgs/cfg1.tcl

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global ad_project_params
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‎pwm_gen/system_bd.tcl

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# ***************************************************************************
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# ***************************************************************************
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# Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
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#
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# In this HDL repository, there are many different and unique modules, consisting
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# of various HDL (Verilog or VHDL) components. The individual modules are
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# developed independently, and may be accompanied by separate and unique license
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# terms.
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#
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# The user should read each of these license terms, and understand the
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# freedoms and responsibilities that he or she has by using this source/core.
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#
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# This core is distributed in the hope that it will be useful, but WITHOUT ANY
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# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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# A PARTICULAR PURPOSE.
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#
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# Redistribution and use of source or resulting binaries, with or without modification
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# of this file, are permitted under one of the following two license terms:
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#
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# 1. The GNU General Public License version 2 as published by the
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# Free Software Foundation, which can be found in the top level directory
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# of this repository (LICENSE_GPL2), and also online at:
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# <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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#
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# OR
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#
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# 2. An ADI specific BSD license, which can be found in the top level directory
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# of this repository (LICENSE_ADIBSD), and also on-line at:
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# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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# This will allow to generate bit files and not release the source code,
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# as long as it attaches to an ADI device.
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#
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# ***************************************************************************
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# ***************************************************************************
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source ../../scripts/adi_env.tcl
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# common zed-based bd for test
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#source ../../projects/common/zed/zed_system_bd.tcl
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# ------------------
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#
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# Block under test
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#
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# ------------------
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create_bd_port -dir O pwm_gen_o_0
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create_bd_port -dir O pwm_gen_o_1
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create_bd_port -dir O pwm_gen_o_2
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create_bd_port -dir O pwm_gen_o_3
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create_bd_port -dir O pwm_gen_o_4
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create_bd_port -dir O pwm_gen_o_5
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create_bd_port -dir O pwm_gen_o_6
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create_bd_port -dir O pwm_gen_o_7
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create_bd_port -dir O pwm_gen_o_8
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create_bd_port -dir O pwm_gen_o_9
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create_bd_port -dir O pwm_gen_o_10
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create_bd_port -dir O pwm_gen_o_11
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create_bd_port -dir O pwm_gen_o_12
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create_bd_port -dir O pwm_gen_o_13
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create_bd_port -dir O pwm_gen_o_14
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create_bd_port -dir O pwm_gen_o_15
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ad_ip_instance axi_pwm_gen dut_pwm_gen
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ad_ip_parameter dut_pwm_gen CONFIG.ASYNC_CLK_EN 1
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ad_ip_parameter dut_pwm_gen CONFIG.N_PWMS 16
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ad_connect ddr_clk_vip/clk_out dut_pwm_gen/ext_clk
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adi_project_files [list \
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"../../library/common/ad_edge_detect.v" \
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"../../library/util_cdc/sync_bits.v"]
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ad_connect pwm_gen_o_0 dut_pwm_gen/pwm_0
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ad_connect pwm_gen_o_1 dut_pwm_gen/pwm_1
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ad_connect pwm_gen_o_2 dut_pwm_gen/pwm_2
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ad_connect pwm_gen_o_3 dut_pwm_gen/pwm_3
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ad_connect pwm_gen_o_4 dut_pwm_gen/pwm_4
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ad_connect pwm_gen_o_5 dut_pwm_gen/pwm_5
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ad_connect pwm_gen_o_6 dut_pwm_gen/pwm_6
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ad_connect pwm_gen_o_7 dut_pwm_gen/pwm_7
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ad_connect pwm_gen_o_8 dut_pwm_gen/pwm_8
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ad_connect pwm_gen_o_9 dut_pwm_gen/pwm_9
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ad_connect pwm_gen_o_10 dut_pwm_gen/pwm_10
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ad_connect pwm_gen_o_11 dut_pwm_gen/pwm_11
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ad_connect pwm_gen_o_12 dut_pwm_gen/pwm_12
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ad_connect pwm_gen_o_13 dut_pwm_gen/pwm_13
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ad_connect pwm_gen_o_14 dut_pwm_gen/pwm_14
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ad_connect pwm_gen_o_15 dut_pwm_gen/pwm_15
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# connect resets
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ad_cpu_interconnect 0x7c000000 dut_pwm_gen
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create_bd_port -dir O sys_clk
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ad_connect sys_clk sys_cpu_clk

‎pwm_gen/system_project.tcl

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source ../scripts/adi_sim.tcl
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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if {$argc < 1} {
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puts "Expecting at least one argument that specifies the test configuration"
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exit 1
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} else {
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set cfg_file [lindex $argv 0]
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}
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# Read config file
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source "cfgs/${cfg_file}"
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# Set the project name
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set project_name [file rootname $cfg_file]
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# Create the project
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adi_sim_project_xilinx $project_name "xc7z020clg484-1"
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# Add test files to the project
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adi_sim_project_files [list \
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"../common/sv/utils.svh" \
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"../common/sv/logger_pkg.sv" \
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"../common/sv/reg_accessor.sv" \
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"../common/sv/m_axis_sequencer.sv" \
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"../common/sv/s_axis_sequencer.sv" \
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"../common/sv/m_axi_sequencer.sv" \
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"../common/sv/s_axi_sequencer.sv" \
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"../common/sv/adi_regmap_pkg.sv" \
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"../common/sv/adi_regmap_common_pkg.sv" \
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"../common/sv/adi_regmap_pwm_gen_pkg.sv" \
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"../common/sv/adi_peripheral_pkg.sv" \
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"../common/sv/test_harness_env.sv" \
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"tests/test_program.sv" \
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"system_tb.sv" \
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]
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#set a default test program
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adi_sim_add_define "TEST_PROGRAM=test_program"
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adi_sim_generate $project_name

‎pwm_gen/system_tb.sv

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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
8+
// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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`include "utils.svh"
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module system_tb();
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wire pwm_gen_o_0;
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wire pwm_gen_o_1;
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wire pwm_gen_o_2;
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wire pwm_gen_o_3;
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wire pwm_gen_o_4;
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wire pwm_gen_o_5;
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wire pwm_gen_o_6;
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wire pwm_gen_o_7;
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wire pwm_gen_o_8;
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wire pwm_gen_o_9;
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wire pwm_gen_o_10;
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wire pwm_gen_o_11;
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wire pwm_gen_o_12;
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wire pwm_gen_o_13;
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wire pwm_gen_o_14;
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wire pwm_gen_o_15;
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wire sys_clk;
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`TEST_PROGRAM test(
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.pwm_gen_o_0 (pwm_gen_o_0),
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.pwm_gen_o_1 (pwn_gen_o_1),
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.pwm_gen_o_2 (pwm_gen_o_2),
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.pwm_gen_o_3 (pwm_gen_o_3),
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.pwm_gen_o_4 (pwm_gen_o_4),
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.pwm_gen_o_5 (pwm_gen_o_5),
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.pwm_gen_o_6 (pwm_gen_o_6),
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.pwm_gen_o_7 (pwm_gen_o_7),
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.pwm_gen_o_8 (pwm_gen_o_8),
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.pwm_gen_o_9 (pwn_gen_o_9),
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.pwm_gen_o_10 (pwm_gen_o_10),
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.pwm_gen_o_11 (pwm_gen_o_11),
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.pwm_gen_o_12 (pwm_gen_o_12),
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.pwm_gen_o_13 (pwm_gen_o_13),
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.pwm_gen_o_14 (pwm_gen_o_14),
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.pwm_gen_o_15 (pwm_gen_o_15),
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.sys_clk (sys_clk));
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test_harness `TH (
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.pwm_gen_o_0 (pwm_gen_o_0),
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.pwm_gen_o_1 (pwn_gen_o_1),
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.pwm_gen_o_2 (pwm_gen_o_2),
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.pwm_gen_o_3 (pwm_gen_o_3),
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.pwm_gen_o_4 (pwm_gen_o_4),
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.pwm_gen_o_5 (pwm_gen_o_5),
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.pwm_gen_o_6 (pwm_gen_o_6),
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.pwm_gen_o_7 (pwm_gen_o_7),
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.pwm_gen_o_8 (pwm_gen_o_8),
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.pwm_gen_o_9 (pwn_gen_o_9),
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.pwm_gen_o_10 (pwm_gen_o_10),
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.pwm_gen_o_11 (pwm_gen_o_11),
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.pwm_gen_o_12 (pwm_gen_o_12),
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.pwm_gen_o_13 (pwm_gen_o_13),
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.pwm_gen_o_14 (pwm_gen_o_14),
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.pwm_gen_o_15 (pwm_gen_o_15),
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.sys_clk (sys_clk));
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endmodule

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