ad7606x: Updated testbenches (#144)

Signed-off-by: Istvan-Zsolt Szekely <[email protected]>

Author: IstvanZsSzekely

testbenches/project/ad7606x/system_bd.tcl

@@ -54,22 +54,20 @@ create_bd_port -dir O sys_clk
 
 ad_connect sys_clk sys_cpu_clk
 
-set BA_AD7606X 0x44A00000
-adi_sim_add_define "AXI_AD7606X_BA=[format "%d" ${BA_AD7606X}]"
-
-set BA_SPI_REGMAP 0x44A00000
-adi_sim_add_define "SPI_AD7606_REGMAP_BA=[format "%d" ${BA_SPI_REGMAP}]"
-
 if {$INTF == 0} {
+  set BA_AD7606X 0x44A00000
   set_property offset $BA_AD7606X [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_ad7606x}]
+  adi_sim_add_define "AXI_AD7606X_BA=[format "%d" ${BA_AD7606X}]"
 } else {
   create_bd_port -dir O spi_clk
   ad_connect spi_clk spi_clkgen/clk_0
 
   create_bd_port -dir O ad7606_irq
   ad_connect ad7606_irq spi_ad7606/irq
 
+  set BA_SPI_REGMAP 0x44A00000
   set_property offset $BA_SPI_REGMAP [get_bd_addr_segs {mng_axi_vip/Master_AXI/spi_ad7606_axi_regmap}]
+  adi_sim_add_define "SPI_AD7606_REGMAP_BA=[format "%d" ${BA_SPI_REGMAP}]"
 
   set BA_CLKGEN 0x44A70000
   set_property offset $BA_CLKGEN [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_spi_clkgen}]

testbenches/project/ad7606x/system_project.tcl

@@ -13,14 +13,6 @@ source "cfgs/${cfg_file}"
 # Set the project name
 set project_name [file rootname $cfg_file]
 
-# Set project params
-
-global ad_project_params
-
-set INTF $ad_project_params(INTF)
-set ADC_N_BITS $ad_project_params(ADC_N_BITS)
-set NUM_OF_SDI $ad_project_params(NUM_OF_SDI)
-
 #set a default test program
 adi_sim_add_define "TEST_PROGRAM=test_program_si"
 

testbenches/project/ad7606x/system_tb.sv

@@ -60,9 +60,6 @@ module system_tb();
 
     wire [4:0] num_chs;
 
-    parameter ADC_N_BITS = 16;
-    localparam NEG_EDGE = 1;
-
     `TEST_PROGRAM test(
       .adc_config_mode (adc_config_mode),
       .rx_cnvst_n (rx_cnvst_n),
@@ -113,14 +110,14 @@ module system_tb();
   end
   else //serial interface
   begin
-      wire                   ad7606_spi_sclk;
-      wire                   ad7606_spi_sdo;
-      wire [`NUM_OF_SDI-1:0] ad7606_spi_sdi;
-      wire                   ad7606_spi_cs;
-      wire                   spi_clk;
-      wire                   adc_busy;
-      wire                   adc_cnvst_n;
-      wire                   ad7606_irq;
+    wire                   ad7606_spi_sclk;
+    wire                   ad7606_spi_sdo;
+    wire [`NUM_OF_SDI-1:0] ad7606_spi_sdi;
+    wire                   ad7606_spi_cs;
+    wire                   spi_clk;
+    wire                   adc_busy;
+    wire                   adc_cnvst_n;
+    wire                   ad7606_irq;
 
     `TEST_PROGRAM test(
       .spi_clk (spi_clk),
@@ -141,6 +138,6 @@ module system_tb();
 
       assign adc_busy = adc_cnvst_n;
     end
-    endgenerate
+  endgenerate
 
 endmodule