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| 1 | +// SPDX-License-Identifier: GPL-2.0 |
| 2 | +/* |
| 3 | + * Analog Devices ADAQ7769-1 |
| 4 | + * https://wiki.analog.com/resources/eval/user-guides/ad7768-1 |
| 5 | + * |
| 6 | + * hdl_project: <ad77681evb/zed> |
| 7 | + * board_revision: <B> |
| 8 | + * |
| 9 | + * Copyright (C) 2024 Analog Devices Inc. |
| 10 | + */ |
| 11 | +/dts-v1/; |
| 12 | + |
| 13 | +#include "zynq-zed.dtsi" |
| 14 | +#include "zynq-zed-adv7511.dtsi" |
| 15 | +#include <dt-bindings/interrupt-controller/irq.h> |
| 16 | +#include <dt-bindings/gpio/gpio.h> |
| 17 | + |
| 18 | +/ { |
| 19 | + vref: regulator-vref { |
| 20 | + compatible = "regulator-fixed"; |
| 21 | + regulator-name = "fixed-supply"; |
| 22 | + regulator-min-microvolt = <4096000>; |
| 23 | + regulator-max-microvolt = <4096000>; |
| 24 | + regulator-always-on; |
| 25 | + }; |
| 26 | + |
| 27 | + clocks { |
| 28 | + ad7768_1_mclk: clock@0 { |
| 29 | + #clock-cells = <0>; |
| 30 | + compatible = "fixed-clock"; |
| 31 | + clock-frequency = <16384000>; |
| 32 | + }; |
| 33 | + }; |
| 34 | +}; |
| 35 | + |
| 36 | +&fpga_axi { |
| 37 | + rx_dma: rx-dmac@0x44a30000 { |
| 38 | + compatible = "adi,axi-dmac-1.00.a"; |
| 39 | + reg = <0x44a30000 0x1000>; |
| 40 | + #dma-cells = <1>; |
| 41 | + interrupt-parent = <&intc>; |
| 42 | + interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; |
| 43 | + clocks = <&clkc 16>; |
| 44 | + |
| 45 | + adi,channels { |
| 46 | + #size-cells = <0>; |
| 47 | + #address-cells = <1>; |
| 48 | + |
| 49 | + dma-channel@0 { |
| 50 | + reg = <0>; |
| 51 | + adi,source-bus-width = <32>; |
| 52 | + adi,source-bus-type = <1>; |
| 53 | + adi,destination-bus-width = <64>; |
| 54 | + adi,destination-bus-type = <0>; |
| 55 | + }; |
| 56 | + }; |
| 57 | + }; |
| 58 | + |
| 59 | + spi_clock: spieng-axi-clkgen@44a70000 { |
| 60 | + compatible = "adi,axi-clkgen-2.00.a"; |
| 61 | + reg = <0x44a70000 0x10000>; |
| 62 | + #clock-cells = <0>; |
| 63 | + clocks = <&clkc 15>, <&clkc 16>; |
| 64 | + clock-names = "s_axi_aclk", "clkin1"; |
| 65 | + }; |
| 66 | + |
| 67 | + axi_spi_engine_0: spi@0x44a00000 { |
| 68 | + compatible = "adi-ex,axi-spi-engine-1.00.a"; |
| 69 | + reg = <0x44a00000 0x1000>; |
| 70 | + interrupt-parent = <&intc>; |
| 71 | + interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; |
| 72 | + clocks = <&clkc 15 &spi_clock>; |
| 73 | + clock-names = "s_axi_aclk", "spi_clk"; |
| 74 | + num-cs = <1>; |
| 75 | + |
| 76 | + #address-cells = <0x1>; |
| 77 | + #size-cells = <0x0>; |
| 78 | + |
| 79 | + adaq7769_1: adc@0 { |
| 80 | + compatible = "adi,adaq7769-1"; |
| 81 | + reg = <0>; |
| 82 | + spi-max-frequency = <40000000>; |
| 83 | + spi-cpol; |
| 84 | + spi-cpha; |
| 85 | + vref-supply = <&vref>; |
| 86 | + adi,sync-in-spi; |
| 87 | + adi,aaf-gain = <143>; |
| 88 | + reset-gpios = <&gpio0 86 GPIO_ACTIVE_LOW>; |
| 89 | + clocks = <&ad7768_1_mclk>; |
| 90 | + clock-names = "mclk"; |
| 91 | + dmas = <&rx_dma 0>; |
| 92 | + dma-names = "rx"; |
| 93 | + #io-channel-cells = <1>; |
| 94 | + }; |
| 95 | + }; |
| 96 | +}; |
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