iio: frequency: ad9508: Support write only mode

There are some evaluation boards (e.g., EVAL-AD916X)
where the direction for the level translator of the
SDIO pin is hardwired to VDD, forcing the device
to operate in write-mode only.

Signed-off-by: PopPaul2021 <[email protected]>

Author: PopPaul2021

drivers/iio/frequency/ad9508.c

@@ -87,7 +87,8 @@ struct ad9508_state {
 
 	struct gpio_desc		*reset_gpio;
 	struct gpio_desc		*sync_gpio;
-
+	bool			write_mode_only;
+	unsigned long		regs_hw[44];
 	struct mutex		lock;
 
 	/*
@@ -106,6 +107,9 @@ static int ad9508_read(struct iio_dev *indio_dev, unsigned addr)
 	int ret;
 	u32 mask = ~0U >> (32 - 8 * AD9508_TRANSF_LEN(addr));
 
+	if (st->write_mode_only)
+		return st->regs_hw[AD9508_ADDR(addr)];
+
 	/* We encode the register size 1..3 bytes into the register address.
 	 * On transfer we get the size from the register datum, and make sure
 	 * the result is properly aligned.
@@ -161,6 +165,8 @@ static int ad9508_write(struct iio_dev *indio_dev, unsigned addr, unsigned val)
 	if (ret < 0)
 		dev_err(&indio_dev->dev, "write failed (%d)", ret);
 
+	st->regs_hw[AD9508_ADDR(addr)] = val;
+
 	return ret;
 }
 
@@ -661,6 +667,20 @@ static int ad9508_probe(struct spi_device *spi)
 	indio_dev->channels = st->ad9508_channels;
 	indio_dev->num_channels = pdata->num_channels;
 
+	if (device_property_present(&st->spi->dev, "adi,write-mode-only"))
+		st->write_mode_only = true;
+
+	memset(st->regs_hw, 0xFF, sizeof(st->regs_hw));
+
+	/* Initialize the regs_hw array with the reset values */
+
+	st->regs_hw[AD9508_ADDR(AD9508_PART_ID)]  = 0x0500;
+	st->regs_hw[AD9508_ADDR(AD9508_SYNC_BAR)] = 0x1;
+	st->regs_hw[AD9508_ADDR(AD9508_CHANNEL_OUT_DRIVER(0))] = 0x14;
+	st->regs_hw[AD9508_ADDR(AD9508_CHANNEL_OUT_DRIVER(1))] = 0x14;
+	st->regs_hw[AD9508_ADDR(AD9508_CHANNEL_OUT_DRIVER(2))] = 0x14;
+	st->regs_hw[AD9508_ADDR(AD9508_CHANNEL_OUT_DRIVER(3))] = 0x14;
+
 	ret = ad9508_setup(indio_dev);
 	if (ret < 0)
 		goto error_disable_reg;