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spi_engine: Create interface_ip.tcl (#1251)
Use tcl script instead of static xmls for the interface. Easier to maintain and are not gitignored. Rename spi_master to spi_engine because every interface should be prefixed by the IP name; in this case, spi_engine. Also, remove interface/*.sv files on make clean and git ignore them. Signed-off-by: Jorge Marques <[email protected]>
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‎.gitignore

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.github/CODEOWNERS
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.github/PULL_REQUEST_TEMPLATE.md
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library/**/.lock
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library/**/interfaces/*.sv

‎docs/library/spi_engine/spi-bus-interface.rst

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* - Name
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- Description
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* - :git-hdl:`library/spi_engine/interfaces/spi_master_rtl.xml`
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* - :git-hdl:`library/spi_engine/interfaces/spi_engine_rtl.xml`
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- Interface definition file
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Signal Pins

‎library/axi_ad5766/Makefile

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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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## Copyright (c) 2018 - 2024 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
@@ -25,4 +25,6 @@ XILINX_DEPS += ../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
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XILINX_LIB_DEPS += util_cdc
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XILINX_INTERFACE_DEPS += spi_engine/interfaces
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include ../scripts/library.mk

‎library/interfaces/Makefile

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M_FLIST := *.log
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M_FLIST += *.jou
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M_FLIST += *.sv
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M_FLIST += if_xcvr_cm.xml
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M_FLIST += if_xcvr_cm_rtl.xml
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M_FLIST += if_xcvr_ch.xml

‎library/jesd204/interfaces/Makefile

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@@ -33,6 +33,7 @@ XML_FLIST += jesd204_rx_event_rtl.xml
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M_FLIST := *.log
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M_FLIST += *.jou
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M_FLIST += *.sv
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M_FLIST += $(XML_FLIST)
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.PHONY: all xilinx clean clean-all

‎library/spi_engine/axi_spi_engine/Makefile

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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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## Copyright (c) 2018 - 2024 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
@@ -22,6 +22,8 @@ XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
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XILINX_LIB_DEPS += util_axis_fifo
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XILINX_LIB_DEPS += util_cdc
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XILINX_INTERFACE_DEPS += spi_engine/interfaces
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INTEL_DEPS += ../../common/ad_mem.v
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INTEL_DEPS += ../../intel/common/up_rst_constr.sdc
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INTEL_DEPS += ../../util_axis_fifo/util_axis_fifo.v

‎library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl

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###############################################################################
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## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
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## Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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@@ -34,37 +34,36 @@ adi_add_bus "spi_engine_ctrl" "master" \
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"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
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"analog.com:interface:spi_engine_ctrl:1.0" \
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{
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{"cmd_ready" "CMD_READY"} \
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{"cmd_valid" "CMD_VALID"} \
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{"cmd_data" "CMD_DATA"} \
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{"sdo_data_ready" "SDO_READY"} \
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{"sdo_data_valid" "SDO_VALID"} \
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{"sdo_data" "SDO_DATA"} \
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{"sdi_data_ready" "SDI_READY"} \
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{"sdi_data_valid" "SDI_VALID"} \
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{"sdi_data" "SDI_DATA"} \
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{"sync_ready" "SYNC_READY"} \
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{"sync_valid" "SYNC_VALID"} \
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{"sync_data" "SYNC_DATA"} \
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{"cmd_ready" "cmd_ready"} \
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{"cmd_valid" "cmd_valid"} \
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{"cmd_data" "cmd_data"} \
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{"sdo_data_ready" "sdo_ready"} \
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{"sdo_data_valid" "sdo_valid"} \
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{"sdo_data" "sdo_data"} \
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{"sdi_data_ready" "sdi_ready"} \
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{"sdi_data_valid" "sdi_valid"} \
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{"sdi_data" "sdi_data"} \
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{"sync_ready" "sync_ready"} \
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{"sync_valid" "sync_valid"} \
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{"sync_data" "sync_data"} \
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}
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adi_add_bus_clock "spi_clk" "spi_engine_ctrl" "spi_resetn" "master"
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adi_add_bus "spi_engine_offload_ctrl0" "master" \
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"analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" \
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"analog.com:interface:spi_engine_offload_ctrl:1.0" \
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{ \
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{ "offload0_cmd_wr_en" "CMD_WR_EN"} \
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{ "offload0_cmd_wr_data" "CMD_WR_DATA"} \
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{ "offload0_sdo_wr_en" "SDO_WR_EN"} \
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{ "offload0_sdo_wr_data" "SDO_WR_DATA"} \
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{ "offload0_enable" "ENABLE"} \
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{ "offload0_enabled" "ENABLED"} \
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{ "offload0_mem_reset" "MEM_RESET"} \
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{ "offload_sync_ready" "SYNC_READY"} \
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{ "offload_sync_valid" "SYNC_VALID"} \
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{ "offload_sync_data" "SYNC_DATA"} \
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{ "offload0_cmd_wr_en" "cmd_wr_en"} \
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{ "offload0_cmd_wr_data" "cmd_wr_data"} \
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{ "offload0_sdo_wr_en" "sdo_wr_en"} \
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{ "offload0_sdo_wr_data" "sdo_wr_data"} \
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{ "offload0_enable" "enable"} \
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{ "offload0_enabled" "enabled"} \
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{ "offload0_mem_reset" "mem_reset"} \
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{ "offload_sync_ready" "sync_ready"} \
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{ "offload_sync_valid" "sync_valid"} \
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{ "offload_sync_data" "sync_data"} \
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}
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adi_add_bus_clock "s_axi_aclk" "spi_engine_offload_ctrl0:s_axi" "s_axi_aresetn"
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foreach port {"up_clk" "up_rstn" "up_wreq" "up_waddr" "up_wdata" "up_rreq" "up_raddr"} {

‎library/spi_engine/interfaces/Makefile

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####################################################################################
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####################################################################################
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## Copyright (c) 2018 - 2024 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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####################################################################################
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M_DEPS := interfaces_ip.tcl
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M_DEPS += ../../../scripts/adi_env.tcl
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M_DEPS += ../../scripts/adi_ip_xilinx.tcl
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M_VIVADO := vivado -mode batch -source
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XML_FLIST := spi_engine.xml
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XML_FLIST += spi_engine_rtl.xml
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XML_FLIST += spi_engine_ctrl.xml
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XML_FLIST += spi_engine_ctrl_rtl.xml
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XML_FLIST += spi_engine_offload_ctrl.xml
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XML_FLIST += spi_engine_offload_ctrl_rtl.xml
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M_FLIST := *.log
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M_FLIST += *.jou
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M_FLIST += *.sv
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M_FLIST += $(XML_FLIST)
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.PHONY: all xilinx clean clean-all
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all: xilinx
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xilinx: $(XML_FLIST)
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clean:clean-all
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clean-all:
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rm -rf $(M_FLIST)
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%.xml: $(M_DEPS)
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$(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1
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####################################################################################
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####################################################################################

‎library/spi_engine/interfaces/interfaces_ip.tcl

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###############################################################################
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## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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source ../../../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
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# SPI interface
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adi_if_define "spi_engine"
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adi_if_ports output 1 sclk
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adi_if_ports output 1 sdo
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adi_if_ports output 1 sdo_t
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adi_if_ports input -1 sdi
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adi_if_ports output -1 cs
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adi_if_ports output 1 three_wire
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# Control interface
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adi_if_define "spi_engine_ctrl"
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adi_if_ports input 1 cmd_ready
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adi_if_ports output 1 cmd_valid
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adi_if_ports output 16 cmd_data
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adi_if_ports input 1 sdo_data_ready
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adi_if_ports output 1 sdo_data_valid
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adi_if_ports output -1 sdo_data
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adi_if_ports output 1 sdi_data_ready
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adi_if_ports input 1 sdi_data_valid
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adi_if_ports input -1 sdi_data
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adi_if_ports output 1 sync_ready
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adi_if_ports input 1 sync_valid
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adi_if_ports input 8 sync_data
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# Offload control interface
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adi_if_define "spi_engine_offload_ctrl"
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adi_if_ports output 1 cmd_wr_en
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adi_if_ports output 16 cmd_wr_data
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adi_if_ports output 1 sdo_wr_en
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adi_if_ports output -1 sdo_wr_data
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adi_if_ports output 1 mem_reset
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adi_if_ports output 1 enable
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adi_if_ports input 1 enabled
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adi_if_ports output 1 sync_ready
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adi_if_ports input 1 sync_valid
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adi_if_ports input 8 sync_data

‎library/spi_engine/interfaces/spi_engine_ctrl.xml

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