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FilipG24FilipG24
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projects: ad9084_ebz: vcu118: Add support for single-link mode
Signed-off-by: Filip Gherman <[email protected]>
1 parent 9719b71 commit afa347c

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3 files changed

+52
-26
lines changed

3 files changed

+52
-26
lines changed

‎projects/ad9084_ebz/common/ad9084_ebz_bd.tcl‎

Lines changed: 46 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -491,7 +491,7 @@ ad_ip_parameter axi_apollo_rx_dma CONFIG.MAX_BYTES_PER_BURST 4096
491491
ad_ip_parameter axi_apollo_rx_dma CONFIG.CYCLIC 0
492492
ad_ip_parameter axi_apollo_rx_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_data_width
493493
if {$ADI_PHY_SEL} {
494-
ad_ip_parameter axi_apollo_rx_dma CONFIG.DMA_DATA_WIDTH_DEST $adc_data_width
494+
ad_ip_parameter axi_apollo_rx_dma CONFIG.DMA_DATA_WIDTH_DEST [expr min(1024, $adc_data_width)]
495495
} else {
496496
# Versal limitation
497497
ad_ip_parameter axi_apollo_rx_dma CONFIG.DMA_DATA_WIDTH_DEST [expr min(512, $adc_data_width)]
@@ -592,7 +592,7 @@ ad_ip_parameter axi_apollo_tx_dma CONFIG.DMA_2D_TRANSFER 0
592592
ad_ip_parameter axi_apollo_tx_dma CONFIG.CYCLIC 1
593593
ad_ip_parameter axi_apollo_tx_dma CONFIG.MAX_BYTES_PER_BURST 4096
594594
if {$ADI_PHY_SEL} {
595-
ad_ip_parameter axi_apollo_tx_dma CONFIG.DMA_DATA_WIDTH_SRC $dac_data_width
595+
ad_ip_parameter axi_apollo_tx_dma CONFIG.DMA_DATA_WIDTH_SRC [expr min(1024, $dac_data_width)]
596596
} else {
597597
# Versal limitation
598598
ad_ip_parameter axi_apollo_tx_dma CONFIG.DMA_DATA_WIDTH_SRC [expr min(512, $dac_data_width)]
@@ -797,16 +797,24 @@ if {$ASYMMETRIC_A_B_MODE} {
797797
}
798798
} else {
799799
set max_lane_map {0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23}
800-
# set lane_map {}
801-
802-
# for {set i 0} {$i < $RX_NUM_LINKS} {incr i} {
803-
# for {set j 0} {$j < $RX_JESD_L} {incr j} {
804-
# set cur_lane [expr $i*$MAX_RX_LANES_PER_LINK+$j]
805-
# lappend lane_map [lindex $max_lane_map $cur_lane]
806-
# }
807-
# }
800+
set lane_map {}
801+
802+
for {set i 0} {$i < $RX_NUM_LINKS} {incr i} {
803+
for {set j 0} {$j < $RX_JESD_L} {incr j} {
804+
set cur_lane [expr $i*$MAX_RX_LANES_PER_LINK+$j]
805+
lappend lane_map [lindex $max_lane_map $cur_lane]
806+
}
807+
}
808+
809+
for {set i 0} {$i < $RX_NUM_LINKS} {incr i} {
810+
for {set j $RX_JESD_L} {$j < $MAX_RX_LANES_PER_LINK} {incr j} {
811+
set cur_lane [expr $i*$MAX_RX_LANES_PER_LINK+$j]
812+
lappend lane_map [lindex $max_lane_map $cur_lane]
813+
}
814+
}
815+
808816
if {$ADI_PHY_SEL} {
809-
ad_xcvrcon util_apollo_xcvr axi_apollo_rx_xcvr axi_apollo_rx_jesd $max_lane_map {} rx_device_clk $MAX_RX_LANES
817+
ad_xcvrcon util_apollo_xcvr axi_apollo_rx_xcvr axi_apollo_rx_jesd $lane_map {} rx_device_clk $MAX_RX_LANES
810818
create_bd_port -dir I rx_sysref_12
811819
create_bd_port -dir O rx_sync_12
812820
}
@@ -828,16 +836,34 @@ if {$ASYMMETRIC_A_B_MODE} {
828836
}
829837
} else {
830838
set max_lane_map {0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23}
831-
# set lane_map {}
832-
833-
# for {set i 0} {$i < $TX_NUM_LINKS} {incr i} {
834-
# for {set j 0} {$j < $TX_JESD_L} {incr j} {
835-
# set cur_lane [expr $i*$MAX_TX_LANES_PER_LINK+$j]
836-
# lappend lane_map [lindex $max_lane_map $cur_lane]
837-
# }
838-
# }
839+
set lane_map {}
840+
841+
for {set i 0} {$i < $TX_NUM_LINKS} {incr i} {
842+
for {set j 0} {$j < $TX_JESD_L} {incr j} {
843+
set cur_lane [expr $i*$MAX_TX_LANES_PER_LINK+$j]
844+
lappend lane_map [lindex $max_lane_map $cur_lane]
845+
}
846+
}
847+
848+
for {set i 0} {$i < $TX_NUM_LINKS} {incr i} {
849+
for {set j $TX_JESD_L} {$j < $MAX_TX_LANES_PER_LINK} {incr j} {
850+
set cur_lane [expr $i*$MAX_TX_LANES_PER_LINK+$j]
851+
lappend lane_map [lindex $max_lane_map $cur_lane]
852+
}
853+
}
854+
839855
if {$ADI_PHY_SEL} {
840-
ad_xcvrcon util_apollo_xcvr axi_apollo_tx_xcvr axi_apollo_tx_jesd $max_lane_map {} tx_device_clk $MAX_TX_LANES
856+
ad_xcvrcon util_apollo_xcvr axi_apollo_tx_xcvr axi_apollo_tx_jesd $lane_map {} tx_device_clk $MAX_TX_LANES
857+
858+
if {$TX_JESD_L == 8} {
859+
delete_bd_objs [get_bd_intf_nets axi_apollo_tx_xcvr_up_cm_8]
860+
delete_bd_objs [get_bd_intf_nets axi_apollo_tx_xcvr_up_cm_12]
861+
connect_bd_intf_net [get_bd_intf_pins axi_apollo_tx_xcvr/up_cm_8] [get_bd_intf_pins util_apollo_xcvr/up_cm_12]
862+
connect_bd_intf_net [get_bd_intf_pins axi_apollo_tx_xcvr/up_cm_12] [get_bd_intf_pins util_apollo_xcvr/up_cm_16]
863+
} elseif {$TX_JESD_L == 4} {
864+
delete_bd_objs [get_bd_intf_nets axi_apollo_tx_xcvr_up_cm_4]
865+
connect_bd_intf_net [get_bd_intf_pins axi_apollo_tx_xcvr/up_cm_4] [get_bd_intf_pins util_apollo_xcvr/up_cm_12]
866+
}
841867
create_bd_port -dir I tx_sysref_12
842868
create_bd_port -dir I tx_sync_12
843869
}

‎projects/ad9084_ebz/vcu118/system_project.tcl‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -48,15 +48,15 @@ adi_project ad9084_ebz_vcu118 0 [list \
4848
RX_JESD_L [get_env_param RX_JESD_L 8 ] \
4949
RX_JESD_S [get_env_param RX_JESD_S 1 ] \
5050
RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \
51-
RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \
51+
RX_NUM_LINKS [get_env_param RX_NUM_LINKS 2 ] \
5252
TX_JESD_M [get_env_param TX_JESD_M 4 ] \
5353
TX_JESD_L [get_env_param TX_JESD_L 8 ] \
5454
TX_JESD_S [get_env_param TX_JESD_S 1 ] \
5555
TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \
56-
TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \
56+
TX_NUM_LINKS [get_env_param TX_NUM_LINKS 2 ] \
5757
RX_KS_PER_CHANNEL [get_env_param RX_KS_PER_CHANNEL 32 ] \
5858
TX_KS_PER_CHANNEL [get_env_param TX_KS_PER_CHANNEL 32 ] \
59-
ASYMMETRIC_A_B_MODE [get_env_param ASYMMETRIC_A_B_MODE 1 ] \
59+
ASYMMETRIC_A_B_MODE [get_env_param ASYMMETRIC_A_B_MODE 0 ] \
6060
RX_B_LANE_RATE [get_env_param RX_B_LANE_RATE 20.625 ] \
6161
TX_B_LANE_RATE [get_env_param TX_B_LANE_RATE 20.625 ] \
6262
RX_B_JESD_M [get_env_param RX_B_JESD_M 4 ] \

‎projects/ad9084_ebz/vcu118/system_top.v‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -36,9 +36,9 @@
3636
`timescale 1ns/100ps
3737

3838
module system_top #(
39-
parameter TX_NUM_LINKS = 1,
40-
parameter RX_NUM_LINKS = 1,
41-
parameter ASYMMETRIC_A_B_MODE = 1
39+
parameter TX_NUM_LINKS = 2,
40+
parameter RX_NUM_LINKS = 2,
41+
parameter ASYMMETRIC_A_B_MODE = 0
4242
) (
4343
input sys_rst,
4444
input sys_clk_p,

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